Variable refresh rate control circuit and method thereof, display panel and display device

Abstract

The present application discloses a variable refresh rate control circuit and method thereof, a display panel and a display device, and relates to the field of display technology. The circuit includes pixel units arranged in an array and a corresponding refresh control module, and the refresh control module includes a mode determination unit, a refresh enable unit and a data write unit. The mode determination unit determines the pixel refresh mode through the row selection signal of the scan line and the data signal of the source line, and outputs the first / second potential of the first / second potential line. The refresh enable unit turns off the data write unit based on the first potential output by the mode determination unit in the static refresh mode to maintain the pixel data of the corresponding pixel unit, and turns on the data write unit based on the second potential output by the mode determination unit in the dynamic refresh mode to write the data signal to the corresponding pixel unit, thereby realizing variable refresh rate adjustment at the pixel level, and can simultaneously support high refresh rate and low refresh rate display, effectively reducing power consumption while ensuring the display effect.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a variable refresh rate control circuit and method thereof, a display panel, and a display device. Background Art

[0002] With the continuous development of display technology, users have placed higher demands on the visual smoothness of display panels and the control of device power consumption. Although high refresh rate display panels can significantly improve the smoothness of dynamic images, they inevitably bring higher power consumption burden.

[0003] Existing technologies use an FFR (free frame rate) solution based on GOA (Gate Driver on Array) timing adjustment, reducing power consumption by implementing a localized low refresh rate in static areas of the screen. However, this solution has significant technical drawbacks. Firstly, due to the limitations of the GOA driver architecture, its control granularity is limited to the row level, making it impossible to independently and precisely adjust the refresh rate of different pixel areas within the same row (for example, static content on the left requires a low refresh rate, while dynamic content on the right requires a high refresh rate). Secondly, due to the strict constraints inherent in the GOA progressive scanning mechanism, the refresh rate adjustment must follow the row scanning direction, that is, the refresh rate of the previous row must be higher than that of the next row, which severely limits the flexibility of application scenarios.

[0004] Therefore, how to achieve free variable refresh rate control of the display panel is a technical problem that needs to be solved urgently. Summary of the Invention

[0005] The main purpose of this application is to provide a variable refresh rate control circuit and method thereof, a display panel and a display device, aiming to achieve free variable refresh rate control of the display panel.

[0006] To achieve the above objectives, the present application provides a variable refresh rate control circuit, the variable refresh rate control circuit comprising: pixel units arranged in an array, and a refresh control module corresponding to each pixel unit, the refresh control module comprising:

[0007] a mode determination unit, wherein control terminals on both sides of the mode determination unit are electrically connected to the scan line and the source line respectively, and path terminals on both sides of the mode determination unit are electrically connected to the first potential line and the second potential line respectively;

[0008] a refresh enabling unit, wherein a switch driving side of the refresh enabling unit is electrically connected to the potential output side of the mode determining unit, and an input side of the refresh enabling unit is electrically connected to the scan line;

[0009] a data writing unit, wherein two side interface ends of the data writing unit are electrically connected to the source line and the corresponding pixel unit respectively, and a control side of the data writing unit is electrically connected to the output side of the refresh enabling unit;

[0010] The refresh control module is configured to determine a pixel refresh mode based on a row selection signal of the scan line and a data signal of the source line, and if the pixel refresh mode is a static refresh mode, enable the refresh enable unit to control the refresh enable unit to turn off the data writing unit when the mode determination unit outputs the first potential of the first potential line; and / or,

[0011] If the pixel refresh mode is a dynamic refresh mode, the refresh enabling unit is enabled to control the data writing unit to write the data signal into the corresponding pixel unit when the mode determining unit outputs the second potential of the second potential line.

[0012] In one embodiment, the mode determination unit includes a first switch tube, a second switch tube, a third switch tube and a fourth switch tube;

[0013] The gate terminal of the first switching transistor is electrically connected to the gate terminal of the second switching transistor, the gate terminal of the third switching transistor is electrically connected to the gate terminal of the fourth switching transistor, the first end of the first switching transistor is electrically connected to the first end of the fourth switching transistor, and the second end of the first switching transistor is electrically connected to the second end of the fourth switching transistor;

[0014] The first end of the second switch tube intersects with a connection node where the second end of the first switch tube is electrically connected to the second end of the fourth switch tube, and the second end of the second switch tube is electrically connected to the first end of the third switch tube.

[0015] In one embodiment, the second end of the third switch tube constitutes one of the two side passage ends and is electrically connected to the second potential line;

[0016] The first end of the first switching transistor is electrically connected to the first end of the fourth switching transistor, forming a connection node of the other side of the two-side path ends, which is electrically connected to the first potential line;

[0017] A connection node where the gate terminal of the first switching tube is electrically connected to the gate terminal of the second switching tube constitutes one of the two control terminals, and is electrically connected to the scan line;

[0018] A connection node where the gate terminal of the third switching transistor is electrically connected to the gate terminal of the fourth switching transistor constitutes the other control terminal of the two side control terminals, and is electrically connected to the source line;

[0019] The first end of the second switch tube intersects with the second end of the first switch tube and is electrically connected to the second end of the fourth switch tube. The connection node constitutes the potential output side of the mode determination unit and is electrically connected to the gate drive side of the refresh enable unit.

[0020] In one embodiment, the refresh enabling unit includes a fifth switch tube;

[0021] The gate end of the fifth switch tube constitutes the gate drive side of the refresh enable unit and is electrically connected to the potential output side of the mode determination unit, the first end of the fifth switch tube constitutes the input side of the refresh enable unit and is electrically connected to the scan line, and the second end of the fifth switch tube constitutes the output side of the refresh enable unit and is electrically connected to the control side of the data write unit.

[0022] In one embodiment, the data writing unit includes a sixth switch tube;

[0023] The gate end of the sixth switch tube constitutes the control side of the data writing unit and is electrically connected to the output side of the refresh enabling unit, and the first end of the sixth switch tube constitutes one of the two interface ends and is electrically connected to the source line;

[0024] The second end of the sixth switch tube constitutes the other interface end of the two side interface ends, and is electrically connected to the first end of the pixel capacitor in the corresponding pixel unit, and the second end of the pixel capacitor is connected to the common electrode.

[0025] In one embodiment, the variable refresh rate control circuit further includes a plurality of pull-down modules, a first end of each pull-down module is electrically connected to a corresponding source line, and a second end of each pull-down module is connected to the first potential line.

[0026] In addition, to achieve the above-mentioned purpose, the present application also provides a variable refresh rate control method, which is applied to any of the variable refresh rate control circuits described above, and the variable refresh rate control method includes:

[0027] Determining a pixel refresh mode according to a row selection signal of a scan line and a data signal of a source line;

[0028] If the pixel refresh mode is a static refresh mode, enabling the refresh enabling unit to control the refresh enabling unit to turn off the data writing unit when the mode determining unit outputs the first potential of the first potential line; and / or,

[0029] If the pixel refresh mode is a dynamic refresh mode, the refresh enabling unit is enabled to control the data writing unit to write the data signal into the corresponding pixel unit when the mode determining unit outputs the second potential of the second potential line.

[0030] In one embodiment, the step of determining the pixel refresh mode according to the row selection signal of the scan line and the data signal of the source line includes:

[0031] Determining a row strobe signal of the scan line and a data signal of the source line, and detecting whether the row strobe signal and the data signal are both valid signals;

[0032] If both the row selection signal and the data signal are valid signals, determining that the pixel refresh mode is a dynamic refresh mode;

[0033] If the row selection signal is an invalid signal or the data signal is an invalid signal, it is determined that the pixel refresh mode is a static refresh mode.

[0034] In addition, to achieve the above-mentioned purpose, the present application also provides a display panel, which includes a color film substrate, a liquid crystal layer and an array substrate, the liquid crystal layer is arranged between the array substrate and the color film substrate, and the array substrate includes the variable refresh rate control circuit described in any one of the above items.

[0035] In addition, to achieve the above-mentioned object, the present application also provides a display device, which includes the above-mentioned display panel;

[0036] Or a memory, a processor and a charging driver stored in the memory and executable on the processor, wherein the processor implements the steps of the variable refresh rate control method as described in any one of the above items when executing the charging driver.

[0037] The present application implements free variable refresh rate control at the pixel level by configuring an independent refresh control module for each pixel unit in the variable refresh rate control circuit of the display panel. The refresh control module integrates a mode determination unit, a refresh enable unit, and a data write unit. Specifically, the mode determination unit detects the row selection signal of the scan line and the data signal of the source line in real time, and dynamically determines the pixel refresh mode. When the pixel refresh mode is a static refresh mode, the mode determination unit outputs the first potential of the first potential line to the refresh enable unit to forcibly shut down the data write unit, so that the corresponding pixel unit enters a low refresh state and maintains the original pixel voltage, unaffected by changes in the data signal. When the pixel refresh mode is a dynamic refresh mode, the mode determination unit outputs the second potential of the second potential line to the refresh enable unit, enabling the data write unit to write the data signal provided by the source line into the corresponding pixel unit, thereby achieving high refresh rate display.

[0038] Different from the traditional FFR scheme based on GOA timing adjustment, this application sets up a variable refresh rate control circuit to configure an independent refresh control module for each pixel unit, breaking through the limitations of traditional GOA row-level control. It not only allows different pixels in the same row to independently set differentiated refresh rates according to display content requirements, but also completely removes the limitations of traditional line-by-line scanning on the refresh rate adjustment direction, allowing the display panel to achieve precise on-demand refresh with any pixel as the smallest unit, while ensuring smooth display of dynamic content, minimizing the power consumption of the static area, thereby realizing truly free and flexible variable refresh rate control of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0040] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0041] Figure 1 It is a schematic diagram of the refresh direction of the existing FFR solution based on GOA timing adjustment;

[0042] Figure 2 This is a structural block diagram of the first embodiment of the variable refresh rate control circuit of the present application;

[0043] Figure 3 1 is a schematic diagram of a refresh control module circuit according to an embodiment of the present application;

[0044] Figure 4 Schematic diagram of signal waveforms involved in the dynamic refresh mode involved in the embodiment of the present application;

[0045] Figure 5 1 is a circuit diagram of a dynamic refresh mode according to an embodiment of the present application;

[0046] Figure 6 1 is a schematic diagram of signal waveforms involved in a row transition refresh mode according to an embodiment of the present application;

[0047] Figure 7 1 is a circuit diagram of a row transition refresh mode according to an embodiment of the present application;

[0048] Figure 8 1 is a schematic diagram of signal waveforms involved in the pixel freeze mode involved in the embodiment of the present application;

[0049] Figure 9 1 is a circuit diagram of a pixel freeze mode according to an embodiment of the present application;

[0050] Figure 10 1 is a circuit diagram of a pull-down module according to an embodiment of the present application;

[0051] Figure 11 1 is a configuration diagram of a scan line driving circuit under a mixed refresh rate according to an embodiment of the present application;

[0052] Figure 12 This is a timing diagram of the low refresh row pixel freeze mode operation involved in the embodiment of the present application;

[0053] Figure 13 It is a pixel unit driving circuit with independent left and right side refresh involved in the embodiment of the present application;

[0054] Figure 14 It is a structural diagram of the display device involved in the embodiment of the present application.

[0055] Description of Figure Numbers:

[0056] 100, refresh control module; 10, mode determination unit; 20, refresh enable unit; 30, data write unit; 200, pixel unit; VGL, first potential line; VGH, second potential line; Gi, scan line; Si, source line; T1, first switch tube; T2, second switch tube; T3, third switch tube; T4, fourth switch tube; T5, fifth switch tube; T6, sixth switch tube; Cst, pixel capacitor.

[0057] The realization of the objectives, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0058] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0059] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back, etc.), such directional indications are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0060] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present application, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the fact that they can be implemented by ordinary technicians in this field. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0061] Exemplary embodiments are described in detail herein, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different drawings represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with this application.

[0062] In recent years, with the rapid development of display technology, high refresh rate displays have gradually become a mainstream market demand due to their advantages such as smoother visual experience in dynamic images, faster response speed, and reduced visual fatigue. However, high refresh rates also bring higher power consumption issues. This is especially important in applications such as mobile devices and laptops that require long battery life. High power consumption has become a key factor hindering the popularization of high refresh rate displays.

[0063] To balance visual experience and power consumption, some display manufacturers have proposed a free frame rate (FFR) solution. The basic principle of this solution is that when displaying a static image, the display analyzes the characteristics of subsequent frames to determine whether a specific area of ​​the image has changed. If the content in a certain area remains unchanged, the refresh rate is reduced to reduce power consumption. If the content changes, the refresh rate is maintained at a high level to ensure smoothness.

[0064] At present, the implementation of FFR technology mainly relies on GOA (Gate Driver on Array, array substrate row drive) timing adjustment, which controls the refresh of pixels by scanning row by row. However, FFR technology based on GOA has significant limitations. On the one hand, GOA controls refresh in units of rows, while the actual picture changes may be at the pixel level or in local areas. For example, some pixels in the same row require a high refresh rate, while others require a low refresh rate. At this point, FFR technology based on GOA cannot achieve refined refresh rate adjustment, resulting in limited power consumption optimization effects. On the other hand, referring to Figure 1 As shown in Figure 2, due to the progressive scanning characteristics of GOA, the FFR technology based on GOA requires that the refresh rate of the previous line must be higher than or equal to the next line, that is, Figure 1The refresh rate of area 1 must be ≥…≥ the refresh rate of area n. Otherwise, timing conflicts or picture anomalies will occur, making FFR technology unable to flexibly adapt to complex and changing picture refresh requirements. For example, some scenes may require local high-refresh areas and low-refresh areas to be staggered, which is difficult to support with existing technologies.

[0065] In summary, although the existing GOA-based FFR technology has achieved differentiated control of local refresh rates to a certain extent, its application in a wider range of scenarios is limited due to problems such as excessive refresh adjustment granularity and strong refresh direction dependence.

[0066] Therefore, in order to achieve free variable refresh rate control of a display panel, the present application provides a variable refresh rate control circuit and method thereof, a display panel, and a display device.

[0067] The present application embodiment provides a variable refresh rate control circuit, referring to Figure 2 As shown, Figure 2 This is a block diagram of the structure of the first embodiment of the variable refresh rate control circuit of the present application. The variable refresh rate control circuit includes: pixel units 200 arranged in an array, and a refresh control module 100 corresponding to each pixel unit 200, and the refresh control module 100 includes:

[0068] The mode determination unit 10 has control terminals on both sides electrically connected to the scan line Gi and the source line Si, and channel terminals on both sides electrically connected to the first potential line VGL and the second potential line VGH.

[0069] In this embodiment, the control terminals on both sides of the mode determination unit 10 are electrically connected to the scan line Gi and the source line Si, respectively, and can collect the row selection signal provided by the scan line Gi and the data signal provided by the source line Si in real time, and can dynamically analyze the refresh requirements of the corresponding pixel unit 200 to obtain the pixel refresh mode of the corresponding pixel unit 200; next, according to the obtained pixel refresh mode, it can be flexibly selected to output the first potential of the first potential line VGL or the second potential of the second potential line VGH, thereby realizing true pixel-level variable refresh rate adjustment.

[0070] It should be noted that the first potential of the first potential line VGL can be understood as a low potential, and the second potential of the second potential line VGH can be understood as a high potential; the row selection signal provided by the scan line Gi can be understood as a high potential pulse signal with a normal low potential, and the multiple scan lines Gi (i=1, 2, 3,..., n) can be scan line G1, scan line G2, scan line G3,..., scan line Gn; the source line Si can be understood as a data line, which is configured to provide a data signal carrying a data voltage to the pixel unit 200 of the corresponding column; and the multiple source lines Si (i=1, 2, 3,..., n) can be source line S1, source line S2, source line S3,..., source line Sn.

[0071] The refresh enabling unit 20 has a switch driving side electrically connected to the potential output side of the mode determining unit 10 , and an input side electrically connected to the scan line Gi.

[0072] In this embodiment, the present application sets the switch driving side of the refresh enable unit 20 to be electrically connected to the potential output side of the mode determination unit 10, and at the same time, the input side of the refresh enable unit 20 is electrically connected to the scan line Gi, thereby realizing intelligent control of the refresh behavior of a single pixel.

[0073] The data writing unit 30 has interface ends on both sides electrically connected to the source line Si and the corresponding pixel unit 200 , and a control side of the data writing unit 30 is electrically connected to the output side of the refresh enabling unit 20 .

[0074] In this embodiment, the present application sets the interface ends on both sides of the data write unit 30 to be electrically connected to the source line Si and the corresponding pixel unit 200 respectively, and at the same time electrically connects the control side of the data write unit 30 to the output side of the refresh enable unit 20, thereby achieving precise control of the pixel data writing process of a single pixel unit 200. Specifically, the data writing of the data write unit 30 is completely controlled by the refresh enable unit 20. Only when the refresh enable unit 20 activates the data write unit 30 is the data signal provided by the source line Si allowed to be written to the pixel unit 200, thereby effectively avoiding unnecessary charge leakage and erroneous writing during the non-refresh period, not only ensuring the accuracy and stability of the data display of the pixel unit 200, but also significantly reducing the power consumption during dynamic refresh, and at the same time extending the service life of the pixel unit 200 by reducing invalid data write operations.

[0075] The refresh control module 100 is configured to determine a pixel refresh mode based on the row selection signal of the scan line Gi and the data signal of the source line Si. If the pixel refresh mode is a static refresh mode, the refresh enable unit 20 is enabled to control the refresh enable unit 20 to turn off the data write unit 30 when the mode determination unit 10 outputs the first potential of the first potential line VGL; and / or, if the pixel refresh mode is a dynamic refresh mode, the refresh enable unit 20 is enabled to control the data write unit 30 to write the data signal into the corresponding pixel unit 200 when the mode determination unit 10 outputs the second potential of the second potential line VGH.

[0076] In this embodiment, the refresh control module 100 provided in the present application analyzes the row selection signal of the scan line Gi and the data signal of the source line Si in real time, and can intelligently determine whether the pixel refresh mode is a static refresh mode or a dynamic refresh mode, thereby realizing free variable refresh rate control at the pixel level. Specifically, in the static refresh mode, the refresh enable unit 20 turns off the data writing unit 30 based on the first potential of the first potential line VGL output by the mode determination unit 10, avoiding invalid refresh to reduce power consumption; in the dynamic refresh mode, the refresh enable unit 20 activates the data writing unit 30 based on the second potential of the second potential line VGH output by the mode determination unit 10 to write the data signal into the corresponding pixel unit 200 to complete the data update of the corresponding pixel unit 200, ensuring display smoothness, and breaking through the refresh limitation of the traditional GOA-based FFR technology in line units, so that different areas and even single pixels in the same display panel can operate independently at different refresh rates. At the same time, the dynamic potential control of the mode determination unit 10 realizes the intelligent switching of the pixel refresh mode, which not only meets the smooth display requirements of high-dynamic images, but also significantly reduces the power consumption of static images, providing a truly flexible and efficient variable refresh rate solution for the display panel.

[0077] Further, in some feasible embodiments, referring to Figure 3 The mode determination unit 10 includes a first switch transistor T1, a second switch transistor T2, a third switch transistor T3, and a fourth switch transistor T4; a gate terminal of the first switch transistor T1 is electrically connected to a gate terminal of the second switch transistor T2, a gate terminal of the third switch transistor T3 is electrically connected to a gate terminal of the fourth switch transistor T4, a first end of the first switch transistor T1 is electrically connected to a first end of the fourth switch transistor T4, and a second end of the first switch transistor T1 is electrically connected to a second end of the fourth switch transistor T4; a first end of the second switch transistor T2 intersects with a connection node where the second end of the first switch transistor T1 is electrically connected to the second end of the fourth switch transistor T4, and a second end of the second switch transistor T2 is electrically connected to a first end of the third switch transistor T3.

[0078] In this embodiment, referring to Figure 3 The present application is provided with a mode determination unit 10 composed of a P-type MOS transistor (i.e., a first switch transistor T1 and a fourth switch transistor T4) and an N-type MOS transistor (i.e., a second switch transistor T2 and a third switch transistor T3), which utilizes the complementary switching characteristics of the P-type MOS transistor and the N-type MOS transistor to realize intelligent judgment of the pixel refresh mode. Specifically, when the row selection signal of the scan line Gi and the data signal of the source line Si are combined and triggered, the mode determination unit 10 composed of the first switch tube T1, the second switch tube T2, the third switch tube T3 and the fourth switch tube T4 determines the pixel refresh mode of the corresponding pixel unit 200 according to the potential state of the row selection signal and the potential state of the data signal, and automatically selects whether the potential output side of the mode determination unit 10 is connected to the first potential line VGL or the second potential line VGH according to the determined pixel refresh mode. This not only improves the response speed of the logical judgment of the mode determination unit 10, but also ensures the stability of the signal transmission on its potential output side by directly connecting the potential output side of the mode determination unit 10 with the first / second potential line, thereby achieving accurate and efficient control of the pixel-level refresh rate.

[0079] It should be noted that the switching characteristics of the P-type MOS tube are high level off and low level on; the switching characteristics of the N-type MOS tube are high level on and low level off.

[0080] Furthermore, in some other feasible embodiments, referring to Figure 3 The second end of the third switch transistor T3 constitutes one of the two path ends and is electrically connected to the second potential line VGH. The first end of the first switch transistor T1 is electrically connected to the first end of the fourth switch transistor T4, forming the other path end of the two path ends and electrically connected to the first potential line VGL. The gate end of the first switch transistor T1 is electrically connected to the gate end of the second switch transistor T2, forming one of the two control ends and electrically connected to the scan line Gi. The gate end of the third switch transistor T3 is electrically connected to the gate end of the fourth switch transistor T4, forming the other of the two control ends and electrically connected to the source line Si. The first end of the second switch transistor T2 intersects with the second end of the first switch transistor T1 and is electrically connected to the second end of the fourth switch transistor T4, forming the potential output side of the mode determination unit 10 and electrically connected to the gate drive side of the refresh enable unit 20.

[0081] In this embodiment, referring to Figures 4 and 5 , when the row selection signal provided by the scanning line Gi has a potential state of Figure 4 The high potential in the dotted rectangular box and the potential state of the data signal provided by the source line Si is Figure 4 When the potential in the dotted rectangle is high, Figure 5 The first switch tube T1 and the fourth switch tube T4 indicated by the dotted line in the figure maintain the cut-off state when the potential is high. Figure 5 The second switch tube T2 and the third switch tube T3 indicated by the solid line are turned on at a high potential, so that the current pixel refresh mode of the corresponding pixel unit 200 can be determined to be the dynamic refresh mode. At this time, the second potential (i.e., high potential) provided by the second potential line VGH is transmitted to the gate drive side of the refresh enable unit 20 via the turned-on third switch tube T3 and the second switch tube T2, and the refresh enable unit 20 is controlled to turn on the data writing unit 30 by the first potential acting on the gate drive side, so as to change the source line Si to the dynamic refresh mode. Figure 4 The high-potential voltage Data1 enclosed by the dotted rectangle is charged into the corresponding pixel unit 200 .

[0082] It should be noted that, taking the row where the pixel unit 200 corresponding to a certain refresh control module 100 is located as the target pixel row, if the potential state of the row selection signal is high, the row selection signal is a valid signal for the target pixel row, that is, when the scanning line Gi scans the target pixel row row by row, the high-potential row selection signal is used to activate each pixel unit 200 on the target pixel row; if the potential state of the row selection signal is low, the row selection signal is an invalid signal for the target pixel row.

[0083] If the potential state of the data signal is high, the data signal is a valid signal of the pixel unit 200 corresponding to the refresh control module 100; if the potential state of the data signal is low, the data signal is an invalid signal of the corresponding pixel unit 200. For example, the data signal may include Figure 4 The voltage Data1, voltage Data2 and voltage Data3 in .

[0084] Figure 5 The bold solid line in the figure indicates the high potential flow link and is Figure 5 In the figure, the solid line represents the on state of each switch tube, and the dotted line represents the off state of each switch tube.

[0085] In another embodiment, referring to Figures 6 to 7 When the scan line Gi scans any pixel row except the target pixel row, the row selection signal is an invalid signal of the target pixel row, that is, the potential state of the row selection signal provided by the scan line Gi is Figure 6 The low potential in the dotted rectangular box, that is, each pixel unit 200 on the target pixel row does not need to update the data signal temporarily and still displays the previously written data signal. At this time, Figure 7 The bold solid line in the figure indicates the high potential flow link. Figure 7 The bold dashed line in the figure indicates the low potential flow link. Figure 7The first switch tube T1 in the pixel unit 200 is turned on at a low potential and the second switch tube T2 is kept in the off state at the low potential, so that the current pixel refresh mode of the corresponding pixel unit 200 can be determined to be the row transition mode in the static refresh mode; at this time, no matter the source line Si provides a data signal and its potential state is Figure 6 The high potential shown in the waveform of section a is Figure 6 The middle number is a low potential shown in the waveform of segment b. The first potential (i.e., low potential) on the first potential line VGL directly acts on the gate drive side of the refresh enable unit 20 via the turned-on first switch tube T1, and controls the refresh enable unit 20 through the first potential acting on the gate drive side to prevent the data write unit 30 from inputting the data signal provided by the source line Si into the corresponding pixel unit 200, so as to lock the originally charged voltage Data1 in the corresponding pixel unit 200, maintain the original data voltage of the corresponding pixel unit 200, and is not affected by the data signal currently provided by the source line Si.

[0086] It should be noted that Figure 6 The signal timing waveform marked with a corresponds to Figure 7 The working mode of the circuit shown in (a); Figure 6 The signal timing waveform marked with b corresponds to Figure 7 The working mode of the circuit shown in (b) is Figure 7 The bold solid line in the figure indicates the high potential flow link and is Figure 7 In the figure, the solid line represents the on state of each switch tube, and the dotted line represents the off state of each switch tube.

[0087] In yet another embodiment, referring to Figures 8 to 9 , when the source line Si provides a data signal such as Figure 8 When there is no data voltage in the dotted box, Figure 8 The fourth switch tube T4 is turned on at a low potential and the third switch tube T3 is maintained in an off state at the low potential, thereby determining that the current pixel refresh mode of the corresponding pixel unit 200 is the pixel freeze mode in the static refresh mode; at this time, regardless of the level of the row selection signal provided by the scan line Gi, the first potential (i.e., the low potential) on the first potential line VGL directly acts on the gate drive side of the refresh enable unit 20 via the turned-on fourth switch tube T4, and controls the refresh enable unit 20 through the first potential acting on the gate drive side to prevent the data write unit 30 from inputting the data signal provided by the source line Si into the corresponding pixel unit 200, so as to lock the originally charged voltage Data1 in the corresponding pixel unit 200, maintain the original data voltage of the corresponding pixel unit 200, and not be affected by the data signal currently provided by the source line Si.

[0088] It should be noted that Figure 8The signal timing waveform marked with a corresponds to Figure 9 The working mode of the circuit shown in (a); Figure 8 The signal timing waveform marked with b corresponds to Figure 9 The working mode of the circuit shown in (b) is Figure 9 The bold solid line in the figure indicates the high potential flow link and is Figure 9 In the figure, the solid line represents the on state of each switch tube, and the dotted line represents the off state of each switch tube.

[0089] In a specific embodiment, Figure 8 The signal timing waveform marked with a corresponds to Figure 9 Taking the working mode of the circuit shown in (a) as an example, when the row selection signal provided by the scan line Gi has a high potential state and the data signal provided by the source line Si has a low potential state, that is, when the scan line Gi scans the target pixel row, the data signal displayed by each pixel unit 200 on the target pixel row needs to be frozen, that is, each pixel unit 200 on the target pixel row needs to display the data signal written last time. At this time, the low potential data signal provided by the source line Si makes the gate drive side of the refresh enable unit 20 at a low potential, so as to turn off the refresh enable unit 20 (that is, the refresh enable unit 20 maintains the off state), and then turn off the data write unit 30 (that is, the data write unit 30 also maintains the off state), so that the data signal (that is, voltage Data1) written last time by each pixel unit 200 on the target pixel row will not be lost.

[0090] In another embodiment, when the row selection signal of the scan line Gi and the data signal of the source line Si are Figure 6 The signal timing waveform marked with a in the middle or Figure 8 The signal timing waveform labeled a may include the following two scenarios.

[0091] Scenario 1: Indicates that the scan line Gi scans any pixel row other than the target pixel row (i.e., other pixel rows), and the data signals displayed by each pixel unit 200 on the other pixel rows need to be frozen, so that the other pixel rows continue to display the data signal written last time and do not update the display content. Therefore, the source line Si provides a low-potential data signal. In addition, since the scan line Gi also provides a low-potential row selection signal at this time, the target pixel row is not affected by the low-potential data signal provided by the source line Si, and continues to display the previously written data signal.

[0092] Scenario 2: Indicates that the scan line Gi has scanned all pixel rows in the current frame, and there is a time gap in which the next frame of the current frame has not yet started scanning.

[0093] Further, in some feasible embodiments, referring to Figure 3The refresh enable unit 20 includes a fifth switch tube T5; the gate end of the fifth switch tube T5 constitutes the gate driving side of the refresh enable unit 20 and is electrically connected to the potential output side of the mode determination unit 10, the first end of the fifth switch tube T5 constitutes the input side of the refresh enable unit 20 and is electrically connected to the scan line Gi, and the second end of the fifth switch tube T5 constitutes the output side of the refresh enable unit 20 and is electrically connected to the control side of the data writing unit 30.

[0094] In this embodiment, referring to Figure 3 The gate terminal of the fifth switch tube T5 is connected to the potential output side of the mode determination unit 10 so as to receive the potential signal (i.e., the first potential or the second potential) output by the potential output side, and the first end of the fifth switch tube T5 is connected to the scan line Gi, and the second end of the fifth switch tube T5 is connected to the control side of the data writing unit 30 to form a driving circuit for controlling whether the data writing unit 30 is turned on. When the mode determination unit 10 outputs the first potential through its potential output side, regardless of whether the row selection signal of the scan line Gi and the data signal of the source line Si are valid, the fifth switch tube T5 is driven by its gate terminal. The first potential connected is forcibly pulled low and turned off, thereby shutting down the data writing unit 30 to achieve pixel refresh freeze. When the mode determination unit 10 outputs a second potential via its potential output side, and the row strobe signal of the scan line Gi and the data signal of the source line Si are both high-potential valid signals, the fifth switch tube T5 is driven by the second potential to turn on and provide the high-potential row strobe signal to the data writing unit 30. When the data writing unit 30 is driven by the high-potential row strobe signal, it is turned on and the high-potential data signal is charged into the corresponding pixel unit 200 to complete the pixel voltage update. In other words, the present application sets up a "potential-timing dual-condition trigger" of the fifth switch tube T5 to ensure that the refresh operation is strictly synchronized with the scan timing, and to achieve independent control of pixel-level refresh enable / disable through the output potential of the mode determination unit 10, thereby achieving precise refresh rate control at the hardware level that is independent of the scan direction and free of row and column constraints.

[0095] Furthermore, in some other feasible embodiments, the data writing unit 30 includes a sixth switch tube T6; the gate end of the sixth switch tube T6 constitutes the control side of the data writing unit 30 and is electrically connected to the output side of the refresh enable unit 20, the first end of the sixth switch tube T6 constitutes one of the two side interface ends and is electrically connected to the source line Si; the second end of the sixth switch tube T6 constitutes the other side interface end and is electrically connected to the first end of the pixel capacitor Cst in the corresponding pixel unit 200, and the second end of the pixel capacitor Cst is connected to the common electrode.

[0096] In this embodiment, referring to Figure 3The present application configures the gate terminal of the sixth switch transistor T6 to be connected to the output side of the refresh enable unit 20 to control whether the sixth switch transistor T6 is turned on, and directly connects the first terminal of the sixth switch transistor T6 to the source line Si to obtain the data signal provided by the source line Si. The first terminal of the sixth switch transistor T6 is connected to the pixel unit 200 to form a charge storage path. Specifically, when the refresh enable unit 20 outputs a high voltage, the sixth switch transistor T6 charges the data signal of the source line Si into the pixel capacitor Cst to complete the pixel state update of the pixel unit 200; and when the refresh enable unit 20 outputs a low voltage, the sixth switch transistor T6 remains in the off state, so that the pixel capacitor Cst maintains the stored voltage without being interfered with by the source line Si. In other words, the present application achieves the functional integration of data writing and voltage maintenance through the single-tube control architecture of the sixth switch transistor T6. In conjunction with the control signal on the output side of the refresh enable unit 20, while ensuring data writing accuracy, it effectively isolates the interference of the source line Si on the stored voltage of the pixel capacitor Cst, providing reliable hardware support for pixel-level refresh rate control.

[0097] Further, in some feasible embodiments, referring to Figure 10 The variable refresh rate control circuit further includes a plurality of pull-down modules, a first end of each pull-down module being electrically connected to a corresponding source line Si, and a second end of each pull-down module being connected to the first potential line VGL.

[0098] In this embodiment, the present application adds a corresponding pull-down module for each source line Si, significantly improving the reliability and response speed of variable refresh rate control. Specifically, when a source line Si is not providing a data signal, the corresponding pull-down module rapidly pulls the data signal provided by the connected source line Si down to the first potential (i.e., low potential) of the first potential line VGL, allowing the potential state of the data signal to quickly reach a low level. This, through the coordinated action of the mode determination unit 10 and the refresh enable unit 20, reliably shuts down the data write unit 30. This not only effectively eliminates the problem of false refreshes that may be caused by the floating state of the source line Si when no data signal is output, but also significantly shortens the response time from the refresh state to the frozen state, enabling completely independent refresh rate control for adjacent pixels in the same row. Furthermore, the pull-down module provided in this application requires minimal modification to the existing display panel driver circuitry, requiring only a simple pull-down switch integrated into the source driver circuitry for implementation, resulting in excellent process compatibility and mass production feasibility.

[0099] It should be noted that when there are multiple source lines Si, the multiple source lines Si can be Figure 10 The source lines S1, S2, S3, ..., and Sn are shown. The pull-down module may be a pull-down resistor.

[0100] In summary, the present application implements pixel-level free variable refresh rate control by configuring an independent refresh control module 100 for each pixel unit 200 in the variable refresh rate control circuit of the display panel. The refresh control module 100 integrates a mode determination unit 10, a refresh enable unit 20, and a data write unit 30. Specifically, the mode determination unit 10 detects the row selection signal of the scan line Gi and the data signal of the source line Si in real time, and dynamically determines the pixel refresh mode. When the pixel refresh mode is the static refresh mode, the mode determination unit 10 outputs the first potential of the first potential line VGL to the refresh enable unit 20 to forcibly shut down the data write unit 30, so that the corresponding pixel unit 200 enters a low refresh state and maintains the original pixel voltage, which is not affected by changes in the data signal. When the pixel refresh mode is the dynamic refresh mode, the mode determination unit 10 outputs the second potential of the second potential line VGH to the refresh enable unit 20, enabling the data write unit 30 to write the data signal provided by the source line Si into the corresponding pixel unit 200, thereby achieving high refresh rate display.

[0101] Different from the traditional FFR scheme based on GOA timing adjustment, the present application sets a variable refresh rate control circuit to configure an independent refresh control module 100 for each pixel unit 200, breaking through the limitations of traditional GOA row-level control. It not only allows different pixels in the same row to independently set differentiated refresh rates according to display content requirements, but also completely removes the limitations of traditional line-by-line scanning on the refresh rate adjustment direction, allowing the display panel to achieve precise on-demand refresh with any pixel as the smallest unit, while ensuring smooth display of dynamic content, minimizing the power consumption of the static area, thereby realizing truly free and flexible variable refresh rate control of the display panel.

[0102] Furthermore, based on the first embodiment of the variable refresh rate control circuit of the present application, a second embodiment of the variable refresh rate control method of the present application is proposed.

[0103] The variable refresh rate control method of the present application is applied to any of the above-mentioned variable refresh rate control circuits. The variable refresh rate control method of the present application is executed by a display device applied to the variable refresh rate control circuit. The variable refresh rate control method of the present application includes the following implementation steps S10 to S20.

[0104] Step S10: determining a pixel refresh mode according to the row selection signal of the scan line Gi and the data signal of the source line Si.

[0105] In this embodiment, referring to Figure 3In this application, the control terminals on both sides of the mode determination unit 10 are electrically connected to the scan line Gi and the source line Si respectively, so that the potential state of the row selection signal provided by the scan line Gi and the potential state of the data signal provided by the source line Si can be accurately determined; if the potential states of the row selection signal and the data signal are high, it can be said that the row selection signal and the data signal are both valid signals, and then the pixel refresh mode can be determined to be the dynamic refresh mode, and the refresh enable unit 20 is automatically triggered to turn on the data write unit 30 in the dynamic refresh mode to perform pixel voltage update (that is, the data signal of the source line Si is provided to the pixel unit 200 through the data write unit 30); if any one of the row selection signal and the data signal is invalid, the pixel refresh mode is determined to be the static refresh mode, and the refresh enable unit 20 is automatically triggered to turn off the data write unit 30 in the static refresh mode, thereby forcing the pixel unit 200 to maintain the current pixel state.

[0106] Step S20: If the pixel refresh mode is a static refresh mode, enable the refresh enable unit 20 to control the refresh enable unit 20 to turn off the data write unit 30 when the mode determination unit 10 outputs the first potential of the first potential line VGL; and / or, if the pixel refresh mode is a dynamic refresh mode, enable the refresh enable unit 20 to control the data write unit 30 to write the data signal into the corresponding pixel unit 200 when the mode determination unit 10 outputs the second potential of the second potential line VGH.

[0107] In this embodiment, in the static refresh mode, the refresh enable unit 20 turns off the data writing unit 30 based on the first potential of the first potential line VGL output by the mode determination unit 10, avoiding invalid refresh to reduce power consumption; in the dynamic refresh mode, the refresh enable unit 20 activates the data writing unit 30 based on the second potential of the second potential line VGH output by the mode determination unit 10 to write the data signal into the corresponding pixel unit 200, so as to complete the data update of the corresponding pixel unit 200, ensure the smoothness of the display, and break through the refresh limitation of the traditional GOA-based FFR technology in line units, so that different areas and even single pixels in the same display panel can operate independently at different refresh rates. At the same time, the intelligent switching of the pixel refresh mode is realized through the dynamic potential control of the mode determination unit 10, which not only meets the smooth display requirements of high-dynamic images, but also significantly reduces the power consumption of static images, providing a truly flexible and efficient variable refresh rate solution for the display panel.

[0108] Furthermore, in some other feasible embodiments, the above step S10: determining the pixel refresh mode according to the row selection signal of the scan line Gi and the data signal of the source line Si may also include the following implementation steps S101 to S103.

[0109] Step S101: determining the row strobe signal of the scan line Gi and the data signal of the source line Si, and detecting whether the row strobe signal and the data signal are both valid signals.

[0110] In this embodiment, the present application establishes a dual signal detection mechanism by real-time monitoring of the row strobe signal of the scan line Gi and the data signal of the source line Si, ensuring comprehensive perception of the pixel refresh mode. Specifically, the present application employs a mode determination unit 10 to synchronously capture the potential state of the row strobe signal and the potential state of the source line Si within a single clock cycle, thereby providing accurate and reliable input data for subsequent pixel refresh mode determination.

[0111] Step S102: If the row selection signal and the data signal are both valid signals, determining that the pixel refresh mode is a dynamic refresh mode.

[0112] In this embodiment, the pixel refresh operation is initiated only when the row selection signal is valid (indicating that it is in the row scanning period) and the data signal is valid (indicating that the pixel value needs to be updated), that is, the pixel refresh mode of the pixel unit 200 is the dynamic refresh mode at this time, thereby ensuring that each pixel refresh operation has a clear timing basis (that is, it is initiated when the row selection signal and the data signal are both high voltage) and content basis (that is, the data voltage carried by the data signal).

[0113] Step S103: If the row selection signal is an invalid signal or the data signal is an invalid signal, determining that the pixel refresh mode is a static refresh mode.

[0114] In this embodiment, if the row selection signal is an invalid signal or the data signal is an invalid signal, the pixel refresh mode is determined to be a static refresh mode, and the refresh enable unit 20 is automatically triggered to turn off the data writing unit 30 in the static refresh mode, thereby forcing the pixel unit 200 to maintain the current pixel state and enter the low refresh mode, thereby reducing the power consumption of the pixel unit 200 in the low refresh mode.

[0115] In another embodiment, referring to Figures 11 to 12 When the pixel rows connected to the scan line Gn-1 and the pixel rows connected to the scan line Gn+1 are refreshed at high speed, and the pixel rows connected to the scan line Gn are refreshed at low speed, it is only necessary to allow each pixel unit 200 in the pixel row connected to the scan line Gn to enter the pixel freeze mode when data is written. The timing of the pixel freeze mode is as follows: Figure 12 As shown, Figure 12 The reference numeral Cst_n-1 represents the pixel capacitor Cst in each pixel unit 200 on the pixel row connected to the scan line Gn-1; Figure 12 The reference numeral Cst_n represents the pixel capacitor Cst in each pixel unit 200 on the pixel row connected to the scan line Gn; Figure 12 The reference numeral Cst_n+1 represents the pixel capacitor Cst in each pixel unit 200 on the pixel row connected to the scan line Gn+1.

[0116] When the left and right pixel units 200 of the same pixel row require different refresh rates, such as Figure 13 As shown, the pixel units 200 connected to the source line S1 are the pixel units 200 on the left, and the pixel units 200 connected to the source line Sn are the pixel units 200 on the right. Assuming that the scan line Gn and the pixel units 200 connected to the source line S1 are low-brush, the source line S1 does not output a data signal (a low-potential data signal) when the scan line Gn provides a high-potential row selection signal, and normally outputs a high-potential data signal at other times.

[0117] In summary, the present application implements pixel-level free variable refresh rate control by configuring an independent refresh control module 100 for each pixel unit 200 in the variable refresh rate control circuit of the display panel. The refresh control module 100 integrates a mode determination unit 10, a refresh enable unit 20, and a data write unit 30. Specifically, the mode determination unit 10 detects the row selection signal of the scan line Gi and the data signal of the source line Si in real time, and dynamically determines the pixel refresh mode. When the pixel refresh mode is the static refresh mode, the mode determination unit 10 outputs the first potential of the first potential line VGL to the refresh enable unit 20 to forcibly shut down the data write unit 30, so that the corresponding pixel unit 200 enters a low refresh state and maintains the original pixel voltage, which is not affected by changes in the data signal. When the pixel refresh mode is the dynamic refresh mode, the mode determination unit 10 outputs the second potential of the second potential line VGH to the refresh enable unit 20, enabling the data write unit 30 to write the data signal provided by the source line Si into the corresponding pixel unit 200, thereby achieving high refresh rate display.

[0118] Different from the traditional FFR scheme based on GOA timing adjustment, the present application sets a variable refresh rate control circuit to configure an independent refresh control module 100 for each pixel unit 200, breaking through the limitations of traditional GOA row-level control. It not only allows different pixels in the same row to independently set differentiated refresh rates according to display content requirements, but also completely removes the limitations of traditional line-by-line scanning on the refresh rate adjustment direction, allowing the display panel to achieve precise on-demand refresh with any pixel as the smallest unit, while ensuring smooth display of dynamic content, minimizing the power consumption of the static area, thereby realizing truly free and flexible variable refresh rate control of the display panel.

[0119] In addition, the present application also provides a display panel, which includes a color filter substrate, a liquid crystal layer and an array substrate, the liquid crystal layer is arranged between the array substrate and the color filter substrate, and the array substrate includes any of the above-mentioned variable refresh rate control circuits.

[0120] In addition, this application also provides a display device. Figure 14 , Figure 14 1 is a schematic diagram of the structure of a display device according to an embodiment of the present application. The display device according to the embodiment of the present application may be a device for locally running a variable refresh rate control method.

[0121] like Figure 14 As shown, the display device of the embodiment of the present application may include: a display panel; or a processor 1001, such as a CPU, a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. Among them, the communication bus 1002 is used to realize the connection and communication between these components. The user interface 1003 may include a display screen (Display), an input unit such as a keyboard (Keyboard), and optionally the user interface 1003 may also include a standard wired interface and a wireless interface. The network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a Wi-Fi interface).

[0122] Memory 1005 is provided on the display device body and stores programs that, when executed by processor 1001, implement corresponding operations. Memory 1005 is also used to store parameters used by the display device. Memory 1005 can be high-speed RAM or non-volatile memory, such as disk storage. Memory 1005 can also optionally be a storage device independent of processor 1001.

[0123] Those skilled in the art will understand that Figure 14 The display device structure shown in the figure does not constitute a limitation on the display device, and may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0124] like Figure 14 As shown, the memory 1005 as a storage medium may include an operating system, a network communication module, a user interface module, and a charging driver.

[0125] exist Figure 14 In the display device shown, the processor 1001 can be used to call the charging driver stored in the memory 1005 and execute the steps of the variable refresh rate control method as described above.

[0126] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or system comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or system. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or system comprising the element.

[0127] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0128] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium such as ROM / RAM, magnetic disk, or optical disk as mentioned above, and includes a number of instructions for enabling a display device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0129] The above are only preferred embodiments of the present application and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A variable refresh rate control circuit, characterized in that: The variable refresh rate control circuit includes: pixel units arranged in an array, and a refresh control module corresponding to each pixel unit, wherein the refresh control module includes: a mode determination unit, wherein control terminals on both sides of the mode determination unit are electrically connected to the scan line and the source line respectively, and path terminals on both sides of the mode determination unit are electrically connected to the first potential line and the second potential line respectively; a refresh enabling unit, wherein a switch driving side of the refresh enabling unit is electrically connected to the potential output side of the mode determining unit, and an input side of the refresh enabling unit is electrically connected to the scan line; a data writing unit, wherein two side interface ends of the data writing unit are electrically connected to the source line and the corresponding pixel unit respectively, and a control side of the data writing unit is electrically connected to the output side of the refresh enabling unit; The refresh control module is configured to determine a pixel refresh mode based on a row selection signal of the scan line and a data signal of the source line, and if the pixel refresh mode is a static refresh mode, enable the refresh enable unit to control the refresh enable unit to turn off the data writing unit when the mode determination unit outputs the first potential of the first potential line; and / or, If the pixel refresh mode is a dynamic refresh mode, the refresh enabling unit is enabled to control the data writing unit to write the data signal into the corresponding pixel unit when the mode determining unit outputs the second potential of the second potential line.

2. The variable refresh rate control circuit according to claim 1, wherein: The mode determination unit includes a first switch tube, a second switch tube, a third switch tube and a fourth switch tube; The gate terminal of the first switching transistor is electrically connected to the gate terminal of the second switching transistor, the gate terminal of the third switching transistor is electrically connected to the gate terminal of the fourth switching transistor, the first end of the first switching transistor is electrically connected to the first end of the fourth switching transistor, and the second end of the first switching transistor is electrically connected to the second end of the fourth switching transistor; The first end of the second switch tube intersects with a connection node where the second end of the first switch tube is electrically connected to the second end of the fourth switch tube, and the second end of the second switch tube is electrically connected to the first end of the third switch tube.

3. The variable refresh rate control circuit according to claim 2, wherein: The second end of the third switch tube constitutes one of the two side passage ends and is electrically connected to the second potential line; The first end of the first switching transistor is electrically connected to the first end of the fourth switching transistor, forming a connection node of the other side of the two-side path ends, which is electrically connected to the first potential line; A connection node where the gate terminal of the first switching tube is electrically connected to the gate terminal of the second switching tube constitutes one of the two control terminals, and is electrically connected to the scan line; A connection node where the gate terminal of the third switching transistor is electrically connected to the gate terminal of the fourth switching transistor constitutes the other control terminal of the two side control terminals, and is electrically connected to the source line; The first end of the second switch tube intersects with the second end of the first switch tube and is electrically connected to the second end of the fourth switch tube. The connection node constitutes the potential output side of the mode determination unit and is electrically connected to the gate drive side of the refresh enable unit.

4. The variable refresh rate control circuit according to claim 1, wherein: The refresh enabling unit includes a fifth switch tube; The gate end of the fifth switch tube constitutes the gate drive side of the refresh enable unit and is electrically connected to the potential output side of the mode determination unit, the first end of the fifth switch tube constitutes the input side of the refresh enable unit and is electrically connected to the scan line, and the second end of the fifth switch tube constitutes the output side of the refresh enable unit and is electrically connected to the control side of the data write unit.

5. The variable refresh rate control circuit according to claim 1, wherein: The data writing unit includes a sixth switch tube; The gate end of the sixth switch tube constitutes the control side of the data writing unit and is electrically connected to the output side of the refresh enabling unit, and the first end of the sixth switch tube constitutes one of the two interface ends and is electrically connected to the source line; The second end of the sixth switch tube constitutes the other interface end of the two side interface ends, and is electrically connected to the first end of the pixel capacitor in the corresponding pixel unit, and the second end of the pixel capacitor is connected to the common electrode.

6. The variable refresh rate control circuit according to claim 1, wherein: The variable refresh rate control circuit further includes a plurality of pull-down modules, wherein a first end of each pull-down module is electrically connected to a corresponding source line, and a second end of each pull-down module is connected to the first potential line.

7. A variable refresh rate control method, characterized in that: The variable refresh rate control method is applied to the variable refresh rate control circuit according to any one of claims 1 to 6, and the variable refresh rate control method includes: Determining a pixel refresh mode according to a row selection signal of a scan line and a data signal of a source line; If the pixel refresh mode is a static refresh mode, enabling the refresh enabling unit to control the refresh enabling unit to turn off the data writing unit when the mode determining unit outputs the first potential of the first potential line; and / or, If the pixel refresh mode is a dynamic refresh mode, the refresh enabling unit is enabled to control the data writing unit to write the data signal into the corresponding pixel unit when the mode determining unit outputs the second potential of the second potential line.

8. The variable refresh rate control method according to claim 7, wherein: The step of determining the pixel refresh mode according to the row selection signal of the scan line and the data signal of the source line includes: Determining a row strobe signal of the scan line and a data signal of the source line, and detecting whether the row strobe signal and the data signal are both valid signals; If both the row selection signal and the data signal are valid signals, determining that the pixel refresh mode is a dynamic refresh mode; If the row selection signal is an invalid signal or the data signal is an invalid signal, it is determined that the pixel refresh mode is a static refresh mode.

9. A display panel, characterized in that: The display panel includes a color filter substrate, a liquid crystal layer and an array substrate, wherein the liquid crystal layer is provided between the array substrate and the color filter substrate, and the array substrate includes the variable refresh rate control circuit according to any one of claims 1 to 6.

10. A display device, characterized in that: The display device comprises the display panel according to claim 9; or, A memory, a processor, and a charging driver program stored in the memory and executable on the processor, wherein the processor implements the steps of the variable refresh rate control method according to any one of claims 7 to 8 when executing the charging driver program.

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