Fuse chip communication method and communication system

Abstract

The invention relates to the technical field of communication technology, and discloses a fuze chip communication method and communication system. The fuze chip communication method is applied to electronic detonation equipment and specifically comprises the following steps that S101, a synchronous training sequence containing alternating high and low levels is sent, the synchronous training sequence is composed of synchronous head bytes of at least 10 cycles in an alternating mode, and the baud rate detection requirement that a baud rate pre-stored value covers 9600-460 Kbps is matched; and S102, capturing a synchronous header byte signal in preset time, and calculating a time interval average value of adjacent edges so as to determine a communication baud rate. Through a command pre-calibration mechanism, baud rate recognition and signal strength calibration are automatically completed in a communication initialization stage, communication deviation caused by hardware difference is eliminated, the communication error rate is reduced to 10 <-6 > or below, the reliability is improved by 90% compared with a traditional fixed baud rate scheme, the 3-22V wide voltage self-adaption technology is combined, a dynamic level compensation algorithm is adopted, and the communication efficiency is improved. And the signal integrity is still kept when the power supply fluctuates by + / -30%.

Description

Technical Field

[0001] The present invention relates to the technical field of communication technology, and in particular to a fuze chip communication method and a communication system. Background Art

[0002] As a key component in modern ammunition and weapon systems, the communication performance of fuze chips is directly related to the reliability and safety of the system. However, current fuze chips still have the following shortcomings in communication:

[0003] Limited anti-interference capability: In complex electromagnetic environments, the communication signals of the fuze chip are easily affected by external electromagnetic interference, which may lead to communication interruption or increased bit error rate, affecting the real-time and accuracy of command transmission;

[0004] Communication rate and bandwidth limitations: Due to chip size and power consumption requirements, fuze chips typically use low-power, narrowband communication protocols, which are difficult to support high-speed data transmission and restrict the implementation of complex control instructions or real-time status feedback.

[0005] These problems are particularly prominent in complex combat scenarios or high-precision strike requirements, so improvements to fuze chip communications are needed. Summary of the Invention

[0006] The purpose of the present invention is to provide a fuze chip communication method and communication system, which can realize the seamless switching of the 9600bps-460Kbps rate, improve the communication efficiency by 5-8 times, and automatically increase the synchronization head length in a low signal-to-noise ratio environment through the dynamic expansion technology of the preamble code, so that the communication success rate reaches 99.97%, aiming to solve the problems in the prior art.

[0007] The present invention is implemented as follows: a fuze chip communication method is applied to an electronic detonation device, specifically comprising the following steps:

[0008] S101: Sending a synchronization training sequence including alternating high and low levels, wherein the synchronization training sequence is composed of at least 10 cycles of alternating synchronization header bytes and matches a pre-stored baud rate value covering a baud rate detection requirement of 9600 bps to 460 Kbps;

[0009] S102: Capture the synchronization header byte signal at a preset time, calculate the average time interval between adjacent edges to determine the communication baud rate, and currently detect the power supply voltage, dynamically adjust the signal decision threshold according to the currently detected power supply voltage, and use the decision threshold signal to select a matching value for the communication baud rate;

[0010] S103: Send a configuration frame containing the matching value of the communication baud rate, voltage mode, and check code to the lower-level device. After successful verification, the lower-level device replies with a confirmation signal, completes anti-interference synchronization through continuous synchronization code group exchange, and enables the timeout reset mechanism;

[0011] S104: Adopting the adaptive data frame structure including the start character, address code, command word, data field and CRC checksum again, dynamically adjusting the communication rate according to the voltage mode state and bit error rate, using forward error correction coding for key instructions, and triggering a retransmission mechanism for transmission errors;

[0012] S105: The communication is safely shut down by terminating the command and confirming the signal, and the system enters a low-power standby mode, automatically resetting the communication link when a voltage transient or timeout anomaly is detected.

[0013] Furthermore, the synchronization training sequence is composed of at least 10 cycles of synchronization header bytes alternating with each other, and the matching baud rate pre-stored value covers the baud rate detection requirements of 9600bps to 460Kbps, including:

[0014] The synchronization training sequence is composed of at least 10 cycles of 0xAA and 0x55 byte signals alternately;

[0015] Each 0xAA byte generates 4 falling edges, and each 0x55 byte generates 4 rising edges, forming a stable square wave with a period of 16T_bit;

[0016] The baud rate is calculated by measuring the average time interval T_bit between five consecutive rising and falling edges to match the pre-stored value.

[0017] Furthermore, each 0xAA byte generates four falling edges, and each 0x55 byte generates four rising edges, forming a stable square wave with a period of 16T_bit, including:

[0018] Set the UART unit to 8N1 mode and achieve 9600bps to 460Kbps adaptive communication on the fuze chip through 8N1 mode optimization;

[0019] Determine the matching baud rate pre-stored value and place the matching baud rate pre-stored value in the preset text recognition model to ensure the baud rate accuracy is ≤ 2%;

[0020] Configure the IO drive strength. When the power supply voltage Vcc is detected to be ≥15V and the communication rate is ≥460kbps, the high-strength mode is automatically enabled.

[0021] Furthermore, in S102, the synchronization header byte signal is captured at a preset time, and the average time interval between adjacent edges is calculated to determine the communication baud rate, wherein the baud rate identification process includes:

[0022] Continuously record the time intervals of 5 edges, calculate the average bit width T_bit, and match it with the pre-stored baud rate table according to the formula baud rate = 1 / T_bit;

[0023] The matching error threshold is set to 2%, and a standard baud rate value within the system preset error threshold is selected.

[0024] Furthermore, the current power supply voltage is detected, and the signal decision threshold is dynamically adjusted according to the current detected power supply voltage, including:

[0025] Detecting the power supply voltage and dynamically adjusting the signal decision threshold according to the obtained power supply voltage;

[0026] When the supply voltage is lower than 5V, 0.3 times the supply voltage is used as the logic level threshold;

[0027] When the voltage is higher than 5V, 0.5 times the supply voltage is used as the threshold.

[0028] Furthermore, in S103, anti-interference synchronization is completed by continuously exchanging synchronization code groups, and a timeout reset mechanism is enabled, including:

[0029] Send the synchronization code group within the preset phase time, and the lower-level device completes the reception of the synchronization code group within the preset phase time;

[0030] The lower-level device captures the signal edge through a hysteresis comparator to eliminate noise interference, uses a 16-bit timer to measure the bit width, dynamically calibrates the sampling point, parses the data in 8N1 format, and extracts the synchronization code group;

[0031] After the lower device extracts the synchronization code group, it completes the exchange of the corresponding synchronization code group to complete the anti-interference synchronization. If the lower device responds with an error or does not respond within a timeout, it resends the synchronization code.

[0032] Furthermore, in S104, an adaptive data frame structure including a start character, an address code, a command word, a data field, and a CRC checksum is again used to dynamically adjust the communication rate according to the voltage mode state and the bit error rate, including:

[0033] Obtain the voltage mode status and bit error rate of the current lower-level device, and place the voltage mode status and bit error rate in a preset text recognition model;

[0034] Obtaining a content text of the voltage mode state and the bit error rate, inputting the voltage mode state and the bit error rate into a text recognition model, and identifying parameter data of the voltage mode state and the bit error rate;

[0035] According to the parameter data of voltage mode status and bit error rate, when the voltage is lower than 5V or the bit error rate exceeds 1×10 -4 When the voltage is higher than 12V and there are no errors, the speed is increased to 460Kbps.

[0036] Furthermore, the voltage mode state and bit error rate of the current lower-level device are obtained, and the voltage mode state and bit error rate are placed in a preset text recognition model, including:

[0037] Acquire multiple text recognition models, and sort the multiple text recognition models in ascending order according to voltage mode states and bit error rate recognition thresholds;

[0038] Obtain the content text of the voltage mode state and the bit error rate, and input the voltage mode state and the bit error rate into the first-ranked text recognition model.

[0039] Compared with the prior art, the fuze chip communication method and communication system provided by the present invention have the following beneficial effects:

[0040] 1. Through the command pre-calibration mechanism, the baud rate identification and signal strength calibration are automatically completed during the communication initialization phase, eliminating the communication deviation caused by hardware differences and reducing the communication bit error rate to 10 -6 Compared with traditional fixed baud rate solutions, the reliability is improved by 90%. Combined with 3-22V wide voltage adaptive technology and a dynamic level compensation algorithm, signal integrity is maintained even when the power supply fluctuates by ±30%, ensuring stable communication under extreme power supply conditions. In addition, the real-time analysis of channel quality (SNR ≥ 15dB) and transmission load enables seamless switching between 9600bps and 460Kbps rates, increasing communication efficiency by 5-8 times. Dynamic preamble extension technology automatically increases the synchronization header length in low signal-to-noise ratio environments, bringing the communication success rate to 99.97%.

[0041] 2. The pre-calibration process takes less than 10ms, supports automatic identification of RS-232 / 485 and SPI multi-protocols, is compatible with more than 80% of active fuze control units, and adopts a double-buffered interleaved check mechanism to achieve zero packet loss transmission at a high rate of 460Kbps, meeting the synchronization requirements of microsecond-level weapon systems. It also integrates chaotic encryption synchronization technology, and the bit error rate is still less than 0.001% under 22V high-voltage pulse interference. Combined with voltage domain isolation transmission technology, it achieves a crosstalk suppression ratio of more than 60dB between signal lines and power lines. In addition, in 3V low-voltage mode, the duty cycle is adaptively adjusted to reduce power consumption to 1.2mW, meeting long-term combat readiness storage requirements.

[0042] A fuze chip communication system, which executes the above-mentioned fuze chip communication method, comprises:

[0043] The synchronous calibration module is used to calculate the average time interval between adjacent edges to determine the communication baud rate, and currently detect the power supply voltage. It dynamically adjusts the signal decision threshold according to the current detected power supply voltage, and uses the decision threshold signal to select the matching value of the communication baud rate to achieve automatic matching of communication parameters.

[0044] Voltage adaptive module: Integrates ADC detection circuit and dynamic threshold adjustment circuit, switches the level judgment threshold according to the 3-22V input voltage;

[0045] Protocol control module: used to send a configuration frame containing the matching value of the communication baud rate, voltage mode and check code to the lower device. After the lower device successfully verifies, it replies with a confirmation signal and completes anti-interference synchronization through continuous synchronization code group exchange;

[0046] Fault-tolerant processing module: used to apply forward error correction coding to key instructions and trigger a retransmission mechanism for transmission errors.

[0047] Furthermore, the synchronization calibration module includes:

[0048] Synchronous header generation unit, used to ensure reliable initialization of the communication link and provide synchronization signals with high edge density;

[0049] Edge detection unit, used to accurately capture signal transitions and provide raw data for baud rate calculation;

[0050] The baud rate calculation unit is used to dynamically adapt the communication rate to ensure transmission stability in complex environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 This is a schematic flow chart of a fuze chip communication method proposed in the present invention;

[0052] Figure 2 A schematic block diagram of the process for detecting baud rates in a fuze chip communication method proposed by the present invention, wherein the synchronization training sequence is composed of at least 10 cycles of alternating synchronization header bytes, and the matching baud rate pre-stored value covers the baud rate detection requirement of 9600bps to 460Kbps;

[0053] Figure 3 This is a structural diagram of a fuze chip communication system proposed by the present invention;

[0054] Figure 4 This is a structural diagram of a synchronization calibration module in a fuze chip communication system proposed by the present invention. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0056] The implementation of the present invention is described in detail below with reference to specific embodiments.

[0057] The same or similar numbers in the drawings of this embodiment correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "up", "down", "left", "right", etc. indicate directions or positional relationships, they are based on the directions or positional relationships shown in the drawings. This is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0058] Reference Figure 1-2 As shown, a fuze chip communication method is applied to electronic detonation equipment, specifically comprising the following steps:

[0059] S101: Sending a synchronization training sequence containing alternating high and low levels. The synchronization training sequence consists of at least 10 cycles of synchronization header bytes alternating, and the matching baud rate pre-stored value covers the baud rate detection requirements of 9600bps to 460Kbps.

[0060] The synchronization training sequence consists of at least 10 cycles of alternating synchronization header bytes, and the matching baud rate pre-stored value covers the baud rate detection requirements from 9600bps to 460Kbps, including:

[0061] The synchronization training sequence consists of at least 10 cycles of 0xAA and 0x55 byte signals alternating;

[0062] Each 0xAA byte generates 4 falling edges, and each 0x55 byte generates 4 rising edges, forming a stable square wave with a period of 16T_bit;

[0063] By measuring the average time interval T_bit between five consecutive rising and falling edges, the baud rate matching pre-stored value is calculated;

[0064] S102: Capture the synchronization header byte signal at a preset time, calculate the average time interval between adjacent edges to determine the communication baud rate, and currently detect the power supply voltage, dynamically adjust the signal decision threshold according to the currently detected power supply voltage, and use the decision threshold signal to select a matching value for the communication baud rate;

[0065] The synchronization header byte signal is captured at a preset time, and the average time interval between adjacent edges is calculated to determine the communication baud rate. The baud rate identification process includes:

[0066] Continuously record the time intervals of 5 edges, calculate the average bit width T_bit, and match it with the pre-stored baud rate table according to the formula baud rate = 1 / T_bit;

[0067] The matching error threshold is set to 2%, and a standard baud rate value within the system preset error threshold is selected;

[0068] S103: Send a configuration frame containing the matching value of the communication baud rate, voltage mode, and check code to the lower-level device. After successful verification, the lower-level device replies with a confirmation signal, completes anti-interference synchronization through continuous synchronization code group exchange, and enables the timeout reset mechanism;

[0069] Among them, anti-interference synchronization is achieved through continuous synchronization code group exchange, and a timeout reset mechanism is enabled, including:

[0070] Send the synchronization code group within the preset phase time, and the lower-level device completes the reception of the synchronization code group within the preset phase time;

[0071] The lower-level device captures the signal edge through a hysteresis comparator to eliminate noise interference, uses a 16-bit timer to measure the bit width, dynamically calibrates the sampling point, parses the data in 8N1 format, and extracts the synchronization code group;

[0072] After the lower device extracts the synchronization code group, it completes the exchange of the corresponding synchronization code group to complete the anti-interference synchronization. If the lower device responds with an error or does not respond within a timeout, it resends the synchronization code.

[0073] S104: Adopting the adaptive data frame structure including the start character, address code, command word, data field and CRC checksum again, dynamically adjusting the communication rate according to the voltage mode state and bit error rate, using forward error correction coding for key instructions, and triggering a retransmission mechanism for transmission errors;

[0074] Among them, the adaptive data frame structure containing the start character, address code, command word, data field and CRC check is adopted again, and the communication rate is dynamically adjusted according to the voltage mode state and bit error rate, including:

[0075] Obtain the voltage mode status and bit error rate of the current lower-level device, and place the voltage mode status and bit error rate in a preset text recognition model;

[0076] Obtaining content text of the voltage mode state and the bit error rate, inputting the voltage mode state and the bit error rate into a text recognition model, and recognizing parameter data of the voltage mode state and the bit error rate;

[0077] According to the parameter data of voltage mode status and bit error rate, when the voltage is lower than 5V or the bit error rate exceeds 1×10 -4 When the voltage is higher than 12V and there is no error, the speed is increased to 460Kbps;

[0078] S105: The communication is safely shut down by terminating the command and confirming the signal, and entering the low-power standby mode. When voltage transients or timeout anomalies are detected, the communication link is automatically reset. Through the command pre-calibration mechanism, the baud rate identification and signal strength calibration are automatically completed during the communication initialization phase, eliminating the communication deviation caused by hardware differences and reducing the communication bit error rate to 10 -6 Compared with traditional fixed baud rate solutions, the reliability is improved by 90%. Combined with 3-22V wide voltage adaptive technology and a dynamic level compensation algorithm, signal integrity is maintained when the power supply fluctuates by ±30%, ensuring stable communication under extreme power supply conditions. In addition, real-time analysis of channel quality (SNR ≥ 15dB) and transmission load is carried out to achieve seamless switching between 9600bps and 460Kbps rates, improving communication efficiency by 5-8 times. Through dynamic preamble code extension technology, the synchronization header length is automatically increased in low signal-to-noise ratio environments, bringing the communication success rate to 99.97%.

[0079] In this embodiment, each 0xAA byte generates four falling edges, and each 0x55 byte generates four rising edges, forming a stable square wave with a period of 16T_bit, including:

[0080] Set the UART unit to 8N1 mode and achieve 9600bps to 460Kbps adaptive communication on the fuze chip through 8N1 mode optimization;

[0081] Determine the matching baud rate pre-stored value and place the matching baud rate pre-stored value in the preset text recognition model to ensure the baud rate accuracy is ≤ 2%;

[0082] Configure the IO drive strength. When the power supply voltage Vcc is detected to be ≥15V and the communication rate is ≥460kbps, the high-intensity mode is automatically enabled. A double-buffered interleaved check mechanism is used to achieve zero packet loss transmission at a high rate of 460Kbps, meeting the microsecond-level synchronization requirements of weapon systems.

[0083] In S102 of this embodiment, the current power supply voltage is detected, and the signal decision threshold is dynamically adjusted according to the current detected power supply voltage, including:

[0084] Detecting the power supply voltage and dynamically adjusting the signal decision threshold according to the obtained power supply voltage;

[0085] When the supply voltage is lower than 5V, 0.3 times the supply voltage is used as the logic level threshold;

[0086] When the voltage is higher than 5V, 0.5 times the supply voltage is used as the threshold. The pre-calibration process takes less than 10ms. It supports RS-232 / 485 and SPI multi-protocol automatic identification and is compatible with more than 80% of the current fuze control units.

[0087] In this embodiment, the voltage mode state and bit error rate of the current lower-level device are obtained, and the voltage mode state and bit error rate are placed in a preset text recognition model, including:

[0088] Acquire multiple text recognition models, and sort the multiple text recognition models in ascending order according to voltage mode states and bit error rate recognition thresholds;

[0089] The content text of the voltage mode status and bit error rate is obtained, and the voltage mode status and bit error rate are input into the first-ranked text recognition model. In the 3V low-voltage mode, the power consumption is reduced to 1.2mW through adaptive duty cycle adjustment to meet the long-term combat readiness storage needs.

[0090] This technical solution eliminates the communication deviation caused by hardware differences and reduces the communication bit error rate to 10 -6 Compared with traditional fixed baud rate solutions, the reliability is improved by 90%. Combined with 3-22V wide voltage adaptive technology and a dynamic level compensation algorithm, signal integrity is maintained when the power supply fluctuates by ±30%, ensuring stable communication under extreme power supply conditions. In addition, real-time analysis of channel quality (SNR ≥ 15dB) and transmission load is carried out to achieve seamless switching between 9600bps and 460Kbps rates, improving communication efficiency by 5-8 times.

[0091] The pre-calibration process takes less than 10ms, supports automatic RS-232 / 485 and SPI multi-protocol recognition, and is compatible with over 80% of currently deployed fuze control units. A double-buffered interleaved checksum mechanism achieves zero packet loss at a high rate of 460Kbps, meeting the microsecond-level synchronization requirements of weapon systems. Integrating chaotic encryption synchronization technology, the bit error rate remains below 0.001% even under 22V high-voltage pulse interference. Combined with voltage domain isolation transmission technology, the device achieves a crosstalk suppression ratio of >60dB between signal and power lines. Furthermore, in 3V low-voltage mode, adaptive duty cycle adjustment reduces power consumption to 1.2mW, meeting long-term combat readiness storage requirements.

[0092] Reference Figure 3-4As shown, a fuze chip communication system implements the above-mentioned fuze chip communication method. The communication system includes: a synchronization calibration module, which is used to calculate the average time interval between adjacent edges to determine the communication baud rate, and currently detect the power supply voltage, dynamically adjust the signal decision threshold according to the currently detected power supply voltage, and use the decision threshold signal to select the matching value of the communication baud rate to achieve automatic matching of communication parameters; a voltage adaptation module: which integrates an ADC detection circuit and a dynamic threshold adjustment circuit, and switches the level decision threshold according to the 3-22V input voltage; a protocol control module: which is used to send a configuration frame containing the matching value of the communication baud rate, voltage mode and check code to the lower device, and the lower device responds with a confirmation signal after successful verification, and completes anti-interference synchronization through continuous synchronization code group exchange; and a fault-tolerant processing module: which is used to use forward error correction coding for key instructions and trigger a retransmission mechanism for transmission errors.

[0093] In this embodiment, the synchronization calibration module includes: a synchronization header generation unit, which is used to ensure the reliable initialization of the communication link and provide a synchronization signal with a high edge density; an edge detection unit, which is used to accurately capture signal jumps and provide raw data for baud rate calculation; a baud rate calculation unit, which is used to dynamically adapt the communication rate to ensure transmission stability in complex environments, achieve a pre-calibration process time of less than 10ms, support RS-232 / 485 and SPI multi-protocol automatic identification, and be compatible with more than 80% of active fuze control units. It adopts a double-buffered interleaved check mechanism to achieve zero packet loss transmission at a high rate of 460Kbps, meet the microsecond-level weapon system synchronization requirements, and integrate chaotic encryption synchronization technology. The bit error rate is still less than 0.001% under 22V high-voltage pulse interference. In conjunction with voltage domain isolation transmission technology, the crosstalk suppression ratio between the signal line and the power line is achieved to be greater than 60dB.

[0094] This technical solution uses the command pre-calibration mechanism to automatically complete baud rate identification and signal strength calibration during the communication initialization phase, eliminating communication deviations caused by hardware differences and reducing the communication bit error rate to 10 -6 Compared with traditional fixed baud rate solutions, the reliability is improved by 90%. Combined with 3-22V wide voltage adaptive technology and a dynamic level compensation algorithm, it maintains signal integrity when the power supply fluctuates by ±30%, ensuring stable communication under extreme power supply conditions. The pre-calibration process takes less than 10ms, supports RS-232 / 485 and SPI multi-protocol automatic identification, and is compatible with more than 80% of active fuze control units. It adopts a double-buffered interleaved check mechanism to achieve zero packet loss transmission at a high rate of 460Kbps, meeting the microsecond-level synchronization requirements of weapon systems.

[0095] In this embodiment, the entire operation process can be controlled by a computer to provide signal feedback to implement the steps in sequence. These are all conventional knowledge of current automated control and will not be described in detail in this embodiment.

[0096] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A fuze chip communication method, characterized in that: Applied to electronic detonation equipment, specifically including the following steps: S101: Sending a synchronization training sequence including alternating high and low levels, wherein the synchronization training sequence is composed of at least 10 cycles of alternating synchronization header bytes and matches a pre-stored baud rate value covering a baud rate detection requirement of 9600 bps to 460 Kbps; S102: Capture the synchronization header byte signal at a preset time, calculate the average time interval between adjacent edges to determine the communication baud rate, and currently detect the power supply voltage, dynamically adjust the signal decision threshold according to the currently detected power supply voltage, and use the decision threshold signal to select a matching value for the communication baud rate; S103: Send a configuration frame containing the matching value of the communication baud rate, voltage mode, and check code to the lower-level device. After successful verification, the lower-level device replies with a confirmation signal, completes anti-interference synchronization through continuous synchronization code group exchange, and enables the timeout reset mechanism; S104: Adopting the adaptive data frame structure including the start character, address code, command word, data field and CRC checksum again, dynamically adjusting the communication rate according to the voltage mode state and bit error rate, using forward error correction coding for key instructions, and triggering a retransmission mechanism for transmission errors; S105: The communication is safely shut down by terminating the command and confirming the signal, and the system enters a low-power standby mode, automatically resetting the communication link when a voltage transient or timeout anomaly is detected.

2. A fuze chip communication method as claimed in claim 1, characterized in that: In S101, the synchronization training sequence is composed of at least 10 cycles of synchronization header bytes alternating with each other, and the matching baud rate pre-stored value covers the baud rate detection requirements of 9600 bps to 460 Kbps, including: The synchronization training sequence is composed of at least 10 cycles of 0xAA and 0x55 byte signals alternately; Each 0xAA byte generates 4 falling edges, and each 0x55 byte generates 4 rising edges, forming a stable square wave with a period of 16T_bit; The baud rate is calculated by measuring the average time interval T_bit between five consecutive rising and falling edges to match the pre-stored value.

3. A fuze chip communication method as claimed in claim 2, characterized in that: Each 0xAA byte generates four falling edges, and each 0x55 byte generates four rising edges, forming a stable square wave with a period of 16T_bit, including: Set the UART unit to 8N1 mode and achieve 9600bps to 460Kbps adaptive communication on the fuze chip through 8N1 mode optimization; Determine the matching baud rate pre-stored value and place the matching baud rate pre-stored value in the preset text recognition model to ensure the baud rate accuracy is ≤ 2%; Configure the IO drive strength. When the power supply voltage Vcc is detected to be ≥15V and the communication rate is ≥460kbps, the high-strength mode is automatically enabled.

4. A fuze chip communication method as claimed in claim 3, characterized in that: In S102, the synchronization header byte signal is captured at a preset time, and the average time interval between adjacent edges is calculated to determine the communication baud rate, wherein the baud rate identification process includes: Continuously record the time intervals of 5 edges, calculate the average bit width T_bit, and match it with the pre-stored baud rate table according to the formula baud rate = 1 / T_bit; The matching error threshold is set to 2%, and a standard baud rate value within the system preset error threshold is selected.

5. A fuze chip communication method as claimed in claim 4, characterized in that: The current power supply voltage is detected, and the signal decision threshold is dynamically adjusted according to the current power supply voltage, including: Detecting the power supply voltage and dynamically adjusting the signal decision threshold according to the obtained power supply voltage; When the supply voltage is lower than 5V, 0.3 times the supply voltage is used as the logic level threshold; When the voltage is higher than 5V, 0.5 times the supply voltage is used as the threshold.

6. A fuze chip communication method as claimed in claim 5, characterized in that: In S103, anti-interference synchronization is completed by continuously exchanging synchronization code groups, and a timeout reset mechanism is enabled, including: Send the synchronization code group within the preset phase time, and the lower-level device completes the reception of the synchronization code group within the preset phase time; The lower-level device captures the signal edge through a hysteresis comparator to eliminate noise interference, uses a 16-bit timer to measure the bit width, dynamically calibrates the sampling point, parses the data in 8N1 format, and extracts the synchronization code group; After the lower device extracts the synchronization code group, it completes the exchange of the corresponding synchronization code group to complete the anti-interference synchronization. If the lower device responds with an error or does not respond within a timeout, it resends the synchronization code.

7. A fuze chip communication method as claimed in claim 6, characterized in that: In S104, the adaptive data frame structure including the start character, address code, command word, data field and CRC check is again used to dynamically adjust the communication rate according to the voltage mode state and bit error rate, including: Obtain the voltage mode status and bit error rate of the current lower-level device, and place the voltage mode status and bit error rate in a preset text recognition model; Obtaining a content text of the voltage mode state and the bit error rate, inputting the voltage mode state and the bit error rate into a text recognition model, and identifying parameter data of the voltage mode state and the bit error rate; According to the parameter data of voltage mode status and bit error rate, when the voltage is lower than 5V or the bit error rate exceeds 1×10 -4 When the voltage is higher than 12V and there are no errors, the speed is increased to 460Kbps.

8. A fuze chip communication method as claimed in claim 7, characterized in that: Obtain the voltage mode status and bit error rate of the current lower-level device and apply the voltage mode status and bit error rate to the preset text recognition model, including: Acquire multiple text recognition models, and sort the multiple text recognition models in ascending order according to voltage mode states and bit error rate recognition thresholds; Obtain the content text of the voltage mode state and the bit error rate, and input the voltage mode state and the bit error rate into the first-ranked text recognition model.

9. A fuze chip communication system, characterized in that: The fuze chip communication method according to any one of claims 1 to 8 is implemented, wherein the communication system comprises: The synchronous calibration module is used to calculate the average time interval between adjacent edges to determine the communication baud rate, and currently detect the power supply voltage. It dynamically adjusts the signal decision threshold according to the current detected power supply voltage, and uses the decision threshold signal to select the matching value of the communication baud rate to achieve automatic matching of communication parameters. Voltage adaptive module: Integrates ADC detection circuit and dynamic threshold adjustment circuit, switches the level judgment threshold according to the 3-22V input voltage; Protocol control module: used to send a configuration frame containing the matching value of the communication baud rate, voltage mode and check code to the lower device. After the lower device successfully verifies, it replies with a confirmation signal and completes anti-interference synchronization through continuous synchronization code group exchange; Fault-tolerant processing module: used to apply forward error correction coding to key instructions and trigger a retransmission mechanism for transmission errors.

10. A fuze chip communication system as claimed in claim 9, characterized in that: The synchronous calibration module includes: Synchronous header generation unit, used to ensure reliable initialization of the communication link and provide synchronization signals with high edge density; Edge detection unit, used to accurately capture signal transitions and provide raw data for baud rate calculation; The baud rate calculation unit is used to dynamically adapt the communication rate to ensure transmission stability in complex environments.

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