Automatic quality control method and device for batch testing of switches

Abstract

The invention relates to an automatic quality control method and device for batch test of switches, and the method comprises the following steps: carrying out the performance test of preset batch switches, and obtaining a switch performance test data set; judging whether the batch switches have abnormal switches based on the switch performance test data set; if yes, fault positioning is carried out on the abnormal switch based on the switch performance test data set, and a switch defect distribution report is obtained; and calling the production process of the batch switches from the database, and carrying out quality control point optimization adjustment on the production process based on the switch defect distribution report to realize production of batch target switches, thereby solving the problems that a traditional manual test method is time-consuming and labor-consuming, and the test efficiency is high. And the quality consistency of each switch is difficult to guarantee.

Description

Technical Field

[0001] The present invention relates to the technical field of switches, and in particular to an automated quality control method and device for batch testing of switches. Background Art

[0002] In today's highly connected world, switches, as a core piece of data transmission equipment, have a significant impact on the efficiency and reliability of the entire network system through their performance and stability. However, with the rapid development of information technology, the types and functions of switches are becoming increasingly diverse. For manufacturers, efficient and accurate batch testing of switches has become a major challenge. Traditional manual testing methods are not only time-consuming and labor-intensive, but also struggle to ensure consistent quality across every switch. This limitation is particularly evident in large-scale production environments.

[0003] Faced with these challenges, existing automated testing solutions mostly focus on a single process or specific switch models, lacking a universal automated quality control approach suitable for batch testing of multiple switch models. This results in the inability to fully cover the entire process, from performance testing and fault diagnosis to production process optimization, even with the introduction of some automated tools and technologies. This limits overall production efficiency. Furthermore, since different batches of switches may exhibit different defect patterns, failing to effectively identify and dynamically adjust the production process to address these patterns will make it difficult to fundamentally address quality issues, thus impacting the market competitiveness of the final product.

[0004] Therefore, developing an integrated, automated switch batch testing quality control system is crucial. Such a system needs to be able to conduct comprehensive and detailed performance evaluations of mass-produced switches, quickly locate potential fault points through intelligent analysis, and generate detailed defect distribution reports. More importantly, the system must be able to feed test results back into the production process, optimizing quality control points to ensure that every switch shipped meets high quality standards, meeting market demand while also improving the company's production management efficiency. Summary of the Invention

[0005] The main purpose of the present invention is to provide an automated quality control method and device for batch testing of switches, which solves the technical problem that traditional manual testing methods are not only time-consuming and labor-intensive, but also difficult to ensure the quality consistency of each switch.

[0006] To achieve the above object, the present invention provides an automated quality control method for batch testing of switches, comprising the following steps: Perform performance testing on a preset batch of switches to obtain a switch performance test data set; Determining whether there is an abnormal switch in the batch of switches based on the switch performance test data set; If so, locating the fault of the abnormal switch based on the switch performance test data set to obtain a switch defect distribution report; The production process of the batch of switches is called from the database, and the quality control points of the production process are optimized and adjusted based on the switch defect distribution report to achieve the production of the target batch of switches.

[0007] Furthermore, locating the fault of the abnormal switch based on the switch performance test data set to obtain a switch defect distribution report includes: Performing anomaly detection feature extraction on the switch performance test data set to obtain a switch performance anomaly feature vector set, and performing hierarchical clustering analysis on the switch performance anomaly feature vector set to obtain an abnormal switch fault type classification result; Based on the fault type classification result of the abnormal switch, in-depth fault diagnosis is performed on the abnormal switch to obtain a switch hardware-software fault correlation map, and topological analysis is performed on the switch hardware-software fault correlation map to obtain a fault propagation link; Performing root cause location calculation on the abnormal switch based on the fault propagation link to obtain a fault root source probability distribution matrix, and performing Bayesian network inference on the fault root source probability distribution matrix to obtain a switch fault root cause location result; Based on the switch fault root cause location results, the production records of the batch of switches are retroactively analyzed to obtain a production process defect distribution heat map, and quality bottlenecks are identified on the production process defect distribution heat map to obtain a switch defect distribution report; wherein, the production process defect distribution heat map includes chip manufacturing defect distribution and circuit board assembly defect distribution.

[0008] Furthermore, optimizing and adjusting the quality control points of the production process based on the switch defect distribution report to achieve production of target switches in batches includes: Extracting key defect nodes from the switch defect distribution report to obtain a defect-related topology network, and performing minimum cut set analysis on the defect-related topology network to obtain a set of key points for production process quality control; Based on the set of key quality control points of the production process, quantitative parameters of the production process of the batch switches are reconstructed to obtain a production process parameter optimization matrix, and a non-dominated sorting algorithm is performed on the production process parameter optimization matrix to obtain a multi-objective optimization solution set; wherein the production process parameter optimization matrix includes chip manufacturing precision parameters and circuit board soldering temperature control parameters; The multi-objective optimization solution set is solved iteratively by a genetic-particle hybrid algorithm to obtain a production process adjustment strategy sequence; Performing a digital twin simulation of the production process based on the production process adjustment strategy sequence to obtain production process digital twin model response data, and performing quality control point analysis on the production process digital twin model response data to obtain a quality control point optimization configuration scheme; wherein the production process digital twin model response data includes virtual production line throughput, quality consistency index, defect interception rate, and resource utilization efficiency; Based on the quality control point optimization configuration scheme, an adaptive control system is deployed for the production process to obtain an intelligent quality control execution instruction set, and feedback closed-loop verification is performed on the intelligent quality control execution instruction set to obtain production batch target switches.

[0009] Furthermore, the minimum cut set analysis is performed on the defect association topology network to obtain a set of key points for quality control of the production process, including: The defect association topology network is weighted by using a boundary weight dynamic allocation technology to obtain a weighted defect propagation graph, and the weighted defect propagation graph is calculated by using a Ford-Fulkerson maximum flow algorithm to obtain a defect flow bottleneck edge set; Performing a minimum cut set analysis on the defect-associated topology network based on the defect traffic bottleneck edge set to obtain a key defect cut set, and processing the key defect cut set through sensitivity-vulnerability matrix calculation to obtain a key node sequence for defect propagation; The defect propagation key node sequence is converted into the corresponding production process through graph isomorphism mapping technology to obtain a set of candidate points for production link intervention. The production link intervention candidate point set is analyzed and extracted through a multi-criteria decision optimization algorithm to obtain a set of key points for production process quality control.

[0010] Furthermore, the defect-related topology network is analyzed based on the defect traffic bottleneck edge set to obtain a key defect cut set, including: Performing topological sorting preprocessing on the defective flow bottleneck edge set to obtain a defective flow hierarchical directed acyclic graph, and performing phase contraction iterative calculation on the defective flow hierarchical directed acyclic graph to obtain a contraction sequence candidate set; Based on the contraction sequence candidate set, the defect association topology network is decomposed into biconnected components by cutting edges to obtain a defect subgraph segmentation space, and the defect subgraph segmentation space is optimized by Karger-Stein random contraction to obtain a global minimum cutting edge set; Based on the global minimum cut edge set, a Gomory-Hu tree is constructed on the defect association topology network to obtain a cut edge equivalent tree structure, and multi-source minimum cut value extraction is performed on the cut edge equivalent tree structure to obtain a key cut point matrix; The key cut point matrix is eigen-decomposed by a spectral clustering algorithm to obtain a defect cut feature vector set, and the defect cut feature vector set is verified by the maximum flow-minimum cut theorem to obtain a key defect cut set.

[0011] Furthermore, the defect-associated topological network is decomposed into biconnected components based on the contraction sequence candidate set to obtain a defect subgraph segmentation space, including: Performing cut point identification on the contraction sequence candidate set by using the Tarjan depth-first algorithm to obtain a key cut point sequence, and performing biconnectivity calculation on the key cut point sequence to obtain a set of biconnected subgraphs; Performing Hopcroft-Tarjan edge cutting detection on the biconnected subgraph set to obtain an edge cutting candidate sequence, and performing graph cutting cost calculation on the edge cutting candidate sequence to obtain a minimum edge cutting evaluation matrix; Based on the component boundary tracking of the minimum cut edge evaluation matrix, a subgraph boundary description sequence is obtained, and the boundary overlap analysis of the subgraph boundary description sequence is performed to obtain a subgraph segmentation constraint condition set; The defect-associated topological network is spatially decomposed and partitioned based on the subgraph partitioning constraint condition set to obtain a defect subgraph partitioning space.

[0012] Furthermore, the spatial decomposition and partitioning of the defect-related topological network based on the subgraph partitioning constraint set to obtain a defect subgraph partitioning space includes: Performing a Laplacian matrix construction on the subgraph segmentation constraint condition set to obtain a multidimensional feature constraint space, and performing least squares spectral projection on the multidimensional feature constraint space to obtain an orthogonalized feature projection vector group; Based on the orthogonalized feature projection vector group, singular value decomposition is performed on the defect association topology network to obtain a hyperplane cutting candidate set, and the optimal cutting evaluation is performed on the hyperplane cutting candidate set using the Shi-Malik normalized cutting algorithm to obtain a recursive segmentation decision tree; wherein the hyperplane cutting candidate set includes hardware-software boundary sections, component internal sections, and functional module sections; A hierarchical cutting operation is performed on the defect-related topological network based on the recursive segmentation decision tree to obtain a defect subgraph segmentation space.

[0013] The present invention also provides an automated quality control device for batch testing of switches, comprising: The test module is used to perform performance tests on a preset batch of switches to obtain a switch performance test data set; A judgment module, configured to judge whether there is an abnormal switch in the batch of switches based on the switch performance test data set; a tracing module, configured to, if present, locate the fault of the abnormal switch based on the switch performance test data set and obtain a switch defect distribution report; The adjustment module is configured to call the production process of the batch of switches from a database, and optimize and adjust the quality control points of the production process based on the switch defect distribution report to achieve the production of the target batch of switches.

[0014] The present invention also provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any one of the above methods when executing the computer program.

[0015] The present invention also provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of any of the above methods are implemented.

[0016] The present invention provides an automated quality control method for batch testing of switches, comprising the following steps: performing a performance test on a preset batch of switches to obtain a switch performance test data set; determining whether any abnormal switches are present in the batch of switches based on the switch performance test data set; if so, locating the fault of the abnormal switch based on the switch performance test data set to obtain a switch defect distribution report; calling the production process of the batch of switches from a database, and optimizing and adjusting the quality control points of the production process based on the switch defect distribution report to achieve the production of a batch of target switches. This method solves the technical problem that traditional manual testing methods are not only time-consuming and labor-intensive, but also difficult to ensure the quality consistency of each switch. By calling the production process records of the batch of switches and adjusting and optimizing the key quality control points in the production process in combination with the defect distribution report, this method helps to discover and resolve potential problems in the production process. This not only improves overall product quality, but also reduces the generation of defective products at the source, thereby improving production efficiency and reducing production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 1. It is a schematic diagram of the steps of an automated quality control method for batch testing of switches according to an embodiment of the present invention; Figure 2 This is a structural block diagram of an automated quality control device for batch testing of switches according to an embodiment of the present invention; Figure 3It is a schematic block diagram of the structure of a computer device according to an embodiment of the present invention.

[0018] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0020] like Figure 1 As shown, Figure 1 This is a schematic diagram of the steps of an automated quality control method for batch testing of switches in one embodiment of the present invention; An embodiment of the present invention provides an automated quality control method for batch testing of switches, comprising the following steps: Step S1: Perform performance testing on a preset batch of switches to obtain a switch performance test data set.

[0021] Specifically, when implementing the step of "performant testing on a pre-defined batch of switches to generate a switch performance test dataset," it's important to first clarify that the "pre-defined batch of switches" refers to a specific model or batch of switches to be tested. These switches may be from the same production batch or have the same configuration and specifications, facilitating standardized testing standards and procedures. To ensure test effectiveness and accuracy, a test plan is typically designed based on the technical specifications and expected performance indicators of the switch model or batch. For example, in a data center environment, to ensure efficient network equipment operation, performance testing is performed on a batch of newly purchased high-end switches for the core layer. In practice, technicians use professional testing tools and software, such as IxLoad and Spirent TestCenter, to simulate real-world network environments and apply various load conditions to the switches, including but not limited to high concurrent traffic, complex routing table processing, and multicast transmission scenarios, to comprehensively evaluate their performance. Through these tests, the system automatically collects various performance parameters of the switches under different operating conditions, such as throughput, latency, and packet loss rate, to generate a detailed switch performance test dataset. For example, for high-end switches used in the aforementioned data center scenario, testing might simulate thousands of servers simultaneously accessing external resources, observing and recording the switches' response and stability under these extreme conditions. The results of this step not only provide the foundational data for subsequent identification of abnormal switches but also lay a solid foundation for the successful implementation of the entire automated quality control approach. Furthermore, this detailed data provides manufacturers with a deep understanding of the product's actual performance, providing valuable feedback for further product design optimization. Therefore, this step plays a crucial role in the entire automated quality control process.

[0022] Step S2: determining whether there is an abnormal switch in the batch of switches based on the switch performance test data set.

[0023] Specifically, determining whether any of the batched switches are abnormal based on the switch performance test dataset is a key step in the entire automated quality control process. First, the system analyzes the collected switch performance test dataset based on pre-set performance standards and thresholds. These standards typically include, but are not limited to, core metrics such as throughput, latency, and packet loss rate, each with a specific acceptable range. For example, in a data center application, if a high-end switch's throughput under high concurrent traffic falls below expectations or its latency exceeds the permitted range, the device may be considered to have a potential issue. In specific implementation, the system uses an algorithm to automatically compare the actual test results of each switch with pre-set standard values, calculating the degree of deviation for each performance parameter to determine whether a problem exists. If certain performance metrics of a switch significantly deviate from the normal range, the system will flag the device as abnormal. To improve the accuracy of this assessment, the system may also combine historical data and other relevant factors for a comprehensive evaluation. For example, in the aforementioned data center example, suppose a batch of newly purchased high-end switches is used in the core network. After performance testing, the system discovers that one switch exhibits a high packet loss rate when processing complex routing tables, and its latency is significantly higher than other devices in the batch. In this case, the system identifies this switch as an abnormal device. Furthermore, to ensure the reliability of the judgment results, the system can also incorporate machine learning models. By learning from a large amount of historical test data, it can identify more subtle failure modes. For example, performance degradation that only manifests under certain conditions can be identified. These models can help more accurately locate the abnormal device. Once an abnormal switch is identified, the system not only generates a detailed report but also provides the necessary data support for further troubleshooting, allowing for in-depth analysis of the abnormal device and the development of effective repair solutions. In this way, through scientific and rigorous data analysis methods, the overall quality and stability of the batch of switches can be effectively improved, ensuring that every device leaving the factory meets high quality standards.

[0024] Step S3: If yes, locate the fault of the abnormal switch based on the switch performance test data set to obtain a switch defect distribution report.

[0025] Specifically, if an abnormal switch exists, the fault is located based on the switch performance test dataset to generate a switch defect distribution report. This process relies on detailed performance test datasets that include key metrics such as throughput, latency, and packet loss rate for each switch under various load conditions. The system then uses advanced algorithms and data analysis techniques to deeply analyze this data to identify specific parameters that deviate from normal ranges and further determine the possible cause of the fault. For example, in a data center application scenario, if a high-end switch experiences a high packet loss rate when processing a complex routing table and its latency is significantly higher than other devices in the same batch, the system will analyze these abnormal data points in detail. To accurately locate the fault, the system not only compares the current test results with preset standard values but also conducts a comprehensive assessment based on historical data and other relevant factors. This approach allows for a more accurate determination of the specific location and type of fault. For example, in the high-end switch in the aforementioned data center example, after in-depth analysis, the system may determine that the high packet loss rate during peak network traffic hours is caused by a hardware failure or improper software configuration in a specific internal module. Next, the system generates a detailed switch defect distribution report. This report not only lists all detected anomalies but also provides the possible causes and recommended remediation measures for each issue. Furthermore, to improve diagnostic accuracy, the system can employ machine learning models, leveraging extensive historical fault data to identify more subtle failure modes. For example, these models can help pinpoint the source of performance degradation that only manifests under certain conditions. This approach not only allows for rapid identification of specific faulty components or configuration errors but also provides valuable data for subsequent quality control and production process optimization. This information allows manufacturers to quickly take action to repair or replace problematic switches, ensuring that the products ultimately delivered to customers meet the highest quality standards, thereby enhancing customer satisfaction and improving the company's market competitiveness. Throughout the entire process, the system closely integrates the switch performance test dataset, ensuring that every step is well-founded and scientifically sound.

[0026] Step S4: Retrieve the production process of the batch of switches from the database, and optimize and adjust the quality control points of the production process based on the switch defect distribution report to achieve the production of the target batch of switches.

[0027] Specifically, the production process for the batch of switches is retrieved from the database and, based on the switch defect distribution report, quality control points within the production process are optimized and adjusted to achieve the target batch of switches. This process aims to continuously improve manufacturing processes and ensure product quality through data analysis and feedback mechanisms. First, the system extracts all production process information related to the batch of switches from the database, covering all stages from raw material procurement, assembly, testing, to final packaging. For example, in a data center application scenario, if a batch of high-end switches is found to have certain types of defects during performance testing, such as high packet loss rates or excessive latency, the system will automatically retrieve the complete production records for the batch. Next, the system, combined with the detailed analysis results in the switch defect distribution report, identifies the specific production stages or operational steps that may have caused these defects. For example, if analysis reveals that the high packet loss rate of a high-end switch is due to poor soldering quality on a specific component, the system will search the production process data for all steps involved in soldering that component. This approach can pinpoint specific production process steps, such as improperly set operating parameters at a particular welding station or insufficient worker skills. Based on this, the system will optimize and adjust these critical quality control points. This may include modifying process parameters such as welding temperature and time, or strengthening the training of relevant operators, or even introducing more advanced automated production equipment to replace manual operations. For example, in the above case, in order to reduce welding quality issues, the manufacturer may decide to use a higher-precision welding robot and recalibrate the welding temperature and time parameters to ensure the quality consistency of each solder joint. In addition, the system will also generate a detailed optimization recommendation report for reference and implementation by the production management department. Through this continuous feedback and optimization mechanism, not only can the quality problems of the current batch of products be effectively solved, but similar problems can also be prevented from occurring in the future, thereby achieving stable production of high-quality target switches. Throughout the process, the system relies closely on detailed data support to ensure that every adjustment is based on evidence and is scientific and reasonable, thereby improving overall production efficiency and product quality.

[0028] In a specific embodiment, locating the fault of the abnormal switch based on the switch performance test data set to obtain a switch defect distribution report includes: Performing anomaly detection feature extraction on the switch performance test data set to obtain a switch performance anomaly feature vector set, and performing hierarchical clustering analysis on the switch performance anomaly feature vector set to obtain an abnormal switch fault type classification result; Based on the fault type classification result of the abnormal switch, in-depth fault diagnosis is performed on the abnormal switch to obtain a switch hardware-software fault correlation map, and topological analysis is performed on the switch hardware-software fault correlation map to obtain a fault propagation link; Performing root cause location calculation on the abnormal switch based on the fault propagation link to obtain a fault root source probability distribution matrix, and performing Bayesian network inference on the fault root source probability distribution matrix to obtain a switch fault root cause location result; Specifically, based on the switch fault root cause location results, the production records of the batch of switches are retroactively analyzed to obtain a production process defect distribution heat map. Quality bottlenecks are then identified on the production process defect distribution heat map to generate a switch defect distribution report. The production process defect distribution heat map includes chip manufacturing defect distribution and circuit board assembly defect distribution. Specifically, the process of locating the abnormal switch fault based on the switch performance test dataset and generating the switch defect distribution report first involves extracting anomaly detection features from the switch performance test dataset to obtain a set of switch performance anomaly feature vectors. These features are then subjected to hierarchical clustering analysis to classify the abnormal switch fault types. This process utilizes advanced algorithms to extract fault-related features from massive amounts of data, such as abnormal fluctuations in parameters such as throughput, latency, and packet loss rate. Through hierarchical clustering analysis, the system can group switches with similar failure modes together for further analysis. For example, in a data center application scenario, if a batch of high-end switches exhibits poor performance under high concurrent traffic, the system will automatically extract performance data from these devices and, through clustering analysis, identify those exhibiting the same or similar failure modes. Next, based on the fault type classification results for the abnormal switch, the system performs in-depth fault diagnosis on the abnormal switch, generates a hardware-software fault correlation map, and analyzes its topology to identify the fault propagation paths. This step not only helps identify specific hardware or software issues but also reveals the interrelationships between these issues. For example, suppose a high packet loss rate on a high-end switch is caused by a hardware fault in a specific module, which in turn leads to unstable operation of related software modules. The system constructs a hardware-software fault correlation map to illustrate this complex causal relationship and further analyze how the fault propagates within the system. Then, based on the fault propagation paths, the system calculates the root cause of the abnormal switch, generates a probability distribution matrix for the root cause of the fault, and performs Bayesian network inference on this matrix to ultimately determine the root cause of the switch fault. This approach combines statistical and machine learning techniques to accurately identify the root cause of faults in complex systems. For example, through Bayesian network inference, the system can quantify the probability of each potential fault source and propose the most likely solution based on this probability. Finally, based on the switch fault root cause identification results, the production records of the batch of switches are retroactively analyzed to generate a heat map of defect distribution during the production process. This heat map is then used to identify quality bottlenecks, resulting in a switch defect distribution report. This report not only provides detailed information such as chip manufacturing defect distribution and circuit board assembly defect distribution, but also provides manufacturers with clear directions for quality improvement. For example, in the aforementioned data center case, if a high-frequency failure point for a certain switch model is found to be concentrated in a specific chip, the manufacturer can address this issue by adjusting procurement channels or optimizing production processes.The entire process is closely centered around a data-driven methodology, ensuring that each step is based on detailed data analysis and scientific reasoning, thereby achieving efficient and accurate fault location and continuous improvement of quality issues.

[0029] In a specific embodiment, optimizing and adjusting the quality control points of the production process based on the switch defect distribution report to achieve production of target switches in batches includes: Extracting key defect nodes from the switch defect distribution report to obtain a defect-related topology network, and performing minimum cut set analysis on the defect-related topology network to obtain a set of key points for production process quality control; Based on the set of key quality control points of the production process, quantitative parameters of the production process of the batch switches are reconstructed to obtain a production process parameter optimization matrix, and a non-dominated sorting algorithm is performed on the production process parameter optimization matrix to obtain a multi-objective optimization solution set; wherein the production process parameter optimization matrix includes chip manufacturing precision parameters and circuit board soldering temperature control parameters; The multi-objective optimization solution set is solved iteratively by a genetic-particle hybrid algorithm to obtain a production process adjustment strategy sequence; Performing a digital twin simulation of the production process based on the production process adjustment strategy sequence to obtain production process digital twin model response data, and performing quality control point analysis on the production process digital twin model response data to obtain a quality control point optimization configuration scheme; wherein the production process digital twin model response data includes virtual production line throughput, quality consistency index, defect interception rate, and resource utilization efficiency; Based on the quality control point optimization configuration scheme, an adaptive control system is deployed for the production process to obtain an intelligent quality control execution instruction set, and feedback closed-loop verification is performed on the intelligent quality control execution instruction set to obtain production batch target switches.

[0030] Specifically, optimizing and adjusting quality control points in the production process based on the switch defect distribution report to achieve batch production of target switches is a highly complex and data-driven process designed to improve product quality through systematic analysis and optimization. First, the system extracts key defect nodes from the switch defect distribution report, generating a defect-related topology network. Minimum cut set analysis is then performed on this network to determine the set of key quality control points in the production process. This process utilizes the minimum cut set method from graph theory to identify the links that have the greatest impact on overall production quality. For example, in a data center application scenario, if a batch of high-end switches is found to have a high packet loss rate during performance testing, the system extracts all relevant fault nodes from the defect distribution report, such as specific chip manufacturing defects or circuit board soldering issues, and uses minimum cut set analysis to locate the key locations of these defects in the network. Next, based on the set of key quality control points in the production process, the system reconstructs the quantitative parameters of the production process for the batch of switches, generates a production process parameter optimization matrix, and analyzes this matrix using a non-dominated sorting algorithm to obtain a multi-objective optimization solution. This step involves converting various parameters involved in the production process, such as chip manufacturing precision parameters and circuit board soldering temperature control parameters, into quantifiable values and then using a non-dominated sorting algorithm (NSGA) to find the optimal solution set. For example, in the aforementioned example, if analysis reveals that insufficient chip manufacturing precision and improper soldering temperature control are the primary causes of unstable equipment performance, the system constructs an optimization matrix containing multiple parameter combinations based on this information and uses the NSGA algorithm to find the optimal parameter configuration that both improves product performance and reduces costs. The system then iterates this multi-objective optimization solution set using a genetic-particle swarm optimization (GPA) hybrid algorithm to obtain a sequence of production process adjustment strategies. This approach combines the global search capabilities of the genetic algorithm with the local search advantages of the particle swarm optimization (PSO) algorithm, enabling rapid convergence to the optimal solution within a complex solution space. For example, when optimizing chip manufacturing precision and soldering temperature control parameters, the system might simulate the effects of different parameter combinations, gradually approaching the optimal configuration through multiple iterations. Ultimately, the system generates a series of specific production process adjustment strategies, such as adjusting parameters for specific steps in the chip manufacturing process or optimizing the operating parameters of soldering equipment. Then, based on the sequence of production process adjustment strategies, the system performs a digital twin simulation of the production process, generating digital twin model response data for the production process. This data is then analyzed for quality control points to determine an optimized configuration plan for these points. By creating a virtual model of the physical production line, digital twin technology can simulate the effects of various adjustment strategies without impacting actual production.For example, in the aforementioned example, the system can simulate the impact of different chip manufacturing precision and soldering temperature settings on final product quality, collecting data including virtual production line throughput, quality consistency metrics, defect interception rate, and resource utilization efficiency. Through in-depth analysis of this data, the system can propose an optimized quality control point configuration plan to ensure that every switch leaving the factory meets high quality standards. Finally, based on this optimized quality control point configuration plan, the system will implement an adaptive control system deployment for the production process, generate an intelligent quality control execution instruction set, and conduct feedback closed-loop verification on this instruction set to ensure the quality of the target switch production batch. During this stage, the system automatically adjusts the operating parameters of production equipment based on the optimized configuration plan and monitors various production process indicators in real time. For example, in the aforementioned data center application scenario, the system can automatically adjust the operating parameters of chip manufacturing and soldering equipment based on the optimized parameter settings, and use sensors to monitor various production process indicators such as temperature and pressure in real time. If any deviation from the set values is detected, the system will immediately issue adjustment instructions to ensure that each step is carried out under optimal conditions. Furthermore, the system will continuously evaluate and optimize the production process through a feedback closed-loop verification mechanism to ensure that each switch meets high quality standards. Throughout the entire process, the system closely adheres to a data-driven methodology. From the analysis of defect distribution reports to the optimization and adjustment of production processes, and finally to the deployment of quality control, each step relies on detailed data support and scientific reasoning. Through this systematic optimization process, not only can the quality issues of the current batch of products be effectively resolved, but it can also provide valuable experience and data accumulation for future production, thereby continuously improving product quality and production efficiency. For example, in the application scenario of the above-mentioned data center, by continuously optimizing chip manufacturing and welding processes, manufacturers can not only significantly reduce the failure rate of high-end switches, but also significantly improve their market competitiveness and meet customer demand for high-performance network equipment. In short, this production process improvement method based on data analysis and optimization provides companies with powerful tools to help them achieve their high-quality and high-efficiency production goals.

[0031] In a specific embodiment, performing minimum cut set analysis on the defect association topology network to obtain a set of key points for quality control of the production process includes: The defect association topology network is weighted by using a boundary weight dynamic allocation technology to obtain a weighted defect propagation graph, and the weighted defect propagation graph is calculated by using a Ford-Fulkerson maximum flow algorithm to obtain a defect flow bottleneck edge set; Performing a minimum cut set analysis on the defect-associated topology network based on the defect traffic bottleneck edge set to obtain a key defect cut set, and processing the key defect cut set through sensitivity-vulnerability matrix calculation to obtain a key node sequence for defect propagation; The defect propagation key node sequence is converted into the corresponding production process through graph isomorphism mapping technology to obtain a set of candidate points for production link intervention. The production link intervention candidate point set is analyzed and extracted through a multi-criteria decision optimization algorithm to obtain a set of key points for production process quality control.

[0032] Specifically, the process of performing minimum cut set analysis on the defect-related topology network to determine the set of critical quality control points for the production process is a highly complex, data-driven optimization step. First, the system weights the defect-related topology network using dynamic boundary weight allocation technology to generate a weighted defect propagation graph. This graph is then calculated using the Ford-Fulkerson maximum flow algorithm to determine the defect traffic bottleneck edge set. The core of this process lies in using dynamic boundary weight allocation technology to assign different weights to each node and edge, reflecting their importance in defect propagation. For example, in a data center application scenario, if a batch of high-end switches is found to have high packet loss rates during performance testing, the system will construct a topology network containing all relevant faulty nodes and connections based on the defect distribution report. Using dynamic allocation technology, the system can assign corresponding weights to each node (e.g., chip manufacturing, welding process, etc.) and its connections based on historical data and current test results, forming a weighted defect propagation graph. Next, the system uses the Ford-Fulkerson maximum flow algorithm to calculate the defect traffic bottleneck edge set within this weighted defect propagation graph. This method identifies critical edges that restrict overall flow by finding the maximum flow path from the source node to the destination node, known as the defect flow bottleneck edge set. For example, in the aforementioned example, suppose the system, through a maximum flow algorithm, discovers that a specific soldering process is one of the primary bottlenecks leading to high packet loss rates, as this process has the highest defect propagation efficiency and the widest impact. This method allows the system to precisely locate the links that have the greatest impact on overall product quality. Based on this defect flow bottleneck edge set, the system performs a minimum cut set analysis on the defect-associated topological network to obtain a critical defect cut set. This critical defect cut set is then processed using a sensitivity-vulnerability matrix to generate a sequence of key nodes for defect propagation. Minimal cut set analysis is a method used to identify the weakest links in a network, helping to locate critical components whose failure could cause the entire system to crash. In the aforementioned example, suppose the system, through minimum cut set analysis, discovers that certain chip manufacturing processes and soldering temperature control are the primary drivers of high packet loss rates. The system then applies a sensitivity-vulnerability matrix to evaluate the sensitivity and vulnerability of each node in the critical defect cut set under different conditions, thereby generating a ranked sequence of key nodes for defect propagation. For example, through this calculation, the system can determine which nodes are most prone to failure under specific conditions and prioritize their improvement. Subsequently, the system uses graph isomorphism mapping technology to transform the sequence of key defect propagation nodes into corresponding production process nodes, generating a set of candidate production process intervention points. This set of candidate production process intervention points is then analyzed and extracted using a multi-criteria decision-making optimization algorithm to obtain a set of key production process quality control points.Graph isomorphism mapping technology matches abstract defect propagation networks with actual production processes, helping to identify specific production links requiring intervention. For example, in the aforementioned data center application scenario, the system might discover that a specific process step in chip manufacturing and the operating parameter settings of welding equipment are the primary causes of high packet loss rates. Using graph isomorphism mapping technology, the system can map these abstract key defect propagation nodes to specific production links, such as a specific process step in chip manufacturing or a specific operating parameter setting for welding equipment. The system then applies a multi-criteria decision-making optimization algorithm, comprehensively considering multiple factors (such as cost, efficiency, and quality), to analyze and extract candidate intervention points in these production links, ultimately determining the set of quality control key points with the greatest optimization potential. Throughout this process, the system relies not only on complex algorithms and technical means, but also on extensive data analysis and scientific reasoning. For example, in the aforementioned data center application scenario, using dynamic boundary weight assignment technology and the Ford-Fulkerson maximum flow algorithm, the system can accurately identify bottlenecks that limit overall product quality. Using minimal cut set analysis and sensitivity-vulnerability matrix calculation, the system can further refine the specific locations and impact of these bottlenecks. Finally, using graph isomorphism mapping technology and a multi-criteria decision-making optimization algorithm, the system can translate these theoretical optimization suggestions into specific production process adjustment plans. This not only helps resolve quality issues in current batches of products but also provides valuable experience and data for future production, thereby continuously improving product quality and production efficiency. For example, in practice, suppose a manufacturer discovers that a batch of high-end switches frequently experience high packet loss rates during performance testing. Using the aforementioned method, the system can first construct a detailed defect correlation topology network and assign weights to it using dynamic assignment technology to form a weighted defect propagation graph. Then, using the Ford-Fulkerson maximum flow algorithm, the system can identify the most critical defect propagation paths and bottleneck edge sets. Then, through minimum cut set analysis and sensitivity-vulnerability matrix calculation, the system can further refine the specific location and impact of these bottlenecks, generating an ordered sequence of key nodes for defect propagation. Finally, through graph isomorphism mapping technology and multi-criteria decision-making optimization algorithms, the system can transform these theoretical optimization suggestions into specific production intervention strategies, such as adjusting certain parameters in the chip manufacturing process or optimizing the operating parameter settings of welding equipment. In this way, manufacturers can not only effectively solve the quality problems of the current batch of products, but also provide valuable data support and optimization experience for future production, ensuring that every switch leaving the factory meets high quality standards. In short, this systematic optimization process provides companies with powerful tools to help them achieve high-quality and efficient production goals.

[0033] In a specific embodiment, the defect-related topology network is analyzed based on the defect traffic bottleneck edge set to obtain a key defect cut set, including: Performing topological sorting preprocessing on the defective flow bottleneck edge set to obtain a defective flow hierarchical directed acyclic graph, and performing phase contraction iterative calculation on the defective flow hierarchical directed acyclic graph to obtain a contraction sequence candidate set; Based on the contraction sequence candidate set, the defect association topology network is decomposed into biconnected components by cutting edges to obtain a defect subgraph segmentation space, and the defect subgraph segmentation space is optimized by Karger-Stein random contraction to obtain a global minimum cutting edge set; Based on the global minimum cut edge set, a Gomory-Hu tree is constructed on the defect association topology network to obtain a cut edge equivalent tree structure, and multi-source minimum cut value extraction is performed on the cut edge equivalent tree structure to obtain a key cut point matrix; The key cut point matrix is eigen-decomposed by a spectral clustering algorithm to obtain a defect cut feature vector set, and the defect cut feature vector set is verified by the maximum flow-minimum cut theorem to obtain a key defect cut set.

[0034] Specifically, analyzing the defect-associated topological network based on the defect traffic bottleneck edge set to determine the critical defect cut set is a highly complex, data-driven optimization step. First, the system preprocesses the defect traffic bottleneck edge set by topological sorting to generate a hierarchical directed acyclic graph (DAG) of defect flows. This graph is then iteratively computed using phase contraction to obtain a candidate contraction sequence. The core of this process is to organize the defect propagation path through topological sorting, making subsequent analysis more intuitive and efficient. For example, in a data center application scenario, suppose a batch of high-end switches is found to have high packet loss rates during performance testing. Based on the defect distribution report, the system constructs a topological network containing all relevant faulty nodes and their connections. Using topological sorting, the system arranges these nodes according to their order in the defect propagation path, forming a hierarchical directed acyclic graph (DAG). Next, the system applies iterative phase contraction to gradually merge nodes and edges with similar characteristics, generating a series of candidate contraction sequences. Next, based on the candidate set of contraction sequences, the system performs a cut-edge biconnected component decomposition on the defect-associated topological network to obtain a defect subgraph partition space. This space is then optimized using Karger-Stein random contraction to determine the global minimum set of cut edges. Cut-edge biconnected component decomposition is a method used to identify the most vulnerable links in a network, helping to identify critical components whose failure could cause the entire system to crash. In the above example, suppose the system, through cut-edge biconnected component decomposition, discovers that certain specific chip manufacturing processes and soldering temperature control are the primary causes of high packet loss rates. The system then applies the Karger-Stein random contraction optimization algorithm, performing multiple random contraction operations to find the global minimum set of cut edges, specifically the critical links that have the greatest impact on overall product quality. For example, this optimization method can identify which edges play the most critical role in the network and prioritize their improvement. Subsequently, based on the global minimum set of cut edges, the system constructs a Gomory-Hu tree on the defect-associated topological network to generate a cut-edge equivalent tree structure. This structure is then subjected to multi-source minimum cut value extraction to obtain a critical cut point matrix. The Gomory-Hu tree is a tree structure used to represent the minimum cut values between all pairs of nodes in a network. It can help identify the most critical cut points in the network. In the above example, it is assumed that the system constructs a tree structure containing all critical cut points using the Gomory-Hu tree. Next, the system applies a multi-source minimum cut value extraction algorithm to extract the minimum cut value between each node pair from this tree structure, generating a critical cut point matrix. For example, this method can accurately identify the cut points that play the most important role in the network, providing a basis for subsequent optimization.The system then uses a spectral clustering algorithm to perform eigendecomposition on the key cut point matrix, generating a set of defect cut feature vectors, and verifies the vector set using the maximum flow-minimum cut theorem to obtain a set of key defect cuts. The spectral clustering algorithm is a clustering method based on graph theory and linear algebra that can simplify complex network structures into a form that is easy to analyze. In the above case, it is assumed that the system uses a spectral clustering algorithm to perform eigendecomposition on the key cut point matrix and obtains a set of defect cut feature vectors. The system then applies the maximum flow-minimum cut theorem to verify the validity of these feature vectors to ensure that each cut point is the optimal solution. For example, through this method, the system can further refine the cut points that play a key role in the network and ultimately generate a set containing all key defect cut points. Throughout the entire process, the system not only relies on complex algorithms and technical means, but also requires a large amount of data analysis and scientific reasoning. For example, in the aforementioned data center application scenario, the system uses topological sorting techniques and iterative phase contraction computation to organize complex defect propagation paths into a hierarchical directed acyclic graph (DAG). Through cut-edge biconnected component decomposition and Karger-Stein random contraction optimization, the system identifies the key links that have the greatest impact on overall product quality. Through Gomory-Hu tree construction and multi-source minimum cut value extraction, the system accurately locates the cut points that play the most important roles in the network. Finally, through spectral clustering algorithms and maximum flow-minimum cut theorem verification, the system further refines and verifies these key defect cut points, ensuring that each optimization recommendation is scientifically sound. Specifically, in practice, suppose a manufacturer discovers that a batch of high-end switches frequently experience high packet loss rates during performance testing. Using the aforementioned method, the system first performs topological sorting preprocessing on the defective traffic bottleneck edge set to generate a hierarchical DAG of the defective traffic. Next, the system applies iterative phase contraction computation to gradually merge nodes and edges with similar characteristics, generating a series of candidate contraction sequences. The system then decomposes these candidate contraction sequence sets into biconnected components, identifying the key links that have the greatest impact on overall product quality and finding the global minimum cut edge set using the Karger-Stein randomized contraction optimization algorithm. Next, the system constructs a Gomory-Hu tree based on these global minimum cut edge sets, extracts multi-source minimum cut values, and generates a critical cut point matrix. Finally, the system performs eigendecomposition on the critical cut point matrix using a spectral clustering algorithm and applies the maximum flow-minimum cut theorem for verification to generate a critical defect cut set. In this way, manufacturers can not only effectively address quality issues in the current batch of products, but also provide valuable data support and optimization experience for future production.For example, in the case described above, through detailed analysis and optimization processes, the manufacturer was able to pinpoint the specific production steps that led to high packet loss rates and implement corresponding improvement measures, such as adjusting certain parameters in the chip manufacturing process or optimizing the operating parameters of the soldering equipment. This not only helps improve the overall quality of the current batch of switches but also provides important reference data for future production, ensuring that every switch leaving the factory meets high quality standards. In short, this systematic optimization process provides companies with powerful tools to help them achieve their high-quality and efficient production goals.

[0035] In a specific embodiment, the step of performing edge-cutting biconnected component decomposition on the defect-associated topological network based on the contraction sequence candidate set to obtain a defect subgraph segmentation space includes: Performing cut point identification on the contraction sequence candidate set by using the Tarjan depth-first algorithm to obtain a key cut point sequence, and performing biconnectivity calculation on the key cut point sequence to obtain a set of biconnected subgraphs; Performing Hopcroft-Tarjan edge cutting detection on the biconnected subgraph set to obtain an edge cutting candidate sequence, and performing graph cutting cost calculation on the edge cutting candidate sequence to obtain a minimum edge cutting evaluation matrix; Based on the component boundary tracking of the minimum cut edge evaluation matrix, a subgraph boundary description sequence is obtained, and the boundary overlap analysis of the subgraph boundary description sequence is performed to obtain a subgraph segmentation constraint condition set; The defect-associated topological network is spatially decomposed and partitioned based on the subgraph partitioning constraint condition set to obtain a defect subgraph partitioning space.

[0036] Specifically, the process of performing cut-edge biconnected component decomposition of the defect-associated topological network based on the contraction sequence candidate set to obtain a defect subgraph segmentation space is a complex and systematic optimization step. First, the system uses the Tarjan depth-first algorithm to identify cut points in the contraction sequence candidate set, generating a critical cut point sequence. The biconnectivity of this sequence is then calculated to obtain a set of biconnected subgraphs. The core of this process lies in leveraging the efficiency of the Tarjan algorithm to identify critical cut points in the network. If these nodes fail, the entire network will be partitioned into multiple disconnected parts. For example, in a data center application scenario, suppose a batch of high-end switches is found to have a high packet loss rate during performance testing. Based on the defect distribution report, the system constructs a topological network containing all relevant faulty nodes and their connections. Using the Tarjan depth-first algorithm, the system can identify critical cut points in the network and generate a critical cut point sequence. Next, the system performs biconnectivity calculations on these cut points to determine the importance of each cut point in the network, thereby forming a set of biconnected subgraphs. Next, the system performs Hopcroft-Tarjan edge detection on the biconnected subgraph set, generating a sequence of candidate edges. It then calculates graph cut costs on this sequence to obtain a minimum edge cut evaluation matrix. The Hopcroft-Tarjan algorithm is an efficient edge cut detection method that helps identify the most vulnerable edges in a network—those edges whose removal would result in the entire network being split into multiple components. In the above example, suppose the system uses the Hopcroft-Tarjan algorithm to identify certain chip manufacturing processes and soldering temperature control as the primary causes of high packet loss rates. The system then performs graph cut cost calculations on these candidate edge cut sequences, assessing the importance and impact of each edge in the network and generating a minimum edge cut evaluation matrix. For example, this method can determine which edges play the most critical role in the network, providing a basis for subsequent optimization. The system then performs component boundary tracing based on the minimum edge cut evaluation matrix, generating a sequence of subgraph boundary descriptions. This sequence is then analyzed for boundary overlap to obtain a set of subgraph partitioning constraints. Component boundary tracking technology helps identify critical boundary nodes and edges in the network by analyzing the boundary relationships between subgraphs. In the above example, assume that the system uses component boundary tracking technology to identify the critical locations of certain process steps in the network. The system then performs boundary overlap analysis on these subgraph boundary description sequences, evaluates the degree of overlap between the subgraphs, and generates a set of subgraph segmentation constraints. For example, this method can further refine the boundary nodes and edges that play a critical role in the network, ensuring that each optimization suggestion is scientific and reasonable.Finally, based on the subgraph segmentation constraint set, the system will spatially decompose and divide the defect-associated topological network to generate a defect subgraph segmentation space. This process aims to divide the complex defect propagation network into several relatively independent subgraphs to facilitate subsequent detailed analysis and optimization. For example, in the application scenario of the above-mentioned data center, it is assumed that the system identifies the specific production links that lead to high packet loss rates through detailed analysis and optimization processes, and divides them into several relatively independent subgraphs. Specifically, the system will spatially decompose and divide the entire defect-associated topological network according to the subgraph segmentation constraint set to generate a series of defect subgraph segmentation spaces. Each subgraph represents a specific production link or process step, which is convenient for subsequent targeted improvements. Throughout the process, the system not only relies on complex algorithms and technical means, but also requires a large amount of data analysis and scientific reasoning. For example, in the aforementioned data center application scenario, the system uses the Tarjan depth-first algorithm to identify critical network cut points. Using Hopcroft-Tarjan cut edge detection and graph cut cost calculation, the system identifies critical edges that have the greatest impact on overall product quality. Component boundary tracing and boundary overlap analysis further refine the critical boundary nodes and edges within the network. Finally, using a set of subgraph partitioning constraints, the system can partition a complex defect propagation network into several relatively independent subgraphs, providing a foundation for subsequent detailed analysis and optimization. Specifically, in practice, suppose a manufacturer discovers that a batch of high-end switches frequently experience high packet loss rates during performance testing. Using the aforementioned method, the system first applies the Tarjan depth-first algorithm to the contraction sequence candidate set, identifying critical network cut points and generating a sequence of key cut points. The system then calculates the biconnectivity of these cut points to determine the importance of each cut point within the network, forming a set of biconnected subgraphs. The system then performs Hopcroft-Tarjan edge detection on these sets of biconnected subgraphs, identifies the critical edges that have the greatest impact on overall product quality, and generates a sequence of candidate edge cuts. Next, the system performs graph cut cost calculations on these candidate edge cuts, evaluates the importance and influence of each edge in the network, and generates a minimum edge cut evaluation matrix. The system then performs component boundary tracking based on this matrix, generates a subgraph boundary description sequence, performs boundary overlap analysis on it, and generates a set of subgraph segmentation constraints. Finally, based on these sets of constraints, the system performs spatial decomposition and partitioning on the entire defect association topology network to generate a defect subgraph segmentation space. In this way, manufacturers can not only effectively solve quality problems in the current batch of products, but also provide valuable data support and optimization experience for future production.For example, in the case described above, through detailed analysis and optimization processes, the manufacturer was able to pinpoint the specific production steps that led to high packet loss rates and implement corresponding improvement measures, such as adjusting certain parameters in the chip manufacturing process or optimizing the operating parameters of the soldering equipment. This not only helps improve the overall quality of the current batch of switches but also provides important reference data for future production, ensuring that every switch leaving the factory meets high quality standards. In short, this systematic optimization process provides companies with powerful tools to help them achieve their high-quality and efficient production goals.

[0037] In a specific embodiment, the spatial decomposition and partitioning of the defect-related topological network based on the subgraph partitioning constraint set to obtain a defect subgraph partitioning space includes: Performing a Laplacian matrix construction on the subgraph segmentation constraint condition set to obtain a multidimensional feature constraint space, and performing least squares spectral projection on the multidimensional feature constraint space to obtain an orthogonalized feature projection vector group; Based on the orthogonalized feature projection vector group, singular value decomposition is performed on the defect association topology network to obtain a hyperplane cutting candidate set, and the optimal cutting evaluation is performed on the hyperplane cutting candidate set using the Shi-Malik normalized cutting algorithm to obtain a recursive segmentation decision tree; wherein the hyperplane cutting candidate set includes hardware-software boundary sections, component internal sections, and functional module sections; A hierarchical cutting operation is performed on the defect-related topological network based on the recursive segmentation decision tree to obtain a defect subgraph segmentation space.

[0038] Specifically, the process of spatially decomposing and partitioning the defect-associated topological network based on the subgraph partitioning constraint set to obtain the defect subgraph partitioning space is a highly complex and systematic optimization step. First, the system constructs a Laplacian matrix on the subgraph partitioning constraint set to generate a multidimensional feature constraint space. This space is then subjected to least-squares spectral projection to obtain a set of orthogonalized feature projection vectors. The core of this process lies in utilizing Laplacian matrices and spectral projection techniques to transform complex constraints into a multidimensional feature space that is easily analyzed. For example, in a data center application scenario, suppose a batch of high-end switches is found to have high packet loss rates during performance testing. Based on the defect distribution report, the system constructs a topological network containing all relevant faulty nodes and their connections. Using Laplacian matrix construction, the system transforms these constraints into a mathematical model, forming a multidimensional feature constraint space. Next, the system performs least-squares spectral projection on this multidimensional feature constraint space, mapping the data into a new coordinate system and generating a set of orthogonalized feature projection vectors for subsequent analysis. Next, based on the orthogonalized feature projection vector set, the system performs singular value decomposition on the defect-related topological network to generate a set of hyperplane cut candidates. The Shi-Malik normalized cut algorithm is then used to evaluate the optimal cuts within these hyperplane cut candidates, resulting in a recursive partitioning decision tree. Singular value decomposition (SVD) is a powerful data analysis tool that can decompose complex network structures into several simpler substructures. In the above example, assume that the system uses singular value decomposition to identify key intersections at specific hardware-software boundaries, within components, and between functional modules. The system then applies the Shi-Malik normalized cut algorithm to evaluate each possible cut solution, identify the optimal cut path, and generate a recursive partitioning decision tree. For example, this method can determine which cut paths play the most critical role in the network, providing a basis for subsequent optimization. Subsequently, based on the recursive partitioning decision tree, the system performs hierarchical partitioning operations on the defect-related topological network to generate a defect subgraph segmentation space. This process aims to recursively refine each component of the network, ultimately dividing it into several relatively independent subgraphs. For example, in the aforementioned data center application scenario, assume that the system, through detailed analysis and optimization processes, identifies the specific production links that lead to high packet loss rates and divides them into several relatively independent subgraphs. Specifically, the system performs hierarchical segmentation operations on the entire defect-related topology network based on a recursive partitioning decision tree, generating a series of defect subgraph segmentation spaces. Each subgraph represents a specific production link or process step, facilitating subsequent targeted improvements. Throughout this process, the system relies not only on complex algorithms and technical means, but also on extensive data analysis and scientific reasoning.For example, in the aforementioned data center application scenario, the system transforms complex constraints into an easily analyzable multidimensional feature space through Laplacian matrix construction and least squares spectral projection. Using singular value decomposition and the Shi-Malik normalized cut algorithm, the system identifies the critical aspects that have the greatest impact on overall product quality. Finally, through a recursive partitioning decision tree, the system can divide the complex defect propagation network into several relatively independent subgraphs, providing a foundation for subsequent detailed analysis and optimization. Specifically, in practice, suppose a manufacturer discovers that a batch of high-end switches frequently experience high packet loss rates during performance testing. Using the aforementioned method, the system first constructs a Laplacian matrix for the subgraph partitioning constraint set to generate a multidimensional feature constraint space. Next, the system performs least squares spectral projection on this multidimensional feature constraint space, mapping the data into a new coordinate system and generating a set of orthogonalized feature projection vectors. The system then performs singular value decomposition on these orthogonalized feature projection vectors to identify the most vulnerable critical aspects in the network, such as those at the hardware-software boundary, within components, and between functional modules, generating a set of candidate hyperplane cuts. Next, the system applies the Shi-Malik normalized cutting algorithm to evaluate each possible cutting path, identify the optimal cutting solution, and generate a recursive segmentation decision tree. This decision tree not only includes multiple possible cutting paths but also provides detailed evaluation results for each path, ensuring that each cutting recommendation is scientifically sound. The system then performs hierarchical segmentation operations on the entire defect-related topology network based on this recursive segmentation decision tree. For example, in the above example, the system might first perform a preliminary segmentation of the entire network along the hardware-software boundary, then further segment the network into functional units within each hardware or software module, gradually refining the network until it reaches the finest-grained subgraph. Each subgraph represents a specific production link or process step, such as a specific process step in chip manufacturing or the operating parameter settings of soldering equipment. In this way, the system can accurately identify key nodes and edges in the network, ensuring that each optimization recommendation can be directly applied to the actual production process. Through this systematic optimization process, manufacturers can not only effectively address quality issues in current product batches but also provide valuable data support and optimization experience for future production. For example, in the case described above, through detailed analysis and optimization processes, the manufacturer was able to pinpoint the specific production steps that led to high packet loss rates and implement corresponding improvement measures, such as adjusting certain parameters in the chip manufacturing process or optimizing the operating parameters of the soldering equipment. This not only helps improve the overall quality of the current batch of switches but also provides important reference data for future production, ensuring that every switch leaving the factory meets high quality standards. In short, this systematic optimization process provides companies with powerful tools to help them achieve their high-quality and efficient production goals.

[0039] The above describes the automated quality control method for batch testing of switches in an embodiment of the present invention. The following describes the automated quality control device for batch testing of switches in an embodiment of the present invention. Figure 2 An embodiment of an automated quality control device for batch testing of switches according to the present invention includes: The testing module 21 is used to perform performance testing on a preset batch of switches to obtain a switch performance test data set; A judgment module 22 is configured to judge whether there is an abnormal switch in the batch of switches based on the switch performance test data set; a locating module 23 for locating the fault of the abnormal switch based on the switch performance test data set, if any, to obtain a switch defect distribution report; The adjustment module 24 is configured to retrieve the production process of the batch of switches from a database, and optimize and adjust the quality control points of the production process based on the switch defect distribution report to produce the target batch of switches.

[0040] In this embodiment, for the specific implementation of each unit in the above device embodiment, please refer to the above method embodiment, which will not be repeated here.

[0041] Reference Figure 3 The embodiment of the present invention further provides a computer device, the internal structure of which can be as follows Figure 3 As shown. The computer device includes a processor, memory, display screen, input device, network interface and database connected via a system bus. The processor of the computer design is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The database of the computer device is used to store the corresponding data in this embodiment. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, the above method is implemented.

[0042] Those skilled in the art will understand that Figure 3 The structure shown in the figure is merely a block diagram of a portion of the structure related to the solution of the present invention and does not constitute a limitation on the computer device to which the solution of the present invention is applied.

[0043] An embodiment of the present invention further provides a computer-readable storage medium having a computer program stored thereon, which implements the above-described method when executed by a processor. It is understood that the computer-readable storage medium in this embodiment can be a volatile readable storage medium or a non-volatile readable storage medium.

[0044] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing the relevant hardware using a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the above-described method embodiments. Any reference to memory, storage, database, or other media provided herein and used in the embodiments may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double-speed SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct RAMbus dynamic RAM (DRDRAM), and RAMbus dynamic RAM.

[0045] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, apparatus, article, or method comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, apparatus, article, or method. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, apparatus, article, or method comprising the element.

[0046] The above description is only a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention description and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. An automated quality control method for batch testing of switches, characterized in that: The following steps are involved: Perform performance testing on a preset batch of switches to obtain a switch performance test data set; Determining whether there is an abnormal switch in the batch of switches based on the switch performance test data set; If so, locating the fault of the abnormal switch based on the switch performance test data set to obtain a switch defect distribution report; The production process of the batch of switches is called from the database, and the quality control points of the production process are optimized and adjusted based on the switch defect distribution report to achieve the production of the target batch of switches.

2. The automated quality control method for batch testing of switches according to claim 1, characterized in that: The performing fault location on the abnormal switch based on the switch performance test data set to obtain a switch defect distribution report includes: Performing anomaly detection feature extraction on the switch performance test data set to obtain a switch performance anomaly feature vector set, and performing hierarchical clustering analysis on the switch performance anomaly feature vector set to obtain an abnormal switch fault type classification result; Based on the fault type classification result of the abnormal switch, in-depth fault diagnosis is performed on the abnormal switch to obtain a switch hardware-software fault correlation map, and topological analysis is performed on the switch hardware-software fault correlation map to obtain a fault propagation link; Performing root cause location calculation on the abnormal switch based on the fault propagation link to obtain a fault root source probability distribution matrix, and performing Bayesian network inference on the fault root source probability distribution matrix to obtain a switch fault root cause location result; Based on the switch fault root cause location results, the production records of the batch of switches are retroactively analyzed to obtain a production process defect distribution heat map, and quality bottlenecks are identified on the production process defect distribution heat map to obtain a switch defect distribution report; wherein, the production process defect distribution heat map includes chip manufacturing defect distribution and circuit board assembly defect distribution.

3. The automated quality control method for batch testing of switches according to claim 1, characterized in that: The optimizing and adjusting the quality control points of the production process based on the switch defect distribution report to achieve production of target switches in batches includes: Extracting key defect nodes from the switch defect distribution report to obtain a defect-related topology network, and performing minimum cut set analysis on the defect-related topology network to obtain a set of key points for production process quality control; Based on the set of key quality control points of the production process, quantitative parameters of the production process of the batch switches are reconstructed to obtain a production process parameter optimization matrix, and a non-dominated sorting algorithm is performed on the production process parameter optimization matrix to obtain a multi-objective optimization solution set; wherein the production process parameter optimization matrix includes chip manufacturing precision parameters and circuit board soldering temperature control parameters; The multi-objective optimization solution set is solved iteratively by a genetic-particle hybrid algorithm to obtain a production process adjustment strategy sequence; Performing a digital twin simulation of the production process based on the production process adjustment strategy sequence to obtain production process digital twin model response data, and performing quality control point analysis on the production process digital twin model response data to obtain a quality control point optimization configuration scheme; wherein the production process digital twin model response data includes virtual production line throughput, quality consistency index, defect interception rate, and resource utilization efficiency; Based on the quality control point optimization configuration scheme, an adaptive control system is deployed for the production process to obtain an intelligent quality control execution instruction set, and feedback closed-loop verification is performed on the intelligent quality control execution instruction set to obtain production batch target switches.

4. The automated quality control method for batch testing of switches according to claim 3, characterized in that: The minimum cut set analysis is performed on the defect association topology network to obtain a set of key points for quality control of the production process, including: The defect association topology network is weighted by using a boundary weight dynamic allocation technology to obtain a weighted defect propagation graph, and the weighted defect propagation graph is calculated by using a Ford-Fulkerson maximum flow algorithm to obtain a defect flow bottleneck edge set; Performing a minimum cut set analysis on the defect-associated topology network based on the defect traffic bottleneck edge set to obtain a key defect cut set, and processing the key defect cut set through sensitivity-vulnerability matrix calculation to obtain a key node sequence for defect propagation; The defect propagation key node sequence is converted into the corresponding production process through graph isomorphism mapping technology to obtain a set of candidate points for production link intervention. The production link intervention candidate point set is analyzed and extracted through a multi-criteria decision optimization algorithm to obtain a set of key points for production process quality control.

5. The automated quality control method for batch testing of switches according to claim 4, characterized in that: The defect-related topology network is analyzed based on the defect traffic bottleneck edge set to obtain a key defect cut set, including: Performing topological sorting preprocessing on the defective flow bottleneck edge set to obtain a defective flow hierarchical directed acyclic graph, and performing phase contraction iterative calculation on the defective flow hierarchical directed acyclic graph to obtain a contraction sequence candidate set; Based on the contraction sequence candidate set, the defect association topology network is decomposed into biconnected components by cutting edges to obtain a defect subgraph segmentation space, and the defect subgraph segmentation space is optimized by Karger-Stein random contraction to obtain a global minimum cutting edge set; Based on the global minimum cut edge set, a Gomory-Hu tree is constructed on the defect association topology network to obtain a cut edge equivalent tree structure, and multi-source minimum cut value extraction is performed on the cut edge equivalent tree structure to obtain a key cut point matrix; The key cut point matrix is eigen-decomposed by a spectral clustering algorithm to obtain a defect cut feature vector set, and the defect cut feature vector set is verified by the maximum flow-minimum cut theorem to obtain a key defect cut set.

6. The automated quality control method for batch testing of switches according to claim 5, characterized in that: The step of performing edge-cutting biconnected component decomposition on the defect-associated topological network based on the contraction sequence candidate set to obtain a defect subgraph segmentation space includes: Performing cut point identification on the contraction sequence candidate set by using the Tarjan depth-first algorithm to obtain a key cut point sequence, and performing biconnectivity calculation on the key cut point sequence to obtain a set of biconnected subgraphs; Performing Hopcroft-Tarjan edge cutting detection on the biconnected subgraph set to obtain an edge cutting candidate sequence, and performing graph cutting cost calculation on the edge cutting candidate sequence to obtain a minimum edge cutting evaluation matrix; Based on the component boundary tracking of the minimum cut edge evaluation matrix, a subgraph boundary description sequence is obtained, and the boundary overlap analysis of the subgraph boundary description sequence is performed to obtain a subgraph segmentation constraint condition set; The defect-associated topological network is spatially decomposed and partitioned based on the subgraph partitioning constraint condition set to obtain a defect subgraph partitioning space.

7. The automated quality control method for batch testing of switches according to claim 6, characterized in that: The spatial decomposition and partitioning of the defect-related topological network based on the subgraph partitioning constraint condition set to obtain a defect subgraph partitioning space includes: Performing a Laplacian matrix construction on the subgraph segmentation constraint condition set to obtain a multidimensional feature constraint space, and performing least squares spectral projection on the multidimensional feature constraint space to obtain an orthogonalized feature projection vector group; Based on the orthogonalized feature projection vector group, singular value decomposition is performed on the defect association topology network to obtain a hyperplane cutting candidate set, and the optimal cutting evaluation is performed on the hyperplane cutting candidate set using the Shi-Malik normalized cutting algorithm to obtain a recursive segmentation decision tree; wherein the hyperplane cutting candidate set includes hardware-software boundary sections, component internal sections, and functional module sections; A hierarchical cutting operation is performed on the defect-related topological network based on the recursive segmentation decision tree to obtain a defect subgraph segmentation space.

8. An automated quality control device for batch testing of switches, characterized in that: include: The test module is used to perform performance tests on a preset batch of switches to obtain a switch performance test data set; A judgment module, configured to judge whether there is an abnormal switch in the batch of switches based on the switch performance test data set; a tracing module, configured to, if present, locate the fault of the abnormal switch based on the switch performance test data set and obtain a switch defect distribution report; The adjustment module is configured to call the production process of the batch of switches from a database, and optimize and adjust the quality control points of the production process based on the switch defect distribution report to achieve the production of the target batch of switches.

9. A computer device comprising a memory and a processor, wherein a computer program is stored in the memory, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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