Automatic test system and method for anti-interference capability of IIC (inter-integrated circuit) bus

Abstract

The invention discloses an automatic test system and method for the anti-interference capability of an IIC bus, and the method comprises the steps: simulating the behavior of a main control end through a programmable MCU, and dynamically reconstructing a composite interference scene including Start / Stop condition abnormality, address bit redundancy / loss, data bit sequence distortion and the like; and meanwhile, a hardware feedback loop is combined to monitor the response of the slave equipment in real time, so that the full-closed-loop test of interference injection-protocol analysis-error detection is realized. Compared with a traditional scheme, the system can accurately reproduce typical interference models such as bus competition, time sequence jitter and level drift, batch execution and quantitative evaluation of multi-dimensional test cases are achieved through an automatic script engine, and the test efficiency and the result credibility are remarkably improved.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic equipment communication testing, and in particular to an automatic testing system and method for the anti-interference capability of an IIC bus. Background Art

[0002] In recent years, with the widespread adoption of the I²C (Inter-Integrated Circuit) bus in industrial control, consumer electronics, automotive electronics, and other fields, its communication reliability has faced increasingly severe challenges. In particular, in complex electromagnetic environments, signal interference can lead to lost Start conditions, redundant Stop conditions, address bit distortion, or data bit transitions, potentially causing device communication anomalies and even system-level failures. Therefore, the development of an automated test solution that can systematically evaluate the anti-interference capabilities of I²C devices has become an urgent industry need.

[0003] Traditional testing methods mostly rely on manually injecting interference or using general-purpose signal generators to simulate abnormal scenarios, which have significant limitations: First, manual operation makes it difficult to accurately control the coupling relationship between interference timing and signal morphology, resulting in insufficient test coverage; second, existing test equipment lacks the ability to deeply analyze the IIC protocol stack and cannot dynamically generate interference patterns that are linked to the protocol state machine (such as the missing Stop signal after repeatedly sending the Start signal); third, the interpretation of test results relies on offline analysis using tools such as oscilloscopes, which is inefficient and prone to human error. Summary of the Invention

[0004] In view of the problems existing in the prior art, the object of the present invention is to provide an automated testing system and method for the anti-interference capability of an IIC bus, so as to improve the test efficiency and the credibility of the results.

[0005] To achieve the above object, the technical solution adopted by the present invention is: An automated test system for the anti-interference capability of an IIC bus includes a host computer control layer and a test execution layer. The host computer control layer and the test execution layer are connected by a USB-IIC bridge module to achieve bidirectional data transmission and protocol conversion between the host computer control layer and the test execution layer; the test execution layer is also connected to a device under test via a bus; The host computer control layer packages the interference type and corresponding parameters into a data packet according to the data sequence protocol of the test system; sends the data packet to the test execution layer through the IIC protocol and reads the test result data packet; parses the test result data packet and extracts relevant test data; The test execution layer obtains the data packet sent by the upper computer control layer through the IIC protocol; parses the data packet and extracts the corresponding test information parameters; packages the test result related data into a data packet according to the data sequence protocol of the test system; and sends the data packet when the upper computer control layer extracts the data through the IIC protocol.

[0006] The host computer control layer deploys ATE software, which includes a human-computer interaction interface module, a test parameter configuration module, a test task scheduling module, a status query module, a result acquisition module, a test result parsing module and a test data recording module; The human-computer interaction interface module is used to form a human-computer interaction interface on the host computer and allow users to input test parameters; The test parameter configuration module automatically assigns corresponding parameters to the currently scheduled task based on the interference type and parameter setting range selected by the user; The test task scheduling module automatically generates a task queue based on the interference type and parameter setting range selected by the user to ensure the orderly execution of test tasks; The status query module detects the test status of the test execution layer through a polling mechanism. When it detects that the current test task of the test execution layer has been completed, it triggers the result acquisition module to obtain the test result data packet from the test execution layer and also triggers the test task scheduling module to send the next test case to the test execution layer. The test result parsing module connects the human-computer interaction interface module and the result acquisition module, obtains the test parameters and test result data packets, and parses them to generate standardized test records containing timestamps, test item IDs, and error statistics; The test data recording module is used to record the test content, test parameters, test results and timestamp of each test task, and provide the recorded data to the report file after the test is completed.

[0007] The test parameters include: Interference characteristic parameters: interference type, interference injection quantity; Protocol parameters: communication rate, slave address, register address, data content and length; Test control parameters: number of cycles, timeout threshold, fault tolerance threshold.

[0008] The test execution layer includes a protocol parsing engine, a programmable interference waveform library, a response signal analysis module, a data analysis module and a result determination module; The protocol parsing engine is used to obtain test tasks from the test task scheduling module of the ATE test software, and to obtain test parameters from the test parameter configuration module, and to convert the test parameters into an executable instruction sequence of the IIC protocol state machine, and then generate an interference trigger mark table according to the interference type and injection position; finally, the interference trigger mark table and the executable protocol instruction sequence are synchronously sent to the programmable interference waveform library; the protocol parsing engine is also used to perform task progress management, test result feedback and resource release. Task progress management includes: feedback of test progress according to the execution status of the test task; test result feedback includes: feedback of test result data packets according to the instructions of the result acquisition module of the ATE test software; resource release includes: resetting the automated test system, clearing the interference waveform cache, releasing bus control rights, and preparing to receive the next task; The programmable interference waveform library generates a normal protocol flow and a test interference waveform based on the received interference trigger mark table and the executable protocol instruction sequence; the programmable interference waveform library is also used to perform interference testing, that is, outputting the normal protocol flow and the test interference waveform to the bus through GPIO control, and sending them to the device under test through the bus for interference testing; The response signal analysis module performs frame-level monitoring, compliance determination, and location association in real time during the interference test of the device under test; The data analysis module performs real-time data capture, static verification, dynamic verification and error clustering during the data reading and writing phase; The result judgment logic module obtains the interference waveform and the test interference waveform from the programmable interference waveform library, obtains the response error type from the response signal analysis module, obtains the data difference type from the data analysis module, and performs multi-dimensional judgment and data packaging.

[0009] The normal protocol stream is generated according to an executable instruction sequence, and the test interference waveform is generated after waveform reconstruction according to the interference type and test parameters.

[0010] The frame-level monitoring is to capture the response signal of the device under test in real time within the ACK / NACK clock cycle; the compliance judgment is to compare the difference between the captured ACK / NACK signal and the expected value of the current test waveform position; the position association is to classify the abnormal response errors according to the current test waveform.

[0011] The real-time data capture is as follows: reading the data frame returned by the device under test and caching it in RAM; static check bit: comparing the difference between the data returned by the device under test and the expected value; dynamic check bit: checking the continuity of the data returned by the device under test; error clustering: correlating the current test interference waveform based on the data difference.

[0012] The multi-dimensional judgment is as follows: comprehensively considering the current test interference waveform, response error type, data difference type and other parameters, and judging the test result according to the preset fault tolerance threshold; the data encapsulation is as follows: packaging the test interference type, error type, judgment result, test parameters, executable instruction sequence, captured data value, and expected data value into a structured data packet, and sending the data packet to the protocol parsing engine.

[0013] An automated testing method for the anti-interference capability of an IIC bus is implemented using the automated testing system described above, and specifically comprises the following steps: Step 1: Input test parameters through the human-computer interaction interface of ATE test software; Step 2: Configure test parameters and schedule test tasks, and send the test parameters and test tasks to the protocol parsing engine of the test execution layer; Step 3: The protocol parsing engine obtains the test tasks and test parameters, and performs protocol semantic parsing, dynamic parameter mapping, and task distribution; Protocol semantic parsing: converts test parameters into executable protocol instruction sequences for the IIC test system; dynamic parameter mapping: generates an interference trigger marker table based on interference type and injection location; Task distribution: Synchronously send the interference trigger mark table and the executable protocol instruction sequence to the programmable interference waveform library to trigger waveform preloading; Step 4: parameterize and reconstruct the test waveform using the programmable interference waveform library; The programmable interference waveform library performs the following operations based on the received interference trigger signature table and executable protocol instruction sequence: Normal protocol flow sequence: Generate normal protocol flow according to the executable instruction sequence; Multi-parameter waveform reconstruction: Dynamically generate test interference waveforms based on interference type and test parameters; Bus drive control: Through GPIO control, the reconstructed mixed signal is output to the bus and sent to the device under test through the bus; Step 5: Obtain test process data from the device under test and analyze it, as follows: The response signal analysis module performs real-time execution during the interference test: Frame-level monitoring: capture the response signal from the device in real time within the ACK / NACK clock cycle; Compliance determination: Compare the difference between the captured ACK / NACK signal and the expected value at the current test waveform position; Position association: Classify abnormal response errors based on the current test waveform; The data analysis module is executed during the data reading and writing phase: Real-time data capture: read the data frames returned by the device and cache them into RAM; Static verification: compare the difference between the data returned by the device and the expected value; Dynamic verification: Check the continuity of data returned by the device; Error clustering: Correlate the current test interference waveform based on data differences; Step 6: Determine the test results; The result judgment logic module determines the test results, specifically performing: Multi-dimensional judgment: Comprehensively considers parameters such as the current test interference waveform, response error type, and data difference type, and determines the test result according to the preset fault tolerance threshold; Data encapsulation: Packaging test interference type, error type, judgment result, test parameters, executable instruction sequence, captured data value, expected data value and other data into a structured data packet and sending the data packet to the protocol parsing engine; Step 7: Task progress management and feedback; The protocol parsing engine performs: Task progress management: feedback the test progress based on the execution of the test task; Test result feedback: According to the instructions of the ATE test software of the upper computer control layer, the test result data packet is returned; Resource release: reset the automated test system, clear the interference waveform cache, release bus control, and prepare to receive the next task; Step 8: After the status query module of the upper computer control layer detects that the current test task of the test execution layer is completed, it triggers the result acquisition module to obtain the test result data packet from the test execution layer and proceeds to step 9; it also triggers the test task scheduling module to send the next test case to the test execution layer and proceeds to step 3; Step 9: The test result parsing module obtains the test parameters and test result data packets, parses them, generates standardized test records containing timestamps, test item IDs, and error statistics, and displays them to the user through a human-computer interaction interface; Step 10: Record data. Test data record: Parse the test result data in the result data packet, and append the device name under test, timestamp, test parameters, and test data to the test result data.

[0014] By adopting this approach, the present invention achieves dynamic configuration of interference scenarios, closed-loop control of the test process, and intelligent interpretation of test results through deep protocol-level interaction between ATE software and the MCU. The system, with its core architecture of "parameterized configuration - protocol-aware interference injection - multi-dimensional result analysis," addresses the technical challenges of traditional testing, which often involve a single interference model, high reliance on manual intervention, and low confidence in results.

[0015] Protocol-aware interference injection refers to a core technology that, during IIC bus testing, generates and injects interference signals not independently of the bus protocol but rather deeply couples them with the protocol state machine, dynamically adjusting the interference type and timing based on the current communication phase (e.g., address transmission, data reading and writing, ACK / NACK responses, etc.). Essentially, this technology achieves context-sensitive interference waveform simulation through real-time linkage between protocol parsing and interference generation, thereby reproducing protocol-sensitive anomalies in real-world scenarios.

[0016] This invention simulates master-side behavior through a programmable interference waveform library, dynamically reconstructing complex interference scenarios including abnormal Start / Stop conditions, redundant / missing address bits, and distorted data bit sequences. Simultaneously, a hardware feedback loop monitors slave device responses in real time, enabling a fully closed-loop test of interference injection, protocol parsing, and error detection. Compared to traditional approaches, this system can accurately replicate typical interference models such as bus contention, timing jitter, and level drift. Furthermore, an automated scripting engine enables batch execution and quantitative evaluation of multi-dimensional test cases, significantly improving test efficiency and result credibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a principle block diagram of the present invention; Figure 2 Flowchart of the method of the host computer control layer of the present invention; Figure 3 A flow chart of the method for the test execution layer of the present invention; Figure 4 Schematic diagram of the test waveform selection interface provided by the human-computer interaction module; Figure 5 Schematic diagram of the protocol parameter setting interface provided for the human-computer interaction module. DETAILED DESCRIPTION

[0018] like Figure 1-3 As shown, the present invention discloses an automated testing system for the anti-interference capability of an IIC bus, which includes a host computer control layer and a test execution layer. The host computer control layer and the test execution layer are connected by a USB-IIC bridge module to achieve bidirectional data transmission and protocol conversion between the host computer control layer and the test execution layer; the test execution layer is also connected to the device under test through the bus.

[0019] The host control layer packages the interference type and corresponding parameters into data packets according to the test system's data sequence protocol; sends the data packets to the test execution layer via the IIC protocol and reads the test result data packets; parses the test result data packets and extracts the relevant test data. The test execution layer obtains the data packets sent by the host control layer via the IIC protocol; parses the data packets and extracts the corresponding test information parameters; packages the test result-related data into data packets according to the test system's data sequence protocol; and sends the data packets via the IIC protocol when the host control layer extracts the data.

[0020] Specifically, the upper computer control layer in the present invention deploys ATE software, which includes a human-computer interaction interface module, a test parameter configuration module, a test task scheduling module, a status query module, a result acquisition module, a test result parsing module and a test data recording module.

[0021] The human-computer interaction interface module is used to form a human-computer interaction interface on the host computer and allow users to input test parameters. Test parameters include: Interference characteristic parameters: interference type (such as glitch, level drop, timing jitter), interference injection quantity; Protocol parameters: communication rate, slave address, register address, data content and length; Test control parameters: number of cycles, timeout threshold, fault tolerance threshold.

[0022] The test parameter configuration module automatically assigns corresponding parameters to the currently scheduled task based on the interference type and parameter setting range selected by the user.

[0023] The test task scheduling module automatically generates a task queue based on the interference type and parameter setting range selected by the user to ensure the orderly execution of test tasks.

[0024] The status query module detects the test status of the test execution layer through a polling mechanism. When it detects that the current test task of the test execution layer is completed, it triggers the result acquisition module to obtain the test result data packet from the test execution layer, and also triggers the test task scheduling module to send the next test case to the test execution layer.

[0025] The test result parsing module connects the human-computer interaction interface module and the result acquisition module, obtains the test parameters and test result data packets, and parses them to generate standardized test records containing timestamps, test item IDs, and error statistics.

[0026] The test data recording module is used to record the test content, test parameters, test results and timestamp of each test task, and provide the recorded data to the report file after the test is completed.

[0027] The test execution layer includes a protocol parsing engine, a programmable interference waveform library, a response signal analysis module, a data analysis module and a result judgment module.

[0028] The protocol parsing engine is used to obtain test tasks from the test task scheduling module of the ATE test software and test parameters (including slave address, register map, interference type, injection location, and number of loops) from the test parameter configuration module. It converts the test parameters into an executable instruction sequence for the IIC protocol state machine (e.g., slave address frame + register map frame + data frame). It then generates an interference trigger flag table based on the interference type (e.g., start redundancy, data bit flip) and injection location (e.g., address bit 3, data frame 2). Finally, it synchronously sends the interference trigger flag table and the executable protocol instruction sequence to the programmable interference waveform library. The protocol parsing engine also manages task progress, transmits test results, and releases resources. Task progress management involves transmitting test progress based on the execution of test tasks. Test result transmission involves transmitting test result data packets based on the instructions of the ATE test software's result acquisition module. Resource release involves resetting the automated test system, clearing the interference waveform buffer, and releasing bus control to prepare for the next task.

[0029] The programmable interference waveform library generates normal protocol streams and test interference waveforms based on a received interference trigger flag table and executable protocol instruction sequences. The normal protocol stream is generated based on the executable instruction sequence, while the test interference waveform is generated by reconstructing the waveform based on the interference type and test parameters. The programmable interference waveform library is also used to perform interference testing. This involves outputting the normal protocol stream and test interference waveforms to the bus via GPIO control. These waveforms are then sent to the device under test via the bus for interference testing.

[0030] The response signal analysis module performs real-time frame-level monitoring, compliance determination, and position correlation during interference testing of the device under test. Frame-level monitoring involves capturing the device's response signal in real time during the ACK / NACK clock cycle. Compliance determination involves comparing the captured ACK / NACK signal with the expected value at the current test waveform position. Position correlation involves classifying response anomalies (such as slave address no response error and data frame response error) based on the current test waveform (e.g., the slave address frame ACK phase).

[0031] The expected value of the current test waveform position is the corresponding data block in the data packet sent by the upper computer control layer. For example, if the slave address of the device under test is 0xA2 and it is a unique address, the expected value for addresses other than 0xA2 is NACK. When the address is 0xA2, the expected value is ACK.

[0032] During the data read and write phases, the data analysis module performs real-time data capture, static checksums, dynamic checksums, and error clustering. Real-time data capture involves reading data frames returned by the device under test and buffering them in RAM. Static checksums compare the returned data with the expected value. Dynamic checksums check the continuity of the returned data (e.g., the sequence of increasing data addresses). Error clustering involves correlating the current test interference waveform based on data discrepancies (e.g., data errors and data address errors).

[0033] The result judgment logic module retrieves the interference waveform and test interference waveform from the programmable interference waveform library, obtains the response error type from the response signal analysis module, and obtains the data discrepancy type from the data analysis module. It then performs multi-dimensional judgment and data packaging. Multi-dimensional judgment involves combining parameters such as the current test interference waveform, response error type, and data discrepancy type, and determining the test result based on a preset fault tolerance threshold. Data packaging involves packaging the test interference type, error type, judgment result, test parameters, executable instruction sequence, captured data value, and expected data value into a structured data packet and sending it to the protocol parsing engine.

[0034] Based on the above test system, the present invention also discloses an automated test method for the anti-interference capability of the IIC bus, which includes the following steps: Step 1: Enter the test parameters through the human-computer interaction interface of the ATE test software. The test parameters include: Interference characteristic parameters: interference type (such as glitch, level drop, timing jitter), interference injection quantity; Protocol parameters: communication rate, slave address, register address, data content and length; Test control parameters: number of cycles, timeout threshold, fault tolerance threshold.

[0035] Step 2: Configure test parameters and schedule test tasks, and send the test parameters and test tasks to the protocol parsing engine of the test execution layer.

[0036] Step 3: The protocol parsing engine obtains the test tasks and test parameters, and performs protocol semantic parsing, dynamic parameter mapping, and task distribution.

[0037] Protocol semantic parsing: converts test parameters into executable protocol instruction sequences (such as slave address frame + register map frame + data frame) for the IIC test system.

[0038] Dynamic parameter mapping: Generates an interference trigger mark table based on the interference type (such as start redundancy and data bit flip) and injection position (such as the third bit of the address and the second byte of the data frame).

[0039] Task distribution: Synchronously send the interference trigger mark table and the executable protocol instruction sequence to the programmable interference waveform library to trigger waveform preloading.

[0040] Step 4: parameterize and reconstruct the test waveform using the programmable interference waveform library; The programmable interference waveform library performs the following operations based on the received interference trigger signature table and executable protocol instruction sequence: Normal protocol flow sequence: Generate normal protocol flow according to the executable instruction sequence (slave address, register mapping, data, data length); Multi-parameter waveform reconstruction: Dynamically generate test interference waveforms based on interference type (signal, timing anomaly) and test parameters (signal type, duration).

[0041] Bus drive control: Through GPIO control, the reconstructed mixed signal (test interference waveform + normal protocol flow) is output to the bus and sent to the device under test through the bus.

[0042] Step 5: Obtain test process data from the device under test and analyze it, as follows: The response signal analysis module performs real-time execution during the interference test: Frame-level monitoring: capture the response signal from the device in real time within the ACK / NACK clock cycle; Compliance determination: Compare the difference between the captured ACK / NACK signal and the expected value at the current test waveform position; Position association: Based on the current test waveform (such as the slave address frame ACK stage), the abnormal response error is classified (such as slave address no response error, data frame response error).

[0043] The data analysis module is executed during the data reading and writing phase: Real-time data capture: read the data frames returned by the device and cache them into RAM; Static verification: compare the difference between the data returned by the device and the expected value; Dynamic verification: Check the continuity of data returned by the device (such as the data address increment sequence); Error clustering: Correlate the current test interference waveform based on data differences (such as data errors, data address errors).

[0044] Step 6: Determine the test results.

[0045] The result judgment logic module determines the test results, specifically performing: Multi-dimensional judgment: Comprehensively considers parameters such as the current test interference waveform, response error type, and data difference type, and determines the test result according to the preset fault tolerance threshold; Data encapsulation: Package the test interference type, error type, judgment result, test parameters, executable instruction sequence, captured data value, expected data value and other data into a structured data packet and send the data packet to the protocol parsing engine.

[0046] Step 7: Task progress management and feedback.

[0047] The protocol parsing engine performs: Task progress management: feedback the test progress based on the execution of the test task; Test result feedback: According to the instructions of the ATE test software of the upper computer control layer, the test result data packet is returned; Resource release: reset the automated test system, clear the interference waveform cache, release bus control, and prepare to receive the next task.

[0048] Step 8: After the status query module of the upper computer control layer detects that the current test task of the test execution layer is completed, it triggers the result acquisition module to obtain the test result data packet from the test execution layer and enters step 9; it also triggers the test task scheduling module to send the next test case to the test execution layer and enters step 3.

[0049] Step 9: The test result parsing module obtains the test parameters and test result data packets, parses them, generates standardized test records containing timestamps, test item IDs, and error statistics, and displays them to the user through a human-computer interaction interface.

[0050] Step 10: Record data.

[0051] Test data record: Parse the test result data in the result data packet, and append the device name under test, timestamp, test parameters, and test data to the test result data.

[0052] For example, the test result data contains: Test conclusion: Abnormality found Interference type: N(Start) + Write Error code: -4 Slave address no response Error location: 1 Write data Executed times: 1 Slave address: 0xA2 Exception register: 0x7F Write data length: 1 Read data length: 1 Abnormal data: 0xFF Correct data: 0x7B.

[0053] This invention leverages deep protocol-level interaction between ATE software and the MCU to achieve dynamic configuration of interference scenarios, closed-loop control of the test process, and intelligent interpretation of test results. The system's core architecture combines parameterized configuration, protocol-aware interference injection, and multi-dimensional results analysis, addressing the technical challenges of traditional testing, which often involve a single interference model, high manual dependency, and low confidence levels.

[0054] Protocol-aware interference injection refers to a core technology that, during IIC bus testing, generates and injects interference signals not independently of the bus protocol but rather deeply couples them with the protocol state machine, dynamically adjusting the interference type and timing based on the current communication phase (e.g., address transmission, data reading and writing, ACK / NACK responses, etc.). Essentially, this technology achieves context-sensitive interference waveform simulation through real-time linkage between protocol parsing and interference generation, thereby reproducing protocol-sensitive anomalies in real-world scenarios.

[0055] This invention simulates master-side behavior through a programmable interference waveform library, dynamically reconstructing complex interference scenarios including abnormal Start / Stop conditions, redundant / missing address bits, and distorted data bit sequences. Simultaneously, a hardware feedback loop monitors slave device responses in real time, enabling a fully closed-loop test of interference injection, protocol parsing, and error detection. Compared to traditional approaches, this system can accurately replicate typical interference models such as bus contention, timing jitter, and level drift. Furthermore, an automated scripting engine enables batch execution and quantitative evaluation of multi-dimensional test cases, significantly improving test efficiency and result credibility.

[0056] The present invention has the following beneficial effects: 1. Improved test efficiency: The ATE test system enables batch execution of multiple interference scenarios, shortening the test cycle by more than 90% compared to manual operations. 2. Coverage optimization: Supports combined traversal testing of protocol parameters and interference parameters, covering more than 95% of abnormal scenarios in the IIC standard; 3. Result traceability: The test fully records the original parameters, execution logs, and error details to meet traceability requirements; 4. Device compatibility: Through the abstract design of the USB-IIC interface, it can adapt to IIC slave devices from different manufacturers without hardware modification.

[0057] To better illustrate the technical solution of the present invention, examples are given below.

[0058] Description of the host computer control layer: The host computer control layer deploys ATE test software and performs the following operations: 1. Test parameter configuration The tester selects the interference characteristic parameters (test waveform combination, interference injection quantity) and protocol parameters (communication rate, slave address, register address, data length).

[0059] Interference characteristic parameters are configured through the test waveform configuration interface and the protocol parameter configuration interface.

[0060] Testers can flexibly select the test interference type through a visual interface, which supports combined interference injection configuration and implements simulation tests of different interference scenarios on the IIC bus.

[0061] like Figure 4 As shown, the interference type selection (3 examples): N (Start) test waveform, used to evaluate the anti-interference ability of the device under test to redundant injection of the Start signal; The N(Bit) test waveform is used to test the anti-interference ability of the device under test to level flip and level pulse in IIC communication; The Start+SlaveaddrW / R+Nbit+Start+read test waveform is used to test the device's response characteristics to interference such as glitches and level drops.

[0062] Write / Read selection: Supports injecting interference waveforms into the write or read process to achieve full-link interference test coverage.

[0063] The present invention supports full-dimensional protocol parameter configuration, covering basic communication parameters, test control parameters and timing characteristic parameters, such as Figure 5 As shown, the protocol parameter configuration of this embodiment specifically includes: SlaveAddress: Set the slave address parameters of the device under test; StartRegister: Set the starting register address of the device under test; WriteLength: Set the data length of the device under test to write the test; ReadLength: Set the data length of the device under test to read the test data; TestTimes: Set the number of cycle tests for the test waveform combination; IICRate: Set the communication rate of the test waveform combination; TestItemNum: Set the protocol code of the test waveform combination; Start_Num: Set the maximum number of Start signals in the test waveform; Stop_Num: Set the maximum number of Stop signals in the test waveform; Bit_Num: Set the maximum number of level signals in the test waveform; Bit_Data: Set the distribution of the level signal in the test waveform; Delay_ms: Set the timing delay millisecond parameter in the test waveform; Delay_us: Set the timing delay microsecond parameter in the test waveform; Start_Test: Set the test system to execute the test protocol verification data; Test_Param: provides testers with a single debugging test for a specific combination; Chip_Name: chip name (device name) in the output report file name; File path: Prompts the file save path for the output report.

[0064] 2. Test Task Scheduling ATE software automatically generates a test task queue based on the task set selected by the user, schedules the current test content in an orderly manner, automatically generates test data, number of cycles, timeout threshold, and fault tolerance threshold according to test requirements, and encapsulates and transmits them to the test execution layer according to the IIC communication protocol.

[0065] 3. Status Query The ATE software queries the test execution layer in real time to see if the test is complete. If the test is complete, the results are obtained and the next test task is scheduled. If the test is not complete, the query continues.

[0066] 4. Obtaining Results When the test is completed, the ATE software reads the test result data packet from the test execution layer.

[0067] 5. Test Results Analysis The ATE software parses the result data according to the test execution layer protocol based on the read test result data packet.

[0068] For example, the test conclusion: Anomalies were found; Interference type: N(Start) + Write; Error code: -4 No response from slave address; Error location: 1 write data; Number of times executed: 1; Slave address: 0xA2; Exception register: 0x7F; Write data length: 1; Read data length: 1; Abnormal data: 0xFF; Correct data: 0x7B.

[0069] 6. Test data recording The ATE software records the parsed data in a log file based on the analysis results, the currently scheduled task content (interference characteristic parameters, protocol parameters), and the generated test data, with a timestamp.

[0070] 7. Test result record file When the test is completed, the ATE software will output the test record results of all tasks to a report file in the specified format for storage.

[0071] Test execution layer description: 1. The protocol parsing engine receives data; (1) The protocol parsing engine receives protocol data packets from the ATE test software.

[0072] (2) Parse the data packet content to obtain interference characteristic parameters, protocol parameters, test data, number of cycles, timeout threshold and fault tolerance level.

[0073] (3) Pass the parsed parameters to the programmable interference waveform library.

[0074] 2. Programmable Interference Waveform Library (1) Select the test waveform according to the interference characteristic parameters, and inject interference at the specified position according to the parameters to form an IIC communication sequence containing interference elements.

[0075] For example, N(Start)+Write N = 7: add 7 Start signals before the standard IIC write waveform; N(Bit) + ReadN = 8Bit_Data = 0xAA: Add 8 level flips before the standard IIC read waveform, and the flip waveform is: 10101010; Start+SlaveaddrW+Nbit+Start+readN=5 Bit_Data = 0x15: Inject 5 level pulses after sending the write command, and the level pulse sequence is 10101.

[0076] (2) Reconstruct the IIC communication sequence containing interference elements based on the protocol parameters.

[0077] Synchronize the SlaveAddress, Register, data length, and data content to the IIC communication sequence to ensure that the device under test is in the predetermined condition before the test waveform is executed, the relevant information required to load the test waveform is correct, and the data comparison content of the readback verification is correct.

[0078] Reconstructs the communication rate of the IIC communication sequence according to the IICRate specified in the test requirements.

[0079] Reconstruct the timing delay in the IIC communication sequence according to the timing delay parameters.

[0080] (3) Set the judgment rules based on the number of cycles, timeout threshold, and fault tolerance level.

[0081] According to the number of cycles, the test data content and the readback verification data content are allocated to ensure that the data contents of two adjacent tests are different.

[0082] According to the timeout threshold, set the monitoring wait threshold of the response signal (ACK), clock, and signal.

[0083] According to the fault tolerance level, set the abnormality judgment criteria for response and data content.

[0084] (4) Test execution; The reconstructed IIC communication sequence containing interference elements is executed to the IIC bus mounted on the device under test, and the judgment rules are given to the response signal analysis and data analysis modules.

[0085] 3. Response Signal Analysis After the test waveform is executed, the response signal status is monitored in each response clock cycle, and the current response signal (ACK) and non-response signal (NACK) are determined to be compliant according to the judgment rules.

[0086] Typical error types: -1 No response to writing data.

[0087] -2 SDA signal line is pulled low for timeout.

[0088] -3 SCL signal line low timeout.

[0089] -4 Slave address no response.

[0090] -5 Register address no response.

[0091] Special waveform error types: Not a slave address response. (The error code is classified into the error code of the corresponding test waveform.)

[0092] 4. Data Analysis After the test waveform is executed, the readback data and the verification data are compared, and the compliance of the current data is determined according to the judgment rules.

[0093] Typical error types: Initialization write data error.

[0094] Initialization read data error.

[0095] Test waveform write data error.

[0096] The test waveform data writing address is incorrect.

[0097] Test waveform data reading error.

[0098] The test waveform read data address is incorrect.

[0099] The standard waveform write data after the test waveform is incorrect.

[0100] The standard waveform reading data after the test waveform is incorrect.

[0101] Specific waveform error types: The test waveform data was written incorrectly.

[0102] 5. Result Judgment Logic According to the response signal analysis results and data analysis results, combined with the current test waveform, the final judgment result and error information are given (including: judgment result, test waveform, error code, error type, response status, slave address, register address, error data, normal data, and current test execution times) 6. Protocol parsing engine sends data The protocol analysis engine packages the judgment results and error information into data packets according to the protocol and sends them through the IIC protocol when ATE test software queries them.

[0103] The above description is merely an embodiment of the present invention and does not limit the technical scope of the present invention. Therefore, any minor modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. An automated test system for the anti-interference capability of an IIC bus, characterized by: It includes a host computer control layer and a test execution layer. The host computer control layer and the test execution layer are connected by a USB-IIC bridge module to achieve bidirectional data transmission and protocol conversion between the host computer control layer and the test execution layer. The test execution layer is also connected to the device under test through a bus. The host computer control layer packages the interference type and corresponding parameters into a data packet according to the data sequence protocol of the test system; sends the data packet to the test execution layer through the IIC protocol and reads the test result data packet; parses the test result data packet and extracts relevant test data; The test execution layer obtains the data packet sent by the host computer control layer through the IIC protocol; parses the data packet and extracts the corresponding test information parameters; The test result related data is packaged into data packets according to the data sequence protocol of the test system; and the data packets are sent out when the upper computer control layer extracts the data through the IIC protocol.

2. The automated test system for the anti-interference capability of an IIC bus according to claim 1, characterized in that: The host computer control layer deploys ATE software, which includes a human-computer interaction interface module, a test parameter configuration module, a test task scheduling module, a status query module, a result acquisition module, a test result parsing module and a test data recording module; The human-computer interaction interface module is used to form a human-computer interaction interface on the host computer and allow users to input test parameters; The test parameter configuration module automatically assigns corresponding parameters to the currently scheduled task based on the interference type and parameter setting range selected by the user; The test task scheduling module automatically generates a task queue based on the interference type and parameter setting range selected by the user to ensure the orderly execution of test tasks; The status query module detects the test status of the test execution layer through a polling mechanism. When it detects that the current test task of the test execution layer has been completed, it triggers the result acquisition module to obtain the test result data packet from the test execution layer and also triggers the test task scheduling module to send the next test case to the test execution layer. The test result parsing module connects the human-computer interaction interface module and the result acquisition module, obtains the test parameters and test result data packets, and parses them to generate standardized test records containing timestamps, test item IDs, and error statistics; The test data recording module is used to record the test content, test parameters, test results and timestamp of each test task, and provide the recorded data to the report file after the test is completed.

3. The automated test system for the anti-interference capability of an IIC bus according to claim 2, characterized in that: The test parameters include: Interference characteristic parameters: interference type, interference injection quantity; Protocol parameters: communication rate, slave address, register address, data content and length; Test control parameters: number of cycles, timeout threshold, fault tolerance threshold.

4. The automated test system for the anti-interference capability of an IIC bus according to claim 2 or 3, characterized in that: The test execution layer includes a protocol parsing engine, a programmable interference waveform library, a response signal analysis module, a data analysis module and a result determination module; The protocol parsing engine is used to obtain test tasks from the test task scheduling module of the ATE test software, and to obtain test parameters from the test parameter configuration module, and to convert the test parameters into an executable instruction sequence of the IIC protocol state machine, and then generate an interference trigger mark table according to the interference type and injection position; finally, the interference trigger mark table and the executable protocol instruction sequence are synchronously sent to the programmable interference waveform library; the protocol parsing engine is also used to perform task progress management, test result feedback and resource release. Task progress management includes: feedback of test progress according to the execution status of the test task; test result feedback includes: feedback of test result data packets according to the instructions of the result acquisition module of the ATE test software; resource release includes: resetting the automated test system, clearing the interference waveform cache, releasing bus control rights, and preparing to receive the next task; The programmable interference waveform library generates a normal protocol flow and a test interference waveform based on a received interference trigger marker table and an executable protocol instruction sequence; The programmable interference waveform library is also used to perform interference testing. That is, the normal protocol flow and test interference waveforms are output to the bus through GPIO control, and then sent to the device under test through the bus for interference testing. The response signal analysis module performs frame-level monitoring, compliance determination, and location association in real time during the interference test of the device under test; The data analysis module performs real-time data capture, static verification, dynamic verification and error clustering during the data reading and writing phase; The result judgment logic module obtains the interference waveform and the test interference waveform from the programmable interference waveform library, obtains the response error type from the response signal analysis module, obtains the data difference type from the data analysis module, and performs multi-dimensional judgment and data packaging.

5. The automated test system for the anti-interference capability of an IIC bus according to claim 4, characterized in that: The normal protocol stream is generated according to an executable instruction sequence, and the test interference waveform is generated after waveform reconstruction according to the interference type and test parameters.

6. The automated test system for the anti-interference capability of an IIC bus according to claim 4, characterized in that: The frame-level monitoring is to capture the response signal of the device under test in real time within the ACK / NACK clock cycle; the compliance judgment is to compare the difference between the captured ACK / NACK signal and the expected value of the current test waveform position; the position association is to classify the abnormal response errors according to the current test waveform.

7. The automated test system for the anti-interference capability of an IIC bus according to claim 4, characterized in that: The real-time data capture is as follows: reading the data frame returned by the device under test and caching it in RAM; Static check digit: compares the difference between the data returned by the device under test and the expected value; dynamic check digit: checks the continuity of the data returned by the device under test; Error clustering: Correlate the current test interference waveform based on data differences.

8. The automated test system for the anti-interference capability of an IIC bus according to claim 4, characterized in that: The multi-dimensional judgment is as follows: comprehensively considering the current test interference waveform, response error type, data difference type and other parameters, and judging the test result according to the preset fault tolerance threshold; the data encapsulation is as follows: packaging the test interference type, error type, judgment result, test parameters, executable instruction sequence, captured data value, and expected data value into a structured data packet, and sending the data packet to the protocol parsing engine.

9. An automated test method for the anti-interference capability of an IIC bus, characterized by: The method is implemented using the automated testing system according to any one of claims 4 to 8, and the method specifically comprises the following steps: Step 1: Input test parameters through the human-computer interaction interface of ATE test software; Step 2: Configure test parameters and schedule test tasks, and send the test parameters and test tasks to the protocol parsing engine of the test execution layer; Step 3: The protocol parsing engine obtains the test tasks and test parameters, and performs protocol semantic parsing, dynamic parameter mapping, and task distribution; Protocol semantic parsing: converts test parameters into executable protocol instruction sequences for the IIC test system; dynamic parameter mapping: generates an interference trigger marker table based on interference type and injection location; Task distribution: Synchronously send the interference trigger mark table and the executable protocol instruction sequence to the programmable interference waveform library to trigger waveform preloading; Step 4: parameterize and reconstruct the test waveform using the programmable interference waveform library; The programmable interference waveform library performs the following operations based on the received interference trigger signature table and executable protocol instruction sequence: Normal protocol flow sequence: Generate normal protocol flow according to the executable instruction sequence; Multi-parameter waveform reconstruction: Dynamically generate test interference waveforms based on interference type and test parameters; Bus drive control: Through GPIO control, the reconstructed mixed signal is output to the bus and sent to the device under test through the bus; Step 5: Obtain test process data from the device under test and analyze it, as follows: The response signal analysis module performs real-time execution during the interference test: Frame-level monitoring: capture the response signal from the device in real time within the ACK / NACK clock cycle; Compliance determination: Compare the difference between the captured ACK / NACK signal and the expected value at the current test waveform position; Position association: Classify abnormal response errors based on the current test waveform; The data analysis module is executed during the data reading and writing phase: Real-time data capture: read the data frames returned by the device and cache them into RAM; Static verification: compare the difference between the data returned by the device and the expected value; Dynamic verification: Check the continuity of data returned by the device; Error clustering: Correlate the current test interference waveform based on data differences; Step 6: Determine the test results; The result judgment logic module determines the test results, specifically performing: Multi-dimensional judgment: Comprehensively considers parameters such as the current test interference waveform, response error type, and data difference type, and determines the test result according to the preset fault tolerance threshold; Data encapsulation: Packaging test interference type, error type, judgment result, test parameters, executable instruction sequence, captured data value, expected data value and other data into a structured data packet and sending the data packet to the protocol parsing engine; Step 7: Task progress management and feedback; The protocol parsing engine performs: Task progress management: feedback the test progress based on the execution of the test task; Test result feedback: According to the instructions of the ATE test software of the upper computer control layer, the test result data packet is returned; Resource release: reset the automated test system, clear the interference waveform cache, release bus control, and prepare to receive the next task; Step 8: After the status query module of the upper computer control layer detects that the current test task of the test execution layer is completed, it triggers the result acquisition module to obtain the test result data packet from the test execution layer and proceeds to step 9; it also triggers the test task scheduling module to send the next test case to the test execution layer and proceeds to step 3; Step 9: The test result parsing module obtains the test parameters and test result data packets, parses them, generates standardized test records containing timestamps, test item IDs, and error statistics, and displays them to the user through a human-computer interaction interface; Step 10: Record data. Test data record: Parse the test result data in the result data packet, and append the device name under test, timestamp, test parameters, and test data to the test result data.

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