Instruction preprocessing method and test system

Abstract

The invention relates to an instruction preprocessing method and a test system, and the method comprises the steps: an upper computer preloads all test instruction sets required by a test to a bottom hardware storage system for caching; after the underlying hardware storage system receives a test command sent by the upper computer, the cached test instruction set is distributed to the corresponding resource board card to execute test operation; the underlying hardware storage system caches test results returned after the resource board cards execute the corresponding test operations; and after querying that the resource board card executes all the received test instruction sets, the upper computer reads corresponding test results cached in the underlying hardware storage system. According to the method, all test instruction sets required by testing are pre-loaded to the bottom hardware storage system independent of the resource board cards, and the bottom hardware storage system distributes the test instruction sets to the corresponding resource board cards to execute the test operation during testing, so that long-time and long-path data transmission is avoided; the influence of external abnormity on instruction transmission is reduced, and the test efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor testing technology, and in particular to an instruction preprocessing method and a testing system. Background Art

[0002] Semiconductor automated testing refers to the use of automatic test equipment (ATE) to inspect various parameters of devices under test (DUTs), eliminating defective products and ensuring the quality of semiconductor devices before they leave the factory. In traditional test systems, programs are typically written and executed by host computer software. During execution, instructions are sent one by one to the underlying hardware execution unit, and the results of individual instructions are uploaded in real time. Each instruction is executed serially between the host computer, communication system, and underlying hardware, resulting in a long and time-consuming process. This results in low test efficiency. Summary of the Invention

[0003] Based on this, it is necessary to provide an instruction preprocessing method and a test system that can improve test efficiency in order to address the above problems.

[0004] A first aspect of the present application provides an instruction preprocessing method, comprising: The host computer preloads all test instruction sets required for the test into the underlying hardware storage system for caching; After receiving the test command sent by the host computer, the underlying hardware storage system distributes the cached test instruction set to the corresponding resource board to perform the test operation; The underlying hardware storage system caches the test results returned after each resource board performs the corresponding test operation; After the host computer inquires that the resource board has executed all received test instruction sets, it reads the corresponding test results cached in the underlying hardware storage system.

[0005] In one embodiment, the test instruction set includes at least one of an initialization instruction set, a waveform generation instruction set, a power configuration instruction set, a power clamp instruction set, and an alarm instruction set.

[0006] In one embodiment, the upper computer preloads all test instruction sets required for the test into the underlying hardware storage system for caching, including: the upper computer generates a test instruction set for execution by the resource board based on all compiled test programs, and sends the test instruction set and the configured cache instruction set identifier to the underlying hardware storage system; the cache instruction set identifier is used for the underlying hardware storage system to cache the received test instruction set.

[0007] In one embodiment, after receiving the test command sent by the host computer, the underlying hardware storage system distributes the cached test instruction set to the corresponding resource board to perform the test operation, including: After all test instruction sets are cached, the underlying hardware storage system generates an instruction set loading completion flag; After querying the instruction set loading completion mark, the host computer sends the instruction set execution mark to the underlying hardware storage system; After receiving the instruction set execution identifier, the underlying hardware storage system distributes the cached test instruction set to the corresponding resource board to execute the test operation.

[0008] In one embodiment, the underlying hardware storage system sends a test instruction set with the same function to an instruction processing unit in one or more corresponding resource boards to perform a test operation.

[0009] In one embodiment, the instruction processing unit includes at least one of an analog waveform generating unit, an acquisition unit, a digital waveform generating unit, and a clamping unit.

[0010] In one embodiment, after the host computer inquires that the resource board has executed all received test instruction sets, the step of reading the corresponding test results cached in the underlying hardware storage system includes: After querying that the corresponding resource board has executed all received test instruction sets, the host computer reads the corresponding test results cached in the underlying hardware storage system; or After querying that all resource boards have executed all received test instruction sets, the host computer reads all test results cached in the underlying hardware storage system.

[0011] In one embodiment, after the host computer inquires that the resource board has executed all received test instruction sets, and then reads the corresponding test results cached in the underlying hardware storage system, the host computer further includes: The resource board reads back the test instruction set that has been tested in the underlying hardware storage system and executes the corresponding test operation again.

[0012] In one embodiment, different types of resource boards execute tests at different speeds, and the different types of resource boards execute corresponding test operations in parallel according to the distributed / readback test instruction sets.

[0013] The second aspect of the present application provides a test system, including a host computer, an underlying hardware storage system and a resource board, wherein the host computer is communicatively connected to the underlying hardware storage system, and the underlying hardware storage system is connected to the resource board; the test system performs instruction preprocessing according to the above method.

[0014] In one embodiment, the resource board decodes instructions according to the received test instruction set, controls the external hardware device to perform test operations according to the decoded instructions, records test results, and stores the test results in the underlying hardware storage system.

[0015] In one embodiment, the underlying hardware storage system includes: An instruction set storage unit caches a test instruction set and distributes the cached test instruction set to corresponding resource boards to execute test operations after receiving a test command sent by the host computer; The result storage unit caches the test results returned after each resource board performs the corresponding test operation.

[0016] In one embodiment, the resource board reads back the test instruction set for which the test operation has been executed in the underlying hardware storage system, and executes the corresponding test operation again.

[0017] In one embodiment, the test system further includes a communication system and a resource management system, wherein the communication system is communicatively connected to the host computer and the resource management system, and the resource management system is connected to the underlying hardware storage system.

[0018] In the above-mentioned instruction preprocessing method and test system, the host computer preloads all the test instruction sets required for the test into the underlying hardware storage system for caching; after receiving the test command sent by the host computer, the underlying hardware storage system distributes the cached test instruction sets to the corresponding resource boards to perform the test operations; the underlying hardware storage system caches the test results returned after each resource board performs the corresponding test operations; after the host computer inquires that the resource board has executed all the received test instruction sets, it reads the corresponding test results cached in the underlying hardware storage system. All the test instruction sets required for the test are first preloaded into the underlying hardware storage system independent of the resource board. When the test is performed, the underlying hardware storage system distributes the test instruction sets to the corresponding resource board to perform the test operations. Finally, the host computer reads the corresponding test results cached in the underlying hardware storage system, thereby avoiding long-term and long-path data transmission, reducing the impact of external abnormalities on instruction transmission, and improving test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a flow chart of an instruction preprocessing method in one embodiment; Figure 2 A flowchart of an embodiment in which the underlying hardware storage system distributes a cached test instruction set to a corresponding resource board to perform a test operation after receiving a test command sent by a host computer; Figure 3 A schematic diagram showing a comparison of instruction processing in a test system according to an embodiment. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0021] In one embodiment, Figure 1 As shown, an instruction preprocessing method is provided, comprising: Step S110: The host computer preloads all the test instruction sets required for the test into the underlying hardware storage system for caching. Before testing the device to be tested DUT, the host computer performs a preloading operation to load all the test instruction sets required for the test into the underlying hardware storage system for caching. The device to be tested may be a chip to be tested or other electronic device, and the underlying hardware storage system is a storage system independent of the resource board. Depending on the test scenario, the number and type of test instruction sets will also vary accordingly. Specifically, the test instruction set may include at least one of an initialization instruction set, a waveform generation instruction set, a power configuration instruction set, a power clamp instruction set, and an alarm instruction set. The underlying hardware storage system may include, but is not limited to, memories such as DDR or flash. The test instruction set includes test data, such as pattern data.

[0022] In one embodiment, step S110 includes: the host computer generates a test instruction set for execution by the resource board based on all compiled test programs, and sends the test instruction set and the configured cache instruction set identifier to the underlying hardware storage system; the cache instruction set identifier is used by the underlying hardware storage system to cache the received test instruction set. After the host computer compiles all test programs, it translates them into a test instruction set for execution by the resource board and sets the cache instruction set identifier. The cache instruction set identifier and the test instruction set are sent to the underlying hardware storage system together to inform the underlying hardware storage system to cache the received test instruction set first and temporarily suspend instruction set distribution.

[0023] Step S120: After receiving the test command sent by the host computer, the underlying hardware storage system distributes the cached test instruction set to the corresponding resource board to execute the test operation. The host computer may send a command or set an identifier to send the test command to the underlying hardware storage system. The host computer may send the test command to the underlying hardware storage system at the same time as or after sending the test instruction set. After identifying the test command sent by the host computer, the underlying hardware storage system may distribute the test instruction set to the corresponding resource board to execute the test operation based on the address identifier carried by the test instruction set.

[0024] Specifically, the underlying hardware storage system sends the test instruction set with the same function to the instruction processing unit in one or more corresponding resource boards to perform the test operation. The number and type of instruction processing units in different resource boards can be different. The instruction processing unit can specifically include at least one of an analog waveform generation unit, an acquisition unit, a digital waveform generation unit, and a clamping unit. Taking the waveform generation instruction set as an example, the underlying hardware storage system can distribute the waveform generation instruction set to the analog waveform generation unit / digital waveform generation unit in different resource boards to perform waveform generation operations. For the same test requirements of different resource boards, the secondary loading of instructions can be avoided, thereby improving test efficiency.

[0025] In one embodiment, Figure 2 As shown, step S120 includes steps S122 to S126.

[0026] Step S122: After the underlying hardware storage system has cached all test instruction sets, it generates an instruction set loading completion flag. After the underlying hardware storage system has cached all test instruction sets, it generates an instruction set loading completion flag to notify the host computer of the completion of caching. The instruction set loading completion flag can be stored in the underlying hardware storage system or sent to the host computer for querying whether the test instruction set has been loaded.

[0027] Step S124: After the host computer retrieves the instruction set loading completion flag, it sends the instruction set execution flag to the underlying hardware storage system. After issuing the test instruction set, the host computer continues to query the instruction set loading completion flag, waiting for the instruction set loading to complete. After retrieval of the instruction set loading completion flag, the host computer sends the instruction set execution flag to the underlying hardware storage system, instructing the underlying hardware storage system to distribute the instruction set.

[0028] Step S126: After receiving the instruction set execution identifier, the underlying hardware storage system distributes the cached test instruction set to the corresponding resource board to execute the test operation. Upon receiving the instruction set execution identifier, the underlying hardware storage system initiates the test instruction set distribution operation, spontaneously distributing the instruction set to the resource board. The resource board sequentially executes the relevant instructions according to the instruction set, controlling the operation of the external hardware device. When executing instructions, the resource board does not need to be controlled by the host computer in real time, but independently controls the external hardware device, reducing the transmission of instructions and data back and forth with the host computer.

[0029] Step S130: The underlying hardware storage system caches the test results returned by each resource board after executing the corresponding test operation. After receiving the test instruction set, the resource board decodes the instruction set and controls the operation of the external hardware device based on the decoded instructions to perform the test operation on the device under test. The resource board also records the test results and stores them in the underlying hardware storage system. The test results are the results returned to the resource board by the device under test (DUT).

[0030] Step S140: After the host computer finds that the resource board has executed all received test instruction sets, it reads the corresponding test results cached in the underlying hardware storage system. Because the test functions of different resource boards are not exactly the same, different types of resource boards execute tests at different speeds, that is, different types of resource boards have inconsistent exit instruction execution times. After preloading all test instruction sets into the underlying hardware storage system, the host computer enters a query state. After finding that the resource board has executed all received test instruction sets, it reads the corresponding test results cached in the underlying hardware storage system.

[0031] Among them, the upper computer can read the corresponding test results cached in the underlying hardware storage system after querying that the corresponding resource board has executed all the received test instruction sets, that is, after a resource board has executed all the received test instruction sets, the test results of the resource board can be directly read without waiting for other resource boards to complete the test; the upper computer can also wait until all resource boards have been queried to execute all the received test instruction sets, and then uniformly read the test results returned by all resource boards cached in the underlying hardware storage system.

[0032] Furthermore, after step S140, the method may further include: the resource board reading back the test instruction sets that have already been tested from the underlying hardware storage system, and re-performing the corresponding test operations. Because all required test instruction sets are pre-loaded into the underlying hardware storage system, the resource board can repeatedly read back the test instruction sets and perform test operations as needed, eliminating the need for the host computer to resend the instruction sets. This also reduces the back-and-forth transmission of instructions and data to and from the host computer.

[0033] For the same resource board, the test operation is first executed according to the test instruction set, and the test results are returned to the cache of the underlying hardware storage system. Then, the resource board reads back the test instruction set that has already been executed in the underlying hardware storage system and executes the corresponding test operation again. Because different types of resource boards execute tests at different speeds, the different types of resource boards can execute the corresponding test operations according to the distributed / readback test instruction sets in parallel. In other words, the process of one resource board executing the corresponding test operation according to the distributed test instruction set and returning the test results to the underlying hardware storage system can be executed in parallel with the process of another type of resource board reading back the test instruction set, performing the corresponding test operation, and returning the test results to the underlying hardware storage system, thereby improving testing efficiency. For example, for different types of resource boards, such as a power board and a digital board, the power board executes the test faster. The process of the power board reading back the test instruction set and executing the test operation can be executed in parallel with the process of the underlying hardware storage system distributing the test instruction set to the digital board and the digital board executing the test operation.

[0034] like Figure 3 As shown, the underlying hardware storage system includes an instruction set storage unit and a result storage unit. The instruction set storage unit caches test instruction sets and, upon receiving test commands from a host computer, distributes the cached test instruction sets to the corresponding resource boards for test execution. The result storage unit caches the test results returned by each resource board after executing the corresponding test operations. A communication system is communicatively connected to the host computer and the resource management system, which is connected to the underlying hardware storage system. The resource management system is responsible for data management and interaction between the resource boards, preloading the test instruction sets issued by the host computer into the instruction set storage unit in the underlying hardware storage system, and uploading the corresponding test results cached in the result storage unit to the host computer. It should be noted that the instruction set storage unit and the result storage unit each belong to different storage spaces within the underlying hardware storage system. The communication system and resource management system can be combined to form a communication board, or the communication system can be the communication architecture of the host computer's underlying software, while the resource management system can independently constitute a communication board, or other systems capable of implementing data management and interaction. This is an example implementation method, and this application does not specifically limit this.

[0035] Traditional test machines transmit test instruction sets and test results back and forth between the host computer and the resource board. The host computer sends a test instruction set (such as CMD1) to the resource board, which returns a test result (such as RESULT1) to the host computer. The host computer then sends the next test instruction set (such as CMD2) to the resource board, which returns a test result (such as RESULT2) to the host computer. Each instruction is executed serially between the host computer and the resource board, resulting in a long and time-consuming process.

[0036] The instruction preprocessing method provided by this application is as follows: Figure 3 As shown, the host computer preloads all test instruction sets (such as CMD1 and CMD2) into an underlying hardware storage system independent of the resource boards. After receiving the test commands, the underlying hardware storage system distributes the test instruction sets to the downstream resource boards and caches the test results returned by the downstream resource boards. The host computer waits until a single or all resource boards have executed all received test instruction sets before reading the test results (such as RESULT1 and RESULT2). By preloading the test instruction sets (initialization instruction set, waveform generation instruction set, power supply configuration instruction set, power supply clamping instruction set, and alarm instruction set) into the underlying hardware storage system, they can be directly read and executed from the underlying hardware storage system during execution. This improves speed and reduces the instruction path, allowing for large-scale distribution and transmission, significantly improving efficiency. This also avoids long and arduous data transmission paths, minimizing the impact of external anomalies on instruction transmission.

[0037] In one embodiment, Figure 3 As shown, a test system is also provided, comprising a host computer, an underlying hardware storage system, and a resource board. The host computer is communicatively connected to the underlying hardware storage system, which is in turn connected to the resource board. The test system performs instruction preprocessing according to the above-described method. The resource board decodes the received test instruction set, controls the external hardware device to perform test operations based on the decoded instructions, records the test results, and stores the test results in the underlying hardware storage system. The resource board can also read back the test instruction set that has already been tested in the underlying hardware storage system and execute the corresponding test operation again.

[0038] Furthermore, the underlying hardware storage system includes an instruction set storage unit and a result storage unit. The instruction set storage unit caches the test instruction set and, upon receiving a test command from the host computer, distributes the cached test instruction set to the corresponding resource boards for test execution. The result storage unit caches the test results returned by each resource board after executing the corresponding test operation. Furthermore, the test system also includes a communication system and a resource management system. The communication system communicates with the host computer and the resource management system, and the resource management system is connected to the underlying hardware storage system.

[0039] In one embodiment, a command preprocessing method is provided, implemented on a host computer, comprising: preloading all test instruction sets required for testing into an underlying hardware storage system for caching; and, after querying that a resource board has executed all received test instruction sets, reading the corresponding test results cached in the underlying hardware storage system. Prior to testing a device under test (DUT), the host computer performs a preloading operation to load all test instruction sets required for testing into the underlying hardware storage system for caching. The test instruction sets may include at least one of an initialization instruction set, a waveform generation instruction set, a power configuration instruction set, a power clamp instruction set, and an alarm instruction set. The host computer may issue a test command to the underlying hardware storage system by sending an instruction or setting an identifier. The host computer may issue the test command to the underlying hardware storage system simultaneously with or after issuing the test instruction set. After recognizing the test command sent by the host computer, the underlying hardware storage system may distribute the test instruction set to the corresponding resource board for testing based on the address identifier carried in the test instruction set.

[0040] Specifically, after the upper computer compiles all the test programs, it translates them into a test instruction set executed by the resource board and sets a cache instruction set identifier. The cache instruction set identifier and the test instruction set are sent to the underlying hardware storage system together to inform the underlying hardware storage system to cache the received test instruction set first and not to distribute the instruction set temporarily. After sending the test instruction set, the upper computer keeps querying the instruction set loading completion identifier, waiting for the instruction set loading to be completed. After querying the instruction set loading completion identifier generated after the underlying hardware storage system has completed the caching of all test instruction sets, the upper computer sends the instruction set execution identifier to the underlying hardware storage system, instructing the underlying hardware storage system to distribute the instruction set.

[0041] After receiving the instruction set execution flag, the underlying hardware storage system initiates the test instruction set distribution operation, autonomously distributing the instruction set to the resource board. The resource board then sequentially executes the relevant instructions according to the instruction set, controlling the operation of the external hardware device. After receiving the test instruction set, the resource board decodes the instruction set and controls the operation of the external hardware device based on the decoded instructions, performing the test operation on the device under test. The resource board also records the test results and stores them in the underlying hardware storage system.

[0042] After the host computer preloads all the test instruction sets into the underlying hardware storage system at once, it is in a query state. After querying that the resource board has executed all the received test instruction sets, the host computer reads the corresponding test results cached in the underlying hardware storage system. Specifically, the host computer can read the corresponding test results cached in the underlying hardware storage system after querying that the corresponding resource board has executed all the received test instruction sets, that is, after a resource board has executed all the received test instruction sets, the host computer directly reads the test results of the resource board without waiting for other resource boards to complete the test; the host computer can also wait until all resource boards have been queried to have executed all the received test instruction sets, and then uniformly read the test results returned by all resource boards cached in the underlying hardware storage system.

[0043] It can be understood that the instruction preprocessing process of the host computer has been explained in detail in the previous article and will not be repeated here.

[0044] In one embodiment, an instruction preprocessing method is provided, which is implemented based on an underlying hardware storage system and includes: receiving all test instruction sets required for the test sent by the host computer and caching them; after receiving the test command sent by the host computer, distributing the cached test instruction sets to the corresponding resource boards to perform the test operations, and caching the test results returned by each resource board after performing the corresponding test operations. Before testing the device under test DUT, the host computer performs a preloading operation to load all test instruction sets required for the test into the underlying hardware storage system for caching. The test instruction set may include at least one of an initialization instruction set, a waveform generation instruction set, a power configuration instruction set, a power clamp instruction set, and an alarm instruction set. The underlying hardware storage system is a storage system independent of the resource board, and the underlying hardware storage system may include but is not limited to memories such as DDR or flash.

[0045] After the host computer compiles all test programs, it translates them into a test instruction set for the resource board to execute and sets a cache instruction set identifier. This identifier and the test instruction set are then sent to the underlying hardware storage system, instructing it to cache the received test instruction set and temporarily suspend distribution. After recognizing the test command sent by the host computer, the underlying hardware storage system can distribute the test instruction set to the corresponding resource board to execute the test operation based on the address identifier carried by the test instruction set.

[0046] In one embodiment, after caching all test instruction sets, the underlying hardware storage system generates an instruction set loading completion flag; after receiving the instruction set execution flag, the underlying hardware storage system distributes the cached test instruction sets to the corresponding resource boards to execute the test operations.

[0047] After the underlying hardware storage system completes the caching of all test instruction sets, it generates an instruction set loading completion flag to inform the host computer that the caching is complete. The instruction set loading completion flag can be stored in the underlying hardware storage system or sent to the host computer so that the host computer can query whether the test instruction set has been loaded. After issuing the test instruction set, the host computer keeps querying the instruction set loading completion flag, waiting for the instruction set to be loaded. After querying the instruction set loading completion flag, the host computer sends the instruction set execution flag to the underlying hardware storage system, instructing the underlying hardware storage system to distribute the instruction set. After receiving the instruction set execution flag, the underlying hardware storage system starts the test instruction set distribution operation and spontaneously distributes the instruction set to the resource board. The resource board executes the relevant instructions in sequence according to the instruction set to control the operation of the external hardware device. When executing instructions, the resource board does not need to be controlled by the host computer in real time, and can independently operate to control the external hardware device, reducing the transmission of instructions and data back and forth between the host computer.

[0048] Specifically, the underlying hardware storage system sends the test instruction set with the same function to the instruction processing unit in one or more corresponding resource boards to perform the test operation. The number and type of instruction processing units in different resource boards can be different. The instruction processing unit can specifically include at least one of an analog waveform generation unit, an acquisition unit, a digital waveform generation unit, and a clamping unit. Taking the waveform generation instruction set as an example, the underlying hardware storage system can distribute the waveform generation instruction set to the analog waveform generation unit / digital waveform generation unit in different resource boards to perform waveform generation operations. For the same test requirements of different resource boards, the secondary loading of instructions can be avoided, thereby improving test efficiency.

[0049] After receiving the test instruction set, the resource board decodes it and, based on the decoded instructions, controls the operation of external hardware devices to test the device under test. The resource board also records the test results and stores them in the underlying hardware storage system. The test results are the results returned by the device under test (DUT) to the resource board. After the host computer verifies that the resource board has executed all received test instruction sets, it reads the corresponding test results cached in the underlying hardware storage system.

[0050] Furthermore, the method may include: the resource board reading back the test instruction sets that have already been tested from the underlying hardware storage system and re-executing the corresponding test operations. Since all required test instruction sets are pre-loaded into the underlying hardware storage system, the resource board can repeatedly read back the test instruction sets and execute the test operations as needed, eliminating the need for the host computer to resend the instruction sets. This also reduces the back-and-forth transmission of instructions and data to and from the host computer.

[0051] For the same resource board, the test operation is first executed according to the test instruction set, and the test results are returned to the cache of the underlying hardware storage system. Then, the resource board reads back the test instruction set that has already been executed in the underlying hardware storage system and executes the corresponding test operation again. Because different types of resource boards execute tests at different speeds, the different types of resource boards can execute the corresponding test operations according to the distributed / readback test instruction sets in parallel. In other words, the process of one resource board executing the corresponding test operation according to the distributed test instruction set and returning the test results to the underlying hardware storage system can be executed in parallel with the process of another type of resource board reading back the test instruction set, performing the corresponding test operation, and returning the test results to the underlying hardware storage system, thereby improving testing efficiency. For example, for different types of resource boards, such as a power board and a digital board, the power board executes the test faster. The process of the power board reading back the test instruction set and executing the test operation can be executed in parallel with the process of the underlying hardware storage system distributing the test instruction set to the digital board and the digital board executing the test operation.

[0052] It is understandable that the instruction preprocessing process of the underlying hardware storage system has been explained in detail in the previous article and will not be repeated here.

[0053] The above instruction preprocessing method and test system have the following advantages: 1. The test instruction set is pre-loaded into the underlying hardware storage system, which saves the transmission time of the host computer and communication system when each instruction is executed. The instructions are directly read back and executed by the underlying hardware storage system.

[0054] 2. Storing the test instruction set in the underlying hardware storage system avoids system instability caused by external environment changes during instruction execution and improves communication stability; 3. Storing the test instruction set in the underlying hardware storage system can avoid reloading instructions for the same test requirements (i.e., the same test operations), thereby improving chip testing efficiency.

[0055] 4. Storing the test results in the underlying hardware storage system can facilitate the rapid recording of the results and save the time of immediate transmission back to the host computer.

[0056] In one embodiment, a computer device is provided, which may be a terminal. The computer device includes a processor, memory, an input / output interface, a communication interface, a display unit, and an input device. The processor, memory, and input / output interface are connected via a system bus, and the communication interface, display unit, and input device are connected to the system bus via the input / output interface. The processor of the computer device provides computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operating system and computer program stored in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and external devices. The communication interface of the computer device is used to communicate with external terminals via wired or wireless communication, which may be achieved via Wi-Fi, a mobile cellular network, NFC (near-field communication), or other technologies. When executed by the processor, the computer program implements an instruction preprocessing method. The display unit of the computer device is used to produce a visually visible image and may be a display screen, a projection device, or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the computer device casing, or an external keyboard, touchpad or mouse.

[0057] Those skilled in the art will understand that the structure of the above-mentioned computer device is merely a block diagram of a portion of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0058] In one embodiment, a computer device is provided, including a memory and a processor. The memory stores a computer program, and the processor implements the steps in the above method embodiments when executing the computer program.

[0059] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0060] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0061] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the above-mentioned embodiments. In particular, any reference to memory, database, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The databases involved in the various embodiments provided herein may include at least one of a relational database and a non-relational database. Non-relational databases may include, but are not limited to, distributed databases based on blockchains. The processors involved in the various embodiments provided herein may be, but are not limited to, general-purpose processors, central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), programmable logic devices (PLDs), data processing logic devices based on quantum computing, and the like.

[0062] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0063] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A method for preprocessing instructions, characterized in that: include: The host computer preloads all test instruction sets required for the test into the underlying hardware storage system for caching; After receiving the test command sent by the host computer, the underlying hardware storage system distributes the cached test instruction set to the corresponding resource board to perform the test operation; The underlying hardware storage system caches the test results returned after each resource board performs the corresponding test operation; After the host computer inquires that the resource board has executed all received test instruction sets, it reads the corresponding test results cached in the underlying hardware storage system.

2. The method according to claim 1, characterized in that The test instruction set includes at least one of an initialization instruction set, a waveform generation instruction set, a power configuration instruction set, a power clamping instruction set, and an alarm instruction set.

3. The method according to claim 1, characterized in that The step of the host computer preloading all test instruction sets required for the test into the underlying hardware storage system for caching includes: the host computer generates a test instruction set for execution by the resource board based on all compiled test programs, and sends the test instruction set and the configured cache instruction set identifier to the underlying hardware storage system; the cache instruction set identifier is used for the underlying hardware storage system to cache the received test instruction set.

4. The method according to claim 1, wherein After receiving the test command sent by the host computer, the underlying hardware storage system distributes the cached test instruction set to the corresponding resource board to perform the test operation, including: After all test instruction sets are cached, the underlying hardware storage system generates an instruction set loading completion flag; After querying the instruction set loading completion mark, the host computer sends the instruction set execution mark to the underlying hardware storage system; After receiving the instruction set execution identifier, the underlying hardware storage system distributes the cached test instruction set to the corresponding resource board to execute the test operation.

5. The method according to claim 4, characterized in that The underlying hardware storage system sends a test instruction set with the same function to the instruction processing unit in one or more corresponding resource boards to perform a test operation.

6. The method according to claim 5, characterized in that After the host computer inquires that the resource board has executed all received test instruction sets, the step of reading the corresponding test results cached in the underlying hardware storage system includes: After querying that the corresponding resource board has executed all received test instruction sets, the host computer reads the corresponding test results cached in the underlying hardware storage system; or After querying that all resource boards have executed all received test instruction sets, the host computer reads all test results cached in the underlying hardware storage system.

7. The method according to any one of claims 1 to 6, characterized in that After the host computer inquires that the resource board has executed all received test instruction sets, and then reads the corresponding test results cached in the underlying hardware storage system, the process further includes: The resource board reads back the test instruction set that has been tested in the underlying hardware storage system and executes the corresponding test operation again.

8. The method according to claim 7, characterized in that Different types of resource boards execute tests at different speeds, and the different types of resource boards execute corresponding test operations in parallel according to the distributed / readback test instruction sets.

9. A testing system, characterized in that: It includes a host computer, an underlying hardware storage system and a resource board card, the host computer is communicatively connected to the underlying hardware storage system, and the underlying hardware storage system is connected to the resource board card; the test system performs instruction preprocessing according to the method described in any one of claims 1 to 8.

10. The test system according to claim 9, characterized in that: The resource board decodes instructions according to the received test instruction set, controls the external hardware device to execute the test operation according to the decoded instructions, records the test results, and stores the test results in the underlying hardware storage system.

11. The test system according to claim 9, wherein: The underlying hardware storage system includes: An instruction set storage unit caches a test instruction set and distributes the cached test instruction set to corresponding resource boards to execute test operations after receiving a test command sent by the host computer; The result storage unit caches the test results returned after each resource board performs the corresponding test operation.

12. The test system according to claim 9, wherein: The resource board reads back the test instruction set that has been tested in the underlying hardware storage system and executes the corresponding test operation again.

13. The test system according to any one of claims 9 to 12, characterized in that: It also includes a communication system and a resource management system. The communication system is connected to the host computer and the resource management system, and the resource management system is connected to the underlying hardware storage system.

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