Feeder automation terminal board communication system

Abstract

The invention belongs to the technical field of feeder automation terminal equipment board communication, and particularly relates to a feeder automation terminal board communication system. The system comprises a main board piece and a slave board piece, the main board piece and the slave board piece are connected through a data line, and the slave board piece is connected with a CPU; wherein the main board piece is used for sending data; the slave plate is used for receiving data, detecting whether the received data is correct or not and transmitting a detection result to the CPU, the CPU determines whether to start a self-detection self-adaption function or not, and if the self-detection self-adaption function needs to be started, the slave plate adjusts a data phase according to the detection result and reduces data transmission errors; and the reliability of data transmission is obviously improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of feeder automation terminal equipment board communication, and in particular relates to a feeder automation terminal board communication system. Background Art

[0002] As a key monitoring device in the power system, grid feeder automation terminal equipment is deeply involved in the power transmission and distribution process, shouldering the core task of data collection and processing. It plays an irreplaceable role in ensuring the stable operation of the power system, specifically through its three key functions: real-time monitoring, fault isolation, and self-healing network construction. Through real-time data collection and processing, the equipment can accurately grasp the operating status of the power system, ensuring it remains in normal operation. When a fault occurs at the feeder terminal, the isolation mechanism can be quickly activated to effectively curb the spread of the fault and maintain the overall stability of the power grid. With the help of self-healing technology, the equipment can achieve autonomous repair of the monitoring network, ensure communication reliability, and significantly improve the overall reliability of the power system.

[0003] Feeder automation terminal equipment consists of multiple boards working together, with commands and data exchanged between boards via a bus. Currently, inter-board communication buses are primarily divided into two types: parallel and serial. Regardless of the bus used, the frequency and phase of the communication signal are rigorously tested and fixed before shipment, making it impossible to self-test and adapt to the actual field operating environment. This fixed communication parameter setting method limits the equipment's adaptability to complex and changing field environments and creates potential risks for subsequent system operation and maintenance.

[0004] Parallel buses have numerous drawbacks for inter-board communication in feeder automation terminal equipment. First, the use of multiple data lines for parallel transmission results in a large number of signal lines, which in turn takes up a significant amount of pins and wiring space, increasing system complexity and cost. Furthermore, the lack of self-detection and adaptive capabilities further increases the difficulty and time cost of debugging. Second, mutual interference between signal lines limits transmission speeds. To avoid signal attenuation and distortion, transmission speeds must be reduced to accommodate all situations. Furthermore, parallel buses place stringent demands on device transmission performance and circuit structure, making overall design difficult and further increasing system complexity and cost. Finally, the numerous signal lines and susceptibility to interference reduce the reliability of parallel buses, leading to frequent data transmission errors. Additional error detection and correction mechanisms are required to ensure data accuracy, and self-detection and adaptive adjustments are impossible when environmental changes cause persistent transmission errors.

[0005] Serial buses also have significant shortcomings in inter-board communication within feeder automation terminal equipment. For one thing, their transmission speed is relatively limited due to the bit-by-bit data transmission pattern. Furthermore, they lack the ability to self-detect and adapt when environmental changes cause persistent transmission errors. Summary of the Invention

[0006] In order to overcome the problems in the prior art, the present invention proposes a feeder automation terminal board communication system.

[0007] The technical solution of the present invention to solve the above technical problems is as follows: The present invention provides a feeder automation terminal board communication system, comprising a main board and a slave board, wherein the main board and the slave board are connected via a data line, and the slave board is connected to a CPU; Among them, the main board is used to send data; the slave board is used to receive data, detect whether the received data is correct, and pass the detection result to the CPU. The CPU decides whether to start the self-detection adaptive function. If the self-detection adaptive function needs to be started, the slave board adjusts the data phase according to the detection result.

[0008] Furthermore, the main board component adds a CRC check code after sending data.

[0009] Furthermore, the slave board includes an FPGA, and the FPGA includes a data receiving module, a signal detection module, a signal adjustment module and a register module; The data receiving module is used to receive data transmitted by the mainboard components; the signal detection module is used to detect the received data to determine whether it is correct and transmit the detection result to the CPU through the register module; the CPU decides whether to start the self-detection and adaptive function based on the detection result. If the self-detection and adaptive function needs to be started, the CPU configures the corresponding signal through the register module to start the self-detection and adaptive function; The signal adjustment module is used to complete signal detection and adaptive adjustment after the self-detection adaptive function is started.

[0010] Furthermore, the signal detection module compares the CRC check code in the received data with the check code calculated by the received data. If they are inconsistent, the error counter value is increased by 1, and the CPU reads the error counter value. If the error counter value exceeds the preset threshold, it is determined that there is a problem with the communication and the self-detection and adaptive function needs to be started.

[0011] Furthermore, the startup self-detection adaptive function includes: Compare the received clock signal with the preset normal test data signal. If they are inconsistent, or the clock signal changes irregularly, it is determined that there is a problem with the clock signal. If the clock signal does not need to be adjusted, the received control signal is compared with the preset control signal. If they are inconsistent, it is determined that there is a problem with the control signal; If the clock signal and the control signal do not need to be adjusted, the received data signal is compared with the preset data signal. If they are inconsistent, it is determined that there is a problem with the data signal.

[0012] Furthermore, it is determined that there is a problem with the clock signal, and the adjustment method includes: The FPGA calls the internal phase delay module to generate a clock signal delay of 1 as the clock signal for collecting data signals. The CPU starts the self-detection and adaptive function to detect the collected data signal and determine whether the collected data signal is correct. If not, the above process is repeated. If correct, the clock signal delay value at this time is recorded and determined as the minimum clock delay value. Generate clock signal delays 2 to n in sequence, and execute the self-detection and self-adaptation function in sequence; if the collected data signal is incorrect after executing the self-detection and self-adaptation function using clock signal delay n, determine that the maximum clock signal delay that can correctly complete data signal collection is n-1, record the clock signal delay value at this time, and determine it as the maximum clock delay value; According to the middle value algorithm, the middle value of the clock delay is calculated as (minimum clock delay value + maximum clock delay value) / 2. The calculated middle value of the clock delay is fixed and used as the adjusted optimal clock signal.

[0013] Furthermore, it is determined that there is a problem with the control signal, and the adjustment method includes: If the control signal is advanced, the FPGA calls the internal phase delay module to generate a control signal delay of 1 as the control signal for the collected data signal. The CPU starts the self-detection and adaptive function to detect the collected data signal and determine whether the collected data signal is correct. If not, the above process is repeated. If correct, the control signal delay value at this time is recorded and determined as the minimum control delay value. Generate control signal delays 2 to n in sequence, and execute the self-detection and self-adaptation function in sequence; when executing the self-detection and self-adaptation function using control signal delay n, if a data signal error is detected, determine that the maximum control signal delay that can correctly complete data signal acquisition is n-1, record the control signal delay value at this time, and determine it as the maximum control delay value; According to the intermediate value algorithm, the control intermediate value = (control minimum delay value + control maximum delay value) / 2 is calculated, and the calculated control intermediate value is fixed as the adjusted optimal control signal.

[0014] Furthermore, it is determined that there is a problem with the control signal, and the adjustment method includes: If the transmission delay of the control signal relative to other signals is greater than a preset threshold, the clock signal is delayed, and a clock signal delay of 1 is generated as the clock signal for collecting the data signal. The CPU starts a self-detection and adaptive function to detect the collected data signal to determine whether the collected data signal is correct. If not, the above process is repeated. If correct, the clock signal delay value at this time is recorded and determined as the minimum clock delay value; clock signal delays 2 to n are generated in sequence, and the self-detection and adaptive function is executed in sequence; if the collected data signal is incorrect after the self-detection and adaptive function is executed using clock signal delay n, it is determined that the maximum clock signal delay that can correctly complete the data signal collection is n-1, the clock signal delay value at this time is recorded, and determined as the maximum clock delay value; According to the middle value algorithm, the middle value of the clock delay is calculated as (minimum clock delay value + maximum clock delay value) / 2. The calculated middle value of the clock delay is fixed as the adjusted optimal clock signal.

[0015] Furthermore, it is determined that there is a problem with the data signal, and the adjustment method includes: determining that a problem occurs with one of the data signals and that the data signal is ahead of the other data signals, and then deciding to adjust the delay of the data signal; The FPGA calls the internal phase delay module to generate a data signal delay of 1, which is used as the data signal. The FPGA determines whether the data signal is correct. If not, the above process is repeated. If correct, the data signal delay of 1 is recorded as the minimum delay value. Repeat the above process to gradually generate data signal delay 2, data signal delay 3, ... data signal delay n, and use the newly generated delay signal as the data signal each time; when the self-detection and adaptive function is completed using data signal delay n, the collected data signal is incorrect, and the maximum delay value that can correctly complete data collection is determined to be data signal delay n-1, and this value is recorded; According to the median value algorithm, the data signal median value = (data signal minimum delay value + data signal maximum delay value) / 2 is calculated; the calculated data signal median value is fixed as the adjusted optimal data signal.

[0016] Compared with the prior art, the present invention has the following technical effects: This invention introduces a self-detection and adaptive function. When environmental changes cause persistent transmission errors, it can detect and adjust parameters such as data phase, effectively improving the device's adaptability in complex field environments and reducing communication failures caused by environmental factors. After the self-detection and adaptive function is activated, the system can detect and adjust the clock signal, control signal, and data signal separately. This adaptive adjustment mechanism can optimize signal parameters based on actual communication conditions, reduce the impact of signal interference and attenuation, and reduce the occurrence of data transmission errors, significantly improving data transmission reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions and advantages of the embodiments of the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 It is a schematic diagram of the overall structure of the present invention; Figure 2 This is the timing diagram of each signal under ideal conditions; Figure 3 This is the timing diagram when there is a problem with the clock signal; Figure 4 This is the timing diagram for the first problem of the control signal; Figure 5 This is the timing diagram for the first problem of data signal 0; Figure 6 This is a workflow diagram for the self-detection and adaptive function; Figure 7 Adjust the timing diagram of the clock signal when there is a problem with the clock signal; Figure 8 This is the block diagram of the entire system; Figure 9 This is the timing diagram for adjusting the clock signal when the first problem occurs with the control signal; Figure 10 This is the timing diagram for the second problem of the control signal; Figure 11 Control signal adjustment timing diagram for the second control signal problem; Figure 12 Data signal 0 adjustment timing diagram for the first problem of data signal 0; Figure 13 This is the timing diagram for the second problem of data signal 0; Figure 14 This is the control signal adjustment timing diagram for the second problem of data signal 0; Figure 15 Adjustment timing diagram of data signal 1 for the second problem of data signal 0; Figure 16 The timing diagram of data signal 2 adjustment for the second problem of data signal 0 is shown; Figure 17 The timing diagram for adjusting data signal 3 when the second problem occurs with data signal 0. DETAILED DESCRIPTION

[0019] To further illustrate the technical means and effects employed by the present invention to achieve its intended purpose, the following, in conjunction with the accompanying drawings and preferred embodiments, describes in detail the specific implementations, structures, features, and effects of the technical solutions proposed by the present invention. Specific features, structures, or characteristics in one or more embodiments may be combined in any suitable manner. Unless otherwise defined, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present invention pertains.

[0020] In this embodiment, referring to Figures 1-17 , provides a feeder automation terminal board communication system, including a main board and a slave board, the main board and the slave board are connected via a data line, and the slave board is connected to a CPU; Among them, the main board is used to send data; the slave board is used to receive data, detect whether the received data is correct, and pass the detection result to the CPU. The CPU decides whether to start the self-detection adaptive function. If the self-detection adaptive function needs to be started, the slave board adjusts the data phase according to the detection result.

[0021] In this embodiment, communication between the master and slave boards utilizes six equal-length wires: one clock line, one control line, and four data lines. This data channel is unidirectional, meaning it can only be transmitted from the master to the slave boards. The master controls the output of clock, control, and data signals, and the slave boards receive data signals based on the clock and control signals transmitted from the master.

[0022] In this embodiment, in order to prevent problems in data or command transmission caused by environmental changes or interference, a CRC check is added after each set of transmitted data; at the same time, the CRC check result also provides a reference for the CPU to determine whether the FPGA needs to start self-detection and adaptive tasks.

[0023] In this embodiment, the slave board includes an FPGA, and there are four modules inside the FPGA to complete the self-detection and adaptive process. The four modules are a data receiving module, a signal detection module, a signal adjustment module, and a register module. The data receiving module is used to receive data transmitted by the master board; the signal detection module is used to detect the received data to determine whether it is correct and transmit the detection result to the CPU through the register module; the CPU decides whether to start the self-detection and adaptive function based on the detection result. If the self-detection and adaptive function needs to be started, the CPU configures the corresponding signal through the register module to start the self-detection and adaptive function; the signal adjustment module is used to complete signal detection and adaptive adjustment after the self-detection and adaptive function is started. Among them, the CPU configures the corresponding signal through the register module, including: the CPU changes a register value inside the FPGA through a write operation, and the FPGA starts the self-detection and adaptive function after detecting that the register value is a signal to start the self-detection and adaptive function.

[0024] Specifically, the signal detection module compares the CRC checksum in the received data with the checksum calculated from the received data. If they are inconsistent, it indicates a communication problem between the boards. The FPGA increments the error counter by 1, and the CPU periodically reads the error counter value. If the error counter value changes too quickly or exceeds a preset threshold, it is determined that a communication problem has occurred and the self-detection and adaptive function needs to be activated. The error counter value is an internal signal of the FPGA that can be accumulated and copied to a register. The CPU can then read this register value to determine the error counter value.

[0025] The master and slave boards use the same calculation formula to generate CRC checksums. As the master sends data, it continuously generates CRC checksums using the data it sends until the last data is sent. The resulting CRC checksum is then sent to the slave board. As the slave board receives data, it uses the data it receives to generate CRC checksums, continuing to generate CRC checksums until the last data is received. Because the master and slave boards use the same calculation formula, the resulting CRC checksums are also identical. Communication issues between the boards can lead to different checksums.

[0026] After starting the self-test adaptive function, the FPGA will automatically generate test data for related adjustments. These test times are changed according to the rising edge of the clock signal. The initial value is all 0. After starting the test, the data changes from all 0 to all 1 on the rising edge of the clock signal, and then changes from all 1 to all 0 on the next rising edge of the clock signal, and so on. Because the board design process will use the same length design of the data line, and before leaving the factory, it will be Figure 2The timing shown in the figure is used to set the signal. The clock used is 100MHz, and the maximum delay for each signal adjustment is set to one clock cycle, that is, 10ns. If the signal delay exceeds 10ns, the corresponding adaptive process is stopped. Generally, the delay of the signal with problems does not exceed one clock cycle.

[0027] When the self-detection adaptive function is started, it first determines whether the clock signal needs to be adjusted. The received clock signal is compared with the preset normal test data signal. If they are inconsistent, it is determined that there is a problem with the clock signal and the clock signal needs to be adjusted. Otherwise, the clock signal does not need to be adjusted. Figure 2 As shown, the preset normal test data signal sequence is 4'h0, 4'hf, 4'h0, 4'hf, etc. Figure 3 As shown in the figure, the falling edge of the clock signal is exactly at the edge of the data change, which will cause the collected data to be unstable. If the received clock signal shows irregular changes, such as 4'h0, 4'h2, 4'hc, 4'hf, etc., it is considered that the received clock signal is unstable and it is determined that there is a problem with the clock signal.

[0028] If the clock signal does not need to be adjusted, then continue to determine whether the control signal needs to be adjusted, compare the received control signal with the preset control signal, if they are inconsistent, then determine that the control signal needs to be adjusted, and make relevant adjustments; after the control signal is adjusted, perform relevant verification; if the control signal verification is successful, then exit directly and notify the CPU that the self-test and self-adaptation are completed. If the control signal verification is unsuccessful, then continue to perform relevant detection and adjustment. Figure 4 As shown, the first signal collected is 4'h0, but the first signal actually received is 4'hf, followed by 4'h0, 4'hf, and 4'h0 in sequence. This indicates a problem with the control signal, which is caused by a significant delay in the control signal transmission relative to other signals. The verification process includes using the adjusted control signal as the control signal, continuously receiving data, and comparing the data.

[0029] If the clock signal and control signal do not need to be adjusted, then determine whether the data signal needs to be adjusted, compare the received data signal with the preset data signal, if they are inconsistent, the data signal needs to be adjusted, and then make corresponding adjustments; perform relevant verification on the adjusted data signal, if the verification is successful, exit directly, and notify the CPU that the self-test and self-adaptation are complete, if the verification is unsuccessful, continue to perform relevant tests and adjustments. The whole process is repeated until the entire self-test and self-adaptation are completed. Figure 5 As shown, the received data signals are 4'h1, 4'he, 4'h1, 4'he alternately in sequence, so it can be determined that there is a problem with the first data signal.

[0030] In a specific embodiment, referring to Figure 2 and Figure 3 If a problem with the clock signal is detected, adjustments are required: the phase delay module within the signal adjustment module is called from the FPGA of the board to generate a clock signal delay of 1 as the clock signal for collecting data signals. The CPU activates the self-detection and adaptive function to detect the collected data signal and determine whether the collected data signal is correct. If not, the above process is repeated. If correct, the clock signal delay value at this time is recorded and determined as the minimum clock delay value. Clock signal delays 2 to n are generated in sequence, and the self-detection and adaptive function is executed in sequence. If the collected data signal is incorrect after executing the self-detection and adaptive function using clock signal delay n, the maximum clock signal delay that can correctly complete data signal collection is determined to be n-1. The clock signal delay value at this time is recorded and determined as the maximum clock delay value. According to the median value algorithm, the median clock delay value is calculated as (minimum clock delay value + maximum clock delay value) / 2. The calculated median clock delay value is fixed as the adjusted optimal clock signal.

[0031] like Figure 4 As shown, the first signal that should be collected is 4'h0, but the first signal actually received is 4'hf, followed by 4'h0, 4'hf, and 4'h0 alternately. It is determined that there is a problem with the control signal. This is because the transmission delay of the control signal is too large compared to other signals.

[0032] Because the received control signal cannot be processed in advance, it can only be processed later, so the solution is Figure 4 To solve the problem, other signals need to be delayed accordingly. First, delay the clock signal, such as Figure 9 The figure shows a clock signal delay scenario. Clock signal delay 1 is generated as the clock signal for data signal acquisition. The CPU activates the self-detection and adaptive function, checks the acquired data signal, and determines whether it is correct. If not, the above process is repeated. If correct, the clock signal delay value at that point is recorded and determined as the minimum clock delay value. Clock signal delays 2 through n are generated sequentially, and the self-detection and adaptive function is executed sequentially. If, after executing the self-detection and adaptive function using clock signal delay n, the acquired data signal is incorrect, the maximum clock signal delay that can correctly complete data signal acquisition is determined to be n - 1. The clock signal delay value at that point is recorded and determined as the maximum clock delay value. Using the median value algorithm, the median clock delay is calculated as (minimum clock delay + maximum clock delay) / 2. This calculated median clock delay value is fixed and used as the adjusted optimal clock signal. The self-detection and adaptive function then exits.

[0033] Regarding the above situation where self-detection and self-adaptation can be completed by delaying only the clock signal, although self-detection and self-adaptation are finally completed, since the data signal is not delayed, it cannot be guaranteed that the collected data signal is in the middle of the data.

[0034] Figure 10 The second problematic case of the control signal is shown, Figure 10 As you can see, the first data received is 4'h0, the second data is also 4'h0, and then it is 4'hf, 4'h0, and 4'hf alternately. In this case, you only need to adjust the control signal. Figure 11 , the FPGA calls the internal phase delay module to generate a control signal delay 1 as the control signal for collecting data signals. The CPU starts the self-detection and adaptive function to detect the collected data signals and determine whether the collected data signals are correct. If not, the above process is repeated. If correct, the control signal delay value at this time is recorded and determined as the minimum control delay value; control signal delays 2 to n are generated in sequence, and the self-detection and adaptive function is executed in sequence; when the self-detection and adaptive function is executed using control signal delay n, if the collected data signal is incorrect, it is determined that the maximum control signal delay that can correctly complete data signal collection is n-1, and the control signal delay value at this time is recorded and determined as the maximum control delay value; according to the intermediate value algorithm, the control intermediate value is calculated as (minimum control delay value + maximum control delay value) / 2, and the calculated control intermediate value is fixed as the adjusted optimal control signal, and the self-detection and adaptive functions are exited.

[0035] Figure 5 As shown, it is observed that the received signals are 4'h1, 4'he, 4'h1, 4'he in turn, judging that there is a problem with data signal 0. It is found that data signal 0 is ahead of other signals, so it is decided to adjust the delay of data signal 0. Figure 12The FPGA calls the internal phase delay module to generate Data Signal 0 Delay 1, which is used as Data Signal 0. It then determines whether Data Signal 0 is correct. If not, it repeats the above process. If correct, it records Data Signal 0 Delay 1 as the minimum delay value. It repeats this process, gradually generating Data Signal 0 Delay 2, Data Signal 0 Delay 3, and so on, each time using the newly generated delay signal as Data Signal 0. When using Data Signal 0 Delay n to complete the self-detection and adaptive function, if the collected data signal is incorrect, the maximum delay value that can correctly complete data acquisition is determined to be Data Signal Delay n-1, and this value is recorded. Using the median algorithm, the median value of Data Signal 0 is calculated as (Minimum Data Signal Delay + Maximum Data Signal Delay) / 2. The calculated median value is fixed as the optimal data signal after adjustment. This completes the adjustment of the Data Signal 0 delay, and the self-detection and adaptive functions exit.

[0036] Figure 13 As shown, the first data received is 4'h0, followed by 4'he, 4'h1, and 4'he, which appear alternately. Figure 5 Different, it is determined that data signal 0 is delayed relative to other signals, and data signal 0 cannot be directly advanced, but other signals can only be delayed. Figure 14 As shown, the control signal is first delayed to generate control signal delay 1, which is used as the control signal for data acquisition. The CPU starts the self-detection and adaptive function to detect the acquired data signal to determine whether the acquired data signal is correct. If not, the above process is repeated. If correct, the control signal delay value at this time is recorded and determined as the minimum control delay value. Control signal delays 2 to n are generated in sequence, and the self-detection and adaptive function is performed in sequence. After the self-detection and adaptive function is performed using control signal delay n, if the acquired data signal is incorrect, it is determined that the maximum control signal delay that can correctly complete data signal acquisition is n-1, and the control signal delay value at this time is recorded and determined as the maximum control delay value. According to the intermediate value algorithm, the control intermediate value is calculated as (minimum control delay value + maximum control delay value) / 2, and the calculated control intermediate value is fixed as the adjusted optimal control signal.

[0037] Using the same method as the control signal delay method, data signal 1 is delayed, as shown in FIG15 . Data signal 1 delay 1 is generated and used as data signal 1. Whether data signal 1 is correct is determined. If not, the above process is repeated. If correct, data signal 1 delay 1 is recorded as the minimum delay value. The minimum delay value that meets the requirements is recorded. The delay of data signal 1 is gradually increased to generate data signal 1 delay 2, data signal 1 delay 3, and so on. Data signal 1 delay n is tested in sequence until a data acquisition error occurs. The maximum delay value (data signal 1 delay n - 1) that can correctly complete data acquisition at this time is recorded. The optimal data signal 1 delay value is calculated and determined: according to the median value algorithm, (data signal 1 minimum delay value + data signal 1 maximum delay value) / 2 is calculated. The median value is assumed to be data signal 1 delay m1. Data signal 1 delay m1 is fixed and used as data signal 1.

[0038] like Figure 16 As shown, data signal 2 is delayed using the same method as data signal 1. Data signal 2 with different delay values is generated, and the minimum and maximum delay values of data signal 2 that meet the requirements are recorded. The delay m2 of data signal 2 is calculated by (minimum delay m2 + maximum delay m2) / 2, and this delay m2 is fixed and used as data signal 2.

[0039] Data Signal 3 Delay Processing: As shown in Figure 17 , Data Signal 3 is delayed using the same method as Data Signal 1 and Data Signal 2. Data Signal 3 with different delay values is generated. The minimum and maximum delay values that meet the requirements are recorded. The delay m3 of Data Signal 3 is calculated as (Minimum Delay of Data Signal 3 + Maximum Delay of Data Signal 3) / 2, and this delay m3 is fixed for use as Data Signal 3.

[0040] After adjusting and testing the delays of the control signal, data signal 1, data signal 2, and data signal 3, the optimal control signal delay m, data signal 1 delay m1, data signal 2 delay m2, and data signal 3 delay m3 were ultimately determined. In subsequent data reception, the adjusted optimal delay values are used, namely, the optimal control signal delay m, data signal 1 delay m1, data signal 2 delay m2, and data signal 3 delay m3, respectively, as the corresponding signals.

[0041] After enabling the self-detection and adaptive function, the system can independently detect and adjust the clock, control, and data signals. For example, for the clock signal, the self-detection and adaptive function is performed by generating clock signals with different delays to determine the optimal intermediate clock delay value. Similar adjustments are also made for the control and data signals. This adaptive adjustment mechanism optimizes signal parameters based on actual communication conditions, reduces the impact of signal interference and attenuation, and reduces the occurrence of data transmission errors, significantly improving data transmission reliability.

[0042] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included in the scope of protection of the present invention.

Claims

1. A feeder automation terminal board communication system, characterized in that: It includes a main board and a slave board, wherein the main board and the slave board are connected via a data line, and the slave board is connected to the CPU; Among them, the main board is used to send data; the slave board is used to receive data, detect whether the received data is correct, and pass the detection result to the CPU. The CPU decides whether to start the self-detection adaptive function. If the self-detection adaptive function needs to be started, the slave board adjusts the data phase according to the detection result.

2. A feeder automation terminal board communication system according to claim 1, characterized in that: The main board component adds a CRC check code after sending data.

3. A feeder automation terminal board communication system according to claim 2, characterized in that: The slave board includes an FPGA, and the FPGA includes a data receiving module, a signal detection module, a signal adjustment module and a register module; The data receiving module is used to receive data transmitted by the mainboard components; the signal detection module is used to detect the received data to determine whether it is correct and transmit the detection result to the CPU through the register module; the CPU decides whether to start the self-detection and adaptive function based on the detection result. If the self-detection and adaptive function needs to be started, the CPU configures the corresponding signal through the register module to start the self-detection and adaptive function; The signal adjustment module is used to complete signal detection and adaptive adjustment after the self-detection adaptive function is started.

4. A feeder automation terminal board communication system according to claim 3, characterized in that: The signal detection module compares the CRC check code in the received data with the check code calculated by the received data. If they are inconsistent, the error counter value is increased by 1. The CPU reads the error counter value. If the error counter value exceeds the preset threshold, it is determined that there is a problem with the communication and the self-detection and adaptive function needs to be started.

5. A feeder automation terminal board communication system according to claim 4, characterized in that: The startup self-detection adaptive function includes: Compare the received clock signal with the preset normal test data signal. If they are inconsistent, or the clock signal changes irregularly, it is determined that there is a problem with the clock signal. If the clock signal does not need to be adjusted, the received control signal is compared with the preset control signal. If they are inconsistent, it is determined that there is a problem with the control signal; If the clock signal and the control signal do not need to be adjusted, the received data signal is compared with the preset data signal. If they are inconsistent, it is determined that there is a problem with the data signal.

6. A feeder automation terminal board communication system according to claim 5, characterized in that: If there is a problem with the clock signal, the adjustment methods include: The FPGA calls the internal phase delay module to generate a clock signal delay of 1 as the clock signal for collecting data signals. The CPU starts the self-detection and adaptive function to detect the collected data signal and determine whether the collected data signal is correct. If not, the above process is repeated. If correct, the clock signal delay value at this time is recorded and determined as the minimum clock delay value. Generate clock signal delays 2 to n in sequence, and execute the self-detection and self-adaptation function in sequence; if the collected data signal is incorrect after executing the self-detection and self-adaptation function using clock signal delay n, determine that the maximum clock signal delay that can correctly complete data signal collection is n-1, record the clock signal delay value at this time, and determine it as the maximum clock delay value; According to the middle value algorithm, the middle value of the clock delay is calculated as (minimum clock delay value + maximum clock delay value) / 2. The calculated middle value of the clock delay is fixed and used as the adjusted optimal clock signal.

7. A feeder automation terminal board communication system according to claim 5, characterized in that: If there is a problem with the control signal, the adjustment methods include: If the control signal is advanced, the FPGA calls the internal phase delay module to generate a control signal delay of 1 as the control signal for the collected data signal. The CPU starts the self-detection and adaptive function to detect the collected data signal and determine whether the collected data signal is correct. If not, the above process is repeated. If correct, the control signal delay value at this time is recorded and determined as the minimum control delay value. Generate control signal delays 2 to n in sequence, and execute the self-detection and self-adaptation function in sequence; when executing the self-detection and self-adaptation function using control signal delay n, if a data signal error is detected, determine that the maximum control signal delay that can correctly complete data signal acquisition is n-1, record the control signal delay value at this time, and determine it as the maximum control delay value; According to the intermediate value algorithm, the control intermediate value = (control minimum delay value + control maximum delay value) / 2 is calculated, and the calculated control intermediate value is fixed as the adjusted optimal control signal.

8. The feeder automation terminal board communication system according to claim 5, characterized in that: If there is a problem with the control signal, the adjustment methods include: If the transmission delay of the control signal relative to other signals is greater than a preset threshold, the clock signal is delayed, and a clock signal delay of 1 is generated as the clock signal for collecting the data signal. The CPU starts a self-detection and adaptive function to detect the collected data signal to determine whether the collected data signal is correct. If not, the above process is repeated. If correct, the clock signal delay value at this time is recorded and determined as the minimum clock delay value; clock signal delays 2 to n are generated in sequence, and the self-detection and adaptive function is executed in sequence; if the collected data signal is incorrect after the self-detection and adaptive function is executed using clock signal delay n, it is determined that the maximum clock signal delay that can correctly complete the data signal collection is n-1, the clock signal delay value at this time is recorded, and determined as the maximum clock delay value; According to the middle value algorithm, the middle value of the clock delay is calculated as (minimum clock delay value + maximum clock delay value) / 2. The calculated middle value of the clock delay is fixed as the adjusted optimal clock signal.

9. A feeder automation terminal board communication system according to claim 5, characterized in that: If there is a problem with the data signal, the adjustment methods include: determining that a problem occurs with one of the data signals and that the data signal is ahead of the other data signals, and then deciding to adjust the delay of the data signal; The FPGA calls the internal phase delay module to generate a data signal delay of 1, which is used as the data signal. The FPGA determines whether the data signal is correct. If not, the above process is repeated. If correct, the data signal delay of 1 is recorded as the minimum delay value. Repeat the above process to gradually generate data signal delay 2, data signal delay 3, ... data signal delay n, and use the newly generated delay signal as the data signal each time; when the self-detection and adaptive function is completed using data signal delay n, the collected data signal is incorrect, and the maximum delay value that can correctly complete data collection is determined to be data signal delay n-1, and this value is recorded; According to the median algorithm, the median value of the data signal is calculated as (minimum delay value of the data signal + maximum delay value of the data signal) / 2; the calculated median value of the data signal is fixed as the adjusted optimal data signal.

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