Security test system, method and device for multi-core chip

Abstract

The invention provides a security test system, method and device for a multi-core chip. The system comprises a multi-core chip, an interconnection channel and a core control module, the multi-core chip comprises at least two chip cores with different security levels; the interconnection channel is used for providing a data interaction channel between the at least two chip cores with different security levels, and multiple security mechanisms are built in the interconnection channel; and the core control module is arranged at the top layer of the chip, is connected with an external test device to receive a test instruction, selectively tests the at least two chip cores with different security levels according to the test instruction, and sends test results of the at least two chip cores with different security levels to the external test device.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of integrated circuit testing technology, and in particular to a security testing system, method, and device for a multi-core chip. Background Art

[0002] With the continuous development of chip technology, the use of multi-core chips is becoming more and more common, especially multi-core chips that include chip core architectures with different security levels are widely used in many scenarios with high security requirements (such as automotive electronics, industrial control, financial payment, etc.).

[0003] In the process of implementing this application, the inventors discovered that most of the existing chip testing solutions are aimed at single-core chips of the same level or do not fully consider the special needs of interconnection and testing between dual-core chips of different security levels, resulting in low testing efficiency and inability to ensure the security of multi-core chips during operation and testing. Summary of the Invention

[0004] The embodiments of the present application provide a security testing system, method, and device for a multi-core chip.

[0005] According to a first aspect of an embodiment of the present application, a security testing system for a multi-core chip is provided, the system comprising a multi-core chip, an interconnection channel, and a core control module;

[0006] The multi-core chip includes at least two chip cores with different security levels;

[0007] The interconnection channel is used to provide a data interaction channel between the at least two chip cores with different security levels, and the interconnection channel has multiple security mechanisms built in;

[0008] The core control module is set at the top layer of the chip and is connected to an external testing device to receive test instructions, and selectively tests the at least two chip cores with different security levels according to the test instructions, and sends the test results of the at least two chip cores with different security levels to the external testing device.

[0009] Optionally, the at least two chip cores with different security levels include a first type chip core with a high security level and a second type chip core with a low security level;

[0010] Wherein, the first type of chip core is integrated with a preset security mechanism;

[0011] A basic function test result statistics module is integrated in the second-type chip core; and the test circuits of the first-type chip core and the second-type chip core are physically isolated from each other.

[0012] Optionally, the at least two chip cores with different security levels include a first type chip core with a high security level and a second type chip core with a low security level;

[0013] The core control module is further configured to perform a self-test during a system initialization phase, initialize the test circuits of the first-type chip core and the second-type chip core, and load default test parameters.

[0014] According to a second aspect of an embodiment of the present application, a security testing method for a multi-core chip is provided, the method comprising:

[0015] Receive test instructions sent by external test equipment;

[0016] performing selective testing on at least two chip cores of different security levels included in the multi-core chip according to the test instruction;

[0017] The test results of the at least two chip cores with different security levels are sent to the external testing equipment.

[0018] Optionally, the at least two chip cores with different security levels include a first type chip core with a high security level and a second type chip core with a low security level;

[0019] The selective testing of the at least two chip cores with different security levels according to the test instruction includes at least one of the following:

[0020] If the test instruction is a test request for a first type of chip core, performing a test process on the first type of chip core;

[0021] If the test instruction is a test request for the second type of chip core, performing a test process on the second type of chip core;

[0022] If the test instruction is a synchronous test request for the first type chip core and the second type chip core, a synchronous test process is performed on the first type chip core and the second type chip core.

[0023] Optionally, if the test instruction is a test request for a first-type chip core, performing a test process on the first-type chip core includes:

[0024] If the test instruction is a test request for a first-category chip core, determining whether the test request is a first test request for the first-category chip core;

[0025] If the test request is the first test request for the first type of chip core, use the pre-made key to perform security authentication, and generate a test key after the security authentication passes, and start the test process of the first type of chip core based on the test key;

[0026] If the test request is not the first test request for the first type of chip core, the test key generated during the first test request is used to start the test process of the first type of chip core.

[0027] Optionally, if the test instruction is a synchronous test request for a first-category chip core and a second-category chip core, performing a synchronous test process on the first-category chip core and the second-category chip core includes:

[0028] If the test instruction is a synchronous test request for the first type of chip core and the second type of chip core, the test of the first type of chip core and the second type of chip core is started at the same time, and the first type of chip core and the second type of chip core coordinate the test progress through the synchronization signal to complete their respective test processes within the specified time.

[0029] Optionally, the process of testing the first type of chip core includes:

[0030] Starting the test circuit of the first-type chip core, performing function and performance testing on the first-type chip core, and transmitting the test results to the test result statistics module for statistics; wherein the test instructions, data during the function and performance testing of the first-type chip core, and the test results are all stored and transmitted in an encrypted manner;

[0031] The process of testing the second type of chip core includes:

[0032] The test circuit of the second-type chip core is started to perform function and performance testing on the second-type chip core, and the test results are transmitted to the test result statistics module for statistics.

[0033] Optionally, the security authentication adopts encryption authentication.

[0034] Optionally, the test key is generated using a one-chip-one-key strategy and is only passed to the test circuit when the first test request starts the test process.

[0035] According to a third aspect of an embodiment of the present application, a security testing device for a multi-core chip is provided, the device comprising:

[0036] A receiving unit, receiving a test instruction sent by an external test device;

[0037] a testing unit, configured to selectively test at least two chip cores of different security levels included in the multi-core chip according to the test instruction;

[0038] The feedback unit sends the test results of the at least two chip cores with different security levels to the external testing equipment.

[0039] According to a fourth aspect of the embodiments of the present application, there is provided an electronic device, including:

[0040] processor;

[0041] a memory for storing processor-executable instructions;

[0042] The processor is configured to perform any of the above methods.

[0043] This embodiment of the application provides a security testing solution for multi-core chips in virtual machines running on resource-constrained devices. The core control module parses test instructions and selectively tests chip cores based on their security levels. Only test instructions with the appropriate permissions can initiate the test process for the first-class, high-security chip cores, thus resolving the issue of simultaneous testing of cores at different security levels. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 This is a schematic diagram of a security testing system for a dual-core chip provided in one embodiment of the present application;

[0045] Figure 2 is a schematic diagram of a security testing system for a multi-core chip provided by another embodiment of the present application;

[0046] Figure 3 This is a flow chart of a security testing method for a multi-core chip provided by an embodiment of the present application;

[0047] Figure 4 This is a schematic diagram of the structure of a security testing device for a multi-core chip provided in one embodiment of the present application;

[0048] Figure 5 1 is a schematic diagram of the structure of a security testing device for a multi-core chip provided in one embodiment of the present application. DETAILED DESCRIPTION

[0049] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0050] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. As used in this application and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0051] It should be understood that although the terms first, second, third, etc. may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0052] As application scenarios increase, more and more multi-core chips require testing. However, different chip cores have different security levels, and existing chip testing solutions are mostly designed for single-core chips of the same level or fail to fully consider the interconnection and testing requirements between dual-core chips with different security levels. Therefore, when testing multi-core chips with varying security levels, it's difficult to balance test efficiency and security. For example, testing all chip cores without protection to ensure efficiency creates security risks. Designing all chip cores in a highly secure mode to guarantee security also introduces design redundancy, increasing testing costs and reducing test efficiency.

[0053] In view of this, the present application aims to propose a security testing solution for multi-core chips that can balance security, cost and efficiency, so as to solve the problem that cores with different security levels cannot be tested in parallel at the same time.

[0054] The following describes the security testing system, method, and device for multi-core chips provided by this application.

[0055] First, a security testing system for a multi-core chip is introduced, which may include a multi-core chip, an interconnection channel, and a core control module;

[0056] The multi-core chip includes at least two chip cores with different security levels;

[0057] The interconnection channel is used to provide a data interaction channel between the at least two chip cores with different security levels, and the interconnection channel has multiple security mechanisms built in;

[0058] The core control module is set at the top layer of the chip and is connected to an external testing device to receive test instructions, and selectively tests the at least two chip cores with different security levels according to the test instructions, and sends the test results of the at least two chip cores with different security levels to the external testing device.

[0059] In this system, the at least two chip cores with different security levels can include a first-class chip core with a high security level and a second-class chip core with a low security level. The core control module is also used to perform a self-test during the system initialization phase (to ensure that the chip is in a test state), initialize the test circuits of the first-class chip core and the second-class chip core, and load default test parameters. This initialization lays the foundation for subsequent stable testing. The specific testing process will be described in subsequent embodiments.

[0060] The above test system differs from the traditional test system in that:

[0061] On the one hand, the system of the present application provides an interconnection channel, and data is exchanged between the first type of chip core and the second type of chip core through a dedicated interconnection channel. The interconnection channel can have built-in multiple security mechanisms such as encryption and verification to ensure that the data transmission process is not stolen or tampered with, and meet the strict requirements of data flow between chip cores of different security levels.

[0062] Furthermore, the core control module includes a built-in permissions management unit. Based on pre-defined rules, only test instructions with the appropriate permissions can initiate the test process for high-security, Category I chip cores. This prevents security risks posed by misoperation or illegal testing of high-security chip cores. This permission management provides reliable testing security for chip cores, especially high-security cores.

[0063] On the other hand, each chip core has an independently integrated test circuit. The test circuits for the first-category chip cores are designed for their high security levels and include pre-set security mechanisms. These provide the first-category chip cores with stronger cryptographic algorithm verification and deep fault detection capabilities, used to test the chip core's logical functions and security mechanism execution. The test circuits for the second-category chip cores are relatively streamlined, but include basic functional test result statistics modules to meet the testing requirements for their general performance. The test circuits for the first and second-category chip cores are physically isolated from each other and do not interfere with each other during operation. The test process is synchronized and coordinated only through the top-level core control module. This independent and coordinated test circuit design ensures efficient and accurate testing.

[0064] The multi-core chip in this application may include a dual-core chip with two chip cores and a multi-core chip with more than two chip cores. Figure 1 Figure 1 shows a schematic diagram of a dual-core chip security testing system. The system 10 includes a dual-core chip (i.e., a first-class chip core 12 with a high security level and a second-class chip core 13 with a low security level), an interconnection channel (not shown), and a core control module 11. For ease of description, in the following embodiments, the first-class chip core 12 is referred to as core A, and the second-class chip core 13 is referred to as core B.

[0065] like Figure 1 As shown, the core control module 11 may include a receiving and sending module 111 , a stream encryption module 112 and a test result statistics module 113 .

[0066] The receiving and sending module 111 is used to send and receive test instructions and data with external test equipment, and to communicate with core A and core B;

[0067] The stream encryption and decryption module 112 is responsible for encrypting and decrypting data when communicating with the core A, thereby ensuring that the data is not leaked. For example, the stream encryption and decryption module 112 can use a stream encryption algorithm to encrypt and decrypt data to meet the real-time requirements of data.

[0068] The test result statistics module 113 is responsible for integrating the test results, test data and other related data of each chip core, such as core A and core B, into a specific format and sending it to the external test equipment via the receiving and sending module 111.

[0069] like Figure 1 As shown, core A with a high security level may include a stream encryption module 121 , a security authentication module 122 , an instruction decoding module 123 , a random key generation module 123 , a test circuit 125 and a test control module 126 .

[0070] The stream encryption module 121 cooperates with the stream encryption / decryption module 112 in the core control module 11 to implement encryption / decryption operations for test instructions and related data transmitted between the core control module 11 and core A. For example, the stream encryption / decryption module 112 locally encrypts the test instructions and sends them to the stream encryption module 121, which then decrypts the encrypted test instructions for use in subsequently initiating the test process for core A. For another example, the stream encryption module 121 locally encrypts the test results and returns them to the stream encryption / decryption module 112, which then decrypts the encrypted test results.

[0071] It is understandable that the aforementioned interconnection channel can implement multiple security mechanisms such as encryption and verification based on the mutual cooperation of the stream encryption module 121 and the stream encryption and decryption module 112 to ensure that the data transmission process is not stolen or tampered with.

[0072] The instruction decoding module 123 is responsible for parsing the test instructions issued by the core control module 11 and sending the parsed commands or data to the test control module 126 .

[0073] The security authentication module 122 is responsible for performing security authentication using the initial key during the first communication between the core control module 11 and core A. After the security authentication is passed, the module can obtain the permission to modify the initial key. The modified key can be generated by the random key product module 124. The modified password is used to start the current test process and the test process of subsequent new test instructions. Therefore, the modified password can be called a test key. In addition, if the security authentication fails, the stream encryption module 121 can be notified to return the authentication failure and close the communication between the core control module 11 and core A.

[0074] It is worth mentioning that the security authentication method of Core A can use encryption methods such as digital certificates and signature verification to prevent the injection of illegal test instructions and protect the dual-core chip testing process from external malicious attacks.

[0075] The random key generation module 124 is used to receive the key update instruction initiated by the security authentication module 122, and randomly generate a set of new keys for stream encryption transmission. The random mechanism can use true random numbers or PUF (physical unclonable function) technology to achieve one-chip one-key, thereby improving security.

[0076] The core control module 126 is used to receive instructions and data sent by the instruction decoding module 123 and test the test circuit 125 .

[0077] The test circuit 125 is the part to be tested in the core A, and its composition can be analog circuit, digital circuit, etc.

[0078] like Figure 1 As shown, the core B with a low security level includes an instruction decoding module 131, a test control module 132 and a test circuit 133; the instruction decoding module 131 is responsible for parsing the test instructions issued by the core control module 11, and sending the parsed commands or data to the test control module 132; the core control module 126 is used to receive the instructions and data sent by the instruction decoding module 131, and test the test circuit 133; the test circuit 133 is the part to be tested in the core B, and its composition can be an analog circuit, a digital circuit, etc.

[0079] As can be seen from the above embodiment, the different security measures employed by high-security chip core 12 and low-security chip core 13 in system 10 ensure data security and system reliability during testing. Furthermore, through the coordination of core control module 11, dual-core synchronous testing is achieved, improving testing efficiency.

[0080] Next, we will introduce a schematic diagram of a multi-core chip security test system. Figure 1System 10 is essentially the same, including a core control module 11, a high-security first-class chip core 12, and a low-security second-class chip core 13, all with the same functions and components. System 20 differs from system 10 in the number of chip cores. System 10 is a dual-core chip with only one first-class chip core 12 and one first-class chip core 13; system 20 has multiple first-class chip cores 12 and multiple first-class chip cores 13.

[0081] Since each first-class chip core 12 in system 20 is identical to the first-class chip core 12 in system 10, reference may be made to the description of the first-class chip core 12 in system 10, and no further details will be given here. Similarly, each second-class chip core 13 in system 20 is identical to the second-class chip core 13 in system 10, and reference may be made to the description of the second-class chip core 13 in system 10, and no further details will be given here.

[0082] Similar to the aforementioned dual-core chip testing, the multi-core chip testing system utilizes different security measures for high-security chip cores 12 and low-security chip cores 13, ensuring data security and system reliability during testing. Simultaneously, through the coordination of the core control module 11, synchronous testing of multiple cores is achieved, improving testing efficiency. This multi-core parallel collaborative testing system not only meets the testing requirements for cores with different security levels, but also effectively balances security and cost.

[0083] After introducing the security test system for multi-core chips, please refer to Figure 3 The flowchart of the security testing method of multi-core chips is further introduced. The method can be applied but not limited to Figure 1 or Figure 2 The system shown. The multi-core chip security testing method may include the following steps:

[0084] Step 310: receiving a test instruction sent by an external test device;

[0085] Step 320: performing selective testing on at least two chip cores of different security levels included in the multi-core chip according to the test instruction;

[0086] Step 330: Send the test results of the at least two chip cores with different security levels to the external testing equipment.

[0087] In an exemplary embodiment, the at least two chip cores with different security levels include a first type chip core with a high security level and a second type chip core with a low security level; accordingly, step 320 may include at least one of the following:

[0088] S1: If the test instruction is a test request for a first type of chip core, then perform a test process on the first type of chip core;

[0089] S2: If the test instruction is a test request for the second type of chip core, then perform a test process on the second type of chip core;

[0090] S3: If the test instruction is a synchronous test request for the first type of chip core and the second type of chip core, a synchronous test process is performed on the first type of chip core and the second type of chip core.

[0091] With the aforementioned Figure 1 Taking core A and core B shown as an example, after receiving the test instruction sent by the external test equipment, the core control module first parses the test instruction to determine whether it is a test request for core A (high security level) or core B (low security level), or a synchronous test request for the two cores.

[0092] S1 may further include:

[0093] If the test instruction is a test request for a first-category chip core, determining whether the test request is a first test request for the first-category chip core;

[0094] If the test request is the first test request for the first type of chip core, use the initial key to perform security authentication, and generate a test key after the authentication is passed, and start the test process of the first type of chip core based on the test key;

[0095] If the test request is not the first test request for the first type of chip core, the test key generated during the first test request is used to start the test process of the first type of chip core.

[0096] In this embodiment, only test instructions with corresponding permissions can start the test process for the first type of chip core with a high security level, preventing misoperation or illegal testing from causing security risks to the high security level chip core. This permission management provides reliable test security protection for chip cores, especially high security level cores.

[0097] Continue with Figure 1 Taking core A in the example, if the test instruction is for core A, it is necessary to further determine whether it is the first communication with the core. The first communication requires the use of an initial key for security authentication; the security authentication can use encryption methods such as digital certificates and signature verification to prevent illegal test instruction injection and protect the dual-core chip test process from external malicious attacks.

[0098] If security authentication is passed, permission to modify the initial key is granted. The modified key is called a test key. This test key is generated using a one-core-one-key strategy and is only transmitted to the test circuit of core A upon the initial test request, initiating the test process for core A. The test circuit performs functional and performance testing on core A using a pre-set test vector sequence. The test data is fed back to the stream encryption module in real time for encryption and transmission to the test result statistics module in the core control module for statistical analysis.

[0099] Multiple high-security cores can repeat the above process to establish communication. When there are multiple first-class chip cores, they can share an initial key and a corresponding test key, or each first-class chip core can use a different initial key and generate a corresponding different test key.

[0100] Exemplarily, S2 may further include:

[0101] The test circuit of the second-type chip core is started to perform function and performance testing on the second-type chip core, and the test results are transmitted to the test module for statistics.

[0102] Continue with Figure 1 Taking core B in the example, the testing process of core B is relatively simple and does not require the same safety mechanism as core A. The core control module interacts directly with core B.

[0103] If the test instruction targets core B, the test instruction can be directly sent to start the test process of the test circuit of core B. The test circuit performs functional and performance tests on the chip core according to the preset test vector sequence, and the test results are directly transmitted to the test result statistics module for statistics.

[0104] Exemplarily, S3 may further include:

[0105] If the test instruction is a synchronous test request for the first type of chip core and the second type of chip core, the test of the first type of chip core and the second type of chip core is started at the same time, and the first type of chip core and the second type of chip core coordinate the test progress through the synchronization signal to complete their respective test processes within the specified time.

[0106] Continue with Figure 1For example, if the test instruction requests simultaneous testing of cores A and B, the core control module must coordinate the simultaneous activation of the test circuits for cores A and B. The test process for core A, as further described in S1, requires security authentication, and all data, including test instructions, test data, and test results, must be encrypted for storage and transmission to meet the security requirements of high-security chip cores like core A. The test process for core B, as further described in S2, does not require the same security mechanisms as core A and can be initiated directly.

[0107] Core A and core B maintain relative coordination of test progress through the synchronization signal set by the core control module at the top level of the chip, ensuring that their respective test tasks are completed within the specified time. Finally, the test results of the multi-core chip are integrated and fed back to the external test equipment. This fine control of multi-core synchronous testing can greatly improve test efficiency and safety.

[0108] Corresponding to the aforementioned multi-core chip security test method embodiment, the present application also provides a multi-core chip security test device embodiment. The device embodiment can be implemented by software, or by hardware or a combination of software and hardware. Taking software implementation as an example, as a device in a logical sense, it is formed by the processor of the device in which it is located reading the corresponding computer program in the non-volatile memory into the memory and running it. From the hardware level, such as Figure 4 As shown in the figure, it is a hardware structure diagram of the device where the multi-core chip security test device in this application is located. Figure 4 In addition to the processor, network interface, memory and non-volatile memory shown, the device in which the apparatus in the embodiment is located may also include other hardware according to the actual communication function, which will not be described in detail.

[0109] See Figure 5 , is a module diagram of a multi-core chip security testing device provided by an embodiment of the present application, the device corresponds to Figure 3 In the embodiment shown, the device comprises:

[0110] The receiving unit 510 receives a test instruction sent by an external test device;

[0111] A testing unit 520 selectively tests at least two chip cores of different security levels included in the multi-core chip according to the test instruction;

[0112] The feedback unit 530 sends the test results of the at least two chip cores with different security levels to the external testing equipment.

[0113] Optionally, the at least two chip cores with different security levels include a first type chip core with a high security level and a second type chip core with a low security level;

[0114] The testing unit 520 includes at least one of the following:

[0115] a first testing subunit, configured to perform a testing process on a first type of chip core if the testing instruction is a testing request for the first type of chip core;

[0116] a second testing subunit, configured to perform a testing process on the second-type chip core if the test instruction is a test request for the second-type chip core;

[0117] The third testing sub-unit performs a synchronous testing process on the first type of chip core and the second type of chip core if the test instruction is a synchronous testing request for the first type of chip core and the second type of chip core.

[0118] Optionally, the first testing subunit includes:

[0119] If the test instruction is a test request for a first-category chip core, determining whether the test request is a first test request for the first-category chip core;

[0120] If the test request is the first test request for the first type of chip core, use the pre-made key to perform security authentication, and generate a test key after the security authentication passes, and start the test process of the first type of chip core based on the test key;

[0121] If the test request is not the first test request for the first type of chip core, the test key generated during the first test request is used to start the test process of the first type of chip core.

[0122] Optionally, the third testing subunit includes:

[0123] If the test instruction is a synchronous test request for the first type of chip core and the second type of chip core, the test of the first type of chip core and the second type of chip core is started at the same time, and the first type of chip core and the second type of chip core coordinate the test progress through the synchronization signal to complete their respective test processes within the specified time.

[0124] Optionally, in the first testing subunit, the testing process for the first type of chip core includes:

[0125] Starting the test circuit of the first-type chip core, performing function and performance testing on the first-type chip core, and transmitting the test results to the test result statistics module for statistics; wherein the test instructions, data during the function and performance testing of the first-type chip core, and the test results are all stored and transmitted in an encrypted manner;

[0126] In the second test sub-unit, a test process is performed on the second type of chip core, including:

[0127] The test circuit of the second-type chip core is started to perform function and performance testing on the second-type chip core, and the test results are transmitted to the test result statistics module for statistics.

[0128] Optionally, the security authentication adopts encryption authentication.

[0129] Optionally, the test key is generated using a one-chip-one-key strategy and is only passed to the test circuit when the first test request starts the test process.

[0130] The systems, devices, modules, or units described in the above embodiments may be implemented by computer chips or entities, or by products having certain functions. A typical implementation device is a computer, which may be in the form of a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email transceiver, game console, tablet computer, wearable device, or any combination of these devices.

[0131] The implementation process of the functions and effects of each unit in the above-mentioned device is specifically described in the implementation process of the corresponding steps in the above-mentioned method, and will not be repeated here.

[0132] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to the partial description of the method embodiments. The device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present application scheme. A person of ordinary skill in the art can understand and implement it without paying any creative work.

[0133] above Figure 5 This article describes the internal functional modules and structural schematic of a multi-core chip security testing device. Its actual execution subject can be an electronic device, including:

[0134] processor;

[0135] a memory for storing processor-executable instructions;

[0136] The processor is configured to execute any of the above-mentioned embodiments of the security testing method for a multi-core chip.

[0137] In the embodiment of the above-mentioned electronic device, it should be understood that the processor can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. The general-purpose processor can be a microprocessor or any conventional processor, etc., and the aforementioned memory can be a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk, or a solid-state drive. The steps of the method disclosed in the embodiment of the present invention can be directly embodied as being executed by a hardware processor, or can be executed by a combination of hardware and software modules in the processor.

[0138] The various embodiments in this application are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the electronic device embodiment is generally similar to the method embodiment, so the description is relatively simple. For relevant parts, refer to the partial description of the method embodiment.

[0139] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0140] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A multi-core chip security testing system, characterized in that: Including multi-core chips, interconnection channels and core control modules; The multi-core chip includes at least two chip cores with different security levels; The interconnection channel is used to provide a data interaction channel between the at least two chip cores with different security levels, and the interconnection channel has multiple security mechanisms built in; The core control module is set at the top layer of the chip and is connected to an external testing device to receive test instructions, and selectively tests the at least two chip cores with different security levels according to the test instructions, and sends the test results of the at least two chip cores with different security levels to the external testing device.

2. The system according to claim 1, wherein: The at least two chip cores of different security levels include a first type chip core of a high security level and a second type chip core of a low security level; Wherein, the first type of chip core is integrated with a preset security mechanism; A basic function test result statistics module is integrated in the second-type chip core; and the test circuits of the first-type chip core and the second-type chip core are physically isolated from each other.

3. The system according to claim 1, wherein: The at least two chip cores of different security levels include a first type chip core of a high security level and a second type chip core of a low security level; The core control module is further configured to perform a self-test during a system initialization phase, initialize the test circuits of the first-type chip core and the second-type chip core, and load default test parameters.

4. A security testing method for a multi-core chip, characterized in that: include: Receive test instructions sent by external test equipment; performing selective testing on at least two chip cores of different security levels included in the multi-core chip according to the test instruction; The test results of the at least two chip cores with different security levels are sent to the external testing equipment.

5. The method according to claim 4, characterized in that The at least two chip cores of different security levels include a first type chip core of a high security level and a second type chip core of a low security level; The selective testing of the at least two chip cores with different security levels according to the test instruction includes at least one of the following: If the test instruction is a test request for a first type of chip core, performing a test process on the first type of chip core; If the test instruction is a test request for the second type of chip core, performing a test process on the second type of chip core; If the test instruction is a synchronous test request for the first type chip core and the second type chip core, a synchronous test process is performed on the first type chip core and the second type chip core.

6. The method according to claim 5, characterized in that If the test instruction is a test request for a first type of chip core, performing a test process on the first type of chip core includes: If the test instruction is a test request for a first-category chip core, determining whether the test request is a first test request for the first-category chip core; If the test request is the first test request for the first type of chip core, use the pre-made key to perform security authentication, and generate a test key after the security authentication passes, and start the test process of the first type of chip core based on the test key; If the test request is not the first test request for the first type of chip core, the test key generated during the first test request is used to start the test process of the first type of chip core.

7. The method according to claim 5, characterized in that If the test instruction is a synchronous test request for the first type chip core and the second type chip core, performing a synchronous test process on the first type chip core and the second type chip core includes: If the test instruction is a synchronous test request for the first type of chip core and the second type of chip core, the test of the first type of chip core and the second type of chip core is started at the same time, and the first type of chip core and the second type of chip core coordinate the test progress through the synchronization signal to complete their respective test processes within the specified time.

8. The method according to claim 5, characterized in that The process of testing the first type of chip core includes: Starting the test circuit of the first-type chip core, performing function and performance testing on the first-type chip core, and transmitting the test results to the test result statistics module for statistics; wherein the test instructions, data during the function and performance testing of the first-type chip core, and the test results are all stored and transmitted in an encrypted manner; The process of testing the second type of chip core includes: The test circuit of the second-type chip core is started to perform function and performance testing on the second-type chip core, and the test results are transmitted to the test result statistics module for statistics.

9. The method according to claim 6, characterized in that The security authentication adopts encryption authentication.

10. The method according to claim 6, characterized in that The test key is generated using a one-chip-one-key strategy and is only passed to the test circuit when the first test request starts the test process.

11. A security testing device for a multi-core chip, characterized in that: The device comprises: A receiving unit, receiving a test instruction sent by an external test device; a testing unit, configured to selectively test at least two chip cores of different security levels included in the multi-core chip according to the test instruction; The feedback unit sends the test results of the at least two chip cores with different security levels to the external testing equipment.

12. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; The processor is configured to execute the method according to any one of claims 4 to 10.

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