Chip integration system, method, equipment and medium

Abstract

The invention provides a chip integration system, method and device and a medium, which are applied to a to-be-integrated chip, and the to-be-integrated chip comprises a plurality of sub-modules. Comprising an input system, an analysis system and a connection system, the input system is configured to: receive configuration information; the configuration information comprises the name, the interface information and the connection information of each sub-module and the preset layer number of the to-be-integrated chip; the analysis system is configured to read the configuration information, and determine the hierarchy to which each sub-module belongs according to the name and the connection information of the sub-module; classifying the sub-modules according to the levels to which the sub-modules belong; and the connection system is configured to read configuration information and integrate each sub-module according to the interface information, so as to solve the problems that each sub-module in the current integrated chip needs to be manually integrated, so that the integration error of each sub-module may occur and the integration efficiency is low when the chip is integrated.

Description

Technical Field

[0001] The present application relates to the field of chip design technology, and in particular to a chip integration system, method, device and medium. Background Art

[0002] In the field of chip design, with the rapid development of integrated circuit technology, the complexity and integration of chips are constantly increasing. When chip engineers integrate chips, they need to write a large amount of code to describe the functions, connections, and interface definitions of each module in the chip to complete the chip integration work.

[0003] Currently, the industry has developed a number of technologies to assist with chip integration programming, primarily through the use of tool-embedded plug-ins. For example, commonly used text editing tools like vim or emacs can be installed with corresponding embedded plug-ins. These plug-ins often feature automatic programming capabilities, allowing engineers to set specific instructions and have the plug-in automatically generate portions of code. In terms of chip integration, plug-ins can instantiate individual modules within the chip according to pre-set rules, adding module instances to the chip design file, laying the foundation for subsequent chip integration.

[0004] However, currently, the integration of each submodule within a chip requires manual integration, which can lead to integration errors and low integration efficiency. Secondly, on-demand definition of module interfaces is not currently supported. During the chip design process, different modules may require different interfaces based on actual needs, making it impossible to flexibly adapt to various complex interface requirements, limiting the flexibility and scalability of chip design. Summary of the Invention

[0005] The present application provides a chip integration system, method, device and medium to solve the technical problem that the various sub-modules in the current integrated chip need to be manually integrated, resulting in possible integration errors of the various sub-modules during chip integration and low integration efficiency.

[0006] In a first aspect, the present application provides a chip integration system, which is applied to a chip to be integrated, wherein the chip to be integrated includes a plurality of sub-modules; including:

[0007] Input system, parsing system, connection system;

[0008] The input system is configured to:

[0009] Receive configuration information; the configuration information includes: the name of each sub-module, interface information, and connection information;

[0010] The parsing system is configured to:

[0011] Read the configuration information and determine the level to which each submodule belongs based on the name and connection information of the submodule;

[0012] Classify the submodules according to the levels to which they belong;

[0013] The connection system is configured to:

[0014] The configuration information is read, and the submodules are integrated according to the interface information.

[0015] In some embodiments, the input system is further configured to:

[0016] receiving functional information of the chip to be integrated;

[0017] According to the functional information, interface information of each of the submodules is determined.

[0018] In some embodiments, the input system is further configured to:

[0019] Determine the function information of the submodule according to the name of the submodule;

[0020] Generate a formulation plan based on the role information; the formulation plan includes: interface information and connection information of each of the submodules and functional information of the chip to be integrated;

[0021] The functional information of the integrated chip obtained by integrating the interface information and connection information of different sub-modules is different.

[0022] In some embodiments, the parsing system is further configured to:

[0023] Reading the configuration information, inputting the connection information of each submodule into a setting template, and generating an executable file; the setting template is configured with a setting script, and the setting template is configured to fill the connection information into the setting script;

[0024] The connection system is further configured to:

[0025] The executable file is read, and each of the submodules is integrated according to the interface information.

[0026] In some embodiments, the parsing system is further configured to:

[0027] The configuration information is read, and the base submodule of the submodule is determined according to the name and connection information of the submodule; and the base submodule determines the submodules of each level step by step until the top submodule.

[0028] In some embodiments, the connection system is further configured to:

[0029] According to the connection information, the base submodule and the submodules of the adjacent layers are integrated according to the interface information, and the base submodule integrates the submodules of each layer step by step until the top submodule.

[0030] In some embodiments, the system further comprises:

[0031] A verification system, the verification system being configured to:

[0032] After the connection system completes the integration of each of the sub-modules, the integrated chip is subjected to functional verification and structural verification to generate a verification report; the functional verification is configured to determine whether the interface information of each of the sub-modules matches the functional information of the chip to be integrated; the structural verification is configured to determine whether the interface information integrated by each sub-module matches the connection information of each of the sub-modules; the verification report includes: verification pass information or verification failure information and the corresponding failure reason.

[0033] A second aspect of the present application provides a chip integration method, which is applied to a chip integration system according to any one of the first aspects above, comprising:

[0034] Receive configuration information; the configuration information includes: the name of each submodule, interface information, and connection information;

[0035] Read the configuration information and determine the level to which each submodule belongs based on the name and connection information of the submodule;

[0036] Classify the submodules according to the levels to which they belong;

[0037] The configuration information is read, and the submodules are integrated according to the interface information.

[0038] A third aspect of the present application provides an electronic device, comprising a processor and a memory, wherein the memory is used to store at least one program, and the at least one program is loaded by the processor and executed by a chip integration method as described in the second aspect.

[0039] A fourth aspect of the present application is a computer-readable storage medium, characterized in that at least one program is stored in the computer-readable storage medium, and the at least one program is loaded and executed by a processor to implement a chip integration method as described in the second aspect.

[0040] The present application provides a chip integration system, method, device and medium, which are applied to a chip to be integrated, wherein the chip to be integrated includes multiple sub-modules; including: an input system, a parsing system, and a connection system; the input system is configured to: receive configuration information; the configuration information includes: the name, interface information, and connection information of each of the sub-modules; the parsing system is configured to: read the configuration information, and determine the level to which each of the sub-modules belongs based on the name and connection information of the sub-modules; and classify the sub-modules according to the level to which they belong; the connection system is configured to: read the configuration information, and integrate each of the sub-modules based on the interface information, so as to reduce the error rate when connecting each sub-module during chip integration and improve chip integration efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solution of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0042] Figure 1 This is a schematic diagram of the structure of the chip integration system in this application;

[0043] Figure 2 This is a schematic diagram of the structure of the verification system in this application;

[0044] Figure 3 This is a schematic diagram of the distribution of each submodule in this application within its own hierarchy;

[0045] Figure 4 This is a schematic diagram of the structure of the integrated chip in this application.

[0046] Description of reference numerals:

[0047] 1-Input system; 2-Parsing system; 3-Connection system; 4-Verification system. DETAILED DESCRIPTION

[0048] In order to enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0049] For example, the current technology for assisting chip integrated programming can only instantiate modules, but cannot automatically connect the various modules in the chip. After instantiating the modules, chip engineers still need to manually connect the modules, which increases the complexity of programming and the risk of errors. Secondly, the plug-in does not support on-demand definition of module interfaces. In chip design, the definition of module interfaces often needs to be adjusted according to specific application scenarios and requirements. However, current plug-ins can usually only support fixed interface definition methods and cannot meet the flexible needs of engineers. Among them, instantiation refers to the process of inserting a predefined module (such as module B) into another module (such as module A). Module B exists in module A as an "instance", and module A can access the ports and functions of module B through this instance.

[0050] Because in some technologies, the integration of various sub-modules in a chip requires manual integration, which may result in integration errors of various sub-modules and low integration efficiency during chip integration. To address this technical problem, the present application provides a chip integration system, method, device, and medium. The chip integration system, method, device, and medium are described below:

[0051] like Figure 1 As shown, it is a structural diagram of the chip integration system in this application.

[0052] In response to the above problems, the first aspect of the present application provides a chip integration system, which is applied to a chip to be integrated, wherein the chip to be integrated includes multiple sub-modules; including:

[0053] Input system 1, parsing system 2, connection system 3; the input system 1, parsing system 2, connection system 3 are communicatively connected and can negotiate information.

[0054] The input system 1 is configured as follows:

[0055] Receive configuration information; the configuration information includes: the name, interface information, and connection information of each sub-module; the configuration information uses the JSON file format with good readability; use the flexible Python language to complete the extraction and classification of the configuration information; the configuration information is defined in advance according to the function of the integrated chip and input into the input system.

[0056] The analysis system 2 is configured to:

[0057] The configuration information is read, and the level to which each submodule belongs is determined based on the name and connection information of the submodule; the submodules are classified according to the level to which they belong. Because each submodule has a corresponding name and the connection information of each submodule is fixed, the position of each submodule in the integrated chip is fixed, and the level to which each submodule belongs can be determined in advance through the parsing system 2. The submodules in the chip are classified by level (such as digital logic layer, analog hybrid layer, interface control layer, power management layer, etc.), and each submodule is classified into the corresponding level based on its name and connection information.

[0058] Specifically, such as Figure 3 As shown, if the connection relationship between sub-modules A, B, C, and D is known, such as sub-module A is connected to sub-modules B and C, and sub-module B is connected to sub-module D, it is determined that the level of the chip to be integrated includes three layers.

[0059] like Figure 3 The figure shows the distribution of each submodule in the present application within its corresponding level.

[0060] Specifically, if the chip to be integrated includes four submodules A, B, C, and D, Figure 3 As shown, the preset number of layers of the chip to be integrated is 3 layers, the bottom layer is module A, the middle layer is module B and module C, and the top layer is module D. According to the above arrangement, the analysis system 2 can classify the corresponding sub-modules into the corresponding levels of each sub-module according to the sub-module name, in preparation for the subsequent integration of each sub-module.

[0061] The connection system 3 is configured as follows:

[0062] The configuration information is read, and each of the submodules is integrated according to the interface information.

[0063] For example, in the existing chip integration process, interface information is often hard-coded into the chip architecture at the beginning of chip design, forming a fixed configuration mode. Although this mode simplifies the design process to a certain extent, it also brings many problems: 1. Limited design flexibility: Fixed interface configuration is difficult to adapt to the diverse needs of different application scenarios, such as different communication protocols, data transmission rates or power management requirements. 2. Increased risk of integration errors: When the chip needs to interface with an external device or system, if the interface standard of the external device does not match the preset interface of the chip, a complex adaptation layer design or external conversion circuit is required, which increases the risk of errors in the integration process. 3. The various sub-modules in the chip cannot be automatically connected.

[0064] Specifically, in response to the above problems, the present application provides a chip integration system that reads configuration information and dynamically determines the interface information of each sub-module according to actual needs. The specific steps are as follows: 1. Configuration information reading: First, through a configuration tool or script, read the configuration information of the chip, including but not limited to the name of each sub-module, interface information, connection information, and the preset number of layers of the chip to be integrated. 2. Interface information parsing and mapping: In-depth analysis of the read configuration information is performed to extract key information related to the chip interface, such as interface type, pin assignment, etc. Then, these interface information are mapped to the various sub-modules inside the chip to clarify which interfaces each sub-module contains and the position of the interface in the overall chip architecture.

[0065] Specifically, after determining the interface information of each sub-module, it is necessary to flexibly integrate each sub-module according to the interface information based on the connection information. The specific practical methods are as follows: 1. Connection information acquisition and parsing: Obtain connection information from the configuration information, including the connection relationship, connection path, connection method (such as direct connection, connection through bus, etc.) and electrical parameters required for connection (such as voltage, current, impedance matching, etc.) between sub-modules. 2. Sub-module connection strategy formulation: Based on the connection information and actual needs, formulate the connection strategy for each sub-module. 3. Sub-module integration and verification: According to the formulated connection strategy, integrate each sub-module according to the interface information to complete the automatic connection of each sub-module.

[0066] In this embodiment, the input system 1 is further configured as follows:

[0067] Receive the functional information of the chip to be integrated; determine the interface information of each submodule based on the functional information. The interface of each submodule can be defined as needed to meet the chip integration requirements of chip engineers.

[0068] For example, the interfaces of each sub-module in the chip are non-unique: due to functional differences, the interfaces are different. The sub-modules in the chip are designed according to functional requirements, and sub-modules with different functions require different interfaces to support their specific operations. For example, the memory interface needs to support data reading and writing, while the communication interface needs to support signal transmission. The interface designs of the two are necessarily different. Moreover, performance requirements also have an impact on interface design. The performance requirements of sub-modules (such as bandwidth, latency, power consumption, etc.) directly affect the interface design. High-performance sub-modules may require more complex interface protocols and higher signal integrity requirements, while low-power sub-modules may adopt a simplified interface design to reduce power consumption.

[0069] In this embodiment, the interface information of each submodule is determined using the functional information, ensuring that each submodule's interface precisely matches the overall chip design requirements. During chip integration, chip engineers no longer need to spend extensive time adjusting and optimizing submodule interfaces; they can simply connect the submodule to the rest of the chip, significantly reducing debugging time and workload during integration and significantly improving chip integration efficiency.

[0070] In this embodiment, the interface information of each of the sub-modules is determined by the functional information, and the interfaces of each sub-module in the chip can be flexibly adjusted according to different application scenarios and customer needs to meet the specific needs of different customers without the need for large-scale changes to the entire chip architecture, thereby enhancing the versatility and adaptability of the chip design.

[0071] In this embodiment, the input system 1 is further configured to:

[0072] According to the name of the sub-module, the function information of the sub-module is determined; according to the function information, a formulation plan is generated; the formulation plan includes: the interface information, connection information of each of the sub-modules and the functional information of the chip to be integrated; wherein, the functional information of the integrated chip obtained by integrating the interface information and connection information of different sub-modules is different.

[0073] For example, in chip design, submodule names typically follow certain naming conventions that often reflect the module's basic function or type. For example, a submodule named "ALU" (arithmetic logic unit) performs basic arithmetic and logical operations. Therefore, the submodule's function can be determined based on its name.

[0074] Specifically, the role information of each submodule can be determined through the name of the submodule. Through the role information, according to the submodule and the corresponding interface information, a variety of integrated chip formation methods can be generated. Among them, the integrated chips formed by different submodule interface information and connection information are different, and the functions and structures are different. Among them, some integrated chips may focus on high-performance computing, with strong data processing capabilities and high-speed data transmission speeds; while some integrated chips may focus more on low power consumption and low cost, and are suitable for some application scenarios with low performance requirements but low manufacturing costs. The resulting formulation plan can be used as a reference for chip engineers and provide data support for subsequent integrated chips.

[0075] In this embodiment, the analysis system 2 is further configured to:

[0076] The configuration information is read, and the connection information of each submodule is input into a setting template to generate an executable file. The setting template is configured with a setting script, and the setting template is configured to fill the connection information into the setting script. The setting template is a Jinja2 format template. The template is used to automatically generate an executable file based on the connection information. The connection system 3 can read the executable file and execute actions to integrate the submodules according to the interface information.

[0077] In this embodiment, by setting the template, the connection information can be quickly and in real time filled into the setting script, thereby generating an executable file that can be read by the connection system 3. The setting of the template greatly improves the efficiency of chip integration. Compared with the current method of manually integrating each sub-module in the chip, this application only needs to input the connection information of each sub-module into the parsing system 2, and use the setting template to directly generate an executable file that can be recognized by the connection system 3, thereby completing the automated integration of each sub-module in the chip through the executable file.

[0078] The connection system 3 is further configured as follows:

[0079] The executable file is read and the submodules are integrated according to the input interface information. The connection system 3 has reading capabilities and can accurately identify and read the generated executable file. Once the executable file is read, the connection system 3 will quickly execute the corresponding actions according to the instructions in the executable file. It will accurately integrate the submodules according to the pre-defined interfaces as required by the instructions.

[0080] In this embodiment, the analysis system 2 is further configured to:

[0081] Read the configuration information and determine the base submodule of the submodule according to the name and connection information of the submodule; and determine the submodules of each level step by step from the base submodule until the top submodule, such as Figure 3 As shown; determine the base submodule (A module), and use the base submodule to determine the submodules of each level step by step until the top submodule (D module).

[0082] Specifically, if the chip to be integrated includes four submodules A, B, C, and D, Figure 3As shown, the preset hierarchy of the chip to be integrated is three layers. First, the base submodule, such as module A, is determined. Next, the modules belonging to the middle level, such as module B and module C, are determined. Finally, the top submodule, such as module D, is determined. Based on the above arrangement, the parsing system 2 can, based on the submodule names, group the corresponding submodules into the hierarchy corresponding to each submodule, preparing for the subsequent connection system 3 to integrate the submodules according to the connection information. By setting the hierarchy, the submodules can be matched according to their corresponding hierarchy first, preventing confusion and errors when the subsequent connection system 3 integrates the submodules according to the connection information.

[0083] like Figure 4 The figure shows the structure of the integrated chip in this application.

[0084] In this embodiment, the connection system 3 is further configured as follows:

[0085] According to the connection information, the base submodule and the submodules of the adjacent layers of the base submodule are integrated according to the interface information, and the base submodule integrates the submodules of each layer step by step until the top submodule. In the process of chip integration, the present application adopts a step-by-step integration method. First, the base submodule and the submodules of the adjacent layers of the base submodule are integrated according to the interface information. After completing the integration of the base submodule and the submodules of the adjacent layers, the integration is carried out step by step upwards. The integration work of each layer is carried out on the basis that the submodules of the previous layer have completed the integration work, and the submodules corresponding to each layer are mapped to each other. Through this step-by-step and progressive integration method, the chip to be integrated is constructed.

[0086] For example, through the above integration method, the submodules corresponding to each level are mapped to each other, which can effectively prevent the problem of disorder and error in the integration process. In the current integration method, all submodules are integrated at one time. Due to the large number of submodules and complex interfaces, connection errors, data conflicts and other problems are likely to occur. The step-by-step integration method decomposes the integration process into multiple steps, and each step only involves submodules of adjacent levels, which greatly reduces the complexity of integration. The integration process of each layer is basically accurate, and finally forms an integrated chip such as Figure 4 shown.

[0087] For example, a step-by-step integration approach can significantly increase integration speed. For example, once a sub-module at a certain level has been successfully integrated and tested, subsequent integration levels can be directly based on the results of this layer, eliminating the need to retrieve the corresponding sub-module from numerous unintegrated sub-modules, thus reducing the sub-module query rate. Furthermore, the step-by-step integration approach facilitates parallel operations, allowing multiple chip engineers to simultaneously integrate sub-modules at different levels, further shortening the integration cycle.

[0088] like Figure 2 As shown, it is a structural diagram of the verification system in this application.

[0089] In this embodiment, the system further comprises:

[0090] Verification system 4, the verification system 4 is configured to:

[0091] After the connection system 3 completes the integration of each of the sub-modules, the integrated chip is subjected to functional verification and structural verification to generate a verification report; the functional verification is configured to determine whether the interface information of each of the sub-modules matches the functional information of each of the chips to be integrated; the structural verification is configured to determine whether the interface information integrated by each sub-module matches the connection information of each of the sub-modules; the verification report includes: verification pass information or verification failure information and the corresponding failure reason.

[0092] Exemplarily, when each of the submodules is integrated to obtain an integrated chip, the verification system 4 can be used to determine whether the interface information of each of the submodules in the integrated chip matches the functional information of the chip to be integrated; it is understandable that when the chip to be integrated is integrated, its function is checked to see whether it matches the input functional information. If it does not match, a reverse check is used to check whether each submodule is connected properly, that is, whether the interface information of the submodule is correct. By determining whether the interface information integrated by each submodule in the integrated chip matches the connection information of each submodule, a verification report can be generated after the judgment is completed. The chip engineer can determine whether the integrated chip matches the configuration information based on the verification report. If it does not match, the cause of the failure can be determined based on the verification report, such as the chip interface access position error and the corresponding chip name, etc., thereby correcting the error points in the integrated chip and improving the efficiency of chip engineers in repairing the integrated chip.

[0093] The present application provides a chip integration system, which receives configuration information, reads the sub-module name, determines the level to which the sub-module belongs, and reads the interface information to determine the interface information of each sub-module. Based on the connection information, each sub-module is integrated according to the interface information, thereby realizing automatic connection of each sub-module in the chip to be integrated and saving labor costs.

[0094] A second aspect of the present application provides a chip integration method, which is applied to a chip integration system described in any of the above embodiments, including:

[0095] Receive configuration information; the configuration information includes: the name of each submodule, interface information, and connection information;

[0096] Read the configuration information and determine the level to which each submodule belongs based on the name and connection information of the submodule;

[0097] Classify the submodules according to the levels to which they belong;

[0098] The configuration information is read, and the submodules are integrated according to the interface information.

[0099] It is worth noting that the effects of the above method embodiments can be found in the effects of the above system embodiments, which will not be described in detail here.

[0100] A third aspect of the present application provides an electronic device, comprising a processor and a memory, wherein the memory is used to store at least one program, and the at least one program is loaded by the processor and executed by a chip integration method as described in the second aspect.

[0101] In some embodiments, the processor may include one or more processing cores, such as a quad-core processor, a quad-core processor, etc. The processor may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), or PLA (Programmable Logic Array). The processor may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0102] The memory may include one or more computer-readable storage media, which may be non-transitory. The memory may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory is used to store at least one program code, which is used to be executed by the processor to implement the process executed by the terminal in the method for data format conversion provided in the method embodiment of the present application.

[0103] It is worth noting that the effects of the above electronic device embodiments can be found in the effects of the above system embodiments, which will not be described in detail here.

[0104] In a fourth aspect, the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores at least one program, and the at least one program is loaded and executed by a processor to implement a chip integration method as described in the second aspect. Optionally, the computer-readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a compact disc (CD-ROM), a magnetic tape, a floppy disk, an optical data storage device, or the like.

[0105] It is worth noting that the effects of the above-mentioned computer-readable storage medium embodiment can be found in the effects of the above-mentioned system embodiment, which will not be described in detail here.

[0106] The above specific implementation methods further explain in detail the purpose, technical solutions and beneficial effects of the embodiments of the present application. It should be understood that the above are only specific implementation methods of the embodiments of the present application and are not intended to limit the scope of protection of the embodiments of the present application. Any modifications, equivalent replacements, improvements, etc. made on the basis of the technical solutions of the embodiments of the present application should be included in the scope of protection of the embodiments of the present application.

Claims

1. A chip integration system, applied to a chip to be integrated, wherein the chip to be integrated includes multiple sub-modules; characterized in that: include: Input system (1), parsing system (2), connection system (3); The input system (1) is configured as follows: Receive configuration information; the configuration information includes: the name of each sub-module, interface information, and connection information; The analysis system (2) is configured as follows: Read the configuration information and determine the level to which each submodule belongs based on the name and connection information of the submodule; Classify the submodules according to the levels to which they belong; The connection system (3) is configured as follows: The configuration information is read, and the submodules are integrated according to the interface information.

2. A chip integration system according to claim 1, characterized in that: The input system (1) is further configured to: receiving functional information of the chip to be integrated; According to the functional information, interface information of each of the submodules is determined.

3. A chip integration system according to claim 1, characterized in that: The input system (1) is further configured to: Determine the function information of the submodule according to the name of the submodule; Generate a formulation plan based on the role information; the formulation plan includes: interface information and connection information of each of the submodules and functional information of the chip to be integrated; The functional information of the integrated chip obtained by integrating the interface information and connection information of different sub-modules is different.

4. A chip integration system according to claim 1, characterized in that: The analysis system (2) is further configured to: Reading the configuration information, inputting the connection information of each submodule into a setting template, and generating an executable file; the setting template is configured with a setting script, and the setting template is configured to fill the connection information into the setting script; The connection system (3) is further configured to: The executable file is read, and each of the submodules is integrated according to the interface information.

5. The chip integration system according to claim 1, characterized in that: The analysis system (2) is further configured to: The configuration information is read, and the base submodule of the submodule is determined according to the name and connection information of the submodule; and the base submodule determines the submodules of each level step by step until the top submodule.

6. A chip integration system according to claim 5, characterized in that: The connection system (3) is further configured to: According to the connection information, the base submodule and the submodules of the adjacent layers are integrated according to the interface information, and the base submodule integrates the submodules of each layer step by step until the top submodule.

7. A chip integration system according to claim 2, characterized in that: The system further comprises: A verification system (4), wherein the verification system (4) is configured to: After the connection system (3) completes the integration of each of the submodules, functional verification and structural verification are performed on the integrated chip to generate a verification report; the functional verification is configured to determine whether the interface information of each of the submodules matches the functional information of the chip to be integrated; the structural verification is configured to determine whether the interface information integrated by each of the submodules matches the connection information of each of the submodules; the verification report includes: verification pass information or verification failure information and the corresponding failure reason.

8. A chip integration method, applied to a chip integration system according to any one of claims 1 to 7, characterized in that: include: Receive configuration information; The configuration information includes: the name, interface information, and connection information of each submodule; Read the configuration information and determine the level to which each submodule belongs based on the name and connection information of the submodule; Classify the submodules according to the levels to which they belong; The configuration information is read, and the submodules are integrated according to the interface information.

9. An electronic device, characterized in that: The electronic device includes a processor and a memory, the memory is used to store at least one program, and the at least one program is loaded and executed by the processor. A chip integration method according to claim 8.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores at least one program, and the at least one program is loaded and executed by the processor to implement the chip integration method according to claim 8.

Images