Clock element code-free design system and method

Abstract

The invention relates to a system and a method for designing individual clock elements constituting a clock management unit of a system on chip in a code-free manner. The code-free design system for a clock element according to one embodiment of the present invention comprises: a clock component repository for storing clock component information for specifying a register address and a field value of a clock instance generated on the basis of a clock component; the hardware code logic storage library is used for storing hardware code logic for generating the designed clock instance into a hardware code; a clock instance processing unit that designs a new clock instance by setting a register field value for defining a function of the new clock instance on the basis of the generated clock instance information and the clock component information; and a hardware code processing section that generates a clock module and a register module corresponding to the clock module based on the register field value of the designed new clock instance and the hardware code logic, and generates a hardware code by combining the clock module and the register module.

Description

Technical Field

[0001] The present invention relates to a system and method for codeless design of clock elements, and in particular to a system and method for designing individual clock elements constituting a clock management unit of a system on chip in a codeless manner. Background Art

[0002] A system-on-chip (SoC) refers to a technology or integrated circuit (IC) that integrates multiple functional blocks, such as a central processing unit (CPU), memory, interfaces, digital signal processing circuits, and analog signal processing circuits, into a single semiconductor integrated circuit (IC) to implement a computer or other electronic system. SoCs are evolving into more complex systems that include multiple functional blocks, such as processors, multimedia, graphics, interfaces, and security.

[0003] Power and clock design is crucial for SoCs. This process includes drawing a power / clock diagram, writing Verilog code and scripting, initial documentation, generating Unified Power Format / Standard Design Constraint (UPF / SDC) files, implementing layout design, secondary documentation, inserting a Design for Testability (DFT) controller, hardware system analysis, and software optimization.

[0004] The power / clock diagram creation step visually represents the power and clock structure and creates a block diagram to represent the power and clock tree. In the power / clock diagram creation step, clock elements and their links are represented only graphically. The Verilog coding and scripting step creates the Verilog code and scripts used to define and implement the system-on-chip's functionality, executing the hardware's register transfer level (RTL) design. In other words, developers manually generate register transfer level (RTL) code based on the power / clock diagram creation artifacts.

[0005] The first textualization step is to textualize the design intent and structure at the beginning of the project, creating various documents such as detailed requirements, architectural designs, power / clock diagrams, etc. required by multiple stakeholders such as the verification team and software development team.

[0006] The Unified Power Format / Standard Design Constraint File Generation Step is a step for generating a Unified Power Format (UPF) and Standard Design Constraint (SDC) file for controlling power management and timing constraints, thereby generating the input required for hardware synthesis.

[0007] The implementation layout design step involves designing the actual SoC chip layout at the gate level and configuring it. The second documentation step involves updating and improving various documents to reflect design and implementation changes. The DFT controller insertion step involves designing the DFT controller and logic circuits for testing and debugging and integrating them into the SoC. The hardware system analysis step involves verifying and analyzing software operation through simulation and verification to confirm the accuracy and effectiveness of the design. The software optimization step involves analyzing and optimizing the software code running on the SoC to maximize software performance.

[0008] Each step of the design process of this system on chip is independently performed by each stakeholder, and the information required in each step may be different. That is, the information required for the first half of the work and the information required for the second half of the work may be different. Therefore, problems with the design work products of the staff in the first half of the project can be discovered through simulation and verification in the second half, and in order to solve such problems, it is necessary to repeatedly perform the work from the first half. Moreover, during the course of the project, when the requirements or design objects change, it is necessary to repeatedly perform the work from the initial design. As mentioned above, in components that repeatedly perform multiple steps, multiple stakeholders need to reflect changes in other steps and repeatedly perform similar tasks. Therefore, the design of the system on chip will consume a lot of time and manpower. Summary of the Invention

[0009] The purpose of the present invention for solving the above-mentioned problem is to provide a clock element codeless design system and method that automatically derives register transfer level (RTL) code corresponding to individual clock elements constituting a clock management unit, taking into account the settings required for the clock design processing of an on-chip system.

[0010] The present invention can be implemented in various ways including an apparatus (system), a method, a computer program stored in a computer-readable medium, or a computer-readable medium storing the computer program.

[0011] A clock element codeless design system according to an embodiment of the present invention includes: a memory for storing at least one instruction; a clock component repository for storing clock component information for specifying register addresses and field values of clock instances, wherein the clock instances are generated based on the clock components; a hardware code logic repository for storing hardware code logic for generating the designed clock instances into hardware code; and at least one processor for executing at least one instruction stored in the memory, wherein the at least one instruction includes the following instructions: generating field values of registers defining the functions of new clock instances and designing new clock instances based on the generated clock instance information and clock component information, generating a clock module and a register module corresponding to the clock module based on the field values of the registers of the designed new clock instance and the hardware code logic, and generating hardware code by combining the clock module and the register module.

[0012] Preferably, at least one instruction also includes the following instructions: generating a new clock instance based on the generated clock instance information and clock component information and storing it in the clock instance repository, determining the field values of the basic registers used to set the necessary functions of the clock source corresponding to the new clock instance and storing it in the clock instance repository, determining the field setting values of the extended registers used to define the extended functions of the new clock instance and storing it in the clock instance repository.

[0013] Preferably, at least one instruction also includes the following instructions: transforming the designed new clock instance according to the hardware code logic and determining the port of the clock module, generating a register module including ports corresponding to the ports of the clock module based on the register field value of the designed new clock instance, connecting the port of the clock module with the port of the register module and generating hardware code reflecting the design of the new clock instance.

[0014] Preferably, the clock component information includes an address range allocated to each clock component, an alignment size of each clock component, a basic register offset size of each component, an extended register offset size of each component, and setting field information of each clock component.

[0015] More preferably, the setting field information of each clock component includes field name, bit position, bit size, access permission, and initial value.

[0016] More preferably, the start address of the register of the new clock instance is determined by the sum of the start address of the register of the generated clock instance and the alignment size.

[0017] More preferably, the clock component is one of a phase-locked loop controller component, a clock divider component, a clock multiplexer component, and a clock gating component.

[0018] More preferably, the clock component is a phase-locked loop controller component, and the field of the extended register of the new clock instance includes at least one of a power-down (DWRDOWN) field and a custom (CUSTOM) field.

[0019] More preferably, the clock component is a clock divider component, and the field of the extended register of the new clock instance includes at least one of a power-off field, a throttle field, and a custom field.

[0020] More preferably, the clock component is a clock multiplexer component, and the field of the extension register of the new clock instance includes at least one of a throttle field and a custom field.

[0021] More preferably, the clock component is a clock gating component, and the fields of the extended register of the new clock instance include at least one of a short stop (SHORTSTOP) field, an early wakeup (EWAKEUP) field, and a custom field.

[0022] A codeless clock element design method according to an embodiment of the present invention is executed by at least one processor in a computer system. The computer system includes: a clock component repository storing clock component information for specifying register addresses and field values of clock instances generated based on the clock components; and a hardware code logic repository storing hardware code for generating the designed clock instances. The codeless clock element design method includes: a first step of setting field values of registers defining the functions of a new clock instance based on the generated clock instance information and clock component information, and designing the new clock instance; and a second step of generating a clock module and a register module corresponding to the clock module based on the field values of the registers of the designed new clock instance and the hardware code logic, and generating hardware code by combining the clock module and the register module.

[0023] Preferably, the first step includes the following steps: generating a new clock instance based on the generated clock instance information and clock component information and storing it in the clock instance repository; determining the field values of the basic registers used to set the necessary functions of the clock source corresponding to the new clock instance and storing it in the clock instance repository; and determining the field setting values of the extended registers used to define the extended functions of the new clock instance and storing it in the clock instance repository.

[0024] Preferably, the second step includes the following steps: determining the port of the clock module according to the new clock instance designed by the hardware code logic transformation; generating a register module including ports corresponding to the ports of the clock module based on the register field value of the designed new clock instance; and connecting the port of the clock module with the port of the register module and generating hardware code reflecting the design of the new clock instance.

[0025] Preferably, the clock component information includes an address range allocated to each clock component, an alignment size of each clock component, a basic register offset size of each component, an extended register offset size of each component, and setting field information of each clock component.

[0026] More preferably, the setting field information of each clock component includes field name, bit position, bit size, access permission, and initial value.

[0027] More preferably, the start address of the register of the new clock instance is determined by the sum of the register start address and the alignment size of the generated clock instance.

[0028] More preferably, the clock component is one of a phase-locked loop controller component, a clock divider component, a clock multiplexer component, and a clock gating component.

[0029] More preferably, the clock component is a phase-locked loop controller component, and the field of the extended register of the new clock instance includes at least one of a power-off field and a custom field.

[0030] More preferably, the clock component is a clock divider component, and the field of the extended register of the new clock instance includes at least one of a power-off field, a throttling field, and a custom field.

[0031] More preferably, the clock component is a clock multiplexer component, and the field of the extension register of the new clock instance includes at least one of a throttle field and a custom field.

[0032] More preferably, the clock component is a clock gating component, and the field of the extended register of the new clock instance includes at least one of a short-stop field, an early-wake-up field, and a custom field.

[0033] An embodiment of the present invention provides a computer program stored in a computer-readable medium for executing the method on a computer.

[0034] In various embodiments of the present invention, individual clock elements constituting a clock management unit may be designed taking into account settings required in a clock design process for a system-on-chip.

[0035] In multiple embodiments of the present invention, hardware codes corresponding to individual clock elements constituting a clock management unit, ie, register transfer level codes, can be automatically derived to effectively improve the efficiency of design work.

[0036] In various embodiments of the present invention, even if a worker has no coding knowledge or clock process knowledge, the hardware code (register transfer level code) of the individual clock elements constituting the clock management unit can be derived in a codeless manner.

[0037] In various embodiments of the present invention, individual clock elements may be designed taking into account the settings required throughout the entire clock design process, thereby easily achieving global optimization.

[0038] The effects of the present invention are not limited to the effects mentioned above, and ordinary technicians in the technical field to which the present invention belongs (referred to as "general technicians") can clearly understand other effects not mentioned from the description of the scope of protection claimed in the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Embodiments of the present invention will be described with reference to the accompanying drawings described below, wherein like reference numerals denote like structural elements, but the present invention is not limited thereto.

[0040] Figure 1 FIG. 1 is a block diagram showing a general system on a chip.

[0041] Figure 2 for Figure 1 Detailed structural block diagram of the clock management unit included in the on-chip system.

[0042] Figure 3 This is a structural diagram of the clock element codeless design system of the present invention.

[0043] Figure 4 A diagram showing an example of a display screen of the clock element codeless design system of the present invention.

[0044] Figure 5 This is an example diagram showing the address range of registers allocated to each clock component.

[0045] Figure 6 This is an illustration showing the address allocation status of registers of three clock divider instances.

[0046] Figure 7 The flowchart shows the code-free design method of the clock element of the present invention.

[0047] Figure 8 An exemplary computer device for executing the described methods and / or embodiments is shown.

[0048] Description of Reference Signs

[0049] 310: Screen window processing unit 311: Command window processing unit

[0050] 312: Content window processing unit 313: Design window processing unit

[0051] 314: Setting window processing unit 320: Clock instance processing unit

[0052] 321: Clock instance generation unit 322: Basic register setting unit

[0053] 323: Extension register setting unit 330: Data storage library

[0054] 331: Clock component repository 332: Content repository

[0055] 333: Clock Example Repository 334: Hardware Code Logic Repository

[0056] 340: Hardware code processing unit 341: Clock module generation unit

[0057] 342: Register module generation unit 343: Hardware code generation unit DETAILED DESCRIPTION

[0058] Hereinafter, the specific contents for implementing the present invention will be described in detail with reference to the accompanying drawings. However, in the following description, when there is a concern that it will unnecessarily obscure the main purpose of the present invention, the specific description of known functions or structures will be omitted.

[0059] In the accompanying drawings, identical or corresponding structural elements are given the same reference numerals. Furthermore, in describing the following embodiments, repeated descriptions of identical or corresponding structural elements may be omitted. However, even if the description of a structural element is omitted, it does not mean that such structural element is not included in any embodiment.

[0060] The advantages, features and methods of implementing the embodiments described in this specification will be referred to in the accompanying Figure 1 However, the present invention is not limited to the embodiments disclosed below, but can be embodied in various forms. However, these embodiments are provided to fully inform those skilled in the art of the scope of the present invention.

[0061] The terms used in this specification are briefly described, and the disclosed embodiments are specifically described. The terms used in this specification take into account their functions in the present invention and are selected as general terms that are currently widely used as much as possible. This may change according to the intentions of technicians in the relevant field, conventions, or the emergence of new technologies. In addition, in certain cases, there is an intention of the applicant to make an arbitrary selection. In this case, its meaning is described in detail in the description section of the corresponding invention. Therefore, the terms used in the present invention are not simple term names, but should be defined based on the meaning of the term and the overall content of the present invention.

[0062] Unless the context clearly specifies the singular, the singular in this specification includes the plural. Furthermore, unless the context clearly specifies the negative, the plural includes the singular. Throughout this specification, when a section includes one structural element, it means that other structural elements are also included, and does not mean that other structural elements are excluded, unless otherwise specified.

[0063] In the present invention, terms such as "include", "comprising" and the like may indicate the existence of features, steps, actions, elements and / or structural elements, and such terms do not exclude the addition of one or more other functions, steps, actions, elements, structural elements and / or combinations thereof.

[0064] In the present invention, when it is mentioned that a specific structural element is "combined," "combined," "connected," "associated," or "reacted" with other structural elements, the specific structural element may be directly combined, combined, connected, and / or associated or reacted with the other structural elements, but is not limited to this. For example, there may be at least one intermediate structural element between the specific structural element and the other structural element. Furthermore, in the present invention, "and / or" may include a combination of at least one item or at least a portion of at least one item listed.

[0065] In the present invention, terms such as "first" and "second" are used to distinguish specific structural elements from other structural elements, and the structural elements are not limited to such terms. For example, a "first" structural element can be used to represent an element with the same or similar form as a "second" structural element.

[0066] In various embodiments of the present invention, a "clock component" may be a tool that can be used in the design of a clock management unit. The clock component may include a phase-locked loop controller component, a clock divider component, a clock multiplexer component, and a clock gating component. In the present invention, the clock component can be displayed as an icon in a clock component window. Each clock component may include an icon, an address range assigned to each clock component, an alignment size of each clock component, a basic register offset size of each clock component, an extended register offset size of each clock component, and setting field information of each clock component (field name, bit position, bit size, access rights, initial value, etc.).

[0067] In various embodiments of the present invention, a "clock instance" can be a clock component added to the design window through user operations. That is, a clock instance can be a clock component included in the design of the clock management unit. If a user drags and drops any clock component icon from the clock component window into the design window area, a clock instance corresponding to the corresponding clock component is generated. When a clock instance is generated, basic registers and optionally extended registers for the corresponding clock instance are automatically generated. The field values that constitute the basic registers and optionally extended registers can be pre-set or changed through user input. The clock management unit can include multiple clock instances for each clock component type. A clock instance generated based on a phase-locked loop controller component is called a phase-locked loop controller instance, a clock instance generated based on a clock divider component is called a clock divider instance, a clock instance generated based on a clock multiplexer component is called a clock multiplexer instance, and a clock instance generated based on a clock gating component is called a clock gating instance. According to the present invention, when a clock instance is generated, basic register field values are automatically assigned. If the corresponding clock instance includes extended registers, extended register field values are automatically assigned. Some register field values can be changed based on user input. Furthermore, hardware code may be generated based on the completed set basic register field values and extended register field values of the clock instance.

[0068] In various embodiments of the present invention, a clock element is a module implemented in hardware coding based on a designed clock instance, which may constitute a clock management unit.

[0069] To summarize, a clock component may be a material used to design a clock management unit, a clock instance may be a node that includes the clock management unit in the design, and a clock element may be a module implemented in the form of hardware code based on the clock instance of the completed design and that may work in the clock management unit.

[0070] Figure 1 FIG. 1 is a block diagram showing half of a system-on-chip.

[0071] The system on chip may include an input / output board 11, a clock management unit (CMU) 12, a power management unit (PMU) 13, and at least one intellectual property (IP) block 14, 15, and 16. The clock management unit 12 may generate clock signals that are provided to a first IP block 14, a second IP block 15, and a third IP block 16, respectively. For example, the clock management unit 12 may generate a first clock signal CLK1, a second clock signal CLK2, and a third clock signal CLK3. The clock management unit 12 may provide the first clock signal CLK1 to the first IP block 14, the second clock signal CLK2 to the second IP block 15, and the third clock signal CLK3 to the third IP block 16.

[0072] The first IP block 14, the second IP block 15, and the third IP block 16 can be connected to a system bus and can communicate with each other via the system bus. The first IP block 14, the second IP block 15, and the third IP block 16 can each include a processor, a graphics processor, a memory controller, an input and output interface block, etc.

[0073] The power management unit 13 controls the power supplied to the first to third IP blocks 14 to 16. For example, when the system on chip enters the standby mode, the power management unit 13 interrupts the power supply provided to the first to third IP blocks 14 to 16, thereby reducing the power consumption of the system on chip.

[0074] Figure 2 for Figure 1 Detailed structural block diagram of the clock management unit 12, 200 included in the on-chip system.

[0075] The clock management unit 200 can be Figure 1 The clock management unit 12.

[0076] Reference Figure 2The clock management unit 200 includes multiple clock elements 211, 212, 213, 214, 215, 216, 217, and 218 (Clock Elements) and a clock management unit controller (CMUController) 220. The multiple clock elements 211, 212, 213, 214, 215, 216, 217, and 218 generate clock signals CLK provided to the IP blocks 14, 15, and 16. The frequencies of the clock signals provided to each IP block 14, 15, and 16 can be different. The clock management unit controller 220 controls the multiple clock elements 211, 212, 213, 214, 215, 216, 217, and 218 to provide clock signals having the frequencies required by the IP blocks 14, 15, and 16.

[0077] The clock elements may include phase locked loop (PLL) controllers 211 and 212 , clock dividers 213 and 215 , a clock multiplexer 214 , and clock gates 216 , 217 , and 218 .

[0078] Each clock element may include a clock source (CS) and a clock control circuit (CC) that controls the clock source. For example, the clock source may include a multiplexing circuit, a frequency division circuit, a gating circuit, etc.

[0079] The PLL controllers 211 and 212 do not include a clock source internally and can control a PLL external to the clock management unit 200 .

[0080] The clock dividers 213 and 215 each include a frequency divider circuit as a clock source CS. The clock control circuit CC of the clock dividers 213 and 215 controls the frequency divider circuit. The frequency divider circuit divides the input clock signal and outputs it. The clock control circuit CC can control the frequency division ratio of the frequency divider circuit.

[0081] The clock multiplexer 214 includes a multiplexing circuit as a clock source CS, and a clock control circuit CC of the clock multiplexer 214 controls the multiplexing circuit. The multiplexing circuit selectively outputs one of the multiple clock signals input. The clock control circuit CC can control which input clock signal the multiplexing circuit selects to output.

[0082] Clock gating circuits 216, 217, and 218 each include a gating circuit as a clock source CS. Clock control circuits CC in clock gating circuits 216, 217, and 218 control the gating circuits. The gating circuits activate the clock signal only when necessary. Otherwise, they temporarily interrupt circuit operation by disconnecting the clock to control unnecessary clock signals. Clock control circuit CC can disable or activate the clocks in the gating circuits.

[0083] Clock element 211 is the parent element of clock element 213. Clock element 213 is the child element of clock element 211 and the parent element of clock element 214. Clock element 214 is the child element of two clock elements 212 and 213 and the parent element of clock element 215. Clock element 215 is the child element of clock element 214 and the parent element of three clock elements 216, 217, and 218. Meanwhile, clock elements 211 and 212, which include a phase-locked loop controller, are root clock elements, while clock elements 216, 217, and 218, which are located near IP blocks 14, 15, and 16 and include gate control circuits, are leaf clock elements.

[0084] The parent-child relationship described above can be formed between clock control circuits CC and clock sources CS based on the parent-child relationship between clock elements 211, 212, 213, 214, 215, 216, 217, and 218. A signal line 219 is connected between the clock control circuits CC, and the two clock control circuits CC can communicate via the signal line 219. The parent clock source CS can transmit the clock CLK to the child clock source CS.

[0085] Clock management unit controller 220 includes registers. Information required to control and configure the operation of clock management unit 200 is stored in these registers as register-transfer-level code. Furthermore, the registers of clock management unit controller 220 define register-transfer-level code that describes the operation of the clock control circuitry for each clock element. This register-transfer-level code can be implemented as actual clock management unit hardware using hardware design tools. In the present invention, register-transfer-level code can be used in conjunction with hardware code.

[0086] Therefore, when constructing a clock management unit, it is necessary to generate register transfer level code for each clock element, and generate register transfer level code that describes the operation of each clock element and store it in the register of the clock management unit controller. In the past, based on the clock diagram drawing product, developers used Verilog code to manually generate hardware code.

[0087] The present invention proposes a clock element codeless design system and method that can set multiple operating characteristics of a clock element based on a graphical user interface (GUI), and derive register transfer level codes corresponding to the clock element in a codeless manner based on the set operating characteristics.

[0088] Figure 3 FIG. 1 is a structural diagram of the clock element codeless design system of the present invention. The clock element codeless design system of the present invention can be implemented by a computer system.

[0089] The codeless clock element design system of the present invention may include: a screen window processing unit 310, which detects user input and outputs the processing results of the user input to a display screen; a clock instance processing unit 320, which generates a clock instance based on clock component information, sets the field values of basic registers that define the basic functions of the clock instance, and designs the clock instance; a data repository 330, which stores hardware code logic that generates hardware code based on the clock component information, the designed clock instance information, and the designed clock instance; and a hardware code processing unit 340, which generates clock elements based on the designed clock instance information, generates register modules corresponding to the clock elements, and combines the clock elements and register modules to generate hardware code. The clock instance processing unit 320 can set the field values of extended registers that define the extended functions of the clock instance to design the clock instance.

[0090] Figure 4 A diagram showing an example of a display screen of the clock element codeless design system of the present invention.

[0091] The display screen of the codeless design system for clock elements of the present invention may include: a command window 410 for inputting user commands; a clock component window 420 for displaying multiple clock component icons; a content window 430 for providing an environment for adding, deleting, and changing the list of clock management units being designed, displaying a list of clock instances constituting the clock management unit being designed and basic register information for each clock instance by layer; a design window 440 for displaying a clock diagram of the clock management unit being designed and providing an environment for adding, deleting, and changing the clock instances constituting the clock management unit being designed; and a setting window 450 for providing an environment for changing the setting values of the clock instance selected in the design window. The content window 430 may also display extended register information for each clock instance by layer.

[0092] The command window 410 may include: a CHECK button for receiving an instruction to check errors in the clock diagram of the clock management unit being designed, the setting values of multiple clock instances of the clock management unit being designed, and the connections between parent-child clock instances; an UNCHECK button for receiving an instruction to deactivate the check result; a SAVE button for receiving an instruction to store the clock diagram displayed in the design window 440; and a GENRTL button for receiving an instruction to generate hardware code for the clock diagram displayed in the design window 440.

[0093] Clock component window 420 displays multiple icons listing clock components for a design of a clock-manageable unit. Clock components may include a phase-locked loop control component, a clock divider component, a clock multiplexer component, and a clock gating component. Label components may also be displayed in clock component window 420. Label components are components inserted between the input and output of two clock components to facilitate partial design work when designing a complex clock diagram. When hardware code is generated, the label components may be coded to be ignored, leaving the two clock components connected.

[0094] Content window 430 displays a list of clock management units currently being designed, providing an environment for adding, deleting, and modifying these units. Below the list of each clock management unit currently being designed, a list of clock instances comprising the clock management unit can be displayed, with basic register information for each clock instance displayed layer by layer. Optionally, extended register information for each clock instance can also be displayed.

[0095] Design window 440 displays the clock diagram of the clock management unit being designed and provides an environment for adding, deleting, and modifying clock instances that make up the clock management unit being designed. By dragging and dropping any clock component from clock component window 420 into design window 440, a clock instance is generated for the corresponding clock management unit being designed. When a clock instance is generated, a new clock instance list and basic register information for the new clock instance can be added layer by layer in content window 430. Optionally, extended register information for the new clock instance can also be added.

[0096] The setting window 450 displays an environment for changing setting values of the clock instance selected in the design window 440 .

[0097] The screen window processing unit 310 may include: a command window processing unit 311, which displays buttons for receiving user instructions in the command window 410, detects input of each button in the command window 410 and performs work corresponding to the input button; a content window processing unit 312, which displays a list of clock management units under design, a list of clock instances included in each clock management unit under design and register information by layer in the content window 430, detects user input in the content window 430 and performs work corresponding to the user input; a design window processing unit 313, which displays a clock diagram of the clock management unit under design selected by the user in the design window 440, detects user input in the design window 440 and performs work corresponding to the user input; and a setting window processing unit 314, which displays setting information of the clock instance selected by the user in the setting window 450, detects user input in the setting window 450 and performs work corresponding to the user input.

[0098] When the CHECK button is selected, the command window processing unit 311 performs an error check on the clock diagram of the clock management unit under design and the setting values of the multiple clock instances of the clock management unit under design, as well as the connections between parent element and child element clock instances, and displays the portion where the error occurred. When the UNCHECK button is selected, the erroneous portion of the clock diagram displayed in the clock management unit under design is restored to its original state and displayed. When the SAVE button is selected, the job content of the clock of the clock management unit under design displayed in the design window 440 is stored in the content data repository 330. When the GENRTL button is selected, the hardware code for the clock diagram of the clock management unit under design displayed in the design window is generated.

[0099] The content window processing unit 312 provides an environment for adding, deleting, and changing the list of clock management units under design and the list of clock instances included in each clock management unit under design. The content window processing unit 312 displays the list of clock instances, basic register information of each clock instance, and optionally displays extended register information by layer under each clock management unit under design. The user can add, delete, or change the name of the clock management unit under design in the content window. Corresponding to the user's input, the content storage library 332 can add, delete, or change the name of the clock management unit under design. When the user changes the name of the clock management unit under design, the content window processing unit 312 also changes the name of the corresponding clock management unit under design, the name of the lower-level clock instance of the corresponding clock management unit under design, and the basic register name and extended register name of the corresponding clock instance.

[0100] The design window processing unit 313 displays the clock diagram of the clock management unit being designed in the design window 440 and provides an environment for adding, deleting, and modifying clock instances that make up the clock management unit being designed. When the user adds any clock component from the clock component window 420 to the design window 440, the design window processing unit 313 detects the addition of the clock instance.

[0101] The setting window processing unit 314 displays the setting information of the clock instance selected by the user in the setting window 450 , detects the user input in the setting window 450 , and performs a task corresponding to the user input.

[0102] The data repository 330 may include: a clock component repository 331, which stores clock component information; a content repository 332, which stores a list of clock management units being designed and a list of clock instances and a list of registers corresponding to the clock instances for each clock management unit being designed; a clock instance repository 333, which stores clock instance information and register information of the clock instances; and a hardware code logic repository 334, which stores hardware code logic for generating hardware code based on the designed clock instance information and register information.

[0103] The register list corresponding to the clock instance may include a basic register list and an extended register list.

[0104] The clock component information stored in the clock component repository 331 may include the address range assigned to each clock component, the alignment size of each clock component, the basic register offset size of each clock component, the extended register offset size of each clock component, and the set field information of each clock component (field name, bit position, bit size, access rights, initial value, etc.). The clock component information specifies the register address and field values of the clock instances generated based on the corresponding clock component. The address range assigned to each clock component and the alignment size of each clock component can be used to calculate the maximum number of clock instances for the corresponding clock component. Clock components may include a phase-locked loop control component, a clock divider component, a clock multiplexer component, and a clock gating component.

[0105] The address range allocated to each clock component, the alignment size of each clock component, the basic register offset size of each clock component, the extended register offset size of each clock component, and the setting field information of each clock component can all be determined differently.

[0106] Figure 5The following diagram illustrates the address range of registers allocated to each clock component. For example, the phase-locked loop control component can be allocated the address range of 0x0000 to 0x0800, the clock divider component can be allocated the address range of 0x1400 to 0x1800, the clock multiplexer component can be allocated the address range of 0x1000 to 0x1400, and the clock gating component can be allocated the address range of 0x1800 to 0x2000.

[0107] The clock management unit may include multiple clock instances according to the type of clock component, for example, it may include three clock divider instances.

[0108] Figure 6 This is an illustration showing the address allocation status of registers of three clock divider instances.

[0109] The addresses of the three clock divider instances are allocated in the address range (0×1400 to 0×1800) allocated to each clock component. The register address of the first clock divider instance DIV_0 can be allocated to the start address (1×1400) of the address range allocated to the clock divider component. The register address of the second clock divider instance DIV_1 can be an address (1×1408) obtained by adding the alignment size (0×8) to the start address of the first clock divider instance. The register address of the third clock divider instance can be an address (0×1414) obtained by adding the alignment size to the start address of the second clock divider instance. The first clock divider instance and the second clock divider instance can only include basic registers, and the third clock divider instance can include basic registers and extended registers. The basic register setting value of the clock divider instance is recorded from the clock divider instance start address to the basic register offset size, and the extended register setting value is recorded in the remaining part.

[0110] The clock component repository 331 stores the field information (field name, bit position, bit size, access rights, initial value, etc.) for each clock component. This field information can be different for each clock component. The bit position is the starting address of the corresponding field in the address assigned to the individual clock instance, the bit size is the range of the corresponding field, the access rights are whether the corresponding field has write permission (read-only / read-write), and the initial value is the initial setting value.

[0111] The PLL control component may include a select (SELECT), busy (BUSY), and debug (DBG_INFO) field as basic register information, and may include a power-down (DWRDOWN) field and a custom (CUSTOM) field as extended register information. Each field may have its own field name, bit position, bit size, access rights, and initial value. The select field is used to select the PLL type, the busy field is used to monitor whether the clock element is working, and the debug field is used to store debug information.

[0112] The clock multiplexer component includes the select (SELECT), busy (BUSY), and debug (DBG_INFO) fields as basic register information, and can include the throttle (THROTTLE) and custom (CUSTOM) fields as extended register information. Each field has a predefined name, bit position, bit size, access rights, and initial value. The select field selects the number of multiplexer inputs, the busy field monitors whether the clock element is operating, and the debug field stores debug information.

[0113] The clock divider component may include the division ratio (DIVRATIO), busy (BUSY), and debug (DBG_INFO) fields as basic register information, and may include the power down (DWRDOWN), throttle (THROTTLE), and custom (CUSTOM) fields as extended register information. Each field has a predefined name, bit position, bit size, access rights, and initial value. The division ratio field sets the division ratio of the clock divider, the busy field monitors whether the clock element is operating, and the debug field stores debug information.

[0114] The clock gating component can include the enable (ENABLE), busy (BUSY), and debug (DBG_INFO) fields as basic register information, and the shortstop (SHORTSTOP), early wakeup (EWAKEUP), and custom (CUSTOM) fields as extended register information. Each field has a predefined name, bit position, bit size, access rights, and initial value. The busy field is used to monitor whether the clock element is operating, and the debug field stores debug information.

[0115] The power-down (DWRDOWN) field is a field that determines whether the function of controlling the corresponding clock element is used during the power-on / power-off sequence of any power domain. In the case of the phase-locked loop controller instance and the clock multiplexer instance, when the power-down field is set to a specific field value, it supports the working feature of forcing the output value to be overridden to 0. In the case of the clock divider instance, when the power-down field is set to a specific field value, it supports the working feature of forcing the output value to be output at a low level.

[0116] The THROTTLE field is a field that determines the characteristics of reducing the problem by instantaneously reducing the frequency when the temperature of the clock element rises above the specified level. In the case of the clock multiplexer instance and the clock divider instance, when the throttle field is set to a specific field value, it supports the operating characteristics of forcibly changing the division ratio and output frequency if a throttling signal is input.

[0117] The Custom field is used to determine whether the corresponding clock element's functionality is controlled by custom hardware. The Shortstop field supports operating characteristics for several cycles before and after a signal changes from 0 to 1 or from 1 to 0. The Shortstop field can be set in a clock gating instance. The Early Wakeup field receives an external signal from the clock management unit to determine whether to activate automatic clock gating for the clock element.

[0118] The clock instance repository 333 stores register information for each of the multiple clock instances included in the clock management unit being designed. The clock instance repository 333 can store the name of the clock management unit being designed, the type of clock component for the clock instance, the start address of the corresponding clock instance, and the field settings of each register. The field settings of each register can be set based on the clock component information or based on user input.

[0119] The hardware code logic storage library 334 stores hardware code logic for generating hardware code based on the designed clock instance information and register information.

[0120] The clock instance processing unit 320 may include: a clock instance generation unit 321, which generates a new clock instance based on the generated clock instance information and clock component information of the same clock component type and stores it in the clock instance repository 333; a basic register setting unit 322, which sets the field value of the basic register that defines the basic function of the new clock instance and stores it in the clock instance repository 333; and an extended register setting unit 323, which sets the field value of the extended register that defines the extended function of the new clock instance and stores it in the clock instance repository 333.

[0121] When a user adds any clock component from the clock component window 420 to the design window 440, the clock instance generation unit 321 is executed and generates a new clock instance. The name of the new clock instance can include the name of the clock management unit in the design process that includes the new clock instance and the clock component type information of the new clock instance. Furthermore, the address of the new clock instance can be set based on the information of the previously generated clock instances and clock component information of the same clock component type. Specifically, the register start address of the new clock component can be determined by combining the register start address of the previously generated clock instance and the alignment size of the clock component information. The initial setting value of the register field can be determined based on the basic register offset size, extended register offset size, and setting field information of the clock component information.

[0122] The basic register setting unit 322 can display the field name, bit position, bit size, and initial value of the access rights included in the setting field of the basic register in the design window 440 or the setting window 450, and change it according to the user's input. The basic register sets the necessary functions of the clock source of the clock element. That is, for the phase-locked loop controller instance, the phase-locked loop type selection function, the clock element operation monitoring function, and the debugging function can be set, and the setting value of the register field corresponding to each function can be set. For the clock multiplexer instance, the multiplexer input number selection function, the clock element operation monitoring function and the debugging function can be set, and the setting value of the register field corresponding to each function can be set. For the clock divider instance, the division ratio function, the clock element operation monitoring function and the debugging function can be set, and the setting value of the register field corresponding to each function can be set. For the clock gating instance, the enable function, the clock element operation monitoring function and the debugging function can be set, and the setting value of the register field corresponding to each function can be set.

[0123] The extended register setting unit 323 can display the extended functions that can be set for each clock component on the screen. When the user selects an extended function, the field of the extended register corresponding to the corresponding extended function can be set. For the phase-locked loop controller instance, the power-off (DWRDOWN) function and the custom function can be selected, and the setting value of the extended register field corresponding to the extended function selected by the user can be set. For the clock multiplexer instance, the throttling (THROTTLE) function and the custom (CUSTOM) function can be selected, and the setting value of the confirmation register field corresponding to the extended function selected by the user can be set. For the clock divider instance, the power-off (DWRDOWN) function, the throttling (THROTTLE) function and the custom (CUSTOM) function can be selected, and the setting value of the confirmation register field corresponding to the extended function selected by the user can be set. For the clock gating instance, the short stop (SHORTSTOP) function, the early wake-up (EWAKEUP) function and the custom (CUSTOM) function can be selected, and the setting value of the confirmation register field corresponding to the extended function selected by the user can be set.

[0124] The hardware code processing unit 340 includes: a clock module generation unit 341, which generates a clock module based on the designed clock instance information; a register module generation unit 342, which generates a register module corresponding to the clock module; and a hardware code generation unit 343, which generates hardware code by combining the clock module and the register module.

[0125] When the GENRTL button in the command window 410 is selected, the hardware code processing unit 340 can be executed. When the design window 440 displays the clock diagram of the clock management unit being designed, the user can select the GENRTL button and execute it. Before executing the GENRTL button, the user can execute the check button to pre-verify whether there are any errors in the clock diagram.

[0126] The clock module generator 341 generates a clock module based on the clock instance information designed by transforming the hardware code logic stored in the hardware code logic repository 334. The port type of the clock module and the layer structure of the hardware module can be determined according to the settings of the designed clock instance.

[0127] The register module generation unit 342 can generate a register module based on the register field values of the designed clock instance and according to the hardware code logic, and can generate ports of the register module corresponding to the ports of the clock module. For example, in the case of a clock divider module, it can include a frequency division ratio port, a busy port, and a debug port. The register module corresponding to the clock divider module can also generate corresponding frequency division ratio ports, busy ports, and debug ports.

[0128] The hardware code generation unit 343 automatically connects the ports of the corresponding clock module and the ports of the register module according to the hardware code logic, and generates hardware code (register transfer level code) reflecting the setting value of the clock instance.

[0129] Figure 7 The flowchart of the codeless design method for clock elements of the present invention is shown in FIG. The codeless design method for clock elements of the present invention can be executed by a processor of a computer system.

[0130] The computer system includes: a clock component repository storing clock component information for specifying register addresses and field values for generating clock instances based on the clock components; and a hardware code logic repository storing hardware code logic for generating the designed clock instances into hardware codes.

[0131] The processor sets field values of registers defining clock instance functions based on the generated clock instance information and the clock component information and designs a new clock instance.

[0132] The process of the processor designing a new clock instance is described in detail. The processor generates a new clock instance based on the generated clock instance information and clock component information and stores it in the clock instance repository (step S710), determines the field values of the basic registers used to set the necessary functions of the clock source corresponding to the new clock instance and stores it in the clock instance repository (step S720), determines the field setting values of the extended registers that define the extended functions of the new clock instance and stores it in the clock instance repository (step S730).

[0133] Next, the processor generates a clock module and a register module corresponding to the clock module based on the field values of the registers of the designed new clock instance and the hardware code logic, and generates hardware code by combining the clock module and the register module.

[0134] The process of the processor generating hardware code is described in detail. The processor transforms the designed new clock instance according to the hardware code logic and determines the port type of the clock module (step S740), generates the port of the clock module and the register module including the corresponding port based on the register field value of the designed new clock instance (step S750), connects the port of the clock module and the port of the register module and generates hardware code reflecting the design of the new clock instance (step S760).

[0135] Figure 8An exemplary computing device 800 for executing the methods and / or embodiments is shown. According to one embodiment, the computing device 800 can be implemented using hardware and / or software for interacting with a user. The computing device 800 may include a laptop, a desktop, a workstation, a personal digital assistant, a server, a blade server, a mainframe, etc., but is not limited thereto. The structural elements of the computing device 800, their connections, and their functions are exemplary, and the examples of the present invention described in this specification and / or the scope of the invention claims are not limited thereto.

[0136] The computing device 800 includes a processor 810, a memory 820, a storage device 830, a communication device 840, a high-speed interface 850 connected to the memory 820 and the high-speed expansion port, and a low-speed interface 860 connected to the low-speed bus and the storage device. Structural elements 810, 820, 830, 840, 850, and 860 can be connected to each other using a variety of buses, can be installed on the same main board, or can be installed and connected by other appropriate means. The processor 810 can perform basic arithmetic, logical, and input / output operations, thereby processing computer program instructions. For example, the processor 810 can process instructions stored in the memory 820, the storage device 830, etc. and / or instructions running within the computing device 800, thereby displaying graphical information on an external input / output device 870 such as a display device combined with the high-speed interface 850.

[0137] The communication device 840 can provide a structure or function that enables the input / output device 870 and the computing device 800 to communicate with each other via a network, and can provide a structure or function that enables the input / output device 870 and / or the computing device 800 to communicate with other external devices, etc. For example, a request or data generated by a processor of an external device based on any program code can be transmitted to the computing device 800 via the network under the control of the communication device 840. Conversely, control signals or instructions provided under the control of the processor 810 of the computing device 800 can be transmitted to other external devices via the communication device 840 and the network.

[0138] Figure 8 The computing device 800 is shown to include a processor 810, a memory 820, etc., but is not limited thereto. The computing device 800 can be implemented using multiple memories, multiple processors and / or multiple buses, etc. Figure 8The figure shows that there is one computing device 800, but it is not limited thereto. Multiple computing devices can interact and perform necessary tasks to execute the method.

[0139] Memory 820 can store information within computing device 800. According to one embodiment, memory 820 can be comprised of a volatile memory unit or multiple memory units. Additionally or alternatively, memory 820 can be comprised of a non-volatile memory unit or multiple memory units. Furthermore, memory 820 can be comprised of other computer-readable media, such as a magnetic disk or optical disk. Furthermore, memory 820 can store an operating system and at least one program code and / or instruction.

[0140] The storage device 830 may be at least one large-capacity storage device for storing data for the computing device 800. For example, the storage device 830 may be a computer-readable medium including a hard disk, a magnetic disc such as a removable disk, an optical disc, an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a semiconductor memory device such as a flash memory device, a CD-ROM, or a DVD-ROM, or may include such a computer-readable medium. Furthermore, the computer program may be tangibly embodied in such a computer-readable medium.

[0141] The high-speed interface 850 and the low-speed interface 860 may be units for interacting with input / output devices 870. For example, input devices may include devices such as a camera with an audio sensor and / or an image sensor, a keyboard, a microphone, and a mouse, and output devices may include devices such as a display, a speaker, and a haptic feedback device. In other examples, the high-speed interface 850 and the low-speed interface 860 may be units for interfacing with a device that combines input and output functions into a single device, such as a touch screen.

[0142] According to one embodiment, the high-speed interface 850 can manage bandwidth-intensive tasks for the computing device 800, and conversely, the low-speed interface 860 can manage tasks that are less bandwidth-intensive than the high-speed interface 850, but this functional allocation is for illustrative purposes only. According to one embodiment, the high-speed interface 850 can be combined with the memory 820, the input / output device 870, and a high-speed expansion port that can accommodate a variety of expansion cards (not shown). Furthermore, the low-speed interface 860 can be combined with the storage device 830 and the low-speed expansion port. Additionally, a low-speed expansion card including multiple communication ports (e.g., USB, Bluetooth, IoT, wireless IoT) can be combined with at least one input / output device 870 such as a keyboard, a pointing device, or a scanner, or can be combined with a network device such as a router or a switch through a network adapter.

[0143] The computing device 800 can be implemented in a variety of different forms. For example, the computing device 800 can be implemented as a standard server or as a group of multiple such standard servers. Additionally or alternatively, the computing device 800 can be implemented as part of a rack server system, or can be implemented as a personal computer such as a laptop computer. In this case, the structural elements of the computing device 800 can be combined with other structural elements in any mobile device (not shown). Such a computing device 800 can include at least one other computing device or communicate with at least one other computing device.

[0144] Figure 8 The input / output device 870 is shown as not being included in the computing device 800, but the present invention is not limited thereto and can be constituted as one device together with the computing device 800. Figure 8 850 and / or the low-speed interface 860 and the processor 810 are shown as separate components, but the present invention is not limited thereto. The high-speed interface 850 and / or the low-speed interface 860 may be included in the processor 810 .

[0145] The method and / or various embodiments may be implemented by digital electronic circuits, computer hardware, firmware, software, and / or combinations thereof. Various embodiments of the present invention may be executed by a data processing device, for example, at least one programmable processor and / or at least one computer device, or may be implemented by a computer-readable medium and / or a computer program stored on a computer-readable medium. The computer program may be written in any programming language, including a compiled language or an interpreted language, and may be distributed in any form, such as a standalone program, a module, a subroutine, etc. The computer program may be distributed by a single computing device, multiple computing devices connected via the same network, and / or multiple computing devices distributed in a manner connected via multiple different networks.

[0146] The methods and / or various embodiments may operate or generate output data based on input data, and thus, may be executed by at least one processor that runs at least one computer program that processes, stores, and / or manages any functions, features, etc. For example, the methods and / or various embodiments of the present invention may be executed by special-purpose logic circuits such as field programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs), and the devices and / or systems for executing the methods and / or embodiments of the present invention may be implemented as special-purpose logic circuits such as field programmable gate arrays or application-specific integrated circuits.

[0147] The at least one processor that executes the computer program may include a general-purpose or special-purpose microprocessor and / or at least one processor of any type of digital computing device. The processor may receive instructions and / or data from a read-only memory, a random access memory, or may receive instructions and / or data from both a read-only memory and a random access memory. In the present invention, the structural elements of the computing device that executes the method and / or embodiment may include at least one processor for executing instructions and at least one memory for storing instructions and / or data.

[0148] According to one embodiment, a computing device can transmit and receive data to at least one mass storage device for storing data. For example, the computing device can receive data from a magnetic disk or an optical disk and can transmit data to the magnetic disk or optical disk. Computer-readable media suitable for storing instructions and / or data related to a computer program may include, but are not limited to, any form of non-volatile memory including semiconductor memory devices such as erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and flash memory devices. For example, computer-readable media may include magnetic disks such as internal hard drives or removable disks, photomagnetic disks, CD-ROMs, and DVD-ROMs.

[0149] To provide interaction with a user, a computing device may include a display device (e.g., a cathode ray tube (CRT), a liquid crystal display (LCD), etc.) that provides or displays information to the user, and a pointing device (e.g., a keyboard, a mouse, a trackball, etc.) that allows the user to provide input and / or instructions to the computing device, but the present invention is not limited thereto. That is, a computing device may also include any other type of device for providing interaction with a user. For example, a computing device may provide the user with any form of sensory feedback, including visual feedback, auditory feedback, and / or tactile feedback, in order to interact with the user. In this regard, the user may provide input to the computing device through various gestures, such as vision, voice, and movement.

[0150] In the present invention, various embodiments can be implemented in a computer device including a back-end structural element (e.g., a data server), a middleware structural element (e.g., an application server), and / or a front-end structural element. In this case, the structural elements can be connected to each other via any form or medium of digital data communication, such as a communication network. According to one embodiment, the communication network can be composed of a wired network such as Ethernet, a wired home network (Power Line Communication), a telephone line communication device, and RS-serial communication, a mobile communication network, a wireless local area network (WLAN), a wireless LAN, Wi-Fi, Bluetooth, and a cellular communication, or a combination thereof. For example, the communication network may include a local area network (LAN), a wide area network (WAN), and the like.

[0151] The computing device based on the exemplary embodiments described in this specification can be implemented using hardware and / or software including user equipment, user interface (UI) equipment, user terminals or client devices to interact with users. For example, the computing device may include a portable computing device such as a laptop computer. Additionally or alternatively, the computing device may include a personal digital assistant (PDA), a tablet computer, a game console, a wearable device, an Internet of Things (IoT), a virtual reality (VR) device, an augmented reality (AR) device, etc., but is not limited thereto. The computing device may also include other types of devices that interact with the user. Furthermore, the computing device may include a portable communication device (e.g., a mobile phone, a smart phone, a wireless cellular phone, etc.) suitable for wireless communication over a network such as a mobile communication network. The computing device may use wireless communication technologies and protocols such as radio frequency (RF), microwave frequency (MWF) and / or infrared ray frequency (IRF) to communicate wirelessly with a network server.

[0152] In the present invention, the various embodiments, including specific structural and functional details, are intended to be illustrative. Therefore, the present invention is not limited to the contents described, but can be embodied in a variety of different forms. Furthermore, the terms used in the present invention are intended to describe some embodiments and do not limit them. For example, unless the context clearly indicates otherwise, words in the singular include the plural.

[0153] In the present invention, unless otherwise defined, all terms used in this specification, including technical or scientific terms, have the same meanings as those commonly understood by those skilled in the art to which the present invention belongs. Furthermore, commonly used terms, such as those defined in dictionaries, have the same meanings as those in the same technical context.

[0154] While the present invention is described in this specification with reference to certain embodiments, it is understood that various modifications and variations may be made by persons skilled in the art without departing from the scope of the present invention. Furthermore, such modifications and variations are intended to fall within the scope of the claims appended to this specification.

Claims

1. A codeless design system for clock elements, which designs clock elements in a codeless manner, characterized by: include: a memory for storing at least one instruction; A clock component repository storing clock component information for specifying register addresses and field values of clock instances, wherein the clock instances are generated based on the clock components; a hardware code logic repository storing hardware code logic for generating the designed clock instance into hardware code; and at least one processor configured to execute the at least one instruction stored in the memory, The at least one instruction includes the following instructions: Generate field values of registers defining a new clock instance function based on the generated clock instance information and the clock component information and design the new clock instance; and A clock module and a register module corresponding to the clock module are generated based on the field values of the designed registers of the new clock instance and the hardware code logic, and hardware code is generated by combining the clock module and the register module.

2. The clock element codeless design system according to claim 1, characterized in that: The at least one instruction further includes the following instruction: generating the new clock instance based on the generated clock instance information and the clock component information and storing the new clock instance in a clock instance repository; determining a field value of a basic register used to set necessary functions of a clock source corresponding to the new clock instance and storing the field value in the clock instance repository; as well as Field setting values of an extension register for defining an extended function of the new clock instance are determined and stored in the clock instance repository.

3. The clock element codeless design system according to claim 1, characterized in that: The at least one instruction further includes the following instruction: Transforming the designed new clock instance according to the hardware code logic and determining the port of the clock module; generating the register module including ports corresponding to the ports of the clock module based on the register field values of the designed new clock instance; as well as Connecting ports of the clock module with ports of the register module and generating hardware code reflecting the design of the new clock instance.

4. The clock element codeless design system according to claim 1, characterized in that: The clock component information includes an address range allocated to each clock component, an alignment size of each clock component, a basic register offset size of each component, an extended register offset size of each component, and setting field information of each clock component.

5. The clock element codeless design system according to claim 4, characterized in that: The setting field information of each clock component includes field name, bit position, bit size, access permission, and initial value.

6. The clock element codeless design system according to claim 4, characterized in that: The start address of the register of the new clock instance is determined by the sum of the start address of the register of the generated clock instance and the alignment size.

7. The clock element codeless design system according to claim 2, characterized in that: The clock component is one of a phase-locked loop controller component, a clock divider component, a clock multiplexer component, and a clock gating component.

8. The clock element codeless design system according to claim 7, characterized in that: The clock component is a phase-locked loop controller component, The field of the extended register of the new clock instance includes at least one of a power-off field and a custom field.

9. The clock element codeless design system according to claim 7, characterized in that: The clock component is a clock divider component, The fields of the extended register of the new clock instance include at least one of a power-off field, a throttling field, and a custom field.

10. The clock element codeless design system according to claim 7, characterized in that: The clock component is a clock multiplexer component, The field of the extended register of the new clock instance includes at least one of a throttle field and a custom field.

11. The codeless design system for clock elements according to claim 7, characterized in that: The clock component is a clock gating component, The fields of the extended register of the new clock instance include at least one of a short stop field, an early wakeup field, and a custom field.

12. A method for designing a clock element without code, comprising designing a clock element executed by at least one processor in a computer system in a codeless manner, the computer system comprising: A clock component repository storing clock component information for specifying register addresses and field values of clock instances generated based on the clock components; and a hardware code logic repository storing hardware code for generating the designed clock instance. The clock element codeless design method is characterized by including: The first step is to set the field values of the registers defining the function of the new clock instance based on the generated clock instance information and the clock component information and design the new clock instance; as well as In the second step, a clock module and a register module corresponding to the clock module are generated based on the field values of the registers of the designed new clock instance and the hardware code logic, and hardware code is generated by combining the clock module and the register module.

13. The codeless design method for clock elements according to claim 12, characterized in that: The first step includes the following steps: generating the new clock instance based on the generated clock instance information and the clock component information and storing the new clock instance in a clock instance repository; determining a field value of a basic register used to set necessary functions of a clock source corresponding to the new clock instance and storing the field value in the clock instance repository; as well as Field setting values of an extension register for defining an extended function of the new clock instance are determined and stored in the clock instance repository.

14. The codeless design method for clock elements according to claim 12, wherein: The second step includes the following steps: Determining a port of the clock module according to the new clock instance designed by the hardware code logic transformation; generating the register module including ports corresponding to the ports of the clock module based on the register field values of the designed new clock instance; as well as Connecting ports of the clock module with ports of the register module and generating hardware code reflecting the design of the new clock instance.

15. The codeless design method for clock elements according to claim 12, wherein: The clock component information includes an address range allocated to each clock component, an alignment size of each clock component, a basic register offset size of each component, an extended register offset size of each component, and setting field information of each clock component.

16. The codeless design method for clock elements according to claim 15, characterized in that: The setting field information of each clock component includes field name, bit position, bit size, access permission, and initial value.

17. The codeless design method for clock elements according to claim 15, wherein: The start address of the register of the new clock instance is determined by the sum of the register start address and the alignment size of the generated clock instance.

18. The codeless design method for clock elements according to claim 13, wherein: The clock component is one of a phase-locked loop controller component, a clock divider component, a clock multiplexer component, and a clock gating component.

19. The codeless design method for clock elements according to claim 18, wherein: The clock component is a phase-locked loop controller component, The field of the extended register of the new clock instance includes at least one of a power-off field and a custom field.

20. The codeless design method for clock elements according to claim 18, wherein: The clock component is a clock divider component, The fields of the extended register of the new clock instance include at least one of a power-off field, a throttling field, and a custom field.

21. The codeless design method for clock elements according to claim 18, wherein: The clock component is a clock multiplexer component, The field of the extended register of the new clock instance includes at least one of a throttle field and a custom field.

22. The codeless design method for clock elements according to claim 18, wherein: The clock component is a clock gating component, The fields of the extended register of the new clock instance include at least one of a short stop field, an early wakeup field, and a custom field.

23. A computer program, characterized in that The method according to any one of claims 12 to 22 is stored on a computer-readable medium for executing the method in a computer.

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