Circuit diagram automatic layout method, storage medium and electronic device

Abstract

The present application discloses a method for automatic layout of circuit diagrams, a storage medium and an electronic device, the method comprising: forming a directed acyclic graph based on components and their connection relationships extracted from a PCB file; the directed acyclic graph comprising a plurality of nodes and edges; assigning nodes of different levels in the directed acyclic graph to different layers, with all nodes of the same layer being located at the same layer; adjusting the order of all nodes in the same layer, and recording the node ordering method with the least number of intersections when connecting nodes between two adjacent layers; traversing all nodes in the directed acyclic graph, setting the branch attributes of each node; and determining the coordinates of all nodes in the directed acyclic graph by combining the node ordering method and the branch attributes. The directed acyclic graph extracted by the present application based on the PCB file has the advantages of a clear hierarchical structure and few line intersections. At the same time, a directed acyclic graph that conforms to circuit rules is set in combination with different branch attributes.

Description

Technical Field

[0001] The present application relates to the field of layout, and in particular to a circuit diagram automatic layout method, storage medium and electronic equipment. Background Art

[0002] After a PCB (printed circuit board) design is completed, it's difficult to visually assess the rationality of the circuit design. To this end, engineers must manually screen components and perform layout and wiring by observing and analyzing the connections between components in the circuit. Furthermore, to ensure a clear topology diagram depicting the overall connectivity, engineers must also spend considerable time adjusting component layout and wiring. This demonstrates the inefficiency of manually drawing topology diagrams. Summary of the Invention

[0003] In order to solve the above problems, the present application provides a circuit diagram automatic layout method, storage medium and electronic device.

[0004] In a first aspect, the present application provides 1. a method for automatic layout of a circuit diagram, comprising:

[0005] Forming a directed acyclic graph based on the components extracted from the PCB file and their connection relationships; the directed acyclic graph includes a plurality of nodes and graph edges for connecting two nodes, the nodes are used to represent the components, and the graph edges are used to represent the connection relationships between the components;

[0006] Assigning nodes of different levels in the directed acyclic graph to different layers, where all nodes of the same level are located in the same layer; the different layers include a first layer, a second layer, and a third layer, the first layer includes at least one first node, the second layer includes at least one second node, and the third layer includes at least one third node;

[0007] Adjust the order of all nodes in the same level and record the node ordering method with the least number of crosses when connecting nodes between two adjacent levels;

[0008] Traversing all nodes in the directed acyclic graph, setting branch attributes of each node, wherein the branch attributes include main path, pull-up, and pull-down;

[0009] The coordinates of all nodes in the directed acyclic graph are determined by combining the node sorting method and the branch attributes.

[0010] Optionally, before adjusting the order of all nodes in the same level and recording the node connections between two adjacent levels, the node sorting method with the least number of crosses may further include:

[0011] The fourth node of the cross-level connection is found through traversal, and a virtual node for direct connection is added according to the number of levels crossed.

[0012] Optionally, forming a directed acyclic graph based on the components extracted from the PCB file and their connection relationships includes:

[0013] Based on the components extracted from the PCB file and their connection relationships, an undirected overall graph is formed;

[0014] After traversing and determining the directions of the edges in the undirected general graph and eliminating the loops in the undirected general graph, the directed acyclic graph is formed; eliminating the loops in the undirected general graph includes adjusting two nodes of the first level to point to the same node of the second level.

[0015] Optionally, the step of forming a directed acyclic graph based on the components extracted from the PCB file and their connection relationships further includes:

[0016] When the third node is connected to the first node through the second node, if it is analyzed that the control signal between the third node and the first node does not pass through the second node, the first node and the third node are adjusted to a direct connection relationship.

[0017] Optionally, the step of forming an undirected general graph based on the components extracted from the PCB file and their connection relationships further includes:

[0018] Forming a first undirected graph according to the components extracted from the PCB file and their connection relationships;

[0019] When traversing the first undirected graph, analyzing missing components in the first undirected graph in combination with all extracted components;

[0020] Any missing component is selected as the first node of the second undirected graph, and all missing components and their connection relationships are combined to form a second undirected graph; the undirected overall graph includes the first undirected graph and the second undirected graph.

[0021] Optionally, allocating nodes at different levels in the directed acyclic graph to different layers includes:

[0022] Searching for the first node with zero in-degree in the directed acyclic graph, and using all the first nodes with zero in-degree to construct a first layer;

[0023] After the first layer is constructed, all first nodes corresponding to the first layer are deleted, and the second nodes with zero in-degree in the directed acyclic graph are queried again to construct a second layer stacked in the direction of extension of the first layer; the above steps are repeated until all nodes in the directed acyclic graph are deleted.

[0024] Optionally, the adjusting the order of all nodes in the same level and recording the node sorting method with the least number of crosses when connecting nodes between two adjacent levels also includes:

[0025] According to the first direction, two adjacent layers are divided into a unit group. The node order of one layer remains unchanged. After adjusting the node order of the other layer, the node ordering method with the least number of crossovers when connecting the nodes between the two adjacent layers is recorded. The total number of crossovers in the even-numbered rounds of order optimization is accumulated for all unit groups.

[0026] According to the second direction, two adjacent layers are divided into a unit group, the node order of one layer remains unchanged, and after adjusting the node order of the other layer, the node ordering method with the least number of crossovers when connecting the nodes between the two adjacent layers is recorded. The total number of crossovers in the odd-numbered rounds of order optimization is accumulated for all unit groups; the second direction is opposite to the first direction;

[0027] Select the node ordering method that minimizes the total number of crossovers in multiple rounds of optimization.

[0028] Optionally, traversing all nodes arranged in the node sorting manner and setting a branch attribute of each node includes:

[0029] Find all third nodes with zero out-degree in the directed acyclic graph, traverse the directed acyclic graph in reverse with the third node as the starting node, and determine the branch attribute of each node; when the branch attribute is set to the main path, the node is a receiving end; when the branch attribute is set to pull-up, the node is a power supply; when the branch attribute is set to pull-down, the node is other cases;

[0030] When the branch attributes determined by different branches of the same node in the directed acyclic graph are different, the branch attributes are determined according to priority; the priority of the main road is higher than the priority of the power supply, and the priority of the power supply is higher than other priorities.

[0031] Optionally, the determining the coordinates of all nodes in the directed acyclic graph by combining the node sorting method and the branch attributes includes:

[0032] Aggregate a first node and a second node connected to the first node in two adjacent layers into a cluster, arrange the order of the clusters according to the order of the first nodes, arrange the branches formed by the nodes in each cluster according to the branch attribute rules, and arrange the nodes in each branch according to the node sorting method.

[0033] Optionally, the determining the coordinates of all nodes in the directed acyclic graph by combining the node sorting method and the branch attributes further includes:

[0034] When the third nodes in a cluster of the third layer cannot be arranged symmetrically with the second node as the center, adjusting the positions of the second nodes so that the third nodes are arranged symmetrically with the second node as the center;

[0035] The position of the first node of the first layer is corrected by traversing and backward deduction, so that the second nodes are arranged symmetrically with the first node as the center, all nodes in each cluster are arranged according to the same branch attribute rule, and all clusters and nodes within the cluster maintain their order.

[0036] In a second aspect, the present application provides a storage medium having a computer program or instruction stored thereon, which, when executed by a processor, implements the steps of a circuit diagram automatic layout method described in any one of the above items.

[0037] In a third aspect, the present application provides an electronic device, further comprising: a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of a circuit diagram automatic layout method as described in any one of the above items.

[0038] Compared with the prior art, this application has at least one of the following beneficial effects:

[0039] This application extracts a directed acyclic graph from the PCB file and reconstructs all the nodes in the directed acyclic graph in layers to eliminate the visual confusion caused by random layout; the topological structure is clearly layered. At the same time, based on the optimization of the node order, the crossing of the lines in the topological diagram is significantly reduced. In addition, circuit rules such as power pull-up and ground pull-down are forcibly injected into the layout to ensure that the physical connections of different branches conform to the electrical logic. Therefore, when the device scale is large, the efficiency and convenience of engineers analyzing schematics will be significantly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The following is a brief introduction to the drawings used in describing the embodiments of this application:

[0041] Figure 1 This is a flow chart of a method for automatic layout of a circuit diagram provided by an embodiment of the present application;

[0042] Figure 2 This is a flowchart of another circuit diagram automatic layout method provided by an embodiment of the present application;

[0043] Figure 3 This is a schematic diagram of an unsorted partial circuit diagram provided in an embodiment of the present application;

[0044] Figure 4 It is a schematic diagram of a partial circuit diagram of a descending cross-ordering hierarchy layout provided in an embodiment of the present application;

[0045] Figure 5is a schematic diagram of a partial circuit diagram of a loop elimination provided in an embodiment of the present application;

[0046] Figure 6 It is a schematic diagram of a partial circuit diagram of two directed acyclic graphs provided in an embodiment of the present application;

[0047] Figure 7 This is a schematic diagram of a local circuit diagram after traversal and back-calculation correction provided in an embodiment of the present application. DETAILED DESCRIPTION

[0048] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the specific implementation methods of the present application will be described below with reference to the accompanying drawings. The drawings and implementation methods described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings and implementation methods can be obtained based on these drawings and implementation methods without creative work. Adjustments and improvements made without departing from the concept of the present application are all within the scope of protection of the present application.

[0049] To simplify the drawings, only the parts relevant to the present application are schematically shown in each figure. They do not represent the actual structure of the product. In addition, to simplify the drawings and facilitate understanding, in some figures, only some of the components with the same structure or function are schematically shown. In reality, more or fewer components with the same structure or function may exist.

[0050] In this application, unless otherwise specified or limited, ordinal numbers such as "first" and "second" are used solely to distinguish and describe related objects and are not to be construed as indicating or implying the relative importance or order of the related objects; furthermore, they do not represent the quantity of the related objects. The terms "installed" and "connected" should be interpreted broadly. For example, "installed" can mean directly installed or installed through other components; "connected" can mean directly connected or connected through other components.

[0051] After a PCB (printed circuit board) design is completed, it's difficult to visually assess the rationality of the circuit design. To this end, engineers must manually screen components and perform layout and wiring by observing and analyzing the connections between components in the circuit. Furthermore, to ensure a clear topology diagram depicting the overall connectivity, engineers must also spend considerable time adjusting component layout and wiring. This demonstrates the inefficiency of manually drawing topology diagrams.

[0052] Existing EDA tools offer some topology extraction and visualization solutions, such as Altium Designer's "Signal Harness" feature and Cadence's Sigrity Topology Explorer. However, these solutions employ relatively simple layout algorithms, which can easily lead to cluttered interface layouts after wiring when working with medium- and large-scale devices. Furthermore, they often fail to consider specific circuit rules, such as the need for pull-up power paths and pull-down ground paths, resulting in a lack of logical clarity in the visualization results.

[0053] Currently, the algorithms widely used for layout problems mainly include the following directions:

[0054] (1) Force-directed algorithms: This algorithm simulates the mechanical equilibrium in physical systems and optimizes layout by calculating the attractive and repulsive forces between nodes. It is suitable for visualizing small and medium-sized networks. However, it often fails to incorporate constraints from specific fields (such as circuit design) during the layout process, resulting in poor logical relevance of the final layout results.

[0055] (2) Structured layout algorithm: mainly includes tree layout and circular layout.

[0056] Tree layout: This emphasizes the hierarchical relationship between parent and child nodes, and uses a radial tree layout (radiating outward from the root node). However, it only works with tree structures and cannot effectively handle topologies containing loops, which are common in PCB topology networks.

[0057] Circular layout: Distribute nodes evenly around the circumference of a circle. PCB topologies presented this way often lack clarity and intuitiveness in their inherent connection logic.

[0058] This application extracts a directed acyclic graph from the PCB file and reconstructs all the nodes in the directed acyclic graph in layers to eliminate the visual confusion caused by random layout; the topological structure is clearly layered. At the same time, based on the optimization of the node order, the crossing of the lines in the topological diagram is significantly reduced. In addition, circuit rules such as power pull-up and ground pull-down are forcibly injected into the layout to ensure that the physical connections of different branches conform to the electrical logic. Therefore, when the device scale is large, the efficiency and convenience of engineers analyzing schematics will be significantly improved.

[0059] The following is a description with reference to the accompanying drawings:

[0060] Please refer to Figure 1 , a circuit diagram automatic layout method, comprising the following steps:

[0061] S10, forming a directed acyclic graph based on the components extracted from the PCB file and their connection relationships; the directed acyclic graph includes a plurality of nodes and edges for connecting two nodes, the nodes are used to represent components, and the edges are used to represent the connection relationship between the components;

[0062] S20, assigning nodes of different levels in the directed acyclic graph to different layers, where all nodes of the same level are located in the same layer; the different layers include a first layer, a second layer, and a third layer, where the first layer includes at least one first node, the second layer includes at least one second node, and the third layer includes at least one third node;

[0063] S40, adjusting the order of all nodes in the same level, and recording the node sorting method with the least number of crosses when connecting nodes between two adjacent levels;

[0064] S50, traversing all nodes in the directed acyclic graph, setting branch attributes of each node, where the branch attributes include main path, pull-up, and pull-down;

[0065] S60. Determine the coordinates of all nodes in the directed acyclic graph by combining the node sorting method and branch attributes.

[0066] In this embodiment, the PCB file (or PCB source file) is the core design file generated by electronic design automation (EDA) software. By performing geometric analysis on the PCB file, components and their parameters can be identified; by parsing the netlist, the connection relationships between components can be extracted. Combining the identified components and their connection relationships, a directed acyclic graph (DAG) can be generated. A DAG consists of multiple branches, each of which contains multiple nodes and directed edges connecting two nodes. Nodes represent components, and directed edges represent the connection relationships between components.

[0067] Since the complete circuit diagram is relatively complex, the complete circuit diagram cannot be clearly displayed, and the embodiments are described using a partial circuit diagram as an example. Figure 5As shown, the directed acyclic graph includes nodes U1, N1, N2, R1, N3, N4, R3, and so on. Node U1's children are N1 and N2, N1's children are R1 and N3, N2's children are N4 and R3, and so on. All nodes with the same hierarchical relationship are grouped into the same level; for example, node U1 is assigned to the first level (top level), nodes N1 and N2 are assigned to the second level (middle level 1), nodes R1, N3, N4, and R3 are assigned to the third level (middle level 2), and node U2 is assigned to the seventh level (bottom level). These nodes are distributed across different levels, and the total number of levels depends on the specific circuit diagram. Among them, node N1, node R1, node N5, node V1, and node N8 constitute a branch, and node N1, node R1, node N6, and node C1 constitute a branch. The directed acyclic graph (DAG) is composed of multiple branches, and other branches are not repeated here.

[0068] If nodes N1 and N2 are placed one above the other in the second layer, adjust the order of nodes N1 and N2, i.e., swap their top-to-bottom placement. If nodes N1 and N2 are placed left-to-right, adjust their left-to-right placement. When nodes N1 and N2 are arranged from top to bottom, adjust the node order, then arrange nodes N2 and N1 from top to bottom. Calculate the number of intersections between the first graph edge connecting node N1 to node U1 and the second graph edge connecting node N2 to node U1.

[0069] For example, the positions of nodes R1, N3, N4, and R3 on the third layer are adjusted. That is, when nodes R1, N3, N4, and R3 are arranged in order from top to bottom, after adjusting the node order, nodes N4, N3, R1, and R3 can be arranged in order from top to bottom, or nodes R1, N4, N3, and R3 can be arranged in order from top to bottom, etc. The third graph edge connecting nodes R1 and N1, the fourth graph edge connecting nodes N3 and N1, the fifth graph edge connecting nodes N4 and N2, and the sixth graph edge connecting nodes N4 and N2 are calculated. The number of intersections between the third graph edge, the fourth graph edge, the fifth graph edge, and the sixth graph edge is calculated. The sorting method with the least number of intersections is used as the sorting method for the nodes. For example, when nodes R1, N3, N4, and R3 are arranged in order from top to bottom, the number of intersections is the least. According to the above method, the node order of nodes at other levels in the directed acyclic graph can be adjusted, which will not be repeated here.

[0070] Traverse nodes U1, N1, N2, R1, N3, N4, R3, and so on. When a node is a receiver, its branch attribute is set to main; when a node is a power source, its branch attribute is set to pull-up; when a node is in other situations (such as grounded), its branch attribute is set to pull-down. Combine the node sorting method and branch attributes to determine the coordinates of all nodes in the directed acyclic graph.

[0071] The directed acyclic graph extracted from the PCB file in this embodiment has the advantages of a clear hierarchical structure and few cross-connections. At the same time, a directed acyclic graph that conforms to circuit rules is set in combination with different branch attributes. This helps industry personnel quickly identify the circuit functions of different branches from the schematic diagram constructed based on the PCB file, thereby more efficiently performing PCB design verification, performance optimization iteration, and debugging and maintenance. If the layout optimization solution of this embodiment is not adopted, the circuit schematic diagram will have the following problems: unclear hierarchical structure, too many cross-connections, and non-compliance with circuit rules. Figure 3 As shown, this partial circuit schematic has not been optimized for line crossing and circuit rules. It can be seen that the diagram has many line crossings and violates circuit rules, which is very unfavorable for R&D personnel to view the circuit principle. If it is a complete circuit diagram, the lines are intertwined and the circuit diagram cannot be viewed at all. Figure 4 As shown in the figure, after the partial circuit schematic has been optimized for cross-connections, cross-connections have been significantly reduced, making it easier for R&D personnel to understand the circuit principles. When the partial circuit schematic is further optimized for circuit rules, it further helps R&D personnel quickly identify the circuit meaning of different branches.

[0072] In some embodiments, please refer to Figure 2 , before adjusting the order of all nodes in the same level and recording the node connections between two adjacent levels, the node sorting method with the least number of crosses also includes the following steps: S30, traverse to find the fourth node of the cross-level connection, and add a virtual node for direct connection according to the number of levels crossed, and add a virtual node for each level crossed.

[0073] In this embodiment, since the subsequent node order adjustment to reduce intersections only works between adjacent layers, it is necessary to create virtual nodes for nodes that span multiple levels to serve as intermediate connections. The specific implementation is: traverse the nodes of each layer and identify the connection relationship with a length (i.e., the number of layers spanned) greater than 1; then fill in the virtual nodes in the intermediate layers involved in these long connections, and synchronously update their parent-child relationships. For example, when the fourth node spans two levels and is connected to the third node, the second node, the first node, or another node, it is necessary to set a virtual node (first virtual node, second virtual node) on each of the two levels spanned, the fourth node is connected to the first virtual node, the first virtual node is connected to the second virtual node, and the second virtual node is connected to the third node, the second node, the first node, or another node. When calculating the coordinates subsequently, the coordinates of the virtual nodes will also be calculated, but the virtual nodes will not be presented in the directed acyclic graph.

[0074] In some embodiments, a directed acyclic graph is formed based on components extracted from a PCB file and their connection relationships, including:

[0075] Based on the components extracted from the PCB file and their connection relationships, an undirected overall graph is formed;

[0076] After traversing and determining the directions of the edges in the undirected overall graph and eliminating the loops in the undirected overall graph, a directed acyclic graph is formed; eliminating the loop includes adjusting two nodes in the first level to point to the same node in the second level.

[0077] In this embodiment, an undirected graph structure is used to store the connection relationships of link nodes during the PCB topology extraction process. However, an undirected graph only records the adjacency relationships between nodes, does not explicitly specify the connection direction, and often contains loops, making it essentially an undirected graph. This does not conform to the DAG (directed acyclic graph) input required by the Sugiyama algorithm (a hierarchical layout algorithm).

[0078] To obtain the desired DAG, the device nodes and their connections are first abstracted into an undirected graph. This undirected graph is then traversed using a breadth-first search (BFS). The traversal begins with the user-defined driver node (signal source) as the initial queue. BFS directs the graph edges and eliminates loops, ultimately generating a directed acyclic graph. Choosing the driver node as the starting point ensures that all drivers are located on the same side of the final layout.

[0079] When eliminating loops, Figure 5As shown, starting from node U1, traverse the child nodes N1 and N2 of node U1, then traverse the child node N3 of node N1 and the child node N4 of node N2, and then traverse the child node R2 of node N3. When traversing node R2, it is found that nodes N1, N2, N3, N4, and R2 form a loop. In order to eliminate the loop, nodes N3 and N4 are adjusted to point to node R2 at the same time.

[0080] The main reason for choosing BFS over depth-first search (DFS) is that BFS can expand all child branches of the same parent node in parallel. This property is crucial when dealing with cycles, as it ensures that the child nodes ultimately visited in a cycle have a similar number of ancestral levels on either side. This balance helps avoid long connections that span multiple levels of ancestry in subsequent layouts.

[0081] In some embodiments, a directed acyclic graph is formed based on components extracted from a PCB file and their connection relationships, and also includes: when a third node is connected to a first node through a second node, when it is analyzed that the control signal between the third node and the first node does not pass through the second node, adjusting the first node and the third node to a directly connected relationship.

[0082] When converting a PCB file to a directed acyclic graph (DAG), the components are abstracted and each component is treated as a node. In some cases, the actual connection on the PCB occurs between the ports of the components, rather than between the components themselves. For example, a child node may be connected to a port of a parent node, and the port of the parent node is directly connected to the grandparent node. This means that the child node is actually connected to the grandparent node through the port of the parent node, and the grandparent node of the child node can be adjusted to the parent node. Figure 5 As shown in the figure, if node N6 is connected to a port of node R1 close to node N1, and node R1 is connected to node N1, then node N6 is actually directly connected to node N1. This can be adjusted to connect node N6 to node N1. This abstraction method can effectively reduce the total number of levels in the directed acyclic graph, thereby reducing the depth of the graph and making the entire graph structure more concise.

[0083] In some embodiments, forming a directed acyclic graph based on components extracted from a PCB file and their connection relationships also includes: forming a first undirected graph based on components extracted from a PCB file and their connection relationships.

[0084] When traversing the first undirected graph, all extracted components are combined to analyze missing components in the first undirected graph.

[0085] Any missing component is selected as the first node of the second undirected graph, and all missing components and their connection relationships are combined to form a second undirected graph; the undirected overall graph includes the first undirected graph and the second undirected graph.

[0086] In this embodiment, if Figure 6 As shown in the figure, when constructing the first undirected graph (the initial undirected graph), when traversing to node V3, the traversal terminates because it has no child nodes and all nodes in the first undirected graph have been visited (the traversal process records all visited nodes). At this point, if the set of traversed nodes is inconsistent with the set of all components to be laid out extracted from the PCB file, it indicates a broken connection, meaning that some nodes are missing from the first undirected graph.

[0087] Once a broken connection is detected, a random node (e.g., node R4) is selected from the untraversed nodes as the new starting node and traversal begins with this node as the root node, generating a second undirected graph. Given the complexity of PCB designs or potential errors in link extraction, the connections between input components may also be broken. To ensure topological integrity, when the BFS traversal fails to cover all nodes, independent sub-DAGs (Directed Acyclic Graphs) are constructed for the unvisited portions. These sub-DAGs are processed separately in the subsequent layout phase.

[0088] In some embodiments, assigning nodes at different levels in the directed acyclic graph to different layers further includes:

[0089] The first node with in-degree zero in the directed acyclic graph is searched, and all the first nodes with in-degree zero are used to construct the first layer.

[0090] After the first layer is constructed, all first nodes corresponding to the first layer are deleted, and the second node with zero in-degree in the directed acyclic graph is searched again to construct the second layer stacked in the direction of the first layer; the above steps are repeated until all nodes in the directed acyclic graph are deleted.

[0091] In this embodiment, based on the idea of ​​Kahn's algorithm in topological sorting, the process repeatedly performs the following operations: query all nodes with zero in-degree in the DAG, create these nodes with zero in-degree as a new layer, and then remove these nodes with zero in-degree and their graph edges from the directed acyclic graph. After the removal operation is completed, the remaining directed acyclic graph is queried again for nodes with zero in-degree, and the next level is constructed and the stack is extended downward. This cycle continues until all nodes in the directed acyclic graph are removed. Ultimately, all nodes are assigned to different levels. A node with zero in-degree refers to a node in the directed acyclic graph where no arrow of any graph edge points to the node.

[0092] like Figure 5 As shown, in the directed acyclic graph, the node with zero in-degree is found to be node U1. After node U1 is created as the first layer, node U1 is deleted from the directed acyclic graph. From the directed acyclic graph from which node U1 is deleted, the nodes with zero in-degree are found to be nodes N1 and N2. After nodes N1 and N2 are created as the second layer and stacked downward from the first layer, nodes N1 and N2 are deleted from the directed acyclic graph. This cycle continues until all nodes in the directed acyclic graph are removed.

[0093] In some embodiments, adjusting the order of all nodes in the same level and recording the node connections between two adjacent levels in a node sorting method with the least number of crossovers also includes:

[0094] According to the first direction, two adjacent layers are divided into a unit group. The node order of one layer remains unchanged. After adjusting the node order of the other layer, the node ordering method with the least number of crossovers when connecting the nodes between the two adjacent layers is recorded. The total number of crossovers in the even-numbered rounds of order optimization is accumulated for all unit groups.

[0095] According to the first direction, two adjacent layers are divided into a unit group. The node order of one layer remains unchanged. After adjusting the node order of the other layer, the node order with the least number of crossovers when connecting the nodes between the two adjacent layers is recorded. The total number of crossovers in the odd-numbered rounds of order optimization is accumulated for all unit groups. The second direction is opposite to the first direction.

[0096] Select the node ordering method that minimizes the total number of crossovers in multiple rounds of optimization.

[0097] In this embodiment, node order adjustments are limited to the same level and do not change the level of the node. The optimization process continues for a maximum of n iterations, where n is determined based on the desired optimization results. Optimization ends when the results stabilize. Within each optimization round, the direction of the layer traversal alternates: for example, even-numbered (2, 4, 6, ...) rounds traverse from the top to the bottom, while odd-numbered (1, 3, 5, ...) rounds traverse from the bottom to the top. When optimizing two adjacent layers in each round, the upper layer is fixed (its node order remains unchanged), while the lower layer becomes the active layer (its node order is adjustable).

[0098] like Figure 5As shown, the first round of optimization traverses from the first to the seventh layer. The first and second layers are divided into a unit group. The first layer is set as a fixed layer, and the order of node U1 in the first layer remains unchanged. The second layer is set as an active layer, and the order of nodes N1 and N2 can be adjusted. The second and third layers are divided into a unit group. The second layer is set as a fixed layer, and the order of nodes N1 and N2 in the second layer remains unchanged. The third layer is set as an active layer, and the order of nodes R1, N3, N4, and R3 can be adjusted. This process continues in this order, completing the first round of optimization.

[0099] The second round of optimization traverses from the seventh layer to the first layer. The seventh and sixth layers are grouped together. The seventh layer is set as a fixed layer, leaving the order of node U2 unchanged. The sixth layer is set as the active layer, allowing for adjustments to the order of nodes N8 and N9. The sixth and fifth layers are grouped together. The sixth layer is set as a fixed layer, leaving the order of nodes N8 and N9 unchanged. The fifth layer is set as the active layer, allowing for adjustments to the order of nodes V1, C1, and V2. This process continues in this order, completing the second round of optimization.

[0100] The third round of optimization traverses from the first layer to the seventh layer, and the fourth round traverses from the seventh layer to the first layer. In each optimization round (whether forward or backward), two adjacent layers are always divided into a unit group (e.g., layers 1-2, layers 2-3, layers 3-4, etc.). However, there is a difference in the fixed layers between forward and backward optimization: for the same unit group (e.g., layers 1-2), forward optimization fixes the previous layer (i.e., layer 1), while backward optimization fixes the next layer (i.e., layer 2). A crossover cost matrix is ​​constructed based on the connection relationships between the nodes in the two layers. This matrix quantifies the number of possible crossovers caused by different node orders in the active layer. Based on this crossover cost matrix, a merge sort algorithm is applied to sort the active layer nodes. The goal of the sorting is to select a node order that minimizes the number of crossovers between the two layers and record the number of crossovers resulting from this order.

[0101] Each optimization round traverses all combinations of adjacent layers, summing the crossover counts calculated for each pair of adjacent layers to obtain the global crossover count for that round. The result of a single optimization round is the optimal solution based on the number of completed optimization rounds.

[0102] To this end, the system performs multiple rounds of optimization, reversing the direction of layer traversal in each round (for example, even-numbered rounds: top to bottom; odd-numbered rounds: bottom to top). After multiple rounds of iteration, the system selects the optimization result with the smallest total number of global crossovers and determines its node order as the final node order for all layers.

[0103] Since only adjusting the order between two adjacent layers cannot guarantee the global optimal layout result (that is, the layout with the minimum number of intersections in the entire graph), in order to effectively control the computational complexity, the actual strategy adopted by this method is: generate multiple candidate solutions through multiple rounds of local optimization, and screen out the node sorting solution with the minimum number of intersections.

[0104] In some embodiments, traversing all nodes arranged in a node sorting manner and setting a branch attribute of each node further includes:

[0105] Find all third nodes with zero out-degree in the directed acyclic graph, traverse the directed acyclic graph in reverse from the third node, and determine the branch attribute of each node; when the branch attribute is set to main path, the node is a receiver; when the branch attribute is set to pull-up, the node is a power supply; when the branch attribute is set to pull-down, the node is other conditions, such as grounding, via, or floating;

[0106] When the branch attributes determined by different branches of the same node in the directed acyclic graph are different, the branch attributes are determined according to the priority; the priority of the main road is higher than the priority of the power supply, and the priority of the power supply is higher than other priorities.

[0107] In this embodiment, to obtain the branch status (pull-up, pull-down, main path) of all nodes, all nodes with an out-degree of zero in the directed acyclic graph are found. If the node is found to be a receiver, the branch attribute is set to main path. If the node is a power supply, the branch attribute is set to pull-up. If the node is other (such as ground), the branch attribute is set to pull-down. Starting from these nodes with an out-degree of zero, a reverse BFS traversal is performed and the type propagation of branch attributes is performed. Ultimately, the branch attributes of all nodes can be determined. A node with an out-degree of zero is a node that has only input and no output.

[0108] like Figure 5 As shown, the nodes with zero out-degree are U2 and C1. Node U2 is a receiver, so the branch attribute is a main path. Node C1 is a ground, so the branch attribute is a pull-down path. A reverse BFS traversal is performed from nodes U2 and C1, and the branch attribute type propagation is performed. Node V1's branch attribute is a main path, and node N6's branch attribute is a pull-down path. From node N6, the branch attribute is propagated to node R1. Node R1's branch attribute is also a pull-down path, and node N5's branch attribute is a main path. From node N5, the branch attribute is propagated to node R1. The main path has a higher priority than the power supply, which has a higher priority than other priorities. Therefore, the branch attribute of node R1 is a main path. This analogy can be used to obtain the branch attributes of other nodes, which will not be further explained here. In a topological circuit simulation scenario, the power supply branch is a pull-up path (located at the top), the ground branch is a pull-down path (located at the bottom), and the IC branch is placed in the middle. This device topology layout is more consistent with circuit common sense and makes circuit analysis more convenient and efficient.

[0109] In some embodiments, determining the coordinates of all nodes in the directed acyclic graph by combining the node sorting method and the branch attributes further includes:

[0110] A first node and a second node connected to the first node in two adjacent layers are aggregated into a cluster, and the order of the clusters is arranged according to the order of the first nodes. The nodes in each cluster are arranged according to the same branch attribute rule.

[0111] In this embodiment, nodes in two adjacent layers are always aggregated into one cluster (for example, layers 1-2, 2-3, 3-4, etc.). After obtaining the branch attributes of all nodes, the specific coordinates of the nodes need to be determined. First, the coordinates of all nodes are determined by maintaining the circuit branch attributes (pull-down, main path, pull-up) as the first criterion, and then combined with the previously optimized node sorting method. For example, starting from the second layer, all first nodes (parent nodes) of the first layer are first traversed in the order of the coordinates of the first node of the first layer, and each parent node of the first layer is aggregated into a cluster corresponding to the child node (second node) of the second layer. When determining the coordinates of the second-layer nodes, all clusters are sorted in the order of the parent nodes (the first node of the first layer). The branches formed by all child nodes within the same cluster are first set according to the circuit branch attributes (pull-down, main path, pull-up), and the order of nodes within each branch is then sorted according to the previously optimized node sorting method.

[0112] The order of all clusters is the same as that of their parent nodes, while child nodes within a cluster are divided into three categories based on their branch attributes. The order of nodes with the same branch attribute within the cluster remains the same as the relative order of nodes within the previous algorithm layer, ensuring that the algorithm's optimized minimum crossover result is maintained as much as possible. Furthermore, within a single cluster, the three categories of pull-down, main path, and pull-up are arranged in the order of left, center, and right, or bottom, center, and top, to ensure consistency with circuit rules. To meet this special requirement while also preserving the minimum number of crossovers guaranteed by the previous algorithm, the node order within the layer needs to be adjusted again before the final coordinates are determined.

[0113] In some embodiments, determining the coordinates of all nodes in the directed acyclic graph by combining the node sorting method and the branch attributes further includes:

[0114] When the third node in a cluster of the third layer cannot be arranged symmetrically with the second node as the center, adjust the position of the second node so that the third node is arranged symmetrically with the second node as the center;

[0115] The position of the first node in the first layer is corrected by traversing backward so that the second nodes are arranged symmetrically with the first node as the center, all nodes in each cluster are arranged according to the same branch attribute rule, and all clusters maintain their order.

[0116] After adjusting the order of all nodes within a single cluster, perform specific coordinate calculations. Using the parent node's x-coordinate as the center, evenly and symmetrically arrange the three types of child nodes (left, center, and right branches). Calculate the estimated right edge (maximum x-coordinate) of the current cluster. Compare this estimated right edge with the x-coordinate of the leftmost node in the current layer (i.e., the right edge of the adjacent cluster to the left). If the estimated right edge is larger, shift the parent node's coordinates to the left to ensure separation between clusters (reduce crossover and clarify branch relationships).

[0117] Shifting a parent node to the left may cause it to conflict with the position of nodes in the upper layer, or even disrupt the order of nodes in the upper layer. The positions of the upper-layer parent node and the node to its left must be adjusted simultaneously. Shifting an upper-layer node can further affect the logical relationships of circuits in even higher layers. BFS (breadth-first search) is used to correct this problem, backtracking layer by layer from bottom to top until the order of all nodes in a given layer matches the initial order, and the circuit connections between the branches within that layer and the parent node in the upper layer are correctly established.

[0118] Now let’s take the adjustment of the three-layer node position as an example to illustrate. Figure 7As shown, when determining the coordinates of node R6 and node N14, child nodes R6 and child nodes N14 are symmetrically distributed with parent node N18 as the center. When determining the coordinates of node N15 and node R7, child nodes N15 and child nodes R7 are symmetrically distributed with parent node N14 as the center. When determining the coordinates of node N16 and node R8, when child nodes N16 and child nodes R8 are symmetrically distributed with parent node N15 as the center, insufficient space may occur below, and node N16 and node V5 may overlap. In this case, the position of parent node N15 needs to be adjusted downward, while maintaining the optimized order of node N16 and node R8, and making child nodes N16 and child nodes R8 symmetrically distributed with parent node N15 as the center. Adjusting the position of parent node N15 downward may cause changes in the positions of node N15 and node R7, placing node R7 above node N15. Therefore, it is necessary to traverse and reverse the position of node N14 and adjust the position of node R7. This ensures that nodes N15 and R7 within the cluster maintain their previously optimized order, with the power branch pulled up (above), the ground branch pulled down (below), and the IC branch placed in the middle. Child nodes N15 and R7 are arranged symmetrically around parent node N14. After the position of node N14 is corrected, child nodes R6 and N14 are no longer symmetrically arranged around parent node N18. Repeat this process for adjusting the positions of more than three layers of nodes. Ultimately, adjusting the root node (e.g., node N14) will result in a no longer symmetrical arrangement around the parent node. In this embodiment, the child nodes are symmetrically arranged with the parent node as the center, which is a preferred method; it can also be arranged with set intervals, for example, the child node N15 is located at a first set distance above the parent node N14, and the child node R7 is located at a second set distance below the parent node N14, and the first set distance and the second set distance are different.

[0119] After the order adjustment is complete, the coordinates of all nodes within the cluster must be calculated based on the final position of the cluster's parent node. After all clusters at the current level are processed in order, the coordinates of the nodes at that level are determined. Once the coordinates of all nodes at all levels are determined, a global mirror flip is performed, aligning the driver end to the left and the receiver end to the right.

[0120] In some embodiments, an electronic device further includes: a memory, a processor, and a computer program stored in the memory, and the processor executes the computer program to implement the steps of a circuit diagram automatic layout method.

[0121] The division of the above units is merely a division of logical functions. In actual implementation, they may be fully or partially integrated into a single physical entity, or physically separated. Furthermore, the above units may be implemented in the form of a processor invoking software. For example, an electronic device may include a processor connected to a memory storing instructions, and the processor invoking the instructions stored in the memory to implement any of the above methods or the functions of each unit. The processor may be a general-purpose processor, such as a central processing unit (CPU), and the memory may be internal or external to the device. Alternatively, the above units may be implemented in the form of hardware circuits, and the functions of some or all of the units may be implemented through the design of the hardware circuits. The hardware circuits may be understood as one or more processors. For example, in some embodiments, the hardware circuits may be application-specific integrated circuits (ASICs), and the functions of some or all of the above units may be implemented through the design of the logical relationships between the components within the circuits. In another embodiment, the hardware circuits may be implemented using programmable logic devices (PLDs), which may include a large number of logic gates. The logical relationships between the logic gates are configured using a configuration file to implement the functions of some or all of the above units. All units of the above apparatus may be implemented entirely in the form of a processor calling a program, or entirely in the form of a hardware circuit, or partially in the form of a processor calling a program and the rest in the form of a hardware circuit.

[0122] In addition, an embodiment of the present application further provides a storage medium, including instructions stored thereon, and when the instructions are called by a processor, any one of the circuit diagram automatic layout methods in the above embodiments is executed.

[0123] The above-mentioned computer-readable storage medium may be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited to these.

[0124] It should be noted that the above embodiments can be freely combined as needed. The above are only some of the implementation methods of this application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of this application, and these improvements and modifications should also be considered as the scope of protection of this application.

Claims

1. A method for automatic layout of a circuit diagram, characterized in that: include: A directed acyclic graph is formed based on the components extracted from the PCB file and their connection relationships; the directed acyclic graph includes a plurality of nodes and graph edges for connecting two nodes, the nodes are used to represent the components, and the graph edges are used to represent the connection relationships between the components; Assigning nodes of different levels in the directed acyclic graph to different layers, where all nodes of the same level are located in the same layer; the different layers include a first layer, a second layer, and a third layer, the first layer includes at least one first node, the second layer includes at least one second node, and the third layer includes at least one third node; Adjust the order of all nodes in the same level and record the node ordering method with the least number of crosses when connecting nodes between two adjacent levels; Traversing all nodes in the directed acyclic graph, setting branch attributes of each node, wherein the branch attributes include main path, pull-up, and pull-down; Determine the coordinates of all nodes in the directed acyclic graph by combining the node sorting method and the branch attributes; The traversing of all nodes arranged in the node sorting manner and setting the branch attributes of each node include: Find all third nodes with zero out-degree in the directed acyclic graph, traverse the directed acyclic graph in reverse with the third node as the starting node, and determine the branch attribute of each node; when the branch attribute is set to the main path, the node is a receiving end; when the branch attribute is set to pull-up, the node is a power supply; when the branch attribute is set to pull-down, the node is other cases; When the branch attributes determined by different branches of the same node in the directed acyclic graph are different, the branch attributes are determined according to priority; the priority of the main road is higher than the priority of the power supply, and the priority of the power supply is higher than other priorities.

2. The circuit diagram automatic layout method according to claim 1, characterized in that: Before adjusting the order of all nodes in the same level and recording the node connections between two adjacent levels, the node sorting method with the least number of crosses also includes: The fourth node of the cross-level connection is found through traversal, and a virtual node for direct connection is added according to the number of levels crossed.

3. The circuit diagram automatic layout method according to claim 1, characterized in that: The directed acyclic graph is formed based on the components extracted from the PCB file and their connection relationships, including: Based on the components extracted from the PCB file and their connection relationships, an undirected overall graph is formed; After traversing and determining the directions of the edges in the undirected general graph and eliminating the loops in the undirected general graph, the directed acyclic graph is formed; eliminating the loops in the undirected general graph includes adjusting two nodes of the first level to point to the same node of the second level; When the third node is connected to the first node through the second node, if it is analyzed that the control signal between the third node and the first node does not pass through the second node, the first node and the third node are adjusted to a direct connection relationship.

4. The circuit diagram automatic layout method according to claim 2, characterized in that: The step of forming an undirected general graph based on the components and their connection relationships extracted from the PCB file also includes: Forming a first undirected graph according to the components extracted from the PCB file and their connection relationships; When traversing the first undirected graph, analyzing missing components in the first undirected graph in combination with all extracted components; Any missing component is selected as the first node of the second undirected graph, and all missing components and their connection relationships are combined to form a second undirected graph; the undirected overall graph includes the first undirected graph and the second undirected graph.

5. The circuit diagram automatic layout method according to claim 1, characterized in that: The allocating nodes at different levels in the directed acyclic graph to different layers includes: Searching for the first node with zero in-degree in the directed acyclic graph, and using all the first nodes with zero in-degree to construct a first layer; After the first layer is constructed, all first nodes corresponding to the first layer are deleted, and the second nodes with zero in-degree in the directed acyclic graph are queried again to construct a second layer stacked in the direction of extension of the first layer; the above steps are repeated until all nodes in the directed acyclic graph are deleted.

6. The circuit diagram automatic layout method according to claim 1, characterized in that: The aforementioned method of adjusting the order of all nodes in the same level and recording the node ordering method with the least number of crosses when connecting nodes between two adjacent levels also includes: According to the first direction, two adjacent layers are divided into a unit group. The node order of one layer remains unchanged. After adjusting the node order of the other layer, the node ordering method with the least number of crossovers when connecting the nodes between the two adjacent layers is recorded. The total number of crossovers in the even-numbered rounds of order optimization is accumulated for all unit groups. According to the second direction, two adjacent layers are divided into a unit group, the node order of one layer remains unchanged, and after adjusting the node order of the other layer, the node ordering method with the least number of crossovers when connecting the nodes between the two adjacent layers is recorded. The total number of crossovers in the odd-numbered rounds of order optimization is accumulated for all unit groups; the second direction is opposite to the first direction; Select the node ordering method that minimizes the total number of crossovers in multiple rounds of optimization.

7. The circuit diagram automatic layout method according to claim 1, characterized in that: The determining of the coordinates of all nodes in the directed acyclic graph by combining the node sorting method and the branch attributes includes: Aggregate a first node and a second node connected to the first node in two adjacent layers into a cluster, arrange the clusters in the order of the first nodes, arrange the branches formed by the nodes in each cluster according to the branch attribute rule, and arrange the nodes in each branch according to the node sorting method; When the third nodes in a cluster of the third layer cannot be arranged symmetrically with the second node as the center, adjusting the positions of the second nodes so that the third nodes are arranged symmetrically with the second node as the center; The position of the first node of the first layer is corrected by traversing and back-calculating, so that the second nodes are arranged symmetrically with the first node as the center, and all clusters and nodes within the clusters maintain their order.

8. A storage medium having a computer program or instruction stored thereon, characterized in that: When the computer program or instruction is executed by a processor, the steps of the circuit diagram automatic layout method according to any one of claims 1 to 7 are implemented.

9. An electronic device, further comprising: A memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the circuit diagram automatic layout method according to any one of claims 1 to 7.

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