Channel data dynamic cutting device and method, equipment and storage medium

Abstract

The invention provides a channel data dynamic cutting device and method, equipment and a storage medium. The device comprises an interleaving module, a first comparator and a second comparator, the first comparator is electrically connected with the second comparator; the interleaving module is electrically connected with the first comparator and the second comparator respectively; in the simultaneous clipping mode, the interleaving module is used for transmitting the clipping upper bound to the first comparator in the (2t + 1) th clock period; the first comparator is used for acquiring to-be-processed channel data, taking the clipping upper bound and data with smaller numerical values in the channel data as an intermediate result, and transmitting the intermediate result to the second comparator; the interleaving module is also used for transmitting the cut lower bound to the second comparator in the (2t + 2) th clock period; and the second comparator is used for taking the intermediate result and data with relatively large numerical values in the cut lower bound as a target result. According to the technical scheme, simultaneous cutting can be achieved by running hardware at a time, and the cutting efficiency of the channel data is improved.

Description

Technical Field

[0001] The present application relates to the field of image processing technology, and in particular to a device, method, equipment and storage medium for dynamic clipping of channel data. Background Art

[0002] During image processing, it is necessary to optimize brightness and contrast while retaining the overall dynamic range of the image to reduce detail loss.

[0003] In related technologies, dynamic clipping is used to process image channel data to achieve the above objectives. Dynamic clipping is a technique that adjusts the brightness and contrast range of an image or video signal. It is primarily used to optimize image quality, highlight key information, and adapt to specific display devices or scenarios. Dynamic clipping includes high clipping, low clipping, and dynamic clipping.

[0004] However, in the related art, high-cropping hardware can only execute high-cropping mode, while low-cropping hardware can only execute low-cropping mode. Therefore, when performing simultaneous cropping, the high-cropping hardware must first be run to obtain the high-cropping result, which is then transferred to the low-cropping hardware and then run. In other words, in the related art, simultaneous cropping requires running two hardware components, which not only wastes hardware resources but also requires running the hardware twice, increasing hardware runtime and requiring a cache to store intermediate data, thereby reducing channel data processing efficiency. Summary of the Invention

[0005] The embodiments of the present application provide a device, method, apparatus, and storage medium for dynamic channel data clipping, which can achieve simultaneous clipping by running the hardware once, without the need to cache and store intermediate data, thereby saving hardware running time and improving the efficiency of channel data clipping. The technical solution is as follows:

[0006] According to a first aspect of an embodiment of the present application, a device for dynamically clipping channel data is provided, the device comprising:

[0007] An interleaving module, a first comparator, and a second comparator; the first comparator is electrically connected to the second comparator; the interleaving module is electrically connected to the first comparator and the second comparator respectively;

[0008] In the simultaneous clipping mode, the interleaving module is configured to transmit the clipping upper bound to the first comparator in the (2t+1)th clock cycle; t is an integer greater than or equal to 0;

[0009] The first comparator is configured to obtain channel data to be processed, use the clipping upper bound and the smaller data in the channel data as an intermediate result, and transmit the intermediate result to the second comparator;

[0010] The interleaving module is further configured to transmit the clipping lower bound to the second comparator in the (2t+2)th clock cycle;

[0011] The second comparator is configured to use the data with the larger value between the intermediate result and the clipping lower bound as the target result.

[0012] In a possible implementation, in the low clipping mode, the second comparator is further used to obtain the channel data to be processed and the clipping lower bound, and use the larger numerical data between the channel data to be processed and the clipping lower bound as the target result.

[0013] In a possible implementation, in the high clipping mode, the first comparator is further used to obtain the channel data to be processed and the clipping upper bound, and use the smaller numerical data between the channel data to be processed and the clipping upper bound as the target result.

[0014] In a possible implementation, the apparatus further includes a first selector, a second selector, and a third selector;

[0015] The first selector is electrically connected to the interleaving module and the first comparator respectively;

[0016] The second selector is electrically connected to the first comparator and the second comparator respectively;

[0017] The third selector is electrically connected to the interleaving module and the second comparator respectively;

[0018] In the simultaneous clipping mode, the first selector is configured to transmit the clipping upper bound to the first comparator in the (2t+1)th clock cycle;

[0019] The second selector is configured to transmit the intermediate result to the second comparator in the (2t+2)th clock cycle;

[0020] The third selector is configured to transmit the clipping lower bound to the second comparator in the (2t+2)th clock cycle.

[0021] In a possible implementation, in the low clipping mode, the second selector is further configured to transmit the to-be-processed channel data to the second comparator;

[0022] The third selector is further configured to transmit the clipping lower bound to the second comparator.

[0023] In a possible implementation, in the high clipping mode, the first selector is further configured to transmit the clipping upper bound to the first comparator.

[0024] In a possible implementation, the device further includes a fourth selector and a fifth selector;

[0025] The fourth selector is electrically connected to the fifth selector, the first comparator and the second comparator respectively;

[0026] The fifth selector is electrically connected to the first comparator.

[0027] In the simultaneous cropping mode, the fourth selector is used to transmit the target result to the fifth selector;

[0028] The fifth selector is used to output the target result.

[0029] In a possible implementation, in the low clipping mode, the fourth selector is further configured to transmit the target result to the fifth selector;

[0030] The fifth selector is further configured to output the target result.

[0031] In a possible implementation, in the high cropping mode, the fifth selector is further configured to output the target result.

[0032] In a possible implementation, in the simultaneous clipping mode, the first comparator is further configured to, in the (2t+1)th clock cycle, convert the type of the to-be-processed channel data and the type of the clipping upper bound to obtain intermediate channel data and the intermediate clipping upper bound; and use the smaller value of the intermediate channel data and the intermediate clipping upper bound as the intermediate result;

[0033] The second comparator is also used to convert the type of the clipping lower bound in the (2t+2)th clock cycle to obtain an intermediate clipping lower bound, and use the larger numerical data in the intermediate clipping lower bound and the intermediate result as the target result.

[0034] In one possible implementation, in the low clipping mode, the second comparator is further used to convert the type of the channel data to be processed and the type of the clipping lower bound to obtain the intermediate channel data and the intermediate clipping lower bound; and the data with the larger numerical value between the intermediate channel data and the intermediate clipping lower bound is used as the target result.

[0035] In one possible implementation, in the high clipping mode, the first comparator is further used to convert the type of the channel data to be processed and the type of the clipping upper bound to obtain the intermediate channel data and the intermediate clipping upper bound; and use the smaller numerical data among the intermediate channel data and the intermediate clipping upper bound as the target result.

[0036] In a possible implementation, the channel data to be processed includes first sub-channel data to be processed and second sub-channel data to be processed;

[0037] In the simultaneous clipping mode, the first comparator is further configured to, in the (2t+1)th clock cycle, convert the type of the first sub-channel data to be processed, the type of the second sub-channel data to be processed, and the clipping upper bound to obtain first sub-intermediate channel data, second sub-intermediate channel data, and the intermediate clipping upper bound; use the smaller of the first sub-intermediate channel data and the intermediate clipping upper bound as a first sub-intermediate result; and use the smaller of the second sub-intermediate channel data and the intermediate clipping upper bound as a second sub-intermediate result.

[0038] The second comparator is also used to convert the type of the clipping lower bound in the (2t+2)th clock cycle to obtain an intermediate clipping lower bound, and use the larger numerical data of the intermediate clipping lower bound and the first sub-intermediate result as the first sub-target result; and use the larger numerical data of the intermediate clipping lower bound and the second sub-intermediate result as the second sub-target result.

[0039] In one possible implementation, in the low clipping mode, the second comparator is further used to convert the type of the first sub-channel data to be processed, the type of the second sub-channel data to be processed, and the type of the clipping lower bound to obtain the first sub-intermediate channel data, the second sub-intermediate channel data, and the intermediate clipping lower bound; the larger numerical data among the first sub-intermediate channel data and the intermediate clipping lower bound is used as the first sub-target result; and the larger numerical data among the second sub-intermediate channel data and the intermediate clipping lower bound is used as the second sub-target result.

[0040] In one possible implementation, in the high clipping mode, the first comparator is further used to convert the type of the first sub-channel data to be processed, the type of the second sub-channel data to be processed, and the type of the clipping upper bound to obtain the first sub-intermediate channel data, the second sub-intermediate channel data, and the intermediate clipping upper bound; the smaller numerical data among the first sub-intermediate channel data and the intermediate clipping upper bound is used as the first sub-target result; and the smaller numerical data among the second sub-intermediate channel data and the intermediate clipping upper bound is used as the second sub-target result.

[0041] According to a second aspect of an embodiment of the present application, a method for dynamic clipping of channel data is provided, the method comprising:

[0042] In the simultaneous clipping mode, the clipping upper bound is transmitted to the first comparator at the (2t+1)th clock cycle; t is an integer greater than or equal to 0;

[0043] Acquire channel data to be processed, use the clipping upper bound and the smaller data in the channel data as an intermediate result, and transmit the intermediate result to a second comparator;

[0044] transmitting the clipping lower bound to the second comparator at the (2t+2)th clock cycle;

[0045] The intermediate result and the data with larger values in the clipping lower bound are taken as the target result.

[0046] According to a third aspect of an embodiment of the present application, a computer device is provided, comprising a processor and a memory, wherein the memory is used to store at least one program, and the at least one program is loaded by the processor and executes the method for dynamic clipping of channel data.

[0047] According to a fourth aspect of an embodiment of the present application, a computer-readable storage medium is provided, in which at least one program is stored. The at least one program is loaded and executed by a processor to implement the method for dynamic clipping of channel data.

[0048] In an embodiment of the present application, a device for dynamic clipping of channel data is provided. In a simultaneous clipping mode, an interleaving module transmits the clipping upper bound to a first comparator in the (2t+1)th clock cycle; the first comparator obtains the channel data to be processed, takes the clipping upper bound and the smaller numerical data in the channel data as an intermediate result, and transmits the intermediate result to a second comparator; the interleaving module transmits the clipping lower bound to a second comparator in the (2t+2)th clock cycle; the second comparator takes the intermediate result and the larger numerical data in the clipping lower bound as the target result. The technical solution of the present application only requires the hardware to run once to achieve simultaneous clipping, and during the hardware operation, there is no need to cache and store data, thereby improving the efficiency of channel data clipping. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0050] Figure 1 is a schematic diagram of an implementation environment provided according to an embodiment of the present application;

[0051] Figure 2 1 is a schematic structural diagram of a channel data dynamic clipping device provided according to an embodiment of the present application;

[0052] Figure 3 This is a first exemplary diagram of the structure of a channel data dynamic clipping device provided according to an embodiment of the present application;

[0053] Figure 4 This is a schematic diagram of a structure working in a simultaneous cutting mode according to an embodiment of the present application;

[0054] Figure 5 This is a schematic diagram of a structure working in a low-crop mode according to an embodiment of the present application;

[0055] Figure 6 This is a schematic diagram of a structure working in a high-cut mode according to an embodiment of the present application;

[0056] Figure 7 This is a second exemplary diagram of the structure of a channel data dynamic clipping device provided according to an embodiment of the present application;

[0057] Figure 8 1 is a flow chart of a method for dynamically clipping channel data according to an embodiment of the present application;

[0058] Figure 9 is a schematic structural diagram of a terminal provided according to an embodiment of the present application;

[0059] Figure 10 It is a structural diagram of a server provided according to an embodiment of the present application. DETAILED DESCRIPTION

[0060] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0061] Exemplary embodiments are described in detail herein, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different drawings represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with this application.

[0062] In this application, the terms "first," "second," and the like are used to distinguish identical or similar items having substantially the same role and function. It should be understood that "first," "second," and "nth" do not have a logical or temporal dependency, nor do they limit the quantity or execution order. It should also be understood that although the following description uses the terms "first," "second," and the like to describe various elements, these elements should not be limited by these terms.

[0063] These terms are simply used to distinguish one element from another. For example, without departing from the scope of various examples, a first action can be referred to as a second action, and similarly, a second action can also be referred to as a first action. Both the first action and the second action can be actions, and in some cases, can be separate and different actions.

[0064] Here, at least one refers to one or more than one. For example, at least one action can be one action, two actions, three actions, or any other action that is an integer greater than or equal to one. And multiple refers to two or more than two. For example, multiple actions can be two actions, three actions, or any other action that is an integer greater than or equal to two.

[0065] Figure 1 10 is a schematic diagram of an implementation environment provided according to an embodiment of the present application, which may include a terminal 101 and a server 102.

[0066] In each terminal 101, a channel data dynamic clipping device is provided, wherein the channel data dynamic clipping device can be integrated into a neural network processor (NPU), and the NPU is electrically connected to the ISP so that the NPU can obtain the channel data to be processed, the clipping upper bound, and the clipping lower bound from the ISP; after completing the clipping of the channel data to be processed, the NPU obtains the target result and transmits the target result to the ISP. Optionally, the terminal has multiple implementation forms. For example, a smartphone, wearable device, personal computer, laptop, tablet computer, smart TV, and vehicle-mounted terminal with a channel data dynamic clipping device.

[0067] The server 102 may be a single server, a server cluster consisting of multiple servers, or a cloud processing center.

[0068] The terminal 101 is connected to the server 102 via a wired or wireless network.

[0069] In some embodiments, the wireless network or wired network uses standard communication technologies and / or protocols. The network is typically the Internet, but can also be any network, including but not limited to a local area network (LAN), a metropolitan area network (MAN), a wide area network (WAN), a mobile, wired or wireless network, a private network or any combination of a virtual private network. In some embodiments, technologies and / or formats including Hypertext Markup Language (HTML), Extensible Markup Language (XML), etc. are used to represent data exchanged over the network. In addition, conventional encryption technologies such as Secure Socket Layer (SSL), Transport Layer Security (TLS), Virtual Private Network (VPN), Internet Protocol Security (IPsec) can also be used to encrypt all or some links. In other embodiments, customized and / or dedicated data communication technologies can also be used to replace or supplement the above-mentioned data communication technologies.

[0070] In the related art, the channel data of the image is processed by dynamic cropping. Dynamic cropping includes high cropping, low cropping, and simultaneous cropping. Among them, high cropping processes the highlight part of the image, that is, the overexposed area, and limits the channel data whose brightness exceeds the target dynamic range to the maximum allowable value range, so as to avoid loss of details due to overexposure and optimize the visual experience. Low cropping processes the low-brightness area of the image, that is, the dark or underexposed part, and limits the channel data below the target dynamic range to the minimum allowable value range to enhance the visibility of dark details and avoid information loss in completely blackened areas. Simultaneous cropping is to crop both the highlight and low-brightness parts of the image to the target dynamic range at the same time. This method optimizes the full dynamic range of the image, ensuring that both dark details and highlight details can be retained, and is usually suitable for high-contrast scenes.

[0071] However, in the related art, high-cropping hardware can only execute high-cropping mode, while low-cropping hardware can only execute low-cropping mode. Therefore, when performing simultaneous cropping, the high-cropping hardware must first be run to obtain the high-cropping result, which is then transferred to the low-cropping hardware and then run. In other words, in the related art, achieving simultaneous cropping requires running two hardware components, which not only wastes hardware resources but also requires running the hardware twice, increasing hardware runtime and requiring a cache to store intermediate data. This reduces channel data processing efficiency and fails to meet the real-time requirements of the ISP. Furthermore, in the related art, the upper and lower cropping bounds must be configured offline. That is, after obtaining the upper and lower cropping bounds, subsequent processing is stopped. Offline, the upper and lower cropping bounds are configured in registers for subsequent processing to call the upper and lower cropping bounds. This processing of the upper and lower cropping bounds significantly increases channel data processing time, thereby reducing channel data processing efficiency and, in turn, image processing efficiency.

[0072] In addition, the related technology only involves single-channel data, which greatly reduces the output efficiency.

[0073] In order to solve the above technical problems, an embodiment of the present application provides a channel data dynamic clipping device, including an interleaving module, a first comparator and a second comparator. The device can respectively execute any one of the simultaneous clipping mode, the low clipping mode and the high clipping mode. Specifically, in the simultaneous clipping mode, the high clipping and low clipping of the channel data to be processed are implemented by the interleaving module, the first comparator and the second comparator. In the low clipping mode, the low clipping of the channel data to be processed is implemented by the second comparator. In the high clipping mode, the high clipping of the channel data to be processed is implemented by the first comparator. The technical solution of the present application, through hardware multiplexing, can perform simultaneous clipping, low clipping and high clipping on the same channel data to be processed respectively, without the need to involve corresponding hardware separately for each clipping mode, thereby greatly saving hardware resources.

[0074] Figure 2 : is a structural diagram of a channel data dynamic clipping device provided according to an embodiment of the present application, the device comprising:

[0075] Interleaving module 201, first comparator 202 and second comparator 203; the first comparator 202 is electrically connected to the second comparator 203; the interleaving module 201 is electrically connected to the first comparator 202 and the second comparator 203 respectively;

[0076] In the simultaneous clipping mode, the interleaving module 201 is configured to transmit the clipping upper bound to the first comparator 202 in the (2t+1)th clock cycle; t is an integer greater than or equal to 0;

[0077] The first comparator 202 is used to obtain the channel data to be processed, clip the upper bound and the smaller data in the channel data as an intermediate result, and transmit the intermediate result to the second comparator 203;

[0078] The interleaving module 201 is further configured to transmit the clipping lower bound to the second comparator 203 in the (2t+2)th clock cycle;

[0079] The second comparator 203 is configured to use the intermediate result and the data with larger values in the clipped lower bound as the target result.

[0080] The interleaving module 201 , the first comparator 202 and the second comparator 203 are all implemented based on hardware.

[0081] It can be understood that in the simultaneous clipping mode, the interleaving module 201 transmits the upper clipping bound to the first comparator 202 in odd-numbered clock cycles and transmits the lower clipping bound to the second comparator 203 in even-numbered clock cycles. That is, the interleaving module 201 alternately transmits the upper clipping bound and the lower clipping bound, thereby implementing the high clipping mode and then the low clipping mode in two adjacent clock cycles, thereby achieving simultaneous clipping and controlling the target result between the upper clipping bound and the lower clipping bound.

[0082] In some embodiments, since the cropping upper bound and the cropping lower bound in the related art need to be configured offline, the efficiency of processing channel data is reduced. In order to solve the above technical problems, the cropping upper bound, the cropping lower bound and the channel data to be processed are obtained from the ISP. Optionally, when the ISP and the NPU directly interact with each other for data, the cropping upper bound, the cropping lower bound and the channel data to be processed are directly obtained from the ISP. Optionally, when the ISP and the NPU interact with each other for data through the memory, the NPU obtains the cropping upper bound, the cropping lower bound and the channel data to be processed from the memory. Compared with the related art, the technical solution of the present application does not need to wait for the offline writing time of the cropping upper bound and the cropping lower bound, thereby improving the efficiency of processing channel data, and further improving the efficiency of processing images.

[0083] In some embodiments, to uniformly configure and control the clipping modes of the interleaving module 201, the first comparator 202, and the second comparator 203, in embodiments of the present application, each of the interleaving module 201, the first comparator 202, and the second comparator 203 is provided with a register. Optionally, when the value in the register is configured as a first preset threshold, the interleaving module 201, the first comparator 202, and the second comparator 203 implement a low clipping mode. Optionally, when the value in the register is configured as a second preset threshold, the interleaving module 201, the first comparator 202, and the second comparator 203 implement a high clipping mode. Optionally, when the data in the register is configured as a third preset threshold, the interleaving module 201, the first comparator 202, and the second comparator 203 implement a simultaneous clipping mode. The first, second, and third preset thresholds can be implemented in various forms. For example, the first preset threshold is 0, the second preset threshold is 1, and the third preset threshold is 2.

[0084] In one example, in the simultaneous cropping mode, in response to a third configuration signal, the interleaving module 201, the first comparator 202, and the second comparator 203 are all in an operating state. The third configuration signal indicates that the values in the registers of the interleaving module 201, the first comparator 202, and the second comparator 203 are a third preset threshold.

[0085] In some embodiments, in the low clipping mode, the second comparator 203 is further configured to obtain the channel data to be processed and the clipping lower bound, and use the data with the larger value between the channel data to be processed and the clipping lower bound as the target result.

[0086] In one example, in the low clipping mode, in response to a first configuration signal, the interleaving module 201 and the first comparator 202 are in a disabled state, and the second comparator 203 is in an enabled state. The first configuration signal indicates that the values in the registers of the interleaving module 201, the first comparator 202, and the second comparator 203 are a first preset threshold.

[0087] In some embodiments, in the high clipping mode, the first comparator 202 is further configured to obtain the channel data to be processed and the clipping upper bound, and use the smaller value of the channel data to be processed and the clipping upper bound as the target result.

[0088] In one example, in high clipping mode, in response to a second configuration signal, the interleaving module 201 and the second comparator 203 are in a disabled state, and the first comparator 202 is in an enabled state. The second configuration signal indicates that the values in the registers of the interleaving module 201, the first comparator 202, and the second comparator 203 are the second preset thresholds.

[0089] Combined with the above analysis, it can be seen that the embodiments of the present application control the operating states of the interleaving module 201, the first comparator 202, and the second comparator 203 by configuring the values of the registers to execute any one of the cropping modes: simultaneous cropping mode, low cropping mode, and high cropping mode. This method of controlling the cropping mode is simple to operate and facilitates hardware implementation. In addition, compared to the related art, the embodiments of the present application do not require running the hardware to execute the high cropping mode a first time and the low cropping mode a second time, combining the two hardware runs to achieve simultaneous cropping. Instead, only one hardware run is required once to perform simultaneous cropping. In other words, the embodiments of the present application reduce the number and time of hardware runs through hardware reuse, thereby improving the processing efficiency of channel data. In addition, the embodiments of the present application share the same hardware for the simultaneous cropping mode, the low cropping mode, and the high cropping mode, significantly saving hardware resources compared to providing a hardware structure for each cropping mode.

[0090] Figure 3 This is the first example diagram of the structure of a channel data dynamic clipping device provided according to an embodiment of the present application.

[0091] The following combination Figure 3 An exemplary description is given of a device for dynamically clipping channel data.

[0092] In some embodiments, since the embodiments of the present application involve multiple cropping modes, multiple selectors are provided to ensure that each cropping mode transmits data through a different data transmission channel. Through the multiple selectors, different data transmission channels are connected in different cropping modes, thereby executing different cropping modes, thereby achieving hardware multiplexing and saving hardware resources.

[0093] In one example, the apparatus further includes a first selector 204, a second selector 205, and a third selector 206. The first selector 204 is electrically connected to the interleaving module 201 and the first comparator 202, respectively; the second selector 205 is electrically connected to the first comparator 202 and the second comparator 203, respectively; and the third selector 206 is electrically connected to the interleaving module 201 and the second comparator 203, respectively. Optionally, registers are provided in the first selector 204, the second selector 205, and the third selector 206. The first input terminal and the second input terminal are two input terminals of the first selector 204; the third input terminal and the fourth input terminal are two input terminals of the second selector 205; and the fifth input terminal and the sixth input terminal are two input terminals of the third selector 206. Optionally, the first input terminal is electrically connected to the ISP, and the second input terminal is electrically connected to the interleaving module 201. The third input terminal is electrically connected to the ISP; the fourth input terminal is electrically connected to the first comparator 202; the fifth input terminal is electrically connected to the ISP; and the sixth input terminal is electrically connected to the interleaving module 201.

[0094] Figure 4 It is a structural diagram of a device operating in a simultaneous cropping mode according to an embodiment of the present application.

[0095] The following combination Figure 4 The simultaneous cropping mode is exemplified.

[0096] In one example, in the simultaneous clipping mode, the first selector 204 transmits the clipping upper bound to the first comparator 202 in the (2t+1)th clock cycle; the second selector 205 transmits the intermediate result to the second comparator 203 in the (2t+2)th clock cycle; and the third selector 206 transmits the clipping lower bound to the second comparator 203 in the (2t+2)th clock cycle. Optionally, in the simultaneous clipping mode, in response to a third configuration signal, in the first clock cycle, the first selector 204 enables the data transmission channel between the second input terminal and the interleaving module 201, and the second selector 205 enables the data transmission channel between the fourth input terminal and the first comparator 202; in the second clock cycle, the first selector 204 closes the data transmission channel between the second output terminal and the interleaving module 201, and the third selector 206 enables the data transmission channel between the sixth input terminal and the interleaving module 201. Specifically, in the simultaneous clipping mode, in response to the third configuration signal, in the first clock cycle, the first comparator 202 obtains the channel data to be processed, the interleaving module 201 obtains the clipping upper bound, and transmits the clipping upper bound to the first selector 204 through the second input terminal; the first selector 204 transmits the clipping upper bound to the first comparator 202; the first comparator 202 compares the clipping upper bound with the channel data to be processed, and takes the smaller value of the clipping upper bound and the channel data to be processed as the intermediate result; the first comparator 202 takes the intermediate result. The intermediate result is transmitted to the second selector 205; in the second clock cycle, the interleaving module 201 obtains the clipping lower bound and transmits the clipping lower bound to the third selector 206 through the sixth input terminal; the third selector 206 transmits the clipping lower bound to the second comparator 203; the second selector 205 transmits the intermediate result to the second comparator 203; the second comparator 203 compares the clipping lower bound and the intermediate result, and takes the larger numerical data between the intermediate result and the clipping lower bound as the target result; the second comparator 203 transmits the target result to the ISP.

[0097] Figure 5 This is a structural diagram of a device operating in a low-crop mode according to an embodiment of the present application.

[0098] The following combination Figure 5 The low crop mode is exemplified.

[0099] In one example, in the low clipping mode, the second selector 205 transmits the channel data to be processed to the second comparator 203; the third selector 206 transmits the clipping lower bound to the second comparator 203. Alternatively, the second selector 205 obtains the channel data to be processed based on the third input terminal and transmits the channel data to be processed to the second comparator 203; the fifth input terminal obtains the clipping lower bound, and the third selector 206 transmits the clipping lower bound to the second comparator 203; the second comparator 203 compares the clipping lower bound with the channel data to be processed, selects the larger of the two as the target result, and transmits the target result to the ISP.

[0100] Figure 6 This is a structural diagram of a device operating in a high-cut mode according to an embodiment of the present application.

[0101] The following combination Figure 6 The high crop mode is exemplified.

[0102] In one example, in high clipping mode, first selector 204 is further configured to transmit the clipping upper bound to first comparator 202. Alternatively, first selector 204 obtains the clipping upper bound based on the first input terminal and transmits the clipping upper bound to first comparator 202. First comparator 202 obtains the channel data to be processed. First comparator 202 compares the clipping upper bound with the channel data to be processed, selects the smaller of the two as the target result, and transmits the target result to the ISP.

[0103] Figure 7 This is a second example diagram of the structure of a channel data dynamic clipping device provided according to an embodiment of the present application.

[0104] The following combination Figure 7 An exemplary description is given of a device for dynamically clipping channel data.

[0105] In some embodiments, the device further includes a fourth selector 207 and a fifth selector 208; the fourth selector 207 is electrically connected to the fifth selector 208, the first comparator 202, and the second comparator 203, respectively; and the fifth selector 208 is electrically connected to the first comparator 202. The seventh and eighth input terminals are two input terminals of the fourth selector 207. The ninth and tenth input terminals are two input terminals of the fifth selector 208. Optionally, the seventh input terminal is electrically connected to the first comparator 202; the eighth input terminal is electrically connected to the second selector 205; the ninth input terminal is electrically connected to the first comparator 202; and the tenth input terminal is electrically connected to the fourth selector 207.

[0106] In one example, in simultaneous cropping mode, the fourth selector 207 transmits the target result to the fifth selector 208; the fifth selector 208 outputs the target result. Alternatively, the fourth selector 207 obtains the target result based on the eighth input terminal and transmits the target result to the fifth selector 208 via the tenth input terminal; the fifth selector 208 transmits the target result to the ISP.

[0107] In one example, in low-clip mode, the fourth selector 207 transmits the target result to the fifth selector 208; the fifth selector 208 outputs the target result. Alternatively, the eighth input terminal obtains the target result, and the fourth selector 207 obtains the target result based on the eighth input terminal and transmits the target result to the fifth selector 208 via the tenth input terminal; the fifth selector 208 transmits the target result to the ISP.

[0108] In one example, in the high clipping mode, the fifth selector 208 outputs the target result. Optionally, the fifth selector 208 obtains the target result based on the ninth input terminal and transmits the target result to the ISP.

[0109] In some embodiments, in order to facilitate data comparison and improve the efficiency of data comparison, an embodiment of the present application, before comparing the upper limit of the clipping and the channel data to be processed, converts the type of the upper limit of the clipping and the type of the channel data to be processed; before comparing the lower limit of the clipping and the channel data to be processed, converts the type of the lower limit of the clipping and the type of the channel data to be processed. For one clock cycle, data conversion and data comparison can be completed within the clock cycle, without the need to increase the clock cycle. In addition, the process of data conversion only needs to fill in 0 or fill in the sign bit, without adding additional comparator resources, thereby ensuring the correctness and efficiency of the calculation.

[0110] In one example, in the simultaneous clipping mode, the first comparator 202 converts the type of the channel data to be processed and the type of the clipping upper bound in the (2t+1)th clock cycle to obtain the intermediate channel data and the intermediate clipping upper bound; the smaller numerical data in the intermediate channel data and the intermediate clipping upper bound is used as the intermediate result; the second comparator 203 converts the type of the clipping lower bound in the (2t+2)th clock cycle to obtain the intermediate clipping lower bound, and the larger numerical data in the intermediate clipping lower bound and the intermediate result is used as the target result. Optionally, the types of the channel data to be processed include multiple types. For example, int8, uint8, int16 and uint16. For int8, a 9-bit sign bit is added before int8. For uint8, a 9-bit 0 is added before uint8. For int16, a 1-bit sign bit is added before int16. For uint16, a 1-bit 0 is added before uint16. In this way, the various types of channel data to be processed are uniformly converted into 17-bit signed numbers, which facilitates data comparison and improves the efficiency of data comparison. Similarly, embodiments of the present application can also uniformly convert the channel data to be processed into 33 bits according to actual needs. In addition, combined with the above analysis, it can be seen that although the present application supports multi-channel data, the upper and lower bounds of the clipping are both single-channel data, thereby reducing the input bandwidth occupied by the upper and lower bounds of the clipping during the transmission process.

[0111] In one example, in low clipping mode, the second comparator 203 converts the type of channel data to be processed and the type of clipping lower bound to obtain intermediate channel data and intermediate clipping lower bound; the data with the larger numerical value between the intermediate channel data and the intermediate clipping lower bound is used as the target result.

[0112] In one example, in high clipping mode, the first comparator 202 converts the type of channel data to be processed and the type of clipping upper bound to obtain intermediate channel data and intermediate clipping upper bound; and takes the smaller numerical data in the intermediate channel data and the intermediate clipping upper bound as the target result.

[0113] In some embodiments, in order to improve the efficiency of processing the channel data to be processed, the channel data to be processed involved in the embodiments of the present application includes first sub-channel data to be processed and second sub-channel data to be processed, which greatly improves the efficiency of data output compared with the single-channel data in the related technology.

[0114] In one example, in the simultaneous clipping mode, the first comparator 202 converts the type of the first sub-channel data to be processed, the type of the second sub-channel data to be processed, and the clipping upper bound in the (2t+1)th clock cycle to obtain the first sub-intermediate channel data, the second sub-intermediate channel data, and the intermediate clipping upper bound; the smaller data in the first sub-intermediate channel data and the intermediate clipping upper bound is used as the first sub-intermediate result; the smaller data in the second sub-intermediate channel data and the intermediate clipping upper bound is used as the second sub-intermediate result; the second comparator 203 converts the type of the clipping lower bound in the (2t+2)th clock cycle to obtain the intermediate clipping lower bound, and the larger data in the intermediate clipping lower bound and the first sub-intermediate result is used as the first sub-target result; the larger data in the intermediate clipping lower bound and the second sub-intermediate result is used as the second sub-target result. Optionally, the values of the first sub-channel data to be processed and the values of the second sub-channel data to be processed include multiple cases. For example, if the clipping upper bound is 5, the clipping lower bound is 2, the first sub-channel data to be processed is 1, and the second sub-channel data to be processed is 6, then the first sub-intermediate result is 1, and the second sub-intermediate result is 5; the first sub-target result is 2, and the second sub-target result is 5.

[0115] In one example, in low clipping mode, the second comparator 203 is further used to convert the type of the first sub-channel data to be processed, the type of the second sub-channel data to be processed, and the type of the clipping lower bound to obtain the first sub-intermediate channel data, the second sub-intermediate channel data, and the intermediate clipping lower bound; the data with the larger numerical value among the first sub-intermediate channel data and the intermediate clipping lower bound is used as the first sub-target result; and the data with the larger numerical value among the second sub-intermediate channel data and the intermediate clipping lower bound is used as the second sub-target result. Optionally, the numerical value of the first sub-channel data to be processed and the numerical value of the second sub-channel data to be processed include multiple cases. For example, if the clipping lower bound is 2, the first sub-channel data to be processed is 1, and the second sub-channel data to be processed is 6, then the first sub-target result is 2 and the second sub-target result is 6.

[0116] In one example, in high clipping mode, the first comparator 202 is further used to convert the type of the first sub-channel data to be processed, the type of the second sub-channel data to be processed, and the type of the clipping upper bound to obtain the first sub-intermediate channel data, the second sub-intermediate channel data, and the intermediate clipping upper bound; the smaller numerical data among the first sub-intermediate channel data and the intermediate clipping upper bound is used as the first sub-target result; and the smaller numerical data among the second sub-intermediate channel data and the intermediate clipping upper bound is used as the second sub-target result. Optionally, the numerical values of the first sub-channel data to be processed and the numerical values of the second sub-channel data to be processed include multiple cases. For example, if the clipping upper bound is 5, the first sub-channel data to be processed is 1, and the second sub-channel data to be processed is 6, then the first sub-target result is 1 and the second sub-target result is 5.

[0117] It should be noted that: when the channel data dynamic clipping device provided in the above embodiment executes the corresponding steps, it only uses the division of the above functional modules as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0118] In an embodiment of the present application, in the simultaneous clipping mode, the interleaving module transmits the clipping upper bound to the first comparator in the (2t+1)th clock cycle; the first comparator obtains the channel data to be processed, takes the clipping upper bound and the smaller numerical data in the channel data as the intermediate result, and transmits the intermediate result to the second comparator; the interleaving module transmits the clipping lower bound to the second comparator in the (2t+2)th clock cycle; the second comparator takes the intermediate result and the larger numerical data in the clipping lower bound as the target result. The technical solution of the present application only needs to be run once to achieve simultaneous clipping, and during the hardware operation, there is no need to cache and store data, thereby improving the clipping efficiency of the channel data.

[0119] Figure 8 FIG. 1 is a flow chart of a method for dynamically clipping channel data according to an embodiment of the present application. Figure 8 As shown, in the embodiment of the present application, the application is described as an example of a terminal having an NPU and an ISP. The method includes the following steps:

[0120] In step 801, in the simultaneous clipping mode, the terminal transmits the clipping upper bound to the first comparator in the (2t+1)th clock cycle.

[0121] Here, t is an integer greater than or equal to 0.

[0122] In step 802, the terminal obtains the channel data to be processed, takes the clipped upper bound and the data with smaller values in the channel data as an intermediate result, and transmits the intermediate result to the second comparator.

[0123] In step 803 , the terminal transmits the clipping lower bound to the second comparator in the (2t+2)th clock cycle.

[0124] In step 804, the terminal uses the intermediate result and the data with larger values in the clipped lower bound as the target result.

[0125] In some embodiments, in the low clipping mode, the second comparator is further configured to obtain the channel data to be processed and the clipping lower bound, and use the larger value of the channel data to be processed and the clipping lower bound as the target result.

[0126] In some embodiments, in the high clipping mode, the first comparator is further configured to obtain the channel data to be processed and the clipping upper bound, and use the smaller value of the channel data to be processed and the clipping upper bound as the target result.

[0127] In some embodiments, the apparatus further comprises a first selector, a second selector, and a third selector;

[0128] The first selector is electrically connected to the interleaving module and the first comparator respectively;

[0129] The second selector is electrically connected to the first comparator and the second comparator respectively;

[0130] The third selector is electrically connected to the interleaving module and the second comparator respectively;

[0131] In the simultaneous clipping mode, the first selector is configured to transmit the clipping upper bound to the first comparator in the (2t+1)th clock cycle;

[0132] a second selector, configured to transmit the intermediate result to the second comparator in a (2t+2)th clock cycle;

[0133] The third selector is configured to transmit the clipping lower bound to the second comparator in a (2t+2)th clock cycle.

[0134] In some embodiments, in the low clipping mode, the second selector is further configured to transmit the channel data to be processed to the second comparator;

[0135] The third selector is further configured to transmit the clipping lower bound to the second comparator.

[0136] In some embodiments, in the high clipping mode, the first selector is further configured to transmit the clipping upper bound to the first comparator.

[0137] In some embodiments, the device further includes a fourth selector and a fifth selector;

[0138] The fourth selector is electrically connected to the fifth selector, the first comparator and the second comparator respectively;

[0139] The fifth selector is electrically connected to the first comparator.

[0140] In the simultaneous cropping mode, the fourth selector is used to transmit the target result to the fifth selector;

[0141] The fifth selector is used to output the target result.

[0142] In some embodiments, in the low clipping mode, the fourth selector is further configured to transmit the target result to the fifth selector;

[0143] The fifth selector is also used to output the target result.

[0144] In some embodiments, in the high cropping mode, the fifth selector is further configured to output a target result.

[0145] In some embodiments, in the simultaneous clipping mode, the first comparator is further configured to convert the type of the channel data to be processed and the type of the clipping upper bound in the (2t+1)th clock cycle to obtain intermediate channel data and an intermediate clipping upper bound; and use the smaller value of the intermediate channel data and the intermediate clipping upper bound as an intermediate result;

[0146] The second comparator is further used to convert the type of the clipping lower bound in the (2t+2)th clock cycle to obtain the intermediate clipping lower bound, and use the intermediate clipping lower bound and the larger numerical data in the intermediate result as the target result.

[0147] In some embodiments, in the low clipping mode, the second comparator is also used to convert the type of the channel data to be processed and the type of the clipping lower bound to obtain the intermediate channel data and the intermediate clipping lower bound; and the data with the larger numerical value between the intermediate channel data and the intermediate clipping lower bound is used as the target result.

[0148] In some embodiments, in the high clipping mode, the first comparator is also used to convert the type of the channel data to be processed and the type of the clipping upper bound to obtain the intermediate channel data and the intermediate clipping upper bound; and use the smaller numerical data in the intermediate channel data and the intermediate clipping upper bound as the target result.

[0149] In some embodiments, the channel data to be processed includes first sub-channel data to be processed and second sub-channel data to be processed; in the simultaneous clipping mode, the first comparator is further used to convert the type of the first sub-channel data to be processed, the type of the second sub-channel data to be processed, and the clipping upper bound in the (2t+1)th clock cycle to obtain first sub-intermediate channel data, second sub-intermediate channel data, and an intermediate clipping upper bound; use the smaller value of the first sub-intermediate channel data and the intermediate clipping upper bound as the first sub-intermediate result; and use the smaller value of the second sub-intermediate channel data and the intermediate clipping upper bound as the second sub-intermediate result;

[0150] The second comparator is also used to convert the type of the clipping lower bound in the (2t+2)th clock cycle to obtain the intermediate clipping lower bound, and use the larger numerical data in the intermediate clipping lower bound and the first sub-intermediate result as the first sub-target result; and use the larger numerical data in the intermediate clipping lower bound and the second sub-intermediate result as the second sub-target result.

[0151] In some embodiments, in the low cropping mode, the second comparator is also used to convert the type of the first sub-channel data to be processed, the type of the second sub-channel data to be processed, and the type of the cropping lower bound to obtain the first sub-intermediate channel data, the second sub-intermediate channel data, and the intermediate cropping lower bound; the larger numerical data among the first sub-intermediate channel data and the intermediate cropping lower bound is used as the first sub-target result; and the larger numerical data among the second sub-intermediate channel data and the intermediate cropping lower bound is used as the second sub-target result.

[0152] In some embodiments, in the high clipping mode, the first comparator is also used to convert the type of the first sub-channel data to be processed, the type of the second sub-channel data to be processed, and the type of the clipping upper bound to obtain the first sub-intermediate channel data, the second sub-intermediate channel data, and the intermediate clipping upper bound; the smaller numerical data in the first sub-intermediate channel data and the intermediate clipping upper bound is used as the first sub-target result; the smaller numerical data in the second sub-intermediate channel data and the intermediate clipping upper bound is used as the second sub-target result.

[0153] It should be noted that the channel data dynamic clipping device and channel data dynamic clipping method embodiments provided in the above embodiments belong to the same concept, and their specific implementation processes are detailed in the device embodiments and will not be repeated here.

[0154] In an embodiment of the present application, in the simultaneous clipping mode, the interleaving module transmits the clipping upper bound to the first comparator in the (2t+1)th clock cycle; the first comparator obtains the channel data to be processed, takes the clipping upper bound and the smaller numerical data in the channel data as the intermediate result, and transmits the intermediate result to the second comparator; the interleaving module transmits the clipping lower bound to the second comparator in the (2t+2)th clock cycle; the second comparator takes the intermediate result and the larger numerical data in the clipping lower bound as the target result. The technical solution of the present application only needs to be run once to achieve simultaneous clipping, and during the hardware operation, there is no need to cache and store data, thereby improving the clipping efficiency of the channel data.

[0155] An embodiment of the present application further provides a computer device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, and the processor implements the above method when executing the computer program.

[0156] Taking computer equipment as the terminal as an example, Figure 9 This is a schematic diagram of the structure of a terminal provided in an embodiment of the present application, see Figure 10Terminal 900 may be a smartphone, tablet computer, MP3 player (Moving Picture Experts Group Audio Layer III), MP4 player (Moving Picture Experts Group Audio Layer IV), laptop computer, or desktop computer. Terminal 900 may also be referred to as user equipment, portable terminal, laptop terminal, desktop terminal, or other similar names.

[0157] Typically, the terminal 900 includes a processor 901 and a memory 902 .

[0158] The processor 901 may include one or more processing cores, such as a quad-core processor, a penta-core processor, etc. The processor 901 may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), or PLA (Programmable Logic Array). The processor 901 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 901 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 901 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0159] The memory 902 may include one or more computer-readable storage media, which may be non-transitory. The memory 902 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 902 is used to store at least one program code, which is used to be executed by the processor 901 to implement the process provided in the method embodiment of the present application for the terminal execution in the above method.

[0160] In some embodiments, terminal 900 may optionally include a peripheral device interface 903 and at least one peripheral device. The processor 901, memory 902, and peripheral device interface 903 may be connected via a bus or signal lines. Each peripheral device may be connected to peripheral device interface 903 via a bus, signal lines, or circuit boards. Specifically, the peripheral device may include at least one of a display screen 904, a camera assembly 905, an audio circuit 906, and a power supply 907.

[0161] The peripheral device interface 903 can be used to connect at least one I / O (Input / Output)-related peripheral device to the processor 901 and the memory 902. In some embodiments, the processor 901, the memory 902, and the peripheral device interface 903 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 901, the memory 902, and the peripheral device interface 903 can be implemented on separate chips or circuit boards, which is not limited in this embodiment of the present application.

[0162] Display screen 904 is used to display a user interface (UI). This UI may include graphics, text, icons, videos, or any combination thereof. When display screen 904 is a touchscreen display, it is also capable of collecting touch signals on or above the surface of display screen 904. These touch signals can be input as control signals to processor 901 for processing. Display screen 904 can also be used to provide virtual buttons and / or a virtual keyboard, also known as soft buttons and / or a soft keyboard. In some embodiments, there can be a single display screen 904, located on the front panel of terminal 900. In other embodiments, there can be at least two display screens 904, located on different surfaces of terminal 900 or in a foldable design. In still other embodiments, display screen 904 can be a flexible display screen, located on a curved or foldable surface of terminal 900. Display screen 904 can also be configured as a non-rectangular, irregular shape, also known as a special-shaped screen. Display screen 904 can be made of materials such as LCD (Liquid Crystal Display) and OLED (Organic Light-Emitting Diode).

[0163] The camera assembly 905 is used to capture images or videos. In some embodiments, the camera assembly 905 includes a front camera and a rear camera. Typically, the front camera is arranged on the front panel of the terminal, and the rear camera is arranged on the back of the terminal. In some embodiments, there are at least two rear cameras, which are any one of a main camera, a depth of field camera, a wide-angle camera, and a telephoto camera, so as to realize the fusion of the main camera and the depth of field camera to realize the background blur function, the fusion of the main camera and the wide-angle camera to realize panoramic shooting and VR (Virtual Reality) shooting function or other fusion shooting functions. In some embodiments, the camera assembly 905 may also include a flash. The flash can be a monochrome temperature flash or a dual-color temperature flash. A dual-color temperature flash refers to a combination of a warm light flash and a cold light flash, which can be used for light compensation at different color temperatures.

[0164] The audio circuit 906 may include a microphone and a speaker. The microphone is used to collect sound waves from the user and the environment, and convert the sound waves into electrical signals to be input into the processor 901 for processing. For the purpose of stereo sound collection or noise reduction, there may be multiple microphones, each disposed at different locations on the terminal 900. The microphone may also be an array microphone or an omnidirectional collection microphone. The speaker is used to convert the electrical signal from the processor 901 into sound waves. The speaker may be a traditional thin film speaker or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, it can not only convert the electrical signal into sound waves audible to humans, but also convert the electrical signal into sound waves inaudible to humans for purposes such as distance measurement. In some embodiments, the audio circuit 906 may also include a headphone jack.

[0165] Power supply 907 is used to power various components in terminal 900. Power supply 907 can be AC power, DC power, a disposable battery, or a rechargeable battery. When power supply 907 includes a rechargeable battery, the rechargeable battery can support wired charging or wireless charging. The rechargeable battery can also be used to support fast charging technology.

[0166] Those skilled in the art will understand that Figure 9 The structure shown in the figure does not constitute a limitation on the terminal 90, and the terminal 90 may include more or fewer components than shown in the figure, or combine certain components, or adopt a different component arrangement.

[0167] Taking the computer device as a server as an example, Figure 10This is a structural diagram of a server provided in an embodiment of the present application. The server 1000 may have relatively large differences due to different configurations or performances, and may include one or more processors (Central Processing Units, CPU) 1001 and one or more memories 1002, wherein at least one computer program is stored in the one or more memories 1002, and the at least one computer program is loaded and executed by the one or more processors 1001 to implement the above-mentioned channel data dynamic clipping method. Of course, the server 1000 may also have components such as a wired or wireless network interface, a keyboard, and an input and output interface for input and output. The server 1000 may also include other components for realizing device functions, which will not be described in detail here.

[0168] An embodiment of the present application further provides a computer-readable storage medium, the computer-readable storage medium including a stored computer program, wherein when the computer program is executed, the device containing the computer-readable storage medium is controlled to execute the above method. Optionally, the computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc (CD-ROM), a magnetic tape, a floppy disk, an optical data storage device, or the like.

[0169] Those skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware, or by a program to instruct the relevant hardware, and the program may be stored in a computer-readable storage medium, which may be a read-only memory, a disk, or an optical disk, etc.

[0170] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A channel data dynamic clipping device, characterized in that: include: An interleaving module, a first comparator and a second comparator; the first comparator is electrically connected to the second comparator; The interleaving module is electrically connected to the first comparator and the second comparator respectively; In the simultaneous clipping mode, the interleaving module is configured to transmit the clipping upper bound to the first comparator in the (2t+1)th clock cycle; t is an integer greater than or equal to 0; The first comparator is configured to obtain channel data to be processed, use the clipping upper bound and the smaller data in the channel data as an intermediate result, and transmit the intermediate result to the second comparator; The interleaving module is further configured to transmit the clipping lower bound to the second comparator in the (2t+2)th clock cycle; The second comparator is configured to use the data with the larger value between the intermediate result and the clipping lower bound as the target result.

2. The device according to claim 1, characterized in that In the low clipping mode, the second comparator is further configured to obtain the channel data to be processed and the clipping lower bound, and use the larger value of the channel data to be processed and the clipping lower bound as the target result.

3. The device according to claim 2, characterized in that In the high clipping mode, the first comparator is further configured to obtain the channel data to be processed and the clipping upper bound, and use the smaller value of the channel data to be processed and the clipping upper bound as the target result.

4. The device according to claim 3, characterized in that The device further includes a first selector, a second selector, and a third selector; The first selector is electrically connected to the interleaving module and the first comparator respectively; The second selector is electrically connected to the first comparator and the second comparator respectively; The third selector is electrically connected to the interleaving module and the second comparator respectively; In the simultaneous clipping mode, the first selector is configured to transmit the clipping upper bound to the first comparator in the (2t+1)th clock cycle; The second selector is configured to transmit the intermediate result to the second comparator in the (2t+2)th clock cycle; The third selector is configured to transmit the clipping lower bound to the second comparator in the (2t+2)th clock cycle.

5. The device according to claim 4, characterized in that In the low clipping mode, the second selector is further configured to transmit the channel data to be processed to the second comparator; The third selector is further configured to transmit the clipping lower bound to the second comparator.

6. The device according to claim 4, characterized in that In the high clipping mode, the first selector is further configured to transmit the clipping upper bound to the first comparator.

7. The device according to claim 4, characterized in that The device further includes a fourth selector and a fifth selector; The fourth selector is electrically connected to the fifth selector, the first comparator and the second comparator respectively; The fifth selector is electrically connected to the first comparator; In the simultaneous cropping mode, the fourth selector is used to transmit the target result to the fifth selector; The fifth selector is used to output the target result.

8. The device according to claim 7, characterized in that In the low clipping mode, the fourth selector is further configured to transmit the target result to the fifth selector; The fifth selector is further configured to output the target result.

9. The device according to claim 7, characterized in that In the high cropping mode, the fifth selector is further configured to output the target result.

10. The device according to claim 3, characterized in that In the simultaneous clipping mode, the first comparator is further configured to convert the type of the channel data to be processed and the type of the clipping upper bound in the (2t+1)th clock cycle to obtain intermediate channel data and the intermediate clipping upper bound; and use the smaller value of the intermediate channel data and the intermediate clipping upper bound as the intermediate result; The second comparator is also used to convert the type of the clipping lower bound in the (2t+2)th clock cycle to obtain an intermediate clipping lower bound, and use the larger numerical data in the intermediate clipping lower bound and the intermediate result as the target result.

11. The device according to claim 10, characterized in that In the low clipping mode, the second comparator is also used to convert the type of the channel data to be processed and the type of the clipping lower bound to obtain the intermediate channel data and the intermediate clipping lower bound; and use the larger numerical data between the intermediate channel data and the intermediate clipping lower bound as the target result.

12. The device according to claim 10, characterized in that In the high clipping mode, the first comparator is also used to convert the type of the channel data to be processed and the type of the clipping upper bound to obtain the intermediate channel data and the intermediate clipping upper bound; and use the smaller numerical data among the intermediate channel data and the intermediate clipping upper bound as the target result.

13. The device according to claim 12, characterized in that The channel data to be processed includes first sub-channel data to be processed and second sub-channel data to be processed; In the simultaneous clipping mode, the first comparator is further configured to, in the (2t+1)th clock cycle, convert the type of the first sub-channel data to be processed, the type of the second sub-channel data to be processed, and the clipping upper bound to obtain first sub-intermediate channel data, second sub-intermediate channel data, and the intermediate clipping upper bound; use the smaller of the first sub-intermediate channel data and the intermediate clipping upper bound as a first sub-intermediate result; and use the smaller of the second sub-intermediate channel data and the intermediate clipping upper bound as a second sub-intermediate result. The second comparator is also used to convert the type of the clipping lower bound in the (2t+2)th clock cycle to obtain an intermediate clipping lower bound, and use the larger numerical data of the intermediate clipping lower bound and the first sub-intermediate result as the first sub-target result; and use the larger numerical data of the intermediate clipping lower bound and the second sub-intermediate result as the second sub-target result.

14. The device according to claim 12, characterized in that In the low clipping mode, the second comparator is also used to convert the type of the first sub-channel data to be processed, the type of the second sub-channel data to be processed and the type of the clipping lower bound to obtain the first sub-intermediate channel data, the second sub-intermediate channel data and the intermediate clipping lower bound; the larger numerical data of the first sub-intermediate channel data and the intermediate clipping lower bound is used as the first sub-target result; the larger numerical data of the second sub-intermediate channel data and the intermediate clipping lower bound is used as the second sub-target result.

15. The device according to claim 12, characterized in that In the high clipping mode, the first comparator is also used to convert the type of the first sub-channel data to be processed, the type of the second sub-channel data to be processed and the type of the clipping upper bound to obtain the first sub-intermediate channel data, the second sub-intermediate channel data and the intermediate clipping upper bound; the smaller numerical data among the first sub-intermediate channel data and the intermediate clipping upper bound is used as the first sub-target result; the smaller numerical data among the second sub-intermediate channel data and the intermediate clipping upper bound is used as the second sub-target result.

16. A method for dynamic clipping of channel data, characterized in that: include: In the simultaneous clipping mode, the clipping upper bound is transmitted to the first comparator at the (2t+1)th clock cycle; t is an integer greater than or equal to 0; Acquire channel data to be processed, use the clipping upper bound and the smaller data in the channel data as an intermediate result, and transmit the intermediate result to a second comparator; transmitting the clipping lower bound to the second comparator at the (2t+2)th clock cycle; The intermediate result and the data with larger values in the clipping lower bound are taken as the target result.

17. A computer device, characterized in that: The computer device includes a processor and a memory, the memory is used to store at least one program, and the at least one program is loaded by the processor and executes the channel data dynamic clipping method according to claim 16.

18. A computer-readable storage medium, characterized in that The computer-readable storage medium stores at least one program, and the at least one program is loaded and executed by the processor to implement the channel data dynamic clipping method according to claim 16.

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