Display system for driving pixels of a pixel array

Abstract

A display system for driving pixels of a pixel array is disclosed, comprising: display driver circuitry for receiving a command; receiving image frame data comprising a pixel intensity or brightness value of a bit plane of an image frame or subframe; processing the image frame data and the command to determine, for at least one pixel in the array of pixels, a pixel drive value and a pixel drive time interval for each of a plurality of bit planes, the pixel drive value and the pixel drive time interval for each bit plane defining a drive waveform; and generating one or more commands corresponding to the driving waveform; and display backplane circuitry to receive one or more commands corresponding to the driving waveform; and driving the at least one pixel according to the driving waveform such that an intensity or luminance value of each of the at least one pixel varies for each bit plane according to a combination of the corresponding pixel driving value and the corresponding pixel driving time interval.

Description

[0001] This application is a divisional application of the invention patent application with the application date of January 7, 2021, application number 202180008196.7 (international stage application number PCT / US2021 / 012472), and invention name “System and method for driving a display with high bit depth”.

[0002] Related applications

[0003] This application claims the benefit of U.S. Provisional Application No. 62 / 958,019, filed January 7, 2020, which is hereby incorporated by reference in its entirety. Technical Field

[0004] The present disclosure relates to display systems. More specifically, the present disclosure relates to display systems and methods for varying the intensity of pixels of a display. Exemplary displays may include LED displays, such as micro-LED displays that modulate the light emission of LEDs or micro-LEDs using a combination of temporal and amplitude (horizontal) modulation of the LEDs. Background Art

[0005] Conventional micro-LED backplanes are either digital voltage driven or analog voltage driven. The driving scheme attempts to convert the digital grayscale (relative brightness) value for each pixel in the image into the amount of light emitted or reflected from each pixel of the display during each frame of the video to be displayed. The digital voltage driven type typically has a fixed voltage or current for all bit planes or time intervals within the frame, and the intensity of the pixel is varied by changing the fixed voltage or current level applied in a binary manner. The analog drive scheme provides a static analog voltage or current for the entire video frame, but analog driven displays are subject to inaccuracies, mismatches (unevenness) and drifts in the drive values within the frame time.

[0006] Digital drive schemes are preferred for improved reproduction of grayscale values as pixel intensities on a display, however digital drive schemes that use only time and on / off state as variables to switch pixels on and off for bit planes or time intervals within a frame to control the intensity (i.e., apparent brightness) of the pixels for each frame impose unnecessary limitations. For example, in a typical digital drive scheme system, an 8-bit color depth means at least 256 bit planes, using for example a PWM scheme where a value of 1 corresponds to one bit plane time high, and 255 bit planes time low, then using a bit plane load time of 50 us means a frame minimum time of 256 x 50 us = 12.8 ms, or a frame rate of 1 / 12.8 ms = 78.125 Hz. This process does not take into account gamma encoding, which would require more bit planes to expand the grayscale data from the gamma encoded values to the equivalent of 12, 14, or 16 bits of linear intensity values, and so in these cases, 2 ^ 12 bit planes to correctly represent the expected intensity range.

[0007] If only binary-weighted durations are used to represent gray levels (e.g., 128 bit-planes for the MSB, 64 bit-planes for the MSB-1, etc.), the limited amount of time available to send a bit-plane to the display limits the system's ability to provide higher frame rates without sacrificing color depth. When a PWM (pulse width modulation) method is used to represent different gray levels, the pulse duration is proportional to the number of bit-plane times that must be sent to the display to achieve the desired gray level, then the ability to achieve higher bit depths is limited by the bit-plane time and the number of those bit-planes that can fit into the color sub-frame time.

[0008] In addition to compressing the time required to represent different intensity levels, gamma correction can often be applied, which is a non-linear operation that, when applied to incoming gamma-encoded gray values, provides, for example, more gray values because the intensity value of each gamma-encoded gray level is converted to a gray value or level that has a non-linear relationship to the other gray values or levels, and therefore requires a greater bit depth to correctly represent the value digitally. Providing gamma correction is also more difficult to implement in display systems with smaller bit depths and those limited by the number of bit planes in a frame time, because it is difficult to represent the intensity with the small amount of time increments available. Therefore, these systems need to use some of the bit depth to map the incoming gray to its gamma-corrected value, and this results in a reduction in bit depth or insufficient time to place a sufficient number of bit planes to allow accurate representation of the gamma-encoded value. Summary of the Invention

[0009] In an aspect of the present disclosure, a display system for driving pixels of a pixel array is provided, comprising: a display driver circuit system for: receiving commands; receiving image frame data, the image frame data comprising pixel intensities or brightness values of bit planes of an image frame or subframe; processing the image frame data and commands to determine a pixel drive value and a pixel drive time interval for each of a plurality of bit planes for at least one pixel in the pixel array, the pixel drive value and the pixel drive time interval for each bit plane defining a drive waveform; and generating one or more commands corresponding to the drive waveform; and a display backplane circuit system for: receiving one or more commands corresponding to the drive waveform; and driving at least one pixel according to the drive waveform, such that: the intensity or brightness value of each of the at least one pixel varies for each bit plane according to a combination of the corresponding pixel drive value and the corresponding pixel drive time interval.

[0010] Embodiments of the present disclosure combine the ability to change pixel drive current on the fly (globally for the entire display) over the course of a frame (e.g., a video frame) with a flexible sequence of bit planes of varying time duration to compose pulses of varying width to give varying intensity levels. By adding additional variables (e.g., current for an LED or voltage for an LCoS), both time and current / voltage can be used to change the intensity value represented by any portion of the drive waveform or any grayscale value by having each intensity level represented as the sum of a series of time / current / voltage pairs.

[0011] Implementations of the present disclosure may include: a) a display backplane IC comprising a display array or matrix comprised of or composed of a plurality of driver pixel circuits, the driver pixel circuits, such as current driver pixel circuits (which may typically include pixel logic gates incorporating current sources such as transistors (e.g., field effect transistors) and pixel drivers to drive LEDs (i.e., pixel elements) coupled to the pixel circuits; b) a drive sequence (which may reside in a driver IC or driver logic co-located in the backplane IC, which programs a global voltage bias DAC setting for biasing current drivers in the pixels, controls or is used to vary the drive current of the pixel driver circuits such that when the system is exposed to a new global bias DAC setting multiple times per video frame (i.e., coinciding with one or more bit planes), the pixel circuits provide a new global bias DAC setting. c) a mechanism, such as an SPI slave, which outputs new binary value updates to registers controlling bias DACs based on commands embedded in image frame data (which may include video data) through the system, such that the bias DACs control the global bias voltage of the current sources for the pixel array; and d) a sequence memory storing one or more programmable mappings that can vary based on desired performance or in response to environmental conditions, such as ambient lighting and temperature (to provide temperature compensation), and is utilized by the display driver logic to convert between input grayscale levels and a sequence of timed current pairs to be sent to the display backplane IC for each pixel over the course of a frame time to achieve the desired grayscale value.

[0012] In an embodiment of a system according to the present disclosure, a sequence generated by sequence generation software capable of creating and calibrating such a sequence can divide the available frame time into regions, where each region uses a different current drive value and uses a PWM waveform generated at the output of each pixel driver circuit in each region, as shown in the accompanying drawings. In an embodiment of a drive sequence (i.e., a set of commands that map grayscale values to bit plane values and timing and current drive values) according to an embodiment of the present disclosure, the drive current to each pixel of the display or to at least a portion of the display can be changed simultaneously for each pixel of the display or a portion of the display based on one or more commands, the one or more commands being transmitted to a backplane IC containing a pixel driver circuit system, together with or simultaneously with the image data being transmitted to a memory element of the driver circuit system of the display. In an embodiment, the driver circuit system may be included in, integrated into, or coupled to the backplane of the display. In an embodiment of the present disclosure, the driver circuit system may or may not be integrated into or included in the backplane and may be electrically coupled to the display via one or more conductive elements.

[0013] According to a second aspect of the present disclosure, a display system for driving pixels of a pixel array is provided, comprising: a display driver circuit system configured to: receive image frame data comprising a plurality of frame areas, each frame area comprising: intensity values of a plurality of bit planes; and a global bias; and process the image frame data to determine, for at least one pixel in the pixel array, a pixel drive value and a pixel drive time interval for each of the plurality of bit planes of at least one frame area corresponding to the at least one pixel; and a display backplane circuit system comprising: a pixel driver circuit system comprising: a pixel circuit for driving at least one pixel of the pixel array so that the intensity of the at least one pixel varies for each bit plane according to the corresponding pixel drive value and the corresponding pixel drive time interval.

[0014] Embodiments of the present disclosure overcome the above-mentioned problems of conventional devices and methods, as well as other shortcomings and deficiencies of the prior art, by providing systems, methods, and apparatus with flexible driving schemes that allow real-time parameter changes and enable higher bit depths at higher frame rates.

[0015] Embodiments of the present disclosure combine the ability to change pixel drive current simultaneously for the entire display and in real time during an image frame with a flexible sequence of bit planes of varying time duration (i.e., varying pixel drive current between bit planes within a single image frame). By adding an additional variable to be controlled by the system, such as the current for an LED or the voltage for a liquid crystal on silicon (LCoS), both time and current / voltage can be used to change the intensity value represented by any portion of the drive waveform and / or any grayscale value, which can therefore change the brightness of the pixel driven by the drive waveform. Thus, according to embodiments of the present disclosure, a flexible drive system according to the present disclosure can combine two variables, such as time and current or time and voltage, and apply them in combination to represent an intensity level, and can change these parameters (i.e., time, voltage, and current) in real time and synchronously, allowing displays according to embodiments of the present disclosure to achieve greater bit depth (color / intensity accuracy) without having to use as much time to display each frame of information, thereby allowing greater accuracy at the same frame rate, or faster frame rates at the same accuracy, compared to prior art systems.

[0016] These and other capabilities of the disclosed subject matter will be more fully understood after reviewing the following drawings, detailed description, and claims.It is to be understood that the phraseology and terminology employed herein are for the purpose of description and should not be regarded as limiting. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present disclosure is herein shown and described with reference to the various figures, wherein like reference numerals are used to refer to like system components where appropriate, and in which:

[0018] Figure 1a A block diagram of a display system according to an embodiment of the present disclosure is shown.

[0019] Figure 1b Shown incorporated Figure 1a Micro LED display system for display system.

[0020] Figure 1c Shown incorporated Figure 1a LCOS display system of the display system.

[0021] Figure 2 A flow chart illustrating a method of operating a display system according to an embodiment of the present disclosure is shown.

[0022] Figure 3 Driving waveforms generated by the method of operation of the display system according to an embodiment of the present disclosure are shown. DETAILED DESCRIPTION

[0023] In the following detailed description, reference is made to the accompanying drawings, which form a part of this detailed description and in which are shown by way of illustration embodiments that may be practiced. It should be understood that other embodiments may be utilized and that structural or logical changes may be made without departing from the scope. Therefore, the following detailed description should not be taken in a limiting sense, and the scope of the embodiments is defined by the appended claims and their equivalents.

[0024] Various operations may be described as multiple discrete operations in turn, in a manner that may aid in understanding the embodiments; however, the order of description should not be construed as to imply that these operations are order dependent.

[0025] The description may use perspective-based descriptions, such as up / down, back / front, and top / bottom. Such descriptions are only used to facilitate discussion and are not intended to limit the application of the disclosed embodiments.

[0026] The terms "coupled" and "connected," and their derivatives, may be used. It should be understood that these terms are not intended to be synonymous with each other. Rather, in particular embodiments, "connected" may be used to indicate that two or more elements are in direct physical contact with each other. "Coupled" may mean that two or more elements are in direct physical contact. However, "coupled" may also mean that two or more elements are not in direct contact with each other but still cooperate or interact with each other.

[0027] For the purposes of this description, a phrase of the form "A / B," "A or B," or "A and / or B" means (A), (B), or (A and B). For the purposes of this description, a phrase of the form "at least one of A, B, and C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). For the purposes of this description, a phrase of the form "(A)B" means (B) or (AB), i.e., A is an optional element.

[0028] The specification may use the terms "embodiment" or "embodiments," which may refer to one or more of the same or different embodiments. In addition, the terms "comprising," "comprise," "including," "having," etc. used with respect to an embodiment are synonymous and generally intended to be "open" terms (e.g., the term "including" should be interpreted as "including but not limited to," the term "having" should be interpreted as "at least having," the term "includes" should be interpreted as "including but not limited to," etc.).

[0029] With respect to the use of any plural and / or singular terms herein, those skilled in the art can convert the plural to the singular and / or the singular to the plural to suit the context and / or application. For clarity, various singular / plural permutations may be explicitly set forth herein.

[0030] Various embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth to facilitate a thorough understanding of one or more embodiments. However, it will be apparent that any of the embodiments described below may be practiced without employing the specific design details described below in some or all instances.

[0031] FIG1 shows a display system 100 according to an embodiment of the present disclosure. Figure 1a As shown in FIG, a data source 102, such as an image, image data, or video source or video data 104, such as a host. In embodiments of the present disclosure, the host may include a processor 105, such as an application processor, that executes applications, instructions, or commands 106 (e.g., software) stored in a storage device (e.g., memory device 107) of the host. In embodiments of the present disclosure, the host may stream image data or images, such as video data.

[0032] In embodiments of the present disclosure, the data source or host can be, for example, a mobile device such as a smartphone, tablet, laptop, head-up display system, headset, or hybrid device (or some combination thereof). In embodiments of the present disclosure, images, image data, and / or video data are received by the real-time data software module 107a and / or MUX 108 of the host 102, and the real-time data software or software module 107a combines the data with commands parsed from a master sequence file containing the desired drive sequence at the multiplexer (MUX) 108 and / or the real-time data software module 107a. Additionally or alternatively, the MUX 108 can be hardware controlled by the real-time data software module 107a. In embodiments of the present disclosure, the data combined with the commands is the combined data output from the data source (e.g., host) 102 and transmitted to the display subsystem. In embodiments of the present disclosure, the combined data is output via the real-time data software module 107a and / or MUX 108 of the data source 102.

[0033] In an embodiment of the present disclosure, the combined data is streamed or transmitted to the display driver IC 120 of the display subsystem 120 or the parser logic software module or software 124 in the display driver circuit system 122 via the communication transmission device, data transmission device, and / or protocol 110. In an embodiment of the present disclosure, the display driver circuit system can be incorporated into an IC (e.g., DDIC 122). In an embodiment of the present disclosure, the communication transmission device and / or protocol is a MIPI controller and / or MIPI protocol 110. In an embodiment of the present disclosure, the combined data is transmitted to the MIPI controller, which uses MIPIPHY (physical layer) to transmit the data to the display subsystem 120. In an embodiment of the present disclosure, the combined data is transmitted to the parser 124 of the display driver IC 122. In an embodiment of the present disclosure, the combined data is transmitted to the display driver IC 122.

[0034] In an embodiment of the present disclosure, the display subsystem 120 may be a micro-LED display subsystem including a display driver circuit system, a display including a display backplane 130 having a backplane circuit system integrated therewith or electrically connected or coupled thereto, and a pixel array 140 (e.g., a pixel array of pixel elements, such as an LED pixel array (e.g., a micro-LED pixel array). In an embodiment of the present disclosure, the LED pixel array (e.g., a micro-LED pixel array) is not included in the display backplane IC 130 or the subsystem 120.

[0035] In an embodiment of the present disclosure, the display subsystem may be a liquid crystal on silicon (LCoS) display subsystem that includes a display driver circuitry, a display device including a liquid crystal material or substance and a backplane having a backplane circuitry integrated therewith or electrically connected or coupled thereto, and a pixel array (e.g., a pixel array of pixel elements, such as a pixel array of reflective devices (e.g., an array of mirror elements / devices that operate when charged to control the position of liquid crystal in the display device)). In an embodiment of the present disclosure, the pixel array of reflective devices is not included in the display backplane IC 130 or subsystem 120.

[0036] In an embodiment of the present disclosure, the display driver circuitry is internal to the display subsystem or electrically coupled to the display. In an embodiment of the present disclosure, at least some of the display driver circuitry may be incorporated into a display driver integrated circuit (DDIC) 122. In an embodiment of the present disclosure, the parser 124 may be included, incorporated into, and / or integrated into the DDIC 122.

[0037] In an embodiment of the present disclosure, the display driver circuit system or subsystem 120 receives combined data from the communication and data transmission device or system 110 and converts the combined data into serial peripheral interface (SPI) commands 150 and bit-plane data 152. In an embodiment of the present disclosure, the parser 124 receives the combined data, parses and / or separates the combined data into commands and image data. Other logic within the DDIC 122 can then convert the image data into bit-plane data. The bit-plane data can then be output to the display backplane 130. In an embodiment of the present disclosure, the parser 124 and / or DDIC parses and / or converts the combined data into (SPI) commands 150 and bit-plane data 152 that are output to the display backplane 130. In an embodiment of the present disclosure, the SPI slave 163 of the driver IC 122 or the display backplane IC 130 receives the SPI commands. In an embodiment of the present disclosure, the display backplane IC 122 includes an SPI slave 163, one or more storage devices 164 (e.g., registers), a bias DAC 166, display backplane logic (e.g., pixel logic 172) and circuitry (e.g., 174), and optionally a pixel electrode 176.

[0038] In an embodiment of the present disclosure, the SPI command 150 is a command to write to an internal register or memory. In an embodiment of the present disclosure, the bit plane data 152 is data that determines or controls the intensity or brightness of a pixel when presented sequentially to the pixel array, and may be arranged in words representing data for a series of pixels in a row or column or rectangular sub-region to be assigned to the pixel array 140 or display. It will be understood by those skilled in the art that the bit depth can vary, but is typically between 6 and 10 bits, and more typically 8 bits.

[0039] Figure 1b is a diagram of a micro LED display system 180 that, in an embodiment, may include the display system 100 of the present disclosure. The micro LED display system 180 generally includes a pixel array 140 of individual pixel LED elements 184 arranged on a substrate 182.

[0040] Similarly, Figure 1c 1 is an illustration of an LCOS display system 190 having similar elements, and in embodiments, this LCOS display system 190 may also include the display system 100 of embodiments of the present disclosure. In particular, a substrate 182 is provided to which the display backplane 120 may be coupled or integrated. The substrate 182 may be silicon. A reflective device or layer 196, which may be an aluminum layer, has a pixel array 140 disposed thereon, coupled or integrated with the display backplane 120. A liquid crystal layer 193, an orientation layer 198, transparent electrodes (typically within an indium tin oxide layer) 199, and a layer of glass or other transparent material 197 forming the display complete the structure. In embodiments, such an LCOS display may include a series of individual square elements.

[0041] In embodiments of the present disclosure, the display backplane IC 130 may be included in, incorporated into, or integrated into the display backplane 120 (which may be coupled to, for example, the reflective device 186; 196 in an LCOS display system or LEDs such as micro-LEDs in a micro-LED display system). The pixel array (i.e., micro-LEDs or LEDs) may be on its own substrate, with each LED coupled to a pixel driver on the backplane. In embodiments of the present disclosure, the display backplane 120 is coupled to the display device 180, 190 (e.g., an LCOS device) or the LCOS pixel array 140 or pixel elements (e.g., the reflective device 186; 196 or the LED or array of LEDs (e.g., micro-LEDs)). In an embodiment of the present disclosure, the display device 100 includes a display backplane 120, a display backplane circuitry 130, a pixel circuitry 174 (e.g., as pixel driver circuitry or pixel circuitry), and a pixel element 140a coupled (e.g., electrically coupled) to, integrated into, included in, and / or positioned within a DDIC 122. In an embodiment of the present disclosure, the display device 100 (including the DDIC 122) is electrically coupled to the DDIC and forms the display subsystem 120 and is assembled together in the display module 100.

[0042] In an embodiment of the present disclosure, the display subsystem 120 includes a display 197. In an embodiment of the present disclosure (e.g. Figure 1c), the display 197 is an array of pixel elements 140 arranged on a backplane 120 or coupled to a backplane circuitry (e.g., pixel circuitry 170, pixel drive circuitry, or drive circuitry incorporated into, coupled to, or integrated into the backplane). In an embodiment of the present disclosure, the display subsystem 120 is a liquid crystal on silicon (LCoS) display subsystem of an LCoS display system 190. In an embodiment of the LCoS system 190 according to an embodiment of the present disclosure, the display 197 is a liquid crystal display or liquid crystal cell (including liquid crystals 193 disposed between two substrates 196, 199) that is electrically coupled to or integrated with the backplane 120 or backplane IC of the display subsystem. In an embodiment of the present disclosure, one of the substrates 196 of the liquid crystal display or liquid crystal cell is the backplane 120 or backplane IC. In an embodiment of the present disclosure, a liquid crystal display or liquid crystal cell 193 is included in, integrated into, or electrically coupled to a display backplane integrated circuit 130 (IC) or its substrate. In an embodiment of the present disclosure, the display backplane IC 130 is electrically coupled to one of the sides of the liquid crystal cell, such as the side of the display that does not emit light or that corresponds to the light of an image. In an embodiment of the present disclosure, the liquid crystal cell is coupled to a silicon substrate 182, and this substrate is either the same silicon substrate as the side that forms the display backplane IC 120 or a silicon substrate that is coupled to a substrate of the display backplane IC (e.g., a substrate such as a silicon substrate that includes the driver circuitry, pixel circuitry, pixel circuits 170, and / or driver circuits 166).

[0043] In embodiments of the present disclosure (e.g. Figure 1b), the display subsystem 120 is a micro-LED display subsystem 180. In an embodiment of the present disclosure, the display subsystem 100 is a micro-LED system 180. In an embodiment of the micro-LED subsystem 180 according to an embodiment of the present disclosure, the display is an array of LEDs 184 or micro-LEDs that are electrically coupled to or integrated into or with the backplane 120 or display backplane IC of the display subsystem 100. In an embodiment of the present disclosure, the array of micro-LEDs 184 is included in, integrated into, or electrically coupled to the display backplane integrated circuit (IC) 122 and / or its substrate 182. In an embodiment of the present disclosure, the display backplane IC 122 is electrically coupled to one of the sides of the array of LEDs (e.g., micro-LEDs), for example, the side of the array of LEDs (e.g., micro-LEDs) that does not emit light or corresponds to light of an image. In an embodiment of the present disclosure, the array of LEDs 184 (e.g., micro-LEDs) is coupled to a silicon substrate 182, which is either the same silicon substrate that forms one side of the display backplane IC 122 or a silicon substrate 182 that is coupled to a substrate 186 of the display backplane IC 122 (e.g., the silicon substrate of the display backplane IC).

[0044] In an embodiment of the present disclosure, the array of pixels 184 includes pixel elements assembled in an array 140, or pixel elements assembled in an array on a substrate 182. In an embodiment of the present disclosure, the array of pixels 180 is an array of light emitting diodes (LEDs). In an embodiment of the present disclosure, the LEDs can be micro-LEDs. In an embodiment of the present disclosure, the array 140 of pixel elements 184 is an array of reflective elements 196 that control the birefringence of the liquid crystals 193 in the LCoS device 190 or other liquid crystal device. In an embodiment of the present disclosure, the pixel element 184 is a reflective element / device, such as a mirror. In an embodiment of the present disclosure, the pixel array 140 or array of pixels is formed in, incorporated into, integrated into, or coupled to the display backplane IC 122. In an embodiment of the present disclosure, a DDIC or display driver circuitry drives the operation of pixel elements (eg, light emitting diodes (LEDs), micro-LEDs 184 , reflective elements) of an array of pixel elements arranged on the backplane 120 of the display subsystem 100 .

[0045] In an embodiment of the present disclosure, the display subsystem 100 may also include registers 164, digital-to-analog converters (DACs) (e.g., bias DACs) 166, and an SPI slave or receiver 163 for an alternative protocol such as I2C or a custom protocol. In an embodiment of the present disclosure, the SPI slave, registers, and digital-to-analog converters (DACs) (e.g., bias DACs) are formed in, incorporated into, integrated into, or coupled to the display driver circuitry, display backplane circuitry, and / or display backplane IC.

[0046] In an embodiment of the present disclosure, the SPI slave 163 is electrically coupled to one or more registers 164 via, for example, an internal parallel bus and a write strobe pulse. In an embodiment of the present disclosure, the register is electrically coupled to a DAC (e.g., a bias DAC) 166 via, for example, a 6-bit or 8-bit DAC designed to provide a voltage suitable for biasing a current source in the pixel array. In an embodiment of the present disclosure, the DAC (e.g., a bias DAC) is electrically coupled to the pixel array via, for example, a Vref signal. In an embodiment of the present disclosure, the SPI slave receives SPI commands from a parser, DDIC, and / or display driver circuitry and generates write strobe pulses and parallel data that are output to one or more registers. In an embodiment of the present disclosure, one or more registers receive data and store values that are continuously output to the DAC. In an embodiment of the present disclosure, the DAC (e.g., a bias DAC) receives a binary value from one or more registers and converts the value into a voltage and continuously outputs the voltage to at least a portion of the pixel array.

[0047] In an embodiment of the present disclosure, at least some of the pixel elements 140a are coupled to pixel circuitry 170. In an embodiment of the present disclosure, each of the utilized or available pixels or each of the pixel elements is electrically coupled to or integrated with pixel circuitry. For example, the pixel circuitry shown in FIG1 shows a bias voltage applied to each pixel or pixel element in the array or each pixel or pixel element in the available array. In an embodiment of the present disclosure, a pixel includes a pixel element (e.g., an LED, a micro-LED, or a reflective device) and a pixel circuitry.

[0048] In an embodiment of the present disclosure, each pixel circuit 170 includes a pixel logic circuit system 172 connected to at least one transistor 174 and a pixel electrode 176. In an embodiment of the present disclosure, the pixel logic includes a logic element (e.g., one or more logic gates or combinational logic circuits) that generates a digital output or value (e.g., an on value or an off value, or a one value or a zero value) that is output to one end of the transistor coupled thereto. In an embodiment of the present disclosure, the transistor is a field effect transistor (FET). In an embodiment of the present disclosure, the transistor is electrically coupled to a voltage source or a DAC (e.g., a bias DAC). In an embodiment of the present disclosure, the other end of the transistor is electrically coupled to the pixel electrode 176 or pixel element. In an embodiment of the present disclosure, the pixel electrode is electrically coupled to a pixel element, such as an LED or a micro-LED. For the purposes of this disclosure, references to LEDs are also references to micro-LEDs. In an embodiment of the present disclosure, the display subsystem 120 is a micro-LED display subsystem, and the transistor 174 is a FET. In an embodiment of the present disclosure, a FET drives a micro-LED display and is electrically coupled (e.g., via a wire / cable) directly or indirectly (e.g., via pixel electrode 176) to pixel element 140a (e.g., a micro-LED) and serves as a current source for the pixel element. In an embodiment of the present disclosure, a device for on / off control of pixel element 140a is directly or indirectly coupled to the source terminal of FET 174. In an embodiment of the present disclosure, the output of the pixel logic is an on / off control or activation / deactivation device for the pixel element and is connected to the source terminal of FET 174. In an embodiment of the present disclosure, a bias voltage (e.g., a center bias voltage DAC) is received at the gate terminal of the FET, for example, from a DAC 166, which is electrically coupled to the gate terminal of FET 174. In an embodiment of the present disclosure, the use of a DAC enables fine (multi-value relative to on / off, e.g., 6-bit or 8-bit precision) control of the drive current.

[0049] like Figure 2, a method 200 for operating a display system 100 according to an embodiment of the present disclosure is described. In embodiments of a method of operating a display system, the method may include the step of providing a display system 100. According to embodiments of the present disclosure, subsequent step 220 may include receiving image frame data and commands from an image data source 120. The image frame data may be received at a real-time data software module 107a and / or MUX 108 that receives data 194 and / or commands 106. In embodiments of the present disclosure, the image frame data may be, for example, an image, image data, video, or video data 104 received from memory 107 in a host 102. In embodiments, the command 106 is a command initiating the writing of bit-plane data to a pixel driver array or a command updating a register value, such as an offset DAC input data word. In embodiments of the present disclosure, the real-time data software module 107a and / or MUX 108 reside on a storage device (e.g., memory device 107) in the data source 102 or the host. In embodiments of the present disclosure, the data source 102 is coupled to the processor 105. The processor 105 executes the instructions of the real-time data software or module 107a and / or the MUX 108. In an embodiment of the present disclosure, the data source 102 is a host device that includes the processor 105, which executes the instructions of the real-time data software or module 107a and / or the MUX 108. In an embodiment of the present disclosure, the real-time data software or module 107a and / or the MUX 108 combines the data and the commands and generates a combined data output and outputs the combined data to the display subsystem in step 230. By adding the commands 106 to the image or video data 104 (or combining the commands with the video data) at the MUX 108, the real-time data software module 107a, etc., the application of the commands 106 becomes delivered in real time along with the image or video data 104. In an embodiment of the present disclosure, the combined data output is transmitted to the display subsystem via a data communication device, interface device and / or communication protocol (e.g., a MIPI interface) 110, which is electrically coupled to the data source 102 and the display subsystem 120, the display driver circuit system 122 and / or the display driver IC, and can be internal or external to the display subsystem 120.

[0050] In step 240, the parser 124 receives and parses the combined data and outputs the SPI command 150 and the image data, which is converted into image data that is converted into bit-plane data 152 via logic in the DDIC 122, and the SPI command 150 and the image data are sent to the display backplane and / or the display backplane IC 130 at the same time or different times (e.g., at different times in the same time period such as a frame or sub-frame). In an embodiment, a display subsystem 120 or system according to an embodiment of the present disclosure may use a parser 240 (which may be internal or external to the display driver IC) to parse the incoming data 110 (e.g., bit-plane data) and commands (e.g., commands) in step 240 and then separate and format and / or convert the incoming data (e.g., bit-plane data) and commands into: 1) bit-plane data 152 (i.e., data containing the on / off state of at least some of the pixels of the display backplane IC within a given time interval of a video frame); 2) a local register 126 configuration that controls parameters of a bit-plane formatting operation performed by the display driver logic and backplane 130 combination by converting a received set of multi-bit grayscale values into a series of n bit-planes, each bit-plane carrying the nth bit of the grayscale values for all pixels in the pixel array; and 3) commands 150 specified for the SPI connection to the display backplane IC 130. This series of operations constitutes a mechanism or means for delivering an immediate parameter change in step 240 , which enables the drive waveform 150 to be formed using both a time duration and an analog drive value corresponding to an intensity when considered together.

[0051] In step 250, SPI slave 163 receives SPI command 150 and converts it into parallel data and write strobe pulses, and then sends or outputs the data and strobe pulses to register 164. In step 260, one or more of pixel circuits 170 receives the bit-plane data (e.g., the instantaneous brightness value or intensity value for each pixel of the display) and modulates its output, thereby controlling the intensity of the pixel.

[0052] In step 270, when the new pixel drive value Vref 152 (i.e., bias voltage or drive current) has been written from the parser 124 to the register 164, the SPI command 150 stored in the register 164 is output or sent to the DAC 166, such as the bias DAC. In an embodiment of the present disclosure, the new value is or can be written to the register 164 when or upon an update command received via the SPI command 150.

[0053] In an embodiment of the present disclosure, in the parser 124 (which may be internal or external to the backplane IC 130), a command (e.g., a change to the global current bias DAC input word) is received, the command 106 is decoded, and the SPI command is transmitted to the SPI slave 163. In an embodiment of the present disclosure, the SPI slave 163 is included in or integrated with or coupled to the backplane IC 130, and upon receiving the SPI command 150 and storing it in the register 164 (if necessary), and when instructed by the master drive sequence stored in the driver IC 122 or driver logic, the parser 124 outputs bit-plane data 152, which is sequentially loaded into the pixel array 140 to control the state of each pixel 140a for a given period of time.

[0054] In step 890, the bias voltage, in combination with the output of the pixel logic, determines when current flows to the pixel electrode 176, which is electrically coupled to the pixel element 140a (e.g., an LED, micro-LED, or a reflective mirror) or directly coupled to the pixel element, so that the pixel element 140a is turned on or off (i.e., activated or deactivated). In an embodiment of the present disclosure, in step 290, the bias voltage, in combination with the output of the pixel logic, determines when current flows to the pixel electrode 176, which is electrically coupled to the pixel element 140a (e.g., an LED, micro-LED, or a reflective mirror) or directly coupled to the pixel element, so that the pixel element is turned on (i.e., activated) and emits light at a level of brightness represented by the bit-plane value of the bit-plane data received at the corresponding pixel element. In an embodiment of the present disclosure, the total light output from the display system 100 according to an embodiment of the present disclosure, for example, within a video frame for each pixel 140a, is the sum of the product of the current value and the on / off state for each pixel (or region of pixels) for each time interval programmed.

[0055] Figure 3 1 shows a driving waveform generated according to an embodiment of the present disclosure. Figure 2 The steps implemented by the system of Figure 1 are generated by biasing the pixel array via commands transmitted along with the incoming video data. Figure 3 The driving waveform shown in . Figure 3 The drive sequence shown in FIG contains an update interval (in which a new DAC control word is transmitted to and stored in a register of the backplane IC) and a drive interval, shown as a number of "current regions," in which driving at a certain current level takes a programmable amount of time. The drive waveform for each pixel or a series of pixels of the pixel array can be transmitted as a command to the display backplane IC 130.

[0056] The embodiments herein have many benefits and advantages. The embodiments herein overcome the limitations of analog systems, which only vary the current and keep the pixel always powered, or digital drive which only has binary on / off states. The embodiments of the present disclosure provide a system where both current and voltage parameters can be controlled simultaneously to determine how long the current is on the pixel within a given time period. Due to the flexible programmability of the format, a variety of different mapping schemes are possible and customizable.

[0057] The subject matter described herein can be implemented in a digital electronic circuit system or in computer software, firmware or hardware, including the structural devices disclosed in this specification and their structural equivalents, or in a combination thereof. The subject matter described herein can be implemented as one or more computer program products, such as tangibly implemented in an information carrier (e.g., in a machine-readable storage device) or implemented in a propagated signal, for execution by a data processing device (e.g., a programmable processor, a computer or multiple computers) or to control one or more computer programs for the operation of a data processing device (e.g., a programmable processor, a computer or multiple computers). A computer program (also referred to as a program, software, software application or code) can be written in any form of programming language, including compiled or interpreted languages, and can be deployed in any form, including as a standalone program or as a module, component, subroutine or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file. A program may be stored in a portion of a file that holds other programs or data, in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files storing code for one or more modules, subroutines, or portions of code). A computer program may be deployed to be executed on one computer or on multiple computers at one site or distributed across multiple sites and interconnected by a communication network.

[0058] The processes and logic flows described in this specification, including the method steps of the subject matter described herein, can be performed by one or more programmable processors executing one or more computer programs to perform the functions of the subject matter described herein by operating on input data and generating output. The processes and logic flows can also be performed by, and the apparatus of the subject matter described herein can be implemented as, special purpose logic circuitry, such as an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit).

[0059] By way of example, processors suitable for executing computer programs include both general-purpose and special-purpose microprocessors, as well as any one or more processors of any type of digital computer. Typically, the processor will receive instructions and data from a read-only memory or a random access memory, or both. The essential elements of a computer are a processor for executing instructions and one or more memory devices for storing instructions and data. Typically, a computer will also include or be operatively coupled to one or more mass storage devices for storing data, such as magnetic, magneto-optical, or optical disks, to receive data from or transfer data to, or both. Information carriers suitable for carrying computer program instructions and data include all forms of non-volatile memory, including, by way of example: semiconductor memory devices (e.g., EPROM, EEPROM, and flash memory devices); magnetic disks (e.g., internal hard disks or removable disks); magneto-optical disks; and optical disks (e.g., CDs and DVDs). The processor and memory may be supplemented by or incorporated into dedicated logic circuitry.

[0060] The subject matter described herein can be implemented in a computing system comprising a back-end component (e.g., a data server), a middleware component (e.g., an application server), or a front-end component (e.g., a client computer mobile device, wearable device having a graphical user interface or a web browser through which a user can interact with an implementation of the subject matter described herein), or any combination of such back-end components, middleware components, and front-end components. The components of the system can be interconnected by any form or medium of digital data communication, such as a communication network. Examples of communication networks include local area networks ("LANs") and wide area networks ("WANs"), such as the Internet.

[0061] It should be understood that the disclosed subject matter is not limited in its application to the details of the construction and the arrangement of parts set forth in the following description or shown in the accompanying drawings. The disclosed subject matter is capable of other embodiments and can be practiced and executed in various ways. In addition, it should be understood that the wording and terminology adopted herein are for descriptive purposes and should not be regarded as restrictive. Therefore, it will be understood by those skilled in the art that the concept on which this disclosure is based can be easily used as the basis for designing other structures, methods and systems for several purposes for performing the disclosed subject matter. Therefore, it is important that the claims should be regarded as including such equivalent constructions where such equivalent constructions do not depart from the spirit and scope of the disclosed subject matter.

[0062] While the disclosed subject matter has been described and illustrated in the foregoing exemplary embodiments, it should be understood that this disclosure is made by way of example only and that many changes may be made in the details of the implementation of the disclosed subject matter without departing from the spirit and scope of the disclosed subject matter, which is limited only by the appended claims.

[0063] In addition, the present disclosure also provides the following configuration.

[0064] 1. A display system for driving pixels of a pixel array, comprising:

[0065] A display subsystem, configured to display images and execute commands from an image or video data source, comprising:

[0066] display driver circuitry configured to receive image frame data and commands from the image or data source, the image frame data comprising pixel intensity or brightness values for bit planes of an image frame or subframe;

[0067] a parser configured to receive the image frame data and the command, and

[0068] configured to determine a driving waveform having a pixel driving value and a pixel driving time interval for each bit plane of the image frame data;

[0069] a display backplane for receiving the drive waveform, the display backplane comprising pixel driver circuitry for driving the pixels in accordance with the drive waveform, and wherein the intensity or brightness of the pixels varies for each bit plane in accordance with the pixel drive value and the pixel drive time interval.

[0070] 2. A system according to configuration 1, wherein the display driver circuit system further includes a digital-to-analog converter (DAC) driven by a register, the digital-to-analog converter (DAC) being configured to convert a digital control word into a bias voltage to control a drive current of the pixel driver circuit system for all pixels.

[0071] 3. A system according to configuration 1 or configuration 2, wherein the display backplane circuit system provides both bit-plane digital data and bias voltage to the pixel driver circuit system for driving all pixels of the pixel array, and wherein the drive waveform changes the pixel drive value.

[0072] 4. The system of any preceding configuration, further comprising a sequence memory for storing one or more programmable mappings that modify at least one of the pixel drive value and its pixel drive time interval based on desired performance or ambient lighting or temperature compensation.

[0073] 5. The system of configuration 4, wherein the display driver circuitry converts at least one of the pixel drive value and / or the pixel drive time interval according to the programmable mapping.

[0074] 6. A system according to any of the preceding configurations, wherein the image frame comprises a series of frame regions, wherein each frame region comprises a plurality of bit planes, and wherein each frame region has a different global bias and therefore a different maximum intensity value.

[0075] 7. A system according to any preceding configuration, wherein drive waveforms for each pixel or series of pixels of the pixel array are transmitted as commands to the display backplane when image data is transmitted to the memory element of the display driver circuitry.

[0076] 8. The system of any preceding configuration, wherein the data source comprises one or more of an image, image data, or a video source.

[0077] 9. The system of any preceding configuration, wherein the data source is a host computer, the host computer comprising a processor that executes an application stored on or streamed to the host computer.

[0078] 10. The system of any preceding configuration, wherein the pixel comprises a light emitting diode, and wherein the analog drive value comprises a pixel drive current.

[0079] 11. The system of any one of configurations 1 to 9, wherein the pixel comprises liquid crystal on silicon, and wherein the analog drive value comprises a voltage.

[0080] 12. The system of any preceding configuration, wherein the display backplane and / or the display driver are integrated circuits.

[0081] 13. The system of any preceding configuration, wherein the display subsystem further comprises a receiver for receiving commands from the parser, the receiver generating a write strobe and parallel data that are output to one or more registers.

[0082] 14. The system of configuration 13, wherein the display subsystem further comprises a digital-to-analog converter configured to determine the pixel drive value based on values output by the one or more registers.

[0083] 15. The system of any preceding configuration, wherein the display driver circuitry includes a pixel circuit for each pixel of the pixel array.

[0084] 16. A system according to configuration 15, wherein the pixel circuit includes a pixel logic circuit system connected to at least one transistor and the transistor is connected to a pixel electrode of the pixel, and wherein the pixel logic circuit system includes a logic element that generates a digital value that is output to the transistor to activate or deactivate current entering the pixel electrode.

[0085] 17. The system of configuration 16, wherein the at least one transistor is electrically coupled to a voltage source or the DAC or the DAC and the pixel electrode, and optionally or preferably wherein the transistor is a field effect transistor.

[0086] 18. The system of configuration 17, wherein the transistor receives a bias voltage from the voltage source or to a DAC output and provides a drive current to a pixel electrode through fine control.

[0087] 19. A method of operating a display system, the method comprising the steps of:

[0088] receiving image frame data and commands from an image or data source, the image frame data comprising pixel intensity values for bit planes of an image frame;

[0089] Parsing the image frame data and commands;

[0090] determining a driving waveform having a pixel driving value and a pixel driving time interval for each bit plane of the image frame data;

[0091] Pixels in a pixel array are driven according to the drive waveform, wherein the intensity of the pixels varies for each bit plane according to the pixel drive value and the pixel drive time interval.

Claims

1. A display system for driving pixels of a pixel array, comprising: Display driver circuit system for: Receive commands; receiving image frame data, the image frame data comprising pixel intensities or brightness values of bit planes of an image frame or subframe; processing the image frame data and commands to determine, for at least one pixel in the pixel array, a pixel drive value and a pixel drive time interval for each of a plurality of bit planes, the pixel drive value and pixel drive time interval for each bit plane defining a drive waveform; as well as generating one or more commands corresponding to the drive waveform; as well as Display backplane circuit system, which is used for: receiving the one or more commands corresponding to the drive waveform; as well as The at least one pixel is driven according to the driving waveform, such that: The intensity or brightness value of each of the at least one pixel varies for each bit plane according to a combination of a corresponding pixel drive value and a corresponding pixel drive time interval.

2. The system according to claim 1, wherein: The display backplane comprises: A pixel driver circuit system includes a pixel circuit for each pixel in the pixel array, each pixel circuit includes a pixel logic circuit system connected to at least one transistor connected to a pixel electrode, the pixel logic circuit system includes a logic element, the logic element generates a digital value in response to the one or more commands corresponding to the drive waveform, the digital value is output to the at least one transistor to activate or deactivate current entering the pixel electrode, thereby driving the pixel according to the corresponding drive waveform.

3. The display system according to claim 1, further comprising a digital-to-analog converter driven by a register for converting a digital control word into a bias voltage to control a drive current of the pixel driver circuit system of all pixels.

4. The display system according to claim 3, wherein: The display backplane circuitry includes circuitry that provides both bit-plane digital data and the bias voltage to the pixel driver circuitry for driving all pixels of the pixel array.

5. The display system of claim 1 , further comprising a sequence memory for storing one or more programmable mappings that modify at least one of the pixel drive value and the pixel drive time interval based on at least one of desired performance, ambient lighting compensation, or temperature compensation. The display system according to claim 5 , wherein: The display driver circuitry converts at least one of the pixel drive values or the pixel drive time intervals of the image data according to the programmable mapping.

7. The display system according to claim 1, wherein: The image frame or sub-frame comprises a series of frame regions, each frame region comprises a plurality of bit planes, and each frame region has a different global bias and thus a different intensity value.

8. The display system according to claim 1, wherein: The pixel driving value includes a pixel driving voltage or a pixel driving current.

9. A display system for driving pixels of a pixel array, comprising: A display driver circuit system configured to: Receive image frame data including a plurality of frame regions, each frame region including: intensity values for the plurality of bit planes; and Global bias; and processing the image frame data to determine, for at least one pixel in the pixel array, a pixel driving value and a pixel driving time interval for each of the plurality of bit planes of at least one frame region corresponding to the at least one pixel; and The display backplane circuit system includes: A pixel driver circuit system comprises: a pixel circuit for driving the at least one pixel of the pixel array such that an intensity of the at least one pixel varies for each bit plane according to a corresponding pixel drive value and a corresponding pixel drive time interval.

10. The display system according to claim 9, wherein: The pixel driving value includes a pixel driving voltage or a pixel driving current.

11. The display system according to claim 9, further comprising: A digital-to-analog converter is driven by the register for converting a digital control word into a bias voltage to control a drive current of the pixel driver circuit system of all pixels of the pixel array.

12. The display system according to claim 11, wherein: The display backplane circuitry includes circuitry that provides both bit-plane digital data and the bias voltage to the pixel driver circuitry for driving all pixels of the pixel array.

13. The display system of claim 9 , further comprising a sequence memory for storing one or more programmable mappings that modify at least one of the pixel drive value and the pixel drive time interval based on at least one of desired performance, ambient lighting compensation, or temperature compensation.

14. The display system according to claim 13, wherein: The display driver circuitry converts at least one of the pixel drive value or the pixel drive time interval according to the programmable mapping.

Images