Display device

Abstract

The present disclosure relates to a display device. The display device includes: a substrate including a display area and a non-display area disposed to surround the display area; a plurality of pixels disposed in the display area of the substrate; a pad portion provided in the non-display area of the substrate and supplied with a selection signal; a connecting line disposed in the non-display area of the substrate, extending in the first direction, and connected to the pad portion; a selection signal pattern disposed in the non-display area of the substrate, extending in a second direction different from the first direction, and connected to the connection line; and a selection signal line provided to extend from the non-display area to the display area of the substrate, connected to the selection signal pattern, and configured to supply a selection signal supplied from the pad portion to the plurality of pixels.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0022545 filed on February 16, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present specification relates to a display device, and more particularly, to a display device capable of controlling a viewing angle. Background Art

[0004] With the development of technology in modern society, display devices are used to provide information to users in various ways. Display devices are included in electronic signs that transmit visual information in only one direction and various electronic devices that require higher technology to confirm user input and provide information in response to the confirmed input.

[0005] For example, a display device may be included in a vehicle to provide various information to the driver and passengers. However, the vehicle's display device must display content appropriately so as not to interfere with vehicle operation. For example, the display device must limit the display of content that could reduce driver attention while the vehicle is in operation. Summary of the Invention

[0006] An object to be achieved by this specification is to provide a display device capable of dividing a display panel into regions and capable of freely and selectively limiting a viewing angle for each of the regions.

[0007] Another object to be achieved by the present specification is to provide a display device capable of reducing a load on a selection signal line that transmits a selection signal for controlling a viewing angle of each area.

[0008] The objects of the present disclosure are not limited to the above-mentioned objects, and other objects not mentioned above may be clearly understood by those skilled in the art from the following description.

[0009] According to one aspect of the present disclosure, a display device is provided. The display device includes: a substrate including a display area and a non-display area arranged to surround the display area; a plurality of pixels arranged in the display area of the substrate; a pad portion arranged in the non-display area of the substrate and supplied with a selection signal; a connection line arranged in the non-display area of the substrate, extending along a first direction, and connected to the pad portion; a selection signal pattern arranged in the non-display area of the substrate, extending in a second direction different from the first direction, and connected to the connection line; and a selection signal line arranged to extend from the non-display area of the substrate to the display area, connected to the selection signal pattern, and configured to provide the selection signal supplied from the pad portion to the plurality of pixels.

[0010] According to one aspect of the present disclosure, a display device is provided. The display device includes: a substrate including a display area and a non-display area arranged to surround the display area; a plurality of pixels arranged in the display area of the substrate; a pad portion arranged in the non-display area of the substrate and supplied with a selection signal; a connection line arranged in the non-display area of the substrate, extending along a first direction and connected to the pad portion; a selection signal pattern arranged in the non-display area of the substrate, extending in a second direction different from the first direction and connected to the connection line; and a plurality of selection signal lines arranged to extend from the non-display area of the substrate to the display area, connected to the selection signal pattern, and configured to provide the selection signal supplied from the pad portion to the plurality of pixels, wherein the plurality of selection signal lines are arranged for each pixel row in the display area.

[0011] According to one aspect of the present disclosure, a display device is provided. The display device includes a display area and a non-display area arranged to surround the display area, wherein: the display area includes a plurality of pixels; each of the plurality of pixels includes: a first light-emitting element that emits light of a first color; a first optical member arranged on the first light-emitting element to provide a first viewing angle range; a first transistor that supplies a first drive current for emitting light from the first transistor to the first light-emitting element; a second light-emitting element that emits light of the first color; a second optical member arranged on the second light-emitting element to provide a second viewing angle range wider than the first viewing angle range; and a second transistor that supplies a second drive current for emitting light from the second transistor to the second light-emitting element; wherein the first transistor and the second transistor are controlled by different selection signal lines. In one example, the display area includes a plurality of sub-display areas arranged along a second direction; the non-display area includes a plurality of selection signal pattern pairs corresponding to the plurality of sub-display areas; the first selection signal pattern and the second selection signal pattern in each of the plurality of selection signal pattern pairs are separated from each other along a first direction perpendicular to the second direction; and for a first selection signal pattern pair in the plurality of selection signal pattern pairs and a pixel in the first sub-display area corresponding to the first selection signal pattern pair, the first selection signal pattern in the first selection signal pattern pair is configured to receive a first selection signal and is connected to the first transistor of the pixel via a first selection signal line to control whether the first light-emitting element of the pixel emits light based on the first selection signal; and the second selection signal pattern in the first selection signal pattern pair is configured to receive a second selection signal and is connected to the second transistor of the pixel via a second selection signal line to control whether the second light-emitting element of the pixel emits light based on the second selection signal.

[0012] According to another aspect of the present disclosure, a display device is provided. The display device includes a display area and a non-display area arranged to surround the display area, and includes: a plurality of pixels arranged in the display area; a pad portion arranged in the non-display area and configured to receive a selection signal; a selection signal pattern arranged in the non-display area and connected to the pad portion; and a selection signal line connecting the selection signal pattern and the plurality of pixels to provide a selection signal to the plurality of pixels.

[0013] Additional details of exemplary embodiments are included in the detailed description and accompanying drawings.

[0014] According to the present specification, the display panel can be divided into areas, and the driving modes of the areas can be independently controlled so that each of the areas can operate in a first mode of providing content with a wide viewing angle, or each of the areas can operate in a second mode of providing content with a narrow viewing angle.

[0015] According to the present specification, the load of the selection signal line can be reduced by the selection signal pattern connected to the selection signal line that transmits the selection signal for controlling the viewing angle of each of the areas.

[0016] The effects according to the present disclosure are not limited to those exemplified above, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0018] Figure 1 is an exemplary diagram illustrating a display device according to an embodiment of the present specification;

[0019] Figure 2 is a functional block diagram of a display device according to an embodiment of the present specification;

[0020] Figure 3 is a circuit diagram illustrating an example of a pixel circuit of a display device according to an embodiment of this specification;

[0021] Figure 4 is a circuit diagram illustrating an example of a pixel circuit of a display device according to an embodiment of this specification;

[0022] Figure 5A and Figure 5B Is used to illustrate Figure 4 Waveform diagram of the pixel circuit in;

[0023] Figure 6 and Figure 7 is a cross-sectional view of a display device according to an embodiment of the present specification;

[0024] Figure 8 is a top plan view schematically showing a display device according to an embodiment of the present specification;

[0025] Figure 9 is a top plan view of a display device according to an embodiment of the present specification;

[0026] Figure 10 is an equivalent circuit diagram of a display device according to an embodiment of this specification; and

[0027] Figure 11 is a top plan view of a display device according to another embodiment of the present specification. DETAILED DESCRIPTION

[0028] The advantages and features of the present disclosure and methods for achieving these advantages and features will be clear by referring to the exemplary embodiments described in detail below in conjunction with the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only as examples so that those skilled in the art can fully understand the disclosure and scope of the present disclosure.

[0029] The shapes, sizes, ratios, angles, numbers, etc. used to describe the exemplary embodiments of the present disclosure shown in the accompanying drawings are merely examples, and the present disclosure is not limited thereto. Throughout the specification, similar reference numerals generally represent similar elements. In addition, in the following description of the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including," "having," and "consisting of" used in this article are generally intended to allow the addition of other components, unless these terms are used together with the term "only." Any reference to the singular may include the plural, unless otherwise expressly provided.

[0030] Even if not explicitly stated, the components are interpreted as including the ordinary error range.

[0031] When terms such as "on," "above," "below," and "beside" are used to describe the positional relationship between two parts, one or more parts may be located between the two parts, unless these terms are used together with the terms "immediately" or "directly."

[0032] When an element or layer is referred to as being “on” another element or layer, the other layer or element can be directly on or directly between the other element.

[0033] Although the terms "first," "second," and the like are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component mentioned below may be the second component in the technical concept of the present disclosure.

[0034] Like reference numerals generally refer to like elements throughout the specification.

[0035] The size and thickness of each component shown in the drawings are illustrated for convenience of description, and the present disclosure is not limited to the size and thickness of the illustrated components.

[0036] The features of the various embodiments of the present disclosure may be partially or completely dependent on or combined with each other, and may be technically interlocked and operated in various ways, and the embodiments may be performed independently of each other or in association with each other.

[0037] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0038] Figure 1 is an exemplary diagram illustrating a display device according to an embodiment of the present specification.

[0039] Reference Figure 1 The display device 100 may be provided on at least a portion of a dashboard of a vehicle. The dashboard of a vehicle may include a configuration provided in front of a front seat (e.g., a driver's seat or a passenger seat) of the vehicle. For example, the dashboard of a vehicle may be equipped with input configurations for operating various functions within the vehicle (e.g., air conditioning, audio system, and navigation system).

[0040] The display device 100 may be provided on a dashboard of a vehicle and may function as an input unit for manipulating at least some of the various functions of the vehicle. The display device 100 may provide various types of information related to the vehicle, such as driving information of the vehicle (e.g., the current speed, remaining fuel level, and travel distance of the vehicle), information about components of the vehicle (e.g., the degree of damage to the vehicle's tires), and the like.

[0041] The display device 100 can be arranged across the driver's seat and the passenger seat, which are set as the front seats of the vehicle. Users of the display device 100 can include the driver of the vehicle and a fellow passenger sitting in the passenger seat. Both the driver and fellow passenger in the vehicle can use the display device 100.

[0042] Figure 1 Only a portion of the display device 100 may be shown. Figure 1 The display device 100 shown in FIG can be shown as a display panel among various components included in the display device 100. Specifically, for example, Figure 1 The display device 100 shown in FIG. 1 may be shown as at least a portion of a display area and at least a portion of a non-display area of a display panel. Figure 1 The components shown in FIG. 1 may be installed in a vehicle (or at least a portion of a vehicle).

[0043] Figure 2 This is a functional block diagram of a display device according to an embodiment of this specification.

[0044] An electroluminescent display device may be used as the display device according to the embodiment of the present specification. An organic light emitting diode display device, a quantum dot light emitting diode display device, or an inorganic light emitting diode display device may be used as the electroluminescent display device.

[0045] Reference Figure 2, the display device 100 may include a display panel PN, a data driving circuit DD, a gate driving circuit GD, and a timing controller TD.

[0046] The display panel PN may generate an image to be provided to the user. For example, the display panel PN may generate and display an image to be provided to the user through a plurality of pixels PX provided with pixel circuits.

[0047] The data driving circuit DD, the gate driving circuit GD, and the timing controller TD may provide signals for operating the pixels PX through signal lines. For example, the signal lines for providing signals for operating the pixels PX may include a plurality of data lines DL and a plurality of gate lines GL.

[0048] The plurality of data lines DL may include a plurality of lines arranged in a column direction and connected to the pixels PX arranged in one column direction. The plurality of gate lines GL may include a plurality of lines arranged in a row direction and connected to the pixels PX arranged in one row direction.

[0049] In some cases, the display device 100 may further include a power supply unit. In this case, a signal for operating the pixel PX may be provided via a power line connecting the power supply unit and the display panel PN. Depending on the embodiment, the power supply unit may provide power to the data drive circuit DD and the gate drive circuit GD. The data drive circuit DD and the gate drive circuit GD may operate based on the power supplied by the power supply unit.

[0050] For example, the data driving circuit DD may apply data signals to the pixels PX through a plurality of data lines DL, the gate driving circuit GD may apply gate signals to the pixels PX through a plurality of gate lines GL, and the power supply unit may supply power voltage to the pixels PX through a power voltage supply line.

[0051] The timing controller TD may control the data driving circuit DD and the gate driving circuit GD. For example, the timing controller TD may realign digital video data input from the outside to adapt to the resolution of the display panel PN and supply the video data to the data driving circuit DD.

[0052] The data driving circuit DD may convert digital video data input from the timing controller TD into analog data voltages based on a data control signal and supply the analog data voltages to the plurality of data lines DL.

[0053] The gate drive circuit GD can generate scan signals and light-emitting signals in response to gate control signals. For example, the gate drive circuit GD may include a scan driver and a light-emitting signal driver. The scan driver can generate scan signals for operating at least one scan line connected to each pixel row in a row-sequential manner and supply the scan signals to the scan lines. The light-emitting signal driver can generate light-emitting signals for operating at least one light-emitting signal line connected to each pixel row in a row-sequential manner and supply the light-emitting signals to the light-emitting signal lines.

[0054] According to an embodiment, the gate driving circuit GD may be provided on the display panel PN in a gate-in-panel (GIP) manner. For example, the gate driving circuit GD may be divided into a plurality of gate driving circuits and respectively provided on at least two side surfaces of the display panel PN.

[0055] The display panel PN may include a display area and a non-display area configured to surround the display area.

[0056] The display area of the display panel PN may include a plurality of pixels PX arranged in row and column directions. For example, the plurality of pixels PX may be arranged in an area where a plurality of data lines DL and a plurality of gate lines GL intersect.

[0057] Multiple pixels PX can emit light beams of different colors. For example, multiple pixels PX can each realize any one of three colors, such as blue, red, and green. In addition, three pixels PX adjacent to each other in the row direction can respectively realize blue, red, and green. However, this specification is not limited to this. In some cases, the pixel PX can also realize a specific color, such as white.

[0058] Among the pixels PX, a pixel for realizing blue may be referred to as a blue pixel, a pixel for realizing red may be referred to as a red pixel, and a pixel for realizing green may be referred to as a green pixel. Meanwhile, according to an embodiment, three pixels PX adjacent to each other in the row direction and respectively realizing blue, red, and green may be referred to as sub-pixels for realizing a color. Furthermore, it may be assumed that the three sub-pixels for realizing a color constitute one pixel.

[0059] The plurality of pixels PX may each include a first light emitting element and a second light emitting element that emit light having the same color.

[0060] Each of the plurality of pixels PX may include a first optical member configured to refract light emitted from a first light-emitting element in a specific direction, and a second optical member configured to refract light emitted from a second light-emitting element in a specific direction. For example, the first optical member and the second optical member may each be implemented as a lens. However, embodiments of the present specification are not limited thereto.

[0061] For example, a first optical member may be provided in an optical region configured to define a first viewing angle by providing light within a first range, and a second optical member may be provided in an optical region configured to define a second viewing angle by providing light within a second range. The first range may correspond to a larger range than the second range. Thus, the first and second optical members may limit the viewing angle of each of the plurality of pixels PX.

[0062] The following will refer to Figure 6 and Figure 7 The first optical member and the second optical member are described in detail.

[0063] The non-display area may be provided along the periphery of the display area. Various components for operating the pixel circuit provided in the pixel PX may be provided in the non-display area. For example, at least a portion of the gate drive circuit GD may be provided in the non-display area. The non-display area may be referred to as a frame area.

[0064] When the display panel PN is used as a reference Figure 1 In the vehicle described above, the field of view of at least some areas of the display panel PN may need to be limited in response to user needs. For example, images displayed in the display area of the display panel PN that provide entertainment functions, seat information, etc. to fellow passengers seated in the passenger seat may obstruct the driver of the vehicle. Therefore, it may sometimes be necessary to limit the field of view of images displayed in corresponding areas in response to user needs.

[0065] Therefore, the pixels PX included in the display panel PN can each operate in the first mode or the second mode according to the driving mode. For example, in the case where the pixel PX operates in the first mode, the first light-emitting element included in the pixel PX can emit light in response to the selection signal, and the light emitted from the first light-emitting element is provided within a first range through the first optical component, so that a first viewing angle, for example, a wide viewing angle, can be defined. In addition, in the case where the pixel PX operates in the second mode, the second light-emitting element included in the pixel PX can emit light in response to the selection signal, and the light emitted from the second light-emitting element can be provided within a second range through the second optical component, so that a second viewing angle, for example, a narrow viewing angle, can be defined. In this case, the first mode can correspond to a mode in which the corresponding pixel PX is controlled in a wide field of view mode (shared mode), and the second mode can correspond to a mode in which the corresponding pixel PX is operated in a narrow field of view mode (private mode).

[0066] At the same time, the display device 100 can divide the display panel PN into regions and independently control the driving mode of each region. For example, the display device 100 can independently operate multiple regions of the display panel PN in a first mode for providing content at a wide viewing angle or in a second mode for providing content at a narrow viewing angle. In this case, in order to control the multiple pixels PX respectively arranged in multiple regions of the display panel PN under the same driving mode, it is necessary to provide the same selection signal to the multiple pixels PX arranged in the corresponding regions. Therefore, the same selection signal line can be connected to the multiple pixels PX arranged in the corresponding regions and can be arranged in the corresponding regions. In this case, since the selection signal is provided to the multiple pixels PX arranged in all corresponding regions through a single line, RC delay may occur.

[0067] Therefore, the display device 100 according to the embodiment of the present specification can minimize the RC delay of the selection signal line for providing the selection signal through the selection signal pattern connected to the selection signal line. Figures 8 to 11 Describe in detail.

[0068] Figure 3 is a circuit diagram illustrating an example of a pixel circuit of a display device according to an embodiment of this specification.

[0069] at the same time, Figure 3 The first pixel circuit PC1 shown in FIG. Figure 2 Each of the plurality of pixels PX included in the display device 100 described herein corresponds to one embodiment of a pixel circuit.

[0070] Reference Figure 3The first pixel circuit PC1 may include a driving transistor DT, a switching transistor ST, a first capacitor C1, a first transistor T1, a second transistor T2, and a plurality of light emitting elements ED1 and ED2.

[0071] The driving transistor DT and the first capacitor C1 may be connected to the switching transistor ST. A first electrode of the driving transistor DT may be connected to a high potential power line configured to provide a high potential power voltage VDD.

[0072] The switching transistor ST may be connected to the gate line GL and may be supplied with a gate signal. The switching transistor ST may be turned on or off by the gate signal. A first electrode of the switching transistor ST may be connected to the data line DL. In this case, a data voltage may be supplied to the gate electrode of the driving transistor DT through the switching transistor ST when the switching transistor ST is turned on.

[0073] The first capacitor C1 may be provided between the gate electrode and the second electrode of the driving transistor DT. The first capacitor C1 may maintain a signal applied to the gate electrode of the driving transistor DT, for example, maintain a data voltage for one frame.

[0074] The first transistor T1 may generate a current path for a first driving current flowing through the first light emitting element ED1 , and the second transistor T2 may generate a current path for a second driving current flowing through the second light emitting element ED2 .

[0075] The first transistor T1 can be disposed between the drive transistor DT and the first light-emitting element ED1, and the gate electrode of the first transistor T1 can be connected to a first selection signal line configured to provide a first selection signal Ss. When the pixel PX to which the first pixel circuit PC1 is applied operates in the first mode, i.e., the wide field mode, the first selection signal Ss can be supplied to the gate electrode of the first transistor T1, turning on the first transistor T1. This forms a current path for the first drive current flowing through the first light-emitting element ED1, allowing the first light-emitting element ED1 to emit light. The first transistor T1 can also be referred to as a first emission control transistor configured to control the light emitted by the first light-emitting element ED1.

[0076] The second transistor T2 can be disposed between the drive transistor DT and the second light-emitting element ED2, and the gate electrode of the second transistor T2 can be connected to a second selection signal line configured to provide a second selection signal Ps. When the pixel PX to which the first pixel circuit PC1 is applied operates in the second mode, i.e., the narrow field of view mode, the second selection signal Ps can be supplied to the gate electrode of the second transistor T2, turning on the second transistor T2. This forms a current path for the second drive current to flow through the second light-emitting element ED2, allowing the second light-emitting element ED2 to emit light. The second transistor T2 can also be referred to as a second emission control transistor configured to control the light emitted by the second light-emitting element ED2.

[0077] The first light-emitting element ED1 may be connected between the first transistor T1 and a low-potential power line, the first transistor T1 being turned on or off by a first selection signal Ss, and the low-potential power line being configured to provide a low-potential power voltage VSS. The second light-emitting element ED2 may be connected between the second transistor T2 and the low-potential power line, the second transistor T2 being turned on or off by a second selection signal Ps, and the low-potential power line being configured to provide a low-potential power voltage VSS.

[0078] In this case, the first light-emitting element ED1 or the second light-emitting element ED2 can be connected to another component of the first pixel circuit PC1, such as the driving transistor DT, via the first transistor T1 or the second transistor T2, which is turned on according to the driving mode. For example, the first light-emitting element ED1 can be connected to the driving transistor DT via the first transistor T1, which is turned on in the first mode, i.e., the wide field of view mode, and the first light-emitting element ED1 provides light at a wide viewing angle, i.e., the first viewing angle, by a first driving current. Alternatively, the second light-emitting element ED2 can be connected to the driving transistor DT via the second transistor T2, which is turned on in the second mode, i.e., the narrow field of view mode, and the second light-emitting element ED2 provides light at a narrow viewing angle, i.e., the second viewing angle, by a second driving current. In this case, the driving mode can be determined based on a condition specified by user input or pre-specified.

[0079] Figure 3 The plurality of transistors DT, ST, T1, and T2 in the transistor may include at least one of an oxide semiconductor such as amorphous silicon, polycrystalline silicon, and IGZO. The first electrode or the second electrode of the transistor may be a source electrode or a drain electrode. For example, the first electrode may be a source electrode, or the second electrode may be a drain electrode. As another example, the first electrode may be a drain electrode, and the second electrode may be a source electrode.

[0080] Figure 4is a circuit diagram illustrating an example of a pixel circuit of a display device according to an embodiment of this specification.

[0081] at the same time, Figure 4 The second pixel circuit PC2 shown in FIG. Figure 2 Each of the plurality of pixels PX included in the display device 100 described herein corresponds to another embodiment of a pixel circuit.

[0082] Reference Figure 4 , at least some of the plurality of transistors included in the second pixel circuit PC2 may each be an n-type transistor or a p-type transistor. In the case of a p-type transistor, a low-level voltage of each of the drive signals may mean a voltage that turns on the TFT, and a high-level voltage of each of the drive signals may mean a voltage that turns off the TFT.

[0083] In this case, the low-level voltage may correspond to a pre-specified voltage lower than the high-level voltage. For example, the low-level voltage may include a voltage corresponding to a range of -8V to -12V. The high-level voltage may correspond to a pre-specified voltage higher than the low-level voltage. For example, the high-level voltage may include a voltage corresponding to a range of 12V to 16V. Depending on the embodiment, the low-level voltage may have a smaller value than the high-level voltage.

[0084] The second pixel circuit PC2 may include a driving transistor DT, a plurality of switching transistors ST1 , ST2 , ST3 , ST4 , and ST5 , a second capacitor C2 , a first transistor T1 , a second transistor T2 , and a plurality of light emitting elements ED1 and ED2 .

[0085] The driving transistor DT can control the driving current applied to the first light emitting element ED1 and the second light emitting element ED2 according to the source-gate voltage. The driving transistor DT may include a source electrode connected to a high potential power line providing a high potential power voltage VDD, a gate electrode connected to a second node N2, and a drain electrode connected to a third node N3.

[0086] The first switching transistor ST1 can apply a data voltage Vdata from the data line DL to the first node N1. The first switching transistor ST1 may include a source electrode connected to the data line DL, a drain electrode connected to the first node N1, and a gate electrode connected to a first scan signal line to which a first scan signal SCAN1 is applied. The first switching transistor ST1 can be turned on or off by the first scan signal SCAN1. Therefore, the first switching transistor ST1 can apply the data voltage Vdata from the data line DL to the first node N1 in response to the first scan signal SCAN1 being at a low level, i.e., an on-level.

[0087] The second switching transistor ST2 can diode-connect the gate electrode and drain electrode of the driving transistor DT. The second switching transistor ST2 may include a drain electrode connected to the second node N2, a source electrode connected to the third node N3, and a gate electrode connected to the second scan signal line to which the second scan signal SCAN2 is applied. The second switching transistor ST2 can be turned on or off by the second scan signal SCAN2. Therefore, the second switching transistor ST2 can diode-connect the gate electrode and drain electrode of the driving transistor DT in response to the second scan signal SCAN2 at a low level, i.e., an on-level.

[0088] The third switching transistor ST3 can apply a reference voltage Vref to the first node N1. The third switching transistor ST3 may include a source electrode connected to a reference voltage line configured to provide the reference voltage Vref, a drain electrode connected to the first node N1, and a gate electrode connected to a light emitting signal line to which the light emitting signal EM is applied. The third switching transistor ST3 can be turned on or off by the light emitting signal EM. Therefore, the third switching transistor ST3 can transmit the reference voltage Vref to the first node N1 in response to the light emitting signal EM being at a low level, i.e., an on-level.

[0089] The fourth switching transistor ST4 can apply a reference voltage Vref to the anode electrode of the first light-emitting element ED1. The fourth switching transistor ST4 may include a source electrode connected to a reference voltage line configured to provide the reference voltage Vref, a drain electrode connected to the anode electrode of the first light-emitting element ED1, and a gate electrode connected to a second scan signal line to which the second scan signal SCAN2 is applied. The fourth switching transistor ST4 can be turned on or off by the second scan signal SCAN2. Therefore, the fourth switching transistor ST4 can apply the reference voltage Vref to the anode electrode of the first light-emitting element ED1 in response to the second scan signal SCAN2 being at a low level, i.e., an on-level.

[0090] The fifth switching transistor ST5 can apply a reference voltage Vref to the anode electrode of the second light-emitting element ED2. The fifth switching transistor ST5 may include a source electrode connected to a reference voltage line configured to provide the reference voltage Vref, a drain electrode connected to the anode electrode of the second light-emitting element ED2, and a gate electrode connected to a second scan signal line to which the second scan signal SCAN2 is applied. The fifth switching transistor ST5 can be turned on or off by the second scan signal SCAN2. Therefore, the fifth switching transistor ST5 can apply the reference voltage Vref to the anode electrode of the second light-emitting element ED2 in response to the second scan signal SCAN2 being at a low level, i.e., an on-level.

[0091] The second capacitor C2 may include a first electrode connected to the first node N1 and a second electrode connected to the second node N2. One electrode of the second capacitor C2, for example, the second electrode, may be connected to the gate electrode of the drive transistor DT, and the other electrode of the second capacitor C2, for example, the first electrode, may be connected to the first switching transistor ST1. When either the first light-emitting element ED1 or the second light-emitting element ED2 emits light, the second capacitor C2 may store a predetermined voltage and maintain the predetermined voltage at the gate electrode of the drive transistor DT.

[0092] The first transistor T1 may generate a current path for a first driving current flowing through the first light emitting element ED1 , and the second transistor T2 may generate a current path for a second driving current flowing through the second light emitting element ED2 .

[0093] The first transistor T1 can be connected between the drive transistor DT and the first light-emitting element ED1, and the gate electrode of the first transistor T1 can be connected to a first selection signal line configured to provide a first selection signal Ss. When the pixel PX to which the second pixel circuit PC2 is applied operates in the first mode, i.e., the wide field mode, the first selection signal Ss can be supplied to the gate electrode of the first transistor T1, turning on the first transistor T1. As a result, a current path is formed for the first drive current to flow through the first light-emitting element ED1, allowing the first light-emitting element ED1 to emit light. The first transistor T1 can also be referred to as a first emission control transistor configured to control the light emission from the first light-emitting element ED1.

[0094] The second transistor T2 can be connected between the drive transistor DT and the second light-emitting element ED2, and the gate electrode of the second transistor T2 can be connected to a second selection signal line configured to provide a second selection signal Ps. When the pixel PX to which the second pixel circuit PC2 is applied operates in the second mode, i.e., the narrow field of view mode, the second selection signal Ps can be supplied to the gate electrode of the second transistor T2, turning on the second transistor T2. As a result, a current path for the second drive current to flow through the second light-emitting element ED2 is formed, allowing the second light-emitting element ED2 to emit light. The second transistor T2 can also be referred to as a second emission control transistor configured to control the light emission from the second light-emitting element ED2.

[0095] The first light-emitting element ED1 may be connected between the first transistor T1 and a low-potential power line, the first transistor T1 being turned on or off by a first selection signal Ss, and the low-potential power line being configured to provide a low-potential power voltage VSS. The second light-emitting element ED2 may be connected between the second transistor T2 and the low-potential power line, the second transistor T2 being turned on or off by a second selection signal Ps, and the low-potential power line being configured to provide a low-potential power voltage VSS.

[0096] In this case, the first light-emitting element ED1 or the second light-emitting element ED2 can be connected to another component of the second pixel circuit PC2, such as the driving transistor DT, via the first transistor T1 or the second transistor T2, which is turned on according to the driving mode. For example, the first light-emitting element ED1 can be connected to the driving transistor DT via the first transistor T1, which is turned on in the first mode, i.e., the wide field of view mode, and the first light-emitting element ED1 provides light at a wide viewing angle, i.e., the first viewing angle, by a first driving current. Alternatively, the second light-emitting element ED2 can be connected to the driving transistor DT via the second transistor T2, which is turned on in the second mode, i.e., the narrow field of view mode, and the second light-emitting element ED2 provides light at a narrow viewing angle, i.e., the second viewing angle, by a second driving current. In this case, the driving mode can be determined based on a condition specified by user input or pre-specified.

[0097] Figure 5A and Figure 5B Is used to illustrate Figure 4 Waveform diagram of the pixel circuit in .

[0098] at the same time, Figure 5A It is used to describe the application of reference Figure 4 The waveform diagram of an example in which the pixel PX of the pixel circuit is operated in the first mode is described, and Figure 5B It is used to describe the application of reference Figure 4 1 and 2 are waveform diagrams illustrating an example in which a pixel PX of a pixel circuit operates in the second mode.

[0099] Reference Figures 4 to 5B , only the first light emitting element ED1 can emit light in the first mode, and only the second light emitting element ED2 can emit light in the second mode. Figure 5A As shown, in the first mode, the second selection signal Ps for controlling light emission from the second light emitting element ED2 can be output only at a high level, ie, an off level, so that only the first light emitting element ED1 emits light. Figure 5BAs shown, in the second mode, the first selection signal Ss for controlling light emission from the first light emitting element ED1 can be output only at a high level, that is, an off level, so that only the second light emitting element ED2 emits light. Meanwhile, in this specification, a high level can be defined as a first level.

[0100] Specifically, we will first refer to Figure 4 and Figure 5A The first mode is described below. This first mode is a wide field of view mode. During the initialization period P1, a low-level second scan signal SCAN2, a low-level first select signal Ss, and a low-level emission signal EM may be output. The second switching transistor ST2, the fourth switching transistor ST4, and the fifth switching transistor ST5 may be turned on by the low-level second scan signal SCAN2, the low-level first select signal Ss, and the low-level emission signal EM. The first transistor T1 may be turned on by the low-level first select signal Ss, and the third switching transistor ST3 may be turned on by the low-level emission signal EM.

[0101] The first node N1 can be initialized to the reference voltage Vref via the turned-on third switching transistor ST3. The voltage of the anode electrode of the first light-emitting element ED1 can be initialized to the reference voltage Vref via the turned-on fourth switching transistor ST4, and the voltage of the anode electrode of the second light-emitting element ED2 can be initialized to the reference voltage Vref via the turned-on fifth switching transistor ST5. The driving transistor DT can be diode-connected via the turned-on second switching transistor ST2, and the gate and drain electrodes of the driving transistor DT can be short-circuited, so that the driving transistor DT can operate as a diode. The reference voltage Vref transmitted to the anode electrode of the first light-emitting element ED1 via the turned-on fourth switching transistor ST4 can be transmitted to the third node N3 and the second node N2 via the turned-on first transistor T1, so that the third node N3 and the second node N2 can be initialized to the reference voltage Vref.

[0102] Next, during the sampling period P2, a low-level first scan signal SCAN1 and a low-level second scan signal SCAN2 may be output, and a high-level first selection signal Ss may be output. When the high-level emission signal EM is output, the first switching transistor ST1 is turned on by the low-level first scan signal SCAN1 while the third switching transistor ST3 is turned on, so that the data voltage Vdata can be transmitted to the first node N1. The driving transistor DT is diode-connected via the turned-on second switching transistor ST2, and the voltage difference between the high-potential power voltage VDD and the threshold voltage can be sampled and supplied to the second node N2. Meanwhile, in this specification, a low level may be defined as a second level, and the second level may have a value smaller than the first level.

[0103] Meanwhile, during the sampling period P2 , the first transistor T1 may be turned off by the first selection signal Ss at a high level.

[0104] In addition, during the holding period P3, the first scan signal SCAN1 and the second scan signal SCAN2 may be output at a high level, and the first switching transistor ST1, the second switching transistor ST2, the fourth switching transistor ST4, and the fifth switching transistor ST5 may all be turned off. However, even if the first switching transistor ST1 is turned off, the data voltage Vdata input during the previous period (e.g., the sampling period P2) may be maintained by the second capacitor C2.

[0105] Finally, during the light-emission period P4, the first selection signal Ss at a low level and the light-emission signal EM at a low level may be output, and the second selection signal Ps at a high level may be output. The reference voltage Vref may be applied to the first node N1 via the third switching transistor ST3, which is turned on by the light-emission signal EM at a low level. The voltage of the first node N1 may be the voltage difference between the reference voltage Vref and the data voltage Vdata, and this voltage change may also be applied to the second node N2. The gate-source voltage of the driving transistor DT may be set to a value (Vdata-Vref+Vth) obtained by subtracting the reference voltage Vref from the data voltage Vdata and adding the data voltage Vdata, thereby controlling the first driving current.

[0106] Furthermore, the first drive current is supplied from the drive transistor DT to the first light-emitting element ED1 by means of the first transistor T1, which is turned on by the first select signal Ss at a low level, so that the first light-emitting element ED1 can emit light. However, the second select signal Ps is output at a high level, and the second transistor T2 is turned off, so that the second drive current is not transmitted from the drive transistor DT to the second light-emitting element ED2. Therefore, when the pixel PX operates in the first mode, the first drive current is applied only to the first light-emitting element ED1, so that only the first light-emitting element ED1 can emit light.

[0107] Next, we will refer to Figure 4 and Figure 5B The second mode is described below, which is the narrow field of view mode. The pixel circuit can also operate in the second mode in a manner substantially similar to the first mode, except that the first selection signal Ss and the second selection signal Ps are output in a manner opposite to the first mode, which is the wide field of view mode. That is, during the light-emitting period P4 in which the second light-emitting element ED2 emits light, the first selection signal Ss can be output only at a high level, i.e., an off-level, while the second selection signal Ps can be output at a low level, i.e., an on-level.

[0108] Specifically, during the initialization period P1, the first scan signal SCAN1 may be output at a high level, while the second scan signal SCAN2 may be output at a low level. Furthermore, the first select signal Ss may be output at a high level, while the second select signal Ps and the emission signal EM may be output at a low level. Therefore, the second switching transistor ST2, the fourth switching transistor ST4, and the fifth switching transistor ST5 may be turned on by the second scan signal SCAN2, the second transistor T2 may be turned on by the second select signal Ps, and the third switching transistor ST3 may be turned on by the emission signal EM.

[0109] The first node N1 can be initialized to a reference voltage Vref by means of the third switching transistor ST3 turned on by the emission signal EM, and the anode electrodes of the first and second light-emitting elements ED1 and ED2 can be initialized to the reference voltage Vref by means of the fourth and fifth switching transistors ST4 and ST5 turned on by the second scan signal SCAN2. The driving transistor DT can be diode-connected via the turned-on second switching transistor ST2 and operate as a diode. The reference voltage Vref transmitted to the anode electrode of the second light-emitting element ED2 via the turned-on fifth switching transistor ST5 can be transmitted to the third and second nodes N3 and N2 via the turned-on second transistor T2, thereby initializing the third and second nodes N3 and N2 to the reference voltage Vref.

[0110] Next, during the sampling period P2, the first scan signal SCAN1 at a low level and the second scan signal SCAN2 at a low level may be output, and the second selection signal Ps and the emission signal EM may be output from a low level to a high level. When the emission signal EM at a high level is output, the third switching transistor ST3 is turned off, and the first switching transistor ST1 is turned on by the first scan signal SCAN1 at a low level, so that the data voltage Vdata can be transmitted to the first node N1. In addition, the driving transistor DT is diode-connected via the turned-on second switching transistor ST2, and the voltage difference between the high-potential power voltage VDD and the threshold voltage can be sampled and supplied to the second node N2.

[0111] Meanwhile, during the sampling period P2 , the second transistor T2 may be turned off by the second selection signal Ps at a high level.

[0112] Finally, during the light-emission period P4, the second selection signal Ps at a low level and the light-emission signal EM at a low level may be output, and the first selection signal Ss at a high level may be output. The reference voltage Vref may be applied to the first node N1 via the third switching transistor ST3, which is turned on by the light-emission signal EM at a low level. The voltage of the first node N1 may be the voltage difference between the reference voltage Vref and the data voltage Vdata, and this voltage change may also be applied to the second node N2. The gate-source voltage of the driving transistor DT may be set to a value (Vdata-Vref+Vth) obtained by subtracting the reference voltage Vref from the data voltage Vdata and adding the data voltage Vdata, thereby controlling the second driving current.

[0113] Furthermore, the second drive current is supplied from the drive transistor DT to the second light-emitting element ED2 by means of the second transistor T2, which is turned on by the second select signal Ps at a low level, so that the second light-emitting element ED2 can emit light. However, the first select signal Ss is output at a high level, and the first transistor T1 is turned off, so that the first drive current is not transmitted from the drive transistor DT to the first light-emitting element ED1. Therefore, when the pixel PX operates in the second mode, the second drive current is applied only to the second light-emitting element ED2, so that only the second light-emitting element ED2 can emit light.

[0114] Figure 6 and Figure 7 is a cross-sectional view of a display device according to an embodiment of this specification.

[0115] Figure 6 shows a pixel in which the first optical member 161 is provided, and Figure 7 A pixel in which the second optical member 162 is disposed is shown.

[0116] Reference Figure 6 and Figure 7 The display device 100 according to an embodiment of the present specification may include a substrate 110, a buffer layer 111, a gate insulating layer 112, an interlayer insulating layer 113, a lower protective layer 114, an outer coating layer 115, a dam insulating layer 116, a first transistor T1, a second transistor T2, a first light-emitting element ED1, a second light-emitting element ED2, a first optical member 161, a second optical member 162, an optical member protective layer 170 and an encapsulation member 180.

[0117] The substrate 110 may include an insulating material. The substrate 110 may include a transparent material. For example, the substrate 110 may include glass or plastic.

[0118] A buffer layer 111 may be provided on the substrate 110. The buffer layer 111 may include an insulating material. For example, the buffer layer 111 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The buffer layer 111 may have a multilayer structure. For example, the buffer layer 111 may have a stacked structure including a layer made of silicon nitride (SiNx) and a layer made of silicon oxide (SiOx).

[0119] A buffer layer 111 may be located between the substrate 110 and the driving unit in each pixel PX. The buffer layer 111 may suppress contamination caused by the substrate 110 during the process of forming the driving unit. For example, the top surface of the substrate 110 facing the driving unit in each pixel PX may be covered by the buffer layer 111. The driving unit in each pixel PX may be located on the buffer layer 111.

[0120] A gate insulating layer 112 may be provided on the buffer layer 111. The gate insulating layer 112 may include an insulating material. For example, the gate insulating layer 112 may include an inorganic insulating material such as silicon oxide (SiO) and silicon nitride (SiN). The gate insulating layer 112 may include a material having a high dielectric constant. For example, the gate insulating layer 112 may include a high-K material such as hafnium oxide (HfO). The gate insulating layer 112 may have a multilayer structure.

[0121] The gate insulating layer 112 may extend between the semiconductor layers 121 and 221 and the gate electrodes 122 and 223 of the transistors T1 and T2. For example, the gate electrodes of the switching transistor and the driving transistor may be insulated from the semiconductor layers of the switching transistor and the driving transistor by the gate insulating layer 112. The gate insulating layer 112 may cover the semiconductor layer in each pixel in the pixel PX. The gate electrodes of the switching transistor and the driving transistor may be located on the gate insulating layer 112.

[0122] An interlayer insulating layer 113 may be provided on the gate insulating layer 112. The interlayer insulating layer 113 may include an insulating material. For example, the interlayer insulating layer 113 may include an inorganic insulating material such as silicon oxide (SiO) and silicon nitride (SiN). The interlayer insulating layer 113 may extend between the gate electrode and the source electrode of the driving transistor and the switching transistor, and between the gate electrode and the drain electrode. For example, the source electrode and the drain electrode of the driving transistor and the switching transistor may be insulated from the gate electrode by the interlayer insulating layer 113. The interlayer insulating layer 113 may cover the gate electrode of the switching transistor and the driving transistor. The source electrode and the drain electrode in each pixel in the pixel PX may be located on the interlayer insulating layer 113. The gate insulating layer 112 and the interlayer insulating layer 113 may expose the source region and the drain region of each semiconductor pattern in each pixel in the pixel PX.

[0123] A lower protective layer 114 may be provided on the interlayer insulating layer 113. The lower protective layer 114 may include an insulating material. For example, the lower protective layer 114 may include an inorganic insulating material such as silicon oxide (SiO) and silicon nitride (SiN). The lower protective layer 114 may suppress damage to the driving unit caused by external moisture and impact. The lower protective layer 114 may extend along the surface of the driving transistor and the surface of the switching transistor opposite to the substrate 110. The lower protective layer 114 may contact the interlayer insulating layer 113 outside the driving unit in each pixel in the pixel PX.

[0124] An overcoat layer 115 may be provided on the lower protective layer 114. The overcoat layer 115 may include an insulating material. The overcoat layer 115 may include a material different from that of the lower protective layer 114. For example, the overcoat layer 115 may include an organic insulating material. The overcoat layer 115 may eliminate a level difference caused by a driving unit in each pixel PX. For example, the top surface of the overcoat layer 115 opposite the element substrate 110 may be a flat surface.

[0125] A first transistor T1 and a second transistor T2 may be provided on the substrate 110. The first transistor T1 may be electrically connected between the drain electrode of the driving transistor DT and the first lower electrode 141 of the first light emitting element ED1. The second transistor T2 may be electrically connected between the drain electrode of the driving transistor DT and the second lower electrode 151 of the second light emitting element ED2.

[0126] The first transistor T1 may include a first semiconductor layer 121, a first gate electrode 122, a first source electrode 123, and a first drain electrode 124. The first transistor T1 may have the same structure as the switching transistor and the driving transistor. For example, the first semiconductor layer 121 may be located between the buffer layer 111 and the gate insulating layer 112, and the first gate electrode 122 may be located between the gate insulating layer 112 and the interlayer insulating layer 113. The first source electrode 123 and the first drain electrode 124 may be located between the interlayer insulating layer 113 and the lower protective layer 114. The first gate electrode 122 may overlap with the channel region of the first semiconductor layer 121. The first source electrode 123 may be electrically connected to the source region of the first semiconductor layer 121. The first drain electrode 124 may be electrically connected to the drain region of the first semiconductor layer 121.

[0127] The second transistor T2 may include a second semiconductor layer 221, a second gate electrode 223, a second source electrode 225, and a second drain electrode 227. For example, the second semiconductor layer 221 may be located on the same layer as the first semiconductor layer 121, the second gate electrode 223 may be located on the same layer as the first gate electrode 122, and the second source electrode 225 and the second drain electrode 227 may be located on the same layer as the first source electrode 123 and the first drain electrode 124.

[0128] The first light emitting element ED1 and the second light emitting element ED2 in each of the pixels PX may be disposed on the overcoat layer 115 in the corresponding pixel PX.

[0129] The first light emitting element ED1 may emit light having a specific color. For example, the first light emitting element ED1 may include a first lower electrode 141 , a first light emitting layer 142 , and a first upper electrode 143 sequentially stacked on the substrate 110 .

[0130] The first lower electrode 141 may include a conductive material. The first lower electrode 141 may include a material having a high reflectivity. For example, the first lower electrode 141 may include a metal such as aluminum (Al) and silver (Ag). The first lower electrode 141 may have a multilayer structure. For example, the first lower electrode 141 may have a structure in which a reflective electrode made of a metal is located between transparent electrodes made of a transparent conductive material such as ITO and IZO. The first lower electrode 141 may be electrically connected to the first drain electrode 124 of the first transistor T1 through a contact hole formed through the lower protective layer 114 and the overcoat layer 115.

[0131] The first light emitting layer 142 may generate light having a brightness corresponding to the voltage difference between the first lower electrode 141 and the first upper electrode 143. For example, the first light emitting layer 142 may include an emission material layer (EML) including a light emitting material. The light emitting material may include an organic material, an inorganic material, or a hybrid material.

[0132] The first light emitting layer 142 may have a multi-layer structure. For example, the first light emitting layer 142 may further include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0133] The first upper electrode 143 may include a conductive material. The first upper electrode 143 may include a material different from that of the first lower electrode 141. The transmittance of the first upper electrode 143 may be higher than the transmittance of the first lower electrode 141. For example, the first upper electrode 143 may be configured as a transparent electrode made of a transparent conductive material such as ITO and IZO. Therefore, in the display device 100 according to the embodiment of the present specification, light generated by the first light-emitting layer 142 can be emitted through the first upper electrode 143.

[0134] The second light-emitting element ED2 can realize the same color as the first light-emitting element ED1. The second light-emitting element ED2 can have the same structure as the first light-emitting element ED1. For example, the second light-emitting element ED2 may include a second lower electrode 151, a second light-emitting layer 152, and a second upper electrode 153 sequentially stacked on the substrate 110.

[0135] The second lower electrode 151 may correspond to the first lower electrode 141, the second light-emitting layer 152 may correspond to the first light-emitting layer 142, and the second upper electrode 153 may correspond to the first upper electrode 143. For example, the second lower electrode 151 may be formed for the second light-emitting element ED2 while having the same structure as the first lower electrode 141. The same applies to the second light-emitting layer 152 and the second upper electrode 153. For example, the first light-emitting element ED1 and the second light-emitting element ED2 may be formed to have the same structure. However, this specification is not limited to this. In some cases, the first light-emitting element ED1 and the second light-emitting element ED2 may be formed to be different from each other in at least some configurations.

[0136] The second light emitting layer 152 may be spaced apart from the first light emitting layer 142. Therefore, in the display device according to the embodiment of the present specification, light emission caused by leakage current may be suppressed.

[0137] According to an embodiment of the present specification, in the display device, only one of the first light emitting layer 142 and the second light emitting layer 152 may generate light according to a user's selection or a pre-specified condition.

[0138] The second lower electrode 151 in each pixel PX may be spaced apart from the first lower electrode 141 in the corresponding pixel PX. For example, in each pixel PX, a bank insulating layer 116 may be provided between the first lower electrode 141 and the second lower electrode 151. The bank insulating layer 116 may include an insulating material. For example, the bank insulating layer 116 may include an organic insulating material. The bank insulating layer 116 may include a material different from that of the overcoat layer 115.

[0139] The second lower electrode 151 in each pixel in the pixels PX can be insulated from the first lower electrode 141 in the corresponding pixel PX by the bank insulating layer 116. For example, the bank insulating layer 116 can cover the edge of the first lower electrode 141 and the edge of the second lower electrode 151 in each pixel in the pixels PX. Therefore, the display device 100 can provide the user with an image in the first optical area of the pixel PX where the first light-emitting element ED1 is located, or the display device 100 can provide the user with an image in the second optical area of the pixel PX where the second light-emitting element ED2 is located.

[0140] The first light-emitting layer 142 and the first upper electrode 143 of the first light-emitting element ED1 located in each pixel in the pixel PX can be stacked in the portion of the corresponding first lower electrode 141 exposed by the bank insulating layer 116. The second light-emitting layer 152 and the second upper electrode 153 of the second light-emitting element ED2 located in each pixel in the pixel PX can be stacked in the portion of the corresponding second lower electrode 151 exposed by the bank insulating layer 116. For example, in each pixel in the pixel PX, the bank insulating layer 116 can be divided into a first light-emitting region, in which light is emitted by the first light-emitting element ED1, and a second light-emitting region, in which light is emitted by the second light-emitting element ED2. In each pixel in the pixel PX, the size of the defined second light-emitting region can be smaller than the size of the defined first light-emitting region.

[0141] In each pixel within the pixels PX, the second upper electrode 153 may be electrically connected to the first upper electrode 143 within the corresponding pixel PX. For example, the voltage applied to the second upper electrode 153 of the second light-emitting element ED2 within each pixel within the pixels PX may be equal to the voltage applied to the first upper electrode 143 of the first light-emitting element ED1 within the corresponding pixel PX. The second upper electrode 153 within each pixel within the pixels PX may include the same material as the first upper electrode 143 within the corresponding pixel PX. For example, the second upper electrode 153 within each pixel within the pixels PX may be formed simultaneously with the first upper electrode 143 within the corresponding pixel PX. The second upper electrode 153 within each pixel within the pixels PX may extend over the bank insulating layer 116 and directly contact the first upper electrode 143 within the corresponding pixel PX. The brightness of the first optical area and the brightness of the second optical area within each pixel within the pixels PX may be controlled by the drive current generated within the corresponding pixel PX.

[0142] The encapsulation member 180 may be located on the first light-emitting element ED1 and the second light-emitting element ED2 in each pixel in the pixel PX. The encapsulation member 180 can suppress damage to the light-emitting elements ED1 and ED2 caused by moisture and impact from the outside. The encapsulation member 180 may have a multilayer structure. For example, the encapsulation member 180 may include a first encapsulation layer 181, a second encapsulation layer 182, and a third encapsulation layer 183 stacked in sequence. However, the present specification is not limited thereto. The first encapsulation layer 181, the second encapsulation layer 182, and the third encapsulation layer 183 may include an insulating material. The second encapsulation layer 182 may include a material different from that of the first encapsulation layer 181 and the third encapsulation layer 183. For example, the first encapsulation layer 181 and the third encapsulation layer 183 may be inorganic encapsulation layers including an inorganic insulating material, while the second encapsulation layer 182 may include an organic encapsulation layer including an organic insulating material. Therefore, damage to the light-emitting elements ED1 and ED2 of the display device 100 caused by moisture and impact from the outside can be more effectively suppressed.

[0143] The first optical member 161 and the second optical member 162 may be disposed on the packaging member 180 .

[0144] The first optical member 161 may be disposed above the first light-emitting element ED1. Light generated by the first light-emitting element ED1 in each pixel PX may be emitted through the first optical member 161 disposed in the first optical region of the corresponding pixel PX. The first optical member 161 may have a shape that allows light to pass unrestricted in at least one direction. For example, the planar shape of the first optical member 161 in each pixel PX may be a stripe extending in one direction.

[0145] In this case, the propagation direction of the corresponding light emitted from the first optical area in each pixel in the pixel PX may not be limited to one direction. For example, the content (or image) provided by the first optical area in each pixel in the pixel PX can be shared with people around the user who are adjacent to the user in one direction. Therefore, the content provided by the light emitted by the first optical member 161 can be provided within a first viewing angle range that has a larger viewing angle than the content provided by the light emitted by the second optical member 162. For example, the content provided by the light emitted by the first optical member 161 can be provided in a wide field of view mode (sharing mode).

[0146] The second light-emitting element ED2 may be disposed on the second optical member 162. Light generated by the second light-emitting element ED2 in each pixel PX may be emitted through the second optical member 162 disposed in the second optical region of the corresponding pixel PX. The second optical member 162 may limit the propagation direction of light passing through the second optical member 162 to one direction and / or another direction. For example, the planar shape of the second optical member 162 in each pixel PX may be circular.

[0147] In this case, the propagation direction of the light emitted from the second optical area in each pixel in the pixel PX can be limited to one direction and / or another direction. For example, the content (or image) provided by the second optical area in each pixel in the pixel PX may not be shared with people around the adjacent user. Therefore, the content provided by the light emitted by the second optical member 162 can be provided within a second viewing angle range that has a smaller viewing angle than the content provided by the light emitted by the first optical member 161. For example, the content provided by the light emitted by the second optical member 162 can be provided in a narrow field of view mode (privacy mode).

[0148] The first light-emitting region in each pixel PX may have a shape corresponding to the first optical member 161 in the corresponding pixel PX. For example, the planar shape of the first light-emitting region in each pixel PX may be a stripe extending in one direction. The first optical member 161 may have a larger size than the first light-emitting region in the corresponding pixel PX. Thus, the efficiency of light emitted from the first light-emitting region in the pixel PX can be improved.

[0149] The second light-emitting region in each pixel PX may have a shape corresponding to the second optical member 162 in the corresponding pixel PX. For example, the planar shape of the second light-emitting region in each pixel PX may be circular. The second optical member 162 may have a larger size than the second light-emitting region in the corresponding pixel PX. Thus, the efficiency of light emitted from the second light-emitting region in the pixel PX can be improved.

[0150] The optical member protection layer 170 may be located on the first optical member 161 and the second optical member 162 in the pixel PX. The optical member protection layer 170 may include an insulating material. For example, the optical member protection layer 170 may include an organic insulating material. The refractive index of the optical member protection layer 170 may be lower than the refractive index of the first optical member 161 and the refractive index of the second optical member 162 in each pixel PX. Therefore, in the display device 100 according to an embodiment of the present specification, light that has passed through the first optical member 161 and the second optical member 162 in each pixel PX is not reflected toward the substrate 110 due to the difference in refractive index with the optical member protection layer 170.

[0151] Figure 8 is a top plan view schematically illustrating a display device according to an embodiment of the present specification.

[0152] Meanwhile, for ease of description, hereinafter, the first direction X is shown as a vertical direction in a plan view, and the second direction Y is shown as a horizontal direction in a plan view. However, this is provided for illustrative purposes only. The first direction X and the second direction Y may be defined differently.

[0153] At the same time, for the convenience of description, Figure 8 Only the display panel PN, the plurality of connection films COF1 and COF2 , and the printed circuit board PCB among various constituent elements of the display device 100 are shown.

[0154] Reference Figure 8 , the display device 100 includes a plurality of connection films COF1 and COF2, at least one printed circuit board PCB, and a display panel PN.

[0155] The plurality of connection films COF1 and COF2 may be provided at one end of the display panel PN. For example, the plurality of connection films COF1 and COF2 may include a first connection film COF1 and a second connection film COF2 electrically connected to one end of the display panel PN. The plurality of connection films COF1 and COF2 may each be a flexible film. However, the present invention is not limited thereto.

[0156] at the same time, Figure 8 The display device 100 is shown to include two connection films, namely, a first connection film COF1 and a second connection film COF2. However, this is provided for illustrative purposes only, and the embodiments of this specification are not limited thereto. For example, the display device 100 may include one connection film or three or more connection films.

[0157] The multiple connection films COF1 and COF2 are each made by disposing various components on a flexible base film and are configured to supply signals to the multiple pixels PX and the driving circuit. The multiple connection films COF1 and COF2 can be electrically connected to the display panel PN. For example, the multiple connection films COF1 and COF2 can supply power voltage, data voltage Vdata, various types of signals, etc. to the multiple pixels PX and the driving circuit.

[0158] A data driving circuit DD, for example, a driver IC such as a data driver IC, may be provided on a plurality of connection films COF1 and COF2. The driver IC may correspond to a component configured to process data for displaying an image and to process a drive signal for processing the data. Depending on how the driver IC is installed, the driver IC may be provided in a manner such as a chip on glass (COG) method, a chip on film (COF) method, and a tape carrier package (TCP) method. For ease of description, a configuration has been described in which the driver IC is mounted on a plurality of connection films COF1 and COF2 by a chip on film method. However, the present specification is not limited thereto. In addition, the driver IC may be integrated with the timing controller TD and provided as a single chip.

[0159] The printed circuit board PCB may be electrically connected to the plurality of connection films COF1 and COF2. The printed circuit board PCB may supply signals to a driver IC mounted on the plurality of connection films COF1 and COF2. Various types of components for supplying various signals such as drive signals and data signals to the driver IC may be provided on the printed circuit board PCB.

[0160] at the same time, Figure 8 The display device 100 is shown to include one printed circuit board PCB. However, this is provided for illustration purposes only, and embodiments of the present specification are not limited thereto. For example, the display device 100 may include two or more printed circuit boards PCB.

[0161] The display panel PN may include a display area AA and a non-display area NA surrounding the display area AA. A plurality of pixels PX may be arranged in row and column directions, such as the second direction Y and the first direction X, in the display area AA of the display panel PN and display an image. Various components for operating pixel circuits provided in the pixels PX may be provided in the non-display area of the display panel PN.

[0162] The display area AA of the display panel PN may include a plurality of areas A1, A2, A3, and A4 extending in a column direction, e.g., a first direction X, and separated in a row direction, e.g., a second direction Y. For example, the display area AA may include a first area A1, a second area A2 adjacent to the first area A1 in the second direction Y, a third area A3 adjacent to the second area A2 in the second direction Y, and a fourth area A4 adjacent to the third area A3 in the second direction Y.

[0163] at the same time, Figure 8 It is shown that the display area AA is divided into four areas in the second direction Y. However, this is provided for illustration purposes only, and the present specification is not limited thereto. The display area AA may be divided into various areas.

[0164] Each of the multiple areas A1, A2, A3, and A4 can be an area in which multiple pixels PX are arranged, and in the multiple pixels PX, the same selection signal line is arranged in the corresponding area and the same selection signal is applied. For example, in the multiple pixels PX arranged in the first area A1 among the multiple areas A1, A2, A3, and A4, a first selection signal line and a second selection signal line can be connected in common. Therefore, the same first selection signal Ss and the same second selection signal Ps are provided to the multiple pixels PX arranged in the first area A1, so that the multiple pixels PX arranged in the first area A1 can be controlled in the same drive mode. Similarly, the multiple pixels PX arranged in the second area A2 can be controlled in the same drive mode, the multiple pixels PX arranged in the third area A3 can be controlled in the same drive mode, and the multiple pixels PX arranged in the fourth area A4 can be controlled in the same drive mode.

[0165] In addition, the multiple areas A1, A2, A3, and A4 of the display area AA can be independently controlled. For example, different selection signal lines can be set in the multiple areas A1, A2, A3, and A4 of the display area AA, so that the multiple areas A1, A2, A3, and A4 can be independently controlled. For example, when the display area AA is divided into four areas (e.g., the first area A1, the second area A2, the third area A3, and the fourth area A4), different first selection signal lines and different second selection signal lines can be set in the first area A1, the second area A2, the third area A3, and the fourth area A4, respectively, and the first selection signal Ss and the second selection signal Ps can be independently provided to the multiple pixels PX arranged in each area of the area. Therefore, the driving modes of the multiple areas A1, A2, A3, and A4 of the display area AA can be independently controlled.

[0166] At the same time, the multiple connection films COF1 and COF2 can each operate multiple areas adjacent to the multiple divided areas A1, A2, A3, and A4 of the display area AA. For example, the multiple connection films COF1 and COF2 can each operate two adjacent areas among the multiple divided areas A1, A2, A3, and A4 of the display area AA. For example, as described above, when the multiple connection films COF1 and COF2 include two connection films (i.e., a first connection film COF1 and a second connection film COF2) and the display area AA is divided into four areas (i.e., a first area A1, a second area A2, a third area A3, and a fourth area A4), the first connection film COF1 can provide power voltage, data voltage Vdata, various types of signals, etc. to the multiple pixels PX arranged in the first area A1 and the second area A2, and the second connection film COF2 can provide power voltage, data voltage Vdata, various types of signals, etc. to the multiple pixels PX arranged in the third area A3 and the fourth area A4. However, the present specification is not limited to this. The plurality of connection films COF1 and COF2 may respectively operate the plurality of divided areas A1, A2, A3, and A4 of the display area AA, or operate three or more adjacent areas among the plurality of areas A1, A2, A3, and A4.

[0167] Hereinafter, for the sake of convenience of description, the following configuration will be described, in which the multiple connecting films COF1 and COF2 include two connecting films, i.e., a first connecting film COF1 and a second connecting film COF2, the display area AA is divided into four areas, i.e., a first area A1, a second area A2, a third area A3 and a fourth area A4, and the first connecting film COF1 and the second connecting film COF2 each operate two adjacent areas among the multiple areas A1, A2, A3 and A4 of the display area AA.

[0168] Figure 9 is a top plan view of a display device according to an embodiment of this specification.

[0169] At the same time, for the convenience of description, Figure 9 , based on a plane defined in the first direction X and the second direction Y, a side of the display device 100 based on the first direction X is defined as an upper side or an upward side, a side of the display device 100 based on a direction opposite to the first direction X is defined as a lower side or a downward side, a side of the display device 100 based on the second direction Y is defined as a right side, and a side of the display device 100 based on a direction opposite to the second direction Y is defined as a left side.

[0170] Reference Figure 8 and Figure 9The display device 100 may include a substrate 110, a gate driving circuit GD, a plurality of pad portions PAD1 and PAD2, a plurality of power patterns PP1, PP2, and PP3, a data distribution circuit MUX, an anti-static portion ESD, an illumination inspection portion AP, a first selection signal pattern SSP1, a second selection signal pattern SSP2, and various types of signal lines.

[0171] The substrate 110 may include a display area AA and a non-display area NA disposed outside the display area AA. For example, the non-display area NA may be disposed to surround the display area AA.

[0172] Meanwhile, as described above, the display area AA may be divided into a plurality of areas, for example, a first area A1, a second area A2, a third area A3, and a fourth area A4. A plurality of pixels PX may be provided in the plurality of areas A1, A2, A3, and A4 included in the display area AA of the substrate 110. In this case, as shown in FIG. Figure 8 As described, the modes of the plurality of areas A1 , A2 , A3 , and A4 of the display area AA may be independently controlled.

[0173] Various components may be provided in the non-display area NA to operate the plurality of pixels PX included in the plurality of areas A1, A2, A3, and A4 of the display area AA. For example, a gate driving circuit GD, a plurality of pad portions PAD1 and PAD2, a plurality of power supply patterns PP1, PP2, and PP3, a data distribution circuit MUX, an anti-static portion ESD, an illumination inspection portion AP, a first selection signal pattern SSP1, a second selection signal pattern SSP2, and various types of signal lines may be provided in the non-display area NA of the substrate 110.

[0174] The gate driving circuit GD may supply gate signals to the plurality of pixels PX disposed in the plurality of areas A1, A2, A3, and A4 of the display area AA. For example, the gate driving circuit GD may supply gate signals in the form of a shift register.

[0175] The gate driving circuit GD may be provided in the non-display area NA of the substrate 110. For example, the gate driving circuit GD may be provided in the non-display area NA of the substrate 110 in a gate-in-panel (GIP) manner.

[0176] In addition, in the non-display area NA of the substrate 110, two gate drive circuits GD may be provided on opposite sides of the display area AA. That is, the two gate drive circuits GD may supply gate signals to the plurality of pixels PX provided in the display area AA in a dual-feed manner. However, this is provided for illustrative purposes only and the present specification is not limited thereto. The display device 100 may include only one gate drive circuit GD provided on one side of the display area AA.

[0177] The plurality of pad portions PAD1 and PAD2 may include: a plurality of data pads DP disposed at the lowermost end of the non-display area NA of the substrate 110 and configured to provide a data voltage Vdata; a plurality of signal pads SP1 and SP2 configured to provide a selection signal; and a plurality of power pads PD1, PD2, and PD3 configured to provide a power voltage to the plurality of power patterns PP1, PP2, and PP3. Meanwhile, the pad portion may be defined as a pad region in which various types of pads are disposed.

[0178] The plurality of pad portions PAD1 and PAD2 may be electrically connected to the reference Figure 8 The multiple connection films COF1 and COF2 described above are connected to each other and receive various types of signals and various types of power voltages. For example, in the case where the display device 100 includes two connection films (for example, the first connection film COF1 and the second connection film COF2 as described above), the multiple pad portions PAD1 and PAD2 may include a first pad portion PAD1 electrically connected to the first connection film COF1 and a second pad portion PAD2 electrically connected to the second connection film COF2. Therefore, the selection signal applied to the first area A1 and the second area A2 adjacent to each other in the multiple areas of the display area AA can be provided to the multiple signal pads SP1 and SP2 included in the first pad portion PAD1, and the selection signal applied to the third area A3 and the fourth area A4 adjacent to each other in the multiple areas of the display area AA can be provided to the multiple signal pads SP1 and SP2 included in the second pad portion PAD2.

[0179] Multiple power patterns PP1, PP2, and PP3 may be provided in the non-display area NA, receive power voltages from multiple power pads PD1, PD2, and PD3, and supply power voltages to multiple pixels PX provided in the display area AA. For example, the multiple power patterns PP1, PP2, and PP3 may include: a first power pattern PP1 configured to transmit a high-potential power voltage VDD to the multiple pixels PX; a second power pattern PP2 configured to transmit a low-potential power voltage VSS to the multiple pixels PX; and a third power pattern PP3 configured to transmit a reference voltage Vref to the multiple pixels PX. In this specification, the term "power pattern" may be changed to power lines.

[0180] The first power pattern PP1 may be disposed in the non-display area NA, that is, in the non-display area NA located above and / or below the display area AA. For example, the first power pattern PP1 may include a first-first power pattern PP1a, a first-second power pattern PP1b, and a first-third power pattern PP1c.

[0181] The first-first power pattern PP1a may be disposed in the non-display area NA, that is, in the non-display area NA located below the display area AA. For example, the first-first power pattern PP1a may be disposed in the non-display area NA between the display area AA and the plurality of pad portions PAD1 and PAD2.

[0182] The first-first power pattern PP1a may include a first portion extending in the second direction Y and a plurality of second portions extending from the first portion in a downward direction (eg, a direction opposite to the first direction X). The first portion and the plurality of second portions of the first-first power pattern PP1a may be integrated together.

[0183] The plurality of second portions of the first-first power pattern PP1a may be electrically connected to the plurality of first power pads PD1 included in the plurality of pad portions PAD1 and PAD2, respectively. Thus, the first-first power pattern PP1a may receive the high potential power voltage VDD from the first power pads PD1.

[0184] The first-second power pattern PP1b may be disposed in the non-display area NA, that is, in the non-display area NA below the display area AA. For example, the first-second power pattern PP1b may be disposed in the non-display area NA between the display area AA and the first-first power pattern PP1a.

[0185] The first-second power pattern PP1b may have a shape extending in the second direction Y. Meanwhile, although Figure 9 Although not shown, the first-second power patterns PP1b may be electrically connected to the first-first power patterns PP1a through a line extending at least in the first direction X. Thus, the first-second power patterns PP1b may receive the high-potential power voltage VDD.

[0186] The first to third power patterns PP1c may be provided in the non-display area NA, that is, in the non-display area NA located above the display area AA. The first to third power patterns PP1c may have a shape extending in the second direction Y. Meanwhile, although Figure 9 Although not shown, the first-third power patterns PP1c may be electrically connected to the first-first power patterns PP1a and / or the first-second power patterns PP1b through lines extending at least in the first direction X. Thus, the first-third power patterns PP1c may receive the high-potential power voltage VDD.

[0187] The first power pattern PP1 can transmit a high-potential power voltage VDD to a plurality of pixels PX disposed in the display area AA. For example, the high-potential power voltage VDD can be provided to the plurality of pixels PX disposed in the display area AA via a high-potential power line electrically connected to the first power pattern PP1. For example, the first-second power pattern PP1b disposed below the display area AA can provide the high-potential power voltage VDD to the plurality of pixels PX disposed in the lower region of the display area AA via the high-potential power line, and the first-third power pattern PP1c disposed above the display area AA can provide the high-potential power voltage VDD to the plurality of pixels PX disposed in the upper region of the display area AA via the high-potential power line. However, the present disclosure is not limited thereto.

[0188] The second power pattern PP2 may be disposed in the non-display area NA, that is, in the non-display area NA located above and / or below the display area AA. For example, the second power pattern PP2 may include a second-first power pattern PP2a, a second-second power pattern PP2b, and a second-third power pattern PP2c.

[0189] The second-first power pattern PP2a may be disposed in the non-display area NA, that is, in the non-display area NA below the display area AA. For example, the second-first power pattern PP2a may be disposed in the non-display area NA between the display area AA and the plurality of pad portions PAD1 and PAD2. For example, the second-first power pattern PP2a may be disposed between the first-first power pattern PP1a of the first power pattern PP1 and the plurality of pad portions PAD1 and PAD2.

[0190] According to this embodiment, the second power pattern PP2 may include a plurality of second-first power patterns PP2a. For example, the plurality of second-first power patterns PP2a may include a second-first power pattern PP2a electrically connected to at least one second power pad PD2 included in the first pad portion PAD1, a second-first power pattern PP2a electrically connected to at least one second power pad PD2 included in the first pad portion PAD1 and at least one second power pad PD2 included in the second pad portion PAD2, and a second-first power pattern PP2a electrically connected to at least one second power pad PD2 included in the second pad portion PAD2. However, the present specification is not limited thereto.

[0191] The plurality of second-first power patterns PP2a may each include a third portion extending in the second direction Y and a plurality of fourth portions extending from the third portion in a downward direction (e.g., a direction opposite to the first direction X). The third portion and the plurality of fourth portions of each second-first power pattern PP2a in the plurality of second-first power patterns PP2a may be integrated together.

[0192] The plurality of fourth portions of each of the plurality of second-first power patterns PP2a can be electrically connected to the plurality of second power pads PD2 included in the plurality of pad portions PAD1 and PAD2, respectively. Therefore, the plurality of second-first power patterns PP2a can each receive the low-potential power voltage VSS from the second power pads PD2.

[0193] The second-second power pattern PP2b may be disposed in the non-display area NA (i.e., the non-display area NA located below the display area AA). For example, the second-second power pattern PP2b may be disposed in the non-display area NA between the display area AA and the second-first power pattern PP2a. For example, the second-second power pattern PP2b may be disposed between the first-first power pattern PP1a and the first-second power pattern PP1b of the first power pattern PP1.

[0194] The second-second power pattern PP2b may have a shape extending in the second direction Y. Meanwhile, although Figure 9 Although not shown, the second-second power pattern PP2b may be electrically connected to at least one of the plurality of second-first power patterns PP2a through a line extending at least in the first direction X. Therefore, the second-second power pattern PP2b may receive the low-potential power voltage VSS.

[0195] The second-third power pattern PP2c may be provided in the non-display area NA (ie, the non-display area NA located above the display area AA). The second-third power pattern PP2c may have a shape extending in the second direction Y. Meanwhile, although Figure 9 Although not shown, the second-third power supply pattern PP2c may be electrically connected to at least one of the plurality of second-first power supply patterns PP2a and / or second-second power supply patterns PP2b through a line extending at least in the first direction X.

[0196] The second power pattern PP2 can transmit the low-potential power voltage VSS to the plurality of pixels PX disposed in the display area AA. For example, the low-potential power voltage VSS can be provided to the plurality of pixels PX disposed in the display area AA via a low-potential power line electrically connected to the second power pattern PP2. For example, the second-second power pattern PP2b disposed below the display area AA can provide the low-potential power voltage VSS to the plurality of pixels PX disposed in the lower region of the display area AA via the low-potential power line, and the second-third power pattern PP2c disposed above the display area AA can provide the low-potential power voltage VSS to the plurality of pixels PX disposed in the upper region of the display area AA via the low-potential power line. However, the present disclosure is not limited thereto.

[0197] The third power pattern PP3 may be disposed in the non-display area NA (ie, the non-display area NA located below the display area AA). For example, the third power pattern PP3 may include a third-first power pattern PP3a and a third-second power pattern PP3b.

[0198] The third-first power pattern PP3a may be disposed in the non-display area NA (i.e., the non-display area NA below the display area AA). For example, the third-first power pattern PP3a may be disposed in the non-display area NA between the display area AA and the plurality of pad portions PAD1 and PAD2. For example, the third-first power pattern PP3a may be disposed between the display area AA and the first-first power pattern PP1a of the first power pattern PP1.

[0199] The third-first power pattern PP3a may have a shape extending in the second direction Y. The third-first power pattern PP3a may be electrically connected to the plurality of third power pads PD3 included in the plurality of pad portions PAD1 and PAD2 via the plurality of power connection patterns CP1 and CP2. For example, the plurality of first power connection patterns CP1 may each be electrically connected to the third power pad PD3 included in each of the plurality of pad portions PAD1 and PAD2, one end of each of the plurality of second power connection patterns CP2 may be connected to each of the plurality of first power connection patterns CP1, and the other end of each of the plurality of second power connection patterns CP2 may be connected to the third-first power pattern PP3a. Therefore, the third-first power pattern PP3a may receive a reference voltage Vref from the third power pad PD3 via the plurality of power connection patterns CP1 and CP2.

[0200] The third-second power pattern PP3b may be disposed in the non-display area NA (i.e., the non-display area NA below the display area AA). For example, the third-second power pattern PP3b may be disposed in the non-display area NA between the display area AA and the third-first power pattern PP3a. For example, the third-second power pattern PP3b may be disposed between the display area AA and the first-second power pattern PP1b of the first power pattern PP1.

[0201] The third-second power pattern PP3b may have a shape extending in the second direction Y. Meanwhile, although Figure 9 Although not shown, the third-second power pattern PP3b may be electrically connected to the third-first power pattern PP3a through a line extending at least in the first direction X. Therefore, the third-second power pattern PP3b may receive the reference voltage Vref.

[0202] The third power pattern PP3 can transmit a reference voltage Vref to the plurality of pixels PX disposed in the display area AA. For example, the reference voltage Vref can be provided to the plurality of pixels PX disposed in the display area AA via a reference voltage line electrically connected to the third power pattern PP3. For example, the third-second power pattern PP3b can provide the reference voltage Vref to the plurality of pixels PX disposed in the display area AA via the reference voltage line. However, the present disclosure is not limited thereto.

[0203] According to an embodiment, the plurality of power patterns PP1, PP2, and PP3 may include a metal material having excellent conductivity for supplying power voltage, but the present specification is not limited thereto.

[0204] However, the shapes and arrangements of the plurality of power patterns PP1 , PP2 , and PP3 and the connection relationships therebetween are provided for illustration purposes only and may be variously modified according to the design of the display device 100 .

[0205] At the same time, as reference Figure 8 As described above, a data driving circuit DD, for example, a driving IC such as a data driver IC, may be provided on the plurality of connection films COF1 and COF2. The data driving circuit DD provided on the plurality of connection films COF1 and COF2 may provide a data voltage Vdata through a plurality of data pads DP included in the plurality of pad portions PAD1 and PAD2.

[0206] In addition, the plurality of data link lines DLL extending in the first direction X may be electrically connected to the plurality of data pads DP, respectively. Therefore, the plurality of data link lines DLL may each receive a data voltage Vdata.

[0207] The plurality of data link lines DLL may be each connected to a data distribution circuit MUX and electrically connected to one data line DL selected from a plurality of data lines DL disposed in the display area AA through the operation of the data distribution circuit MUX. This allows the plurality of data link lines DLL to each transmit a data voltage Vdata to the corresponding data line DL. Thus, the data voltage Vdata may be provided to the plurality of pixels PX disposed in the display area AA.

[0208] The data distribution circuit MUX can distribute the data voltage Vdata transmitted by the plurality of data link lines DLL to the plurality of data lines DL in a time-division manner. For example, the data distribution circuit MUX can electrically connect one data link line DLL among the plurality of data link lines DLL to each of the plurality of data lines DL arranged in the display area AA. For example, the data distribution circuit MUX can be implemented as a multiplexer. However, this specification is not limited thereto.

[0209] The data distribution circuit MUX may be provided in the non-display area NA (ie, the non-display area NA located below the display area AA).

[0210] The lighting inspection part AP may inspect whether the plurality of pixels PX provided in the display area AA are operating abnormally before shipment of the display device 100. For example, the lighting inspection part AP may include a plurality of lighting inspection switches for inspecting the automatic probe (A / P) by applying a data lighting inspection signal and a pattern lighting inspection signal to the plurality of pixels PX before shipment of the display device 100 to inspect whether the pixels PX are operating abnormally.

[0211] The lighting inspection portion AP may be disposed in the non-display area NA (i.e., the non-display area NA located below the display area AA). For example, the lighting inspection portion AP (e.g., the plurality of lighting inspection switches included in the lighting inspection portion AP) may be disposed in the non-display area NA remaining after a trimming process that removes the lighting inspection pad portion configured to provide data lighting inspection signals and / or pattern lighting inspection signals to the plurality of lighting inspection switches after performing a lighting inspection on the display device 100. However, this is provided for illustrative purposes only. The lighting inspection pad portion configured to provide data lighting inspection signals and / or pattern lighting inspection signals to the plurality of lighting inspection switches may remain in the non-display area NA of the display device 100 without being removed.

[0212] The anti-static portion ESD may discharge static electricity applied to the plurality of data lines DL and / or the plurality of selection signal lines SSL1 and SSL2 , thereby protecting the plurality of data lines DL and / or the plurality of selection signal lines SSL1 and SSL2 from static electricity.

[0213] The anti-static portion ESD may be disposed in the non-display area NA (ie, the non-display area NA located below the display area AA).

[0214] The following will refer to Figure 10 The data distribution circuit MUX, the illumination inspection part AP and the antistatic part ESD are described in detail.

[0215] A plurality of first signal pads SP1 and a plurality of second signal pads SP2 may be provided on the plurality of pad portions PAD1 and PAD2, respectively, and the plurality of first signal pads SP1 and the plurality of second signal pads SP2 may supply first selection signals Ss and second selection signals Ps to a plurality of pixels PX in corresponding areas A1, A2, A3, and A4 of the display area AA. For example, the plurality of first signal pads SP1 may include first-first signal pads SP1a and first-second signal pads SP1b provided on the first pad portion PAD1, and first-third signal pads SP1c and first-fourth signal pads SP1d provided on the second pad portion PAD2. Furthermore, the plurality of second signal pads SP2 may include second-first signal pads SP2a and second-second signal pads SP2b provided on the first pad portion PAD1, and second-third signal pads SP2c and second-fourth signal pads SP2d provided on the second pad portion PAD2.

[0216] For example, the first pad portion PAD1 may include a first-first signal pad SP1a supplied with a first selection signal Ss provided to multiple pixels PX set in the first area A1, a first-second signal pad SP1b supplied with a first selection signal Ss provided to multiple pixels PX set in the second area A2, a second-first signal pad SP2a supplied with a second selection signal Ps provided to multiple pixels PX set in the first area A1, and a second-second signal pad SP2b supplied with a second selection signal Ps provided to multiple pixels PX set in the second area A2.

[0217] In addition, the second pad portion PAD2 may include first-third signal pads SP1c supplied with a first selection signal Ss provided to multiple pixels PX set in the third area A3, first-fourth signal pads SP1d supplied with a first selection signal Ss provided to multiple pixels PX set in the fourth area A4, second-third signal pads SP2c supplied with a second selection signal Ps provided to multiple pixels PX set in the third area A3, and second-fourth signal pads SP2d supplied with a second selection signal Ps provided to multiple pixels PX set in the fourth area A4.

[0218] A plurality of first connection lines CLL1 and a plurality of second connection lines CLL2 may be disposed in the non-display area NA and extend in the first direction X.

[0219] One end of each of the plurality of first connection lines CLL1 may be electrically connected to a corresponding first signal pad among the plurality of first signal pads SP1 disposed on the plurality of pad portions PAD1 and PAD2. Thus, the plurality of first connection lines CLL1 may receive the first selection signal Ss provided to the corresponding area of the display area AA.

[0220] For example, the plurality of first connection lines CLL1 may include: a first-first connection line CLL1a, which is disposed on the first pad portion PAD1 and electrically connected to the first-first signal pad SP1a supplied with a first selection signal Ss provided to the plurality of pixels PX provided in the first area A1; a first-second connection line CLL1b, which is disposed on the first pad portion PAD1 and electrically connected to the first-second signal pad SP1b supplied with a first selection signal Ss provided to the plurality of pixels PX provided in the second area A2; a first-third connection line CLL1c, which is disposed on the second pad portion PAD2 and electrically connected to the first-third signal pad SP1c supplied with a first selection signal Ss provided to the plurality of pixels PX provided in the third area A3; and a first-fourth connection line CLL1d, which is disposed on the second pad portion PAD2 and electrically connected to the first-fourth signal pad SP1d supplied with a first selection signal Ss provided to the plurality of pixels PX provided in the fourth area A4. Therefore, the first-first connection line CLL1a can receive the first selection signal Ss provided to the first area A1, the first-second connection line CLL1b can receive the first selection signal Ss provided to the second area A2, the first-third connection line CLL1c can receive the first selection signal Ss provided to the third area A3, and the first-fourth connection line CLL1d can receive the first selection signal Ss provided to the fourth area A4.

[0221] One end of each of the plurality of second connection lines CLL2 may be electrically connected to a corresponding second signal pad among the plurality of second signal pads SP2 disposed on the plurality of pad portions PAD1 and PAD2. Thus, the plurality of second connection lines CLL2 may receive the second selection signal Ps provided to the corresponding area of the display area AA.

[0222] For example, the plurality of second connection lines CLL2 may include: a second-first connection line CLL2a, which is arranged on the first pad portion PAD1 and electrically connected to the second-first signal pad SP2a supplied with the second selection signal Ps provided to the plurality of pixels PX provided in the first area A1; a second-second connection line CLL2b, which is arranged on the first pad portion PAD1 and electrically connected to the second-second signal pad SP2b supplied with the second selection signal Ps provided to the plurality of pixels PX provided in the second area A2; a second-third connection line CLL2c, which is arranged on the second pad portion PAD2 and electrically connected to the second-third signal pad SP2c supplied with the second selection signal Ps provided to the plurality of pixels PX provided in the third area A3; and a second-fourth connection line CLL2d, which is arranged on the second pad portion PAD2 and electrically connected to the second-fourth signal pad SP2d supplied with the second selection signal Ps provided to the plurality of pixels PX provided in the fourth area A4. Therefore, the second-first connection line CLL2a can receive the second selection signal Ps provided to the first area A1, the second-second connection line CLL2b can receive the second selection signal Ps provided to the second area A2, the second-third connection line CLL2c can receive the second selection signal Ps provided to the third area A3, and the second-fourth connection line CLL2d can receive the second selection signal Ps provided to the fourth area A4.

[0223] A plurality of first selection signal patterns SSP1 and a plurality of second selection signal patterns SSP2 may each be disposed in the non-display area NA and extend in the second direction Y. For example, a plurality of first selection signal patterns SSP1 and a plurality of second selection signal patterns SSP2 may each be disposed in the non-display area NA below the display area AA.

[0224] The planar shape of each of the plurality of first selection signal patterns SSP1 and the planar shape of each of the plurality of second selection signal patterns SSP2 may each have a stripe shape extending in one direction (e.g., the second direction Y). For example, the plurality of first selection signal patterns SSP1 and the plurality of second selection signal patterns SSP2 may each have a shape extending in the second direction Y and having a predetermined width in the first direction X. For example, the width of each of the plurality of first selection signal patterns SSP1 and the plurality of second selection signal patterns SSP2 in the first direction X may be greater than the width of each of the other signal lines (e.g., the plurality of selection signal lines SSL1 and SSL2 and / or the plurality of connection lines CLL1 and CLL2). However, the present specification is not limited thereto.

[0225] Each of the plurality of first selection signal patterns SSP1 may be disposed in the non-display area NA below the corresponding area of the display area AA, and each of the plurality of first selection signal patterns SSP1 may be electrically connected to the other end of the corresponding first connection line CLL1 among the plurality of first connection lines CLL1. Therefore, the first selection signal Ss provided to the corresponding area of the display area AA may be supplied to each of the plurality of first selection signal patterns SSP1 through the first connection line CLL1 electrically connected to the corresponding first selection signal pattern SSP1.

[0226] For example, the plurality of first selection signal patterns SSP1 may include a first-first selection signal pattern SSP1a disposed in the non-display area NA below the first area A1, a first-second selection signal pattern SSP1b disposed in the non-display area NA below the second area A2, a first-third selection signal pattern SSP1c disposed in the non-display area NA below the third area A3, and a first-fourth selection signal pattern SSP1d disposed in the non-display area NA below the fourth area A4.

[0227] The first-first selection signal pattern SSP1a may be electrically connected to the other end of the first-first connection line CLL1a, the first-second selection signal pattern SSP1b may be electrically connected to the other end of the first-second connection line CLL1b, the first-third selection signal pattern SSP1c may be electrically connected to the other end of the first-third connection line CLL1c, and the first-fourth selection signal pattern SSP1d may be electrically connected to the other end of the first-fourth connection line CLL1d. Therefore, the first selection signal Ss supplied to the first area A1 may be supplied to the first-first selection signal pattern SSP1a, the first selection signal Ss supplied to the second area A2 may be supplied to the first-second selection signal pattern SSP1b, the first selection signal Ss supplied to the third area A3 may be supplied to the first-third selection signal pattern SSP1c, and the first selection signal Ss supplied to the fourth area A4 may be supplied to the first-fourth selection signal pattern SSP1d.

[0228] In addition, each of the plurality of second selection signal patterns SSP2 may be disposed in the non-display area NA below the corresponding area of the display area AA, and the plurality of second selection signal patterns SSP2 may be electrically connected to the other ends of the corresponding second connection lines CLL2 of the plurality of second connection lines CLL2. Therefore, the second selection signal Ps provided to the corresponding area of the display area AA may be supplied to the plurality of second selection signal patterns SSP2 through the second connection lines CLL2 electrically connected to the corresponding second selection signal patterns SSP2.

[0229] For example, the plurality of second selection signal patterns SSP2 may include a second-first selection signal pattern SSP2a disposed in the non-display area NA below the first area A1, a second-second selection signal pattern SSP2b disposed in the non-display area NA below the second area A2, a second-third selection signal pattern SSP2c disposed in the non-display area NA below the third area A3, and a second-fourth selection signal pattern SSP2d disposed in the non-display area NA below the fourth area A4.

[0230] The second-first selection signal pattern SSP2a may be electrically connected to the other end of the second-first connection line CLL2a, the second-second selection signal pattern SSP2b may be electrically connected to the other end of the second-second connection line CLL2b, the second-third selection signal pattern SSP2c may be electrically connected to the other end of the second-third connection line CLL2c, and the second-fourth selection signal pattern SSP2d may be electrically connected to the other end of the second-fourth connection line CLL2d. Therefore, the second selection signal Ps supplied to the first area A1 may be supplied to the second-first selection signal pattern SSP2a, the second selection signal Ps supplied to the second area A2 may be supplied to the second-second selection signal pattern SSP2b, the second selection signal Ps supplied to the third area A3 may be supplied to the second-third selection signal pattern SSP2c, and the second selection signal Ps supplied to the fourth area A4 may be supplied to the second-fourth selection signal pattern SSP2d.

[0231] According to an embodiment, the plurality of first selection signal patterns SSP1 and the plurality of second selection signal patterns SSP2 may each include a metal material having excellent conductivity for providing a selection signal, but the present specification is not limited thereto.

[0232] The plurality of first selection signal lines SSL1 and the plurality of second selection signal lines SSL2 may each be disposed to extend from the non-display area NA to the display area AA.

[0233] One end of each of the plurality of first selection signal lines SSL1 may be electrically connected to a corresponding first selection signal pattern among the plurality of first selection signal patterns SSP1. Thus, the plurality of first selection signal lines SSL1 may receive the first selection signal Ss provided to corresponding areas of the display area AA.

[0234] For example, the plurality of first selection signal lines SSL1 may include: a first-first selection signal line SSL1a, which is arranged below the first area A1 and electrically connected to a first-first selection signal pattern SSP1a supplied with a first selection signal Ss provided to a plurality of pixels PX arranged in the first area A1; a first-second selection signal line SSL1b, which is arranged below the second area A2 and electrically connected to a first-second selection signal pattern SSP1b supplied with a first selection signal Ss provided to a plurality of pixels PX arranged in the second area A2; a first-third selection signal line SSL1c, which is arranged below the third area A3 and electrically connected to a first-third selection signal pattern SSP1c supplied with a first selection signal Ss provided to a plurality of pixels PX arranged in the third area A3; and a first-fourth selection signal line SSL1d, which is arranged below the fourth area A4 and electrically connected to a first-fourth selection signal pattern SSP1d supplied with a first selection signal Ss provided to a plurality of pixels PX arranged in the fourth area A4.

[0235] Therefore, the first-first selection signal line SSL1a can receive the first selection signal Ss provided to the first area A1, the first-second selection signal line SSL1b can receive the first selection signal Ss provided to the second area A2, the third selection signal line SSL1c can receive the first selection signal Ss provided to the third area A3, and the first-fourth selection signal line SSL1d can receive the first selection signal Ss provided to the fourth area A4.

[0236] In addition, a plurality of first selection signal lines SSL1 may each be connected to a plurality of pixels PX disposed in a corresponding region and provide a first selection signal Ss.

[0237] To this end, the plurality of first selection signal lines SSL1 may each include a main line extending in the first direction X and a plurality of auxiliary lines branched from the main line and disposed to extend in the second direction Y or a direction opposite to the second direction Y.

[0238] For example, the first-first selection signal line SSL1a may include a first main line and a plurality of first auxiliary lines. One end of the first main line is electrically connected to the first-first selection signal pattern SSP1a, and the first main line is arranged to extend from the non-display area NA to the display area AA in a first direction X. The plurality of first auxiliary lines branch from the first main line and are arranged to extend in a second direction Y. In this case, the plurality of first auxiliary lines of the first-first selection signal line SSL1a may be formed in pixel rows. For example, the number of first auxiliary lines of the first-first selection signal line SSL1a may be equal to the number of pixel rows in the display area AA. The plurality of first auxiliary lines may each be commonly connected to a plurality of pixels PX arranged in a corresponding pixel row of the plurality of pixels PX arranged in the first area A1, and the plurality of first auxiliary lines may provide the first selection signal Ss. Therefore, the same first selection signal Ss may be provided to the plurality of pixels PX arranged in the first area A1.

[0239] Furthermore, the first-second selection signal line SSL1b may include a second main line and a plurality of second auxiliary lines. One end of the second main line is electrically connected to the first-second selection signal pattern SSP1b, and the second main line is arranged to extend from the non-display area NA to the display area AA in the first direction X. The plurality of second auxiliary lines branch from the second main line and are arranged to extend in a direction opposite to the second direction Y. In this case, the plurality of second auxiliary lines of the first-second selection signal line SSL1b may be formed in pixel rows. For example, the number of second auxiliary lines of the first-second selection signal line SSL1b may be equal to the number of pixel rows in the display area AA. The plurality of second auxiliary lines may each be commonly connected to a plurality of pixels PX arranged in a corresponding pixel row of the plurality of pixels PX arranged in the second area A2, and the plurality of second auxiliary lines may provide the first selection signal Ss. Therefore, the same first selection signal Ss may be provided to the plurality of pixels PX arranged in the second area A2.

[0240] Furthermore, the first-third selection signal lines SSL1c may include a third main line and a plurality of third auxiliary lines. One end of the third main line is electrically connected to the first-third selection signal pattern SSP1c, and the third main line is arranged to extend from the non-display area NA to the display area AA in the first direction X. The plurality of third auxiliary lines branch from the third main line and are arranged to extend in the second direction Y. In this case, the plurality of third auxiliary lines of the first-third selection signal lines SSL1c may be formed in pixel rows. For example, the number of third auxiliary lines of the first-third selection signal lines SSL1c may be equal to the number of pixel rows in the display area AA. The plurality of third auxiliary lines may each be commonly connected to a plurality of pixels PX arranged in a corresponding pixel row of the plurality of pixels PX arranged in the third area A3, and the plurality of third auxiliary lines may provide the first selection signal Ss. Therefore, the same first selection signal Ss may be provided to the plurality of pixels PX arranged in the third area A3.

[0241] Furthermore, the first to fourth selection signal lines SSL1d may include a fourth main line and a plurality of fourth auxiliary lines. One end of the fourth main line is electrically connected to the first to fourth selection signal pattern SSP1d, and the fourth main line is arranged to extend from the non-display area NA to the display area AA in the first direction X. The plurality of fourth auxiliary lines branch from the fourth main line and are arranged to extend in a direction opposite to the second direction Y. In this case, the plurality of fourth auxiliary lines of the first to fourth selection signal lines SSL1d may be formed in pixel rows. For example, the number of fourth auxiliary lines of the first to fourth selection signal lines SSL1d may be equal to the number of pixel rows in the display area AA. The plurality of fourth auxiliary lines may each be commonly connected to a plurality of pixels PX arranged in a corresponding pixel row of the plurality of pixels PX arranged in the fourth area A4, and the plurality of fourth auxiliary lines may provide the first selection signal Ss. Therefore, the same first selection signal Ss may be provided to the plurality of pixels PX arranged in the fourth area A4.

[0242] One end of each of the plurality of second selection signal lines SSL2 may be electrically connected to a corresponding second selection signal pattern SSP2 .

[0243] For example, the plurality of second selection signal lines SSL2 may include: a second-first selection signal line SSL2a, the second-first selection signal line SSL2a being disposed below the first area A1 and electrically connected to a second-first selection signal pattern SSP2a supplied with a second selection signal Ps provided to the plurality of pixels PX disposed in the first area A1; a second-second selection signal line SSL2b, the second-second selection signal line SSL2b being disposed below the second area A2 and electrically connected to a second-second selection signal pattern SSP2a supplied with a second selection signal Ps provided to the plurality of pixels PX disposed in the second area A2. signal pattern SSP2b; second-third selection signal lines SSL2c, which are arranged below the third area A3 and are electrically connected to the second-third selection signal pattern SSP2c supplied with the second selection signal Ps provided to the plurality of pixels PX arranged in the third area A3; and second-fourth selection signal lines SSL2d, which are arranged below the fourth area A4 and are electrically connected to the second-fourth selection signal pattern SSP2d supplied with the second selection signal Ps provided to the plurality of pixels PX arranged in the fourth area A4.

[0244] Therefore, the second-first selection signal line SSL2a can receive the second selection signal Ps provided to the first area A1, the second-second selection signal line SSL2b can receive the second selection signal Ps provided to the second area A2, the second-third selection signal line SSL2c can receive the second selection signal Ps provided to the third area A3, and the second-fourth selection signal line SSL2d can receive the second selection signal Ps provided to the fourth area A4.

[0245] In addition, the plurality of second selection signal lines SSL2 may each be connected to a plurality of pixels PX disposed in a corresponding region and provide a second selection signal Ps.

[0246] To this end, the plurality of second selection signal lines SSL2 may each include a main line extending in the first direction X and a plurality of auxiliary lines branched from the main line and disposed to extend in the second direction Y or a direction opposite to the second direction Y.

[0247] For example, the second-first selection signal line SSL2a may include: a fifth main line, one end of which is electrically connected to the second-first selection signal pattern SSP2a and is arranged to extend from the non-display area NA to the display area AA in the first direction X; and a plurality of fifth auxiliary lines branching from the fifth main line and arranged to extend in the second direction Y. In this case, the plurality of fifth auxiliary lines of the second-first selection signal line SSL2a may be formed in pixel rows. For example, the number of fifth auxiliary lines of the second-first selection signal line SSL2a may be equal to the number of pixel rows in the display area AA. The plurality of fifth auxiliary lines may each be commonly connected to a plurality of pixels PX arranged in corresponding pixel rows of the plurality of pixels PX in the first area A1, and the plurality of fifth auxiliary lines may provide the second selection signal Ps. Therefore, the same second selection signal Ps may be provided to the plurality of pixels PX arranged in the first area A1.

[0248] Additionally, the second-second selection signal line SSL2b may include: a sixth main line, one end of which is electrically connected to the second-second selection signal pattern SSP2b and is arranged to extend from the non-display area NA to the display area AA in the first direction X; and a plurality of sixth auxiliary lines branching from the sixth main line and arranged to extend in a direction opposite to the second direction Y. In this case, the plurality of sixth auxiliary lines of the second-second selection signal line SSL2b may be formed in pixel rows. For example, the number of sixth auxiliary lines of the second-second selection signal line SSL2b may be equal to the number of pixel rows in the display area AA. The plurality of sixth auxiliary lines may each be commonly connected to a plurality of pixels PX arranged in corresponding pixel rows of the plurality of pixels PX in the second area A2, and the plurality of sixth auxiliary lines may provide the second selection signal Ps. Therefore, the same second selection signal Ps may be provided to the plurality of pixels PX arranged in the second area A2.

[0249] Additionally, the second-third selection signal line SSL2c may include: a seventh main line, one end of which is electrically connected to the second-third selection signal pattern SSP2c and is arranged to extend from the non-display area NA to the display area AA in the first direction X; and a plurality of seventh auxiliary lines branching from the seventh main line and arranged to extend in the second direction Y. In this case, the plurality of seventh auxiliary lines of the second-third selection signal line SSL2c may be formed in pixel rows. For example, the number of seventh auxiliary lines of the second-third selection signal line SSL2c may be equal to the number of pixel rows in the display area AA. The plurality of seventh auxiliary lines may each be commonly connected to a plurality of pixels PX arranged in corresponding pixel rows of the plurality of pixels PX in the third area A3, and the plurality of seventh auxiliary lines may provide the second selection signal Ps. Therefore, the same second selection signal Ps may be provided to the plurality of pixels PX arranged in the third area A3.

[0250] Additionally, the second-fourth selection signal lines SSL2d may include: an eighth main line, one end of which is electrically connected to the second-fourth selection signal pattern SSP2d and is arranged to extend from the non-display area NA to the display area AA in the first direction X; and a plurality of eighth auxiliary lines branching from the eighth main line and arranged to extend in a direction opposite to the second direction Y. In this case, the plurality of eighth auxiliary lines of the second-fourth selection signal lines SSL2d may be formed in pixel rows. For example, the number of eighth auxiliary lines of the second-fourth selection signal lines SSL2d may be equal to the number of pixel rows in the display area AA. The plurality of eighth auxiliary lines may each be commonly connected to a plurality of pixels PX arranged in corresponding pixel rows of the plurality of pixels PX in the fourth area A4, and the plurality of eighth auxiliary lines may provide the second selection signal Ps. Therefore, the same second selection signal Ps may be provided to the plurality of pixels PX arranged in the fourth area A4.

[0251] As described above, the first and second selection signals Ss and Ps may be independently provided to the plurality of areas A1, A2, A3, and A4 of the display area AA, so that driving modes of the plurality of areas A1, A2, A3, and A4 may be independently controlled.

[0252] In addition, the display device 100 according to an embodiment of the present disclosure may include a plurality of selection signal patterns SSP1 and SSP2 for providing the first selection signal Ss and the second selection signal Ps, thereby minimizing the RC delay of the selection signal.

[0253] For example, when a single selection signal line connected to a plurality of signal pads SP1 and SP2 supplied with selection signals is connected to a plurality of pixels PX disposed in all corresponding areas among the plurality of areas A1, A2, A3, and A4 so as to provide a first selection signal Ss and a second selection signal Ps to the plurality of pixels PX, an RC delay may occur on the corresponding selection signal line. In particular, since the width of the selection signal line for supplying the selection signal is designed to be very small to ensure the layout of the display device 100, the resistance of the single selection signal line may increase, and an RC delay may occur significantly.

[0254] Therefore, in the case of the display device 100 according to an embodiment of the present specification, the selection signal can be provided to the multiple selection signal lines SSL1 and SSL2 by being electrically connected to the multiple selection signal patterns SSP1 and SSP2 that are connected to the multiple signal pads SP1 and SP2 and configured to provide the selection signal, so that the resistance of the multiple selection signal lines SSL1 and SSL2 can be reduced and the RC delay that may occur on the multiple selection signal lines SSL1 and SSL2 can be minimized.

[0255] In addition, as described above, the multiple selection signal patterns SSP1 and SSP2 can each be formed to have a width larger than the width of each of the other signal lines (for example, the multiple selection signal lines SSL1 and SSL2 and / or the multiple connection lines CLL1 and CLL2), so that the resistance of each of the multiple selection signal patterns SSP1 and SSP2 can be designed to be minimized, which can more effectively improve the RC delay that may occur on the multiple selection signal lines SSL1 and SSL2.

[0256] Figure 10 is an equivalent circuit diagram of a display device according to an embodiment of this specification.

[0257] at the same time, Figure 10 An equivalent circuit diagram of the display device 100 corresponding to a plurality of pixels PX provided in the first area A1 , for example, among a plurality of areas A1 , A2 , A3 , and A4 included in the display area AA is exemplarily shown.

[0258] In addition, for the convenience of description, Figure 10 Only six pixels, for example, first to sixth pixels PX1 , PX2 , PX3 , PX4 , PX5 , and PX6 disposed in one row among the plurality of pixels PX disposed in the first area A1 are shown.

[0259] Therefore, hereinafter, based on six pixels disposed in the first area A1 of the display area AA, an equivalent circuit of the display device 100 will be described. The equivalent circuit of the display device 100 may include a structure that is substantially the same as or similar to not only the remaining pixels disposed in the first area A1 of the display area AA but also the pixels disposed in the second area A2, the third area A3, and the fourth area A4.

[0260] At the same time, for the sake of convenience, the description will not be repeated Figure 10 In and reference Figure 8 and Figure 9 The content described is the same as the content.

[0261] Reference Figures 8 to 10 The display device 100 may include a first pixel PX1, a second pixel PX2, a third pixel PX3, a fourth pixel PX4, a fifth pixel PX5, and a sixth pixel PX6 disposed in a display area AA (e.g., a first area A1). In addition, the display device 100 may include a data distribution circuit MUX, an anti-static portion ESD, and an illumination inspection portion AP disposed in a non-display area NA.

[0262] The first pixel PX1, the second pixel PX2, the third pixel PX3, the fourth pixel PX4, the fifth pixel PX5, and the sixth pixel PX6 may each be connected to a corresponding data line among the plurality of data lines DL and receive a data voltage Vdata. For example, the first pixel PX1 may be connected to the first data line DL1, the second pixel PX2 may be connected to the second data line DL2, the third pixel PX3 may be connected to the third data line DL3, the fourth pixel PX4 may be connected to the fourth data line DL4, the fifth pixel PX5 may be connected to the fifth data line DL5, and the sixth pixel PX6 may be connected to the sixth data line DL6.

[0263] At the same time, the first pixel PX1, the second pixel PX2, the third pixel PX3, the fourth pixel PX4, the fifth pixel PX5, and the sixth pixel PX6 can emit light beams having different colors. For example, the first pixel PX1 and the fourth pixel PX4 can be red pixels configured to emit red light, the second pixel PX2 and the fifth pixel PX5 can be green pixels configured to emit green light, and the third pixel PX3 and the sixth pixel PX6 can be blue pixels configured to emit blue light. However, the present specification is not limited thereto.

[0264] In addition, as described above, a plurality of pixels PX disposed in one area of the display area AA may be connected to the same first selection signal line SSL1 and supplied with the first selection signal Ss, and a plurality of pixels PX may be connected to the same second selection signal line SSL2 and supplied with the second selection signal Ps. For example, a first pixel PX1, a second pixel PX2, a third pixel PX3, a fourth pixel PX4, a fifth pixel PX5, and a sixth pixel PX6 disposed in the first area A1 may each be electrically connected to the first-first selection signal line SSL1a and the second-first selection signal line SSL2a, and supplied with the first selection signal Ss and the second selection signal Ps.

[0265] At the same time, as reference Figure 9 As described above, the first selection signal line SSL1 and the second selection signal line SSL2 can be electrically connected to the first selection signal pattern SSP1 and the second selection signal pattern SSP2, and the first selection signal pattern SSP1 and the second selection signal pattern SSP2 can be electrically connected to the first connection line CLL1 connected to the first signal pad SP1 and the second connection line CLL2 connected to the second signal pad SP2. Therefore, the first selection signal Ss and the second selection signal Ps can be provided to the first selection signal line SSL1 and the second selection signal line SSL2, and the RC delay of the first selection signal line SSL1 and the second selection signal line SSL2 can be minimized by the first selection signal pattern SSP1 and the second selection signal pattern SSP2, each having a predetermined width.

[0266] The data distribution circuit MUX can distribute the data voltage Vdata transmitted by the plurality of data link lines DLL connected to the plurality of data pads DP to the plurality of data lines DL in a time-division manner. At the same time, the plurality of data pads DP can be electrically connected to each of the plurality of output buffers of the data driving circuit DD included in each of the plurality of connection films COF1 and COF2 and receive the data voltage Vdata.

[0267] To this end, the data distribution circuit MUX may include a plurality of mux switches. For example, the data distribution circuit MUX may include mux switches corresponding in number to the pixel columns. Figure 10 Six mux switches M1 , M2 , M3 , M4 , M5 , and M6 corresponding to six pixels arranged in a row direction are shown.

[0268] The first mux switch M1 can electrically connect a first data link line DLL1 among the plurality of data link lines DLL to the first data line DL1 in response to a first distribution control signal MS1. The second mux switch M2 can electrically connect a second data link line DLL2 among the plurality of data link lines DLL to the second data line DL2 in response to the first distribution control signal MS1. The third mux switch M3 can electrically connect a third data link line DLL3 among the plurality of data link lines DLL to the third data line DL3 in response to the first distribution control signal MS1.

[0269] In addition, the fourth mux switch M4 can electrically connect the first data link line DLL1 among the plurality of data link lines DLL to the fourth data line DL4 in response to the second distribution control signal MS2. The fifth mux switch M5 can electrically connect the second data link line DLL2 among the plurality of data link lines DLL to the fifth data line DL5 in response to the second distribution control signal MS2. The sixth mux switch M6 can electrically connect the third data link line DLL3 among the plurality of data link lines DLL to the sixth data line DL6 in response to the second distribution control signal MS2.

[0270] The first distribution control signal MS1 and the second distribution control signal MS2 may alternately have an on level.

[0271] For example, the second distribution control signal MS2 may have an off-level in a section where the first distribution control signal MS1 has an on-level. In this case, the first mux switch M1, the second mux switch M2, and the third mux switch M3 may be turned on by the first distribution control signal MS1 at the on-level, so that the first data link line DLL1 connected to the first data pad DP1 may be connected to the first data line DL1, the second data link line DLL2 connected to the second data pad DP2 may be connected to the second data line DL2, and the third data link line DLL3 connected to the third data pad DP3 may be connected to the third data line DL3. Therefore, the first pixel PX1, the second pixel PX2, and the third pixel PX3 may receive the data voltage Vdata from the first data line DL1, the second data line DL2, and the third data line DL3.

[0272] In addition, the first distribution control signal MS1 may have an off-level in a section where the second distribution control signal MS2 has an on-level. In this case, the fourth mux switch M4, the fifth mux switch M5, and the sixth mux switch M6 may be turned on by the second distribution control signal MS2 at the on-level, so that the first data link line DLL1 connected to the first data pad DP1 can be connected to the fourth data line DL4, the second data link line DLL2 connected to the second data pad DP2 can be connected to the fifth data line DL5, and the third data link line DLL3 connected to the third data pad DP3 can be connected to the sixth data line DL6. Therefore, the fourth pixel PX4, the fifth pixel PX5, and the sixth pixel PX6 can receive the data voltage Vdata from the fourth data line DL4, the fifth data line DL5, and the sixth data line DL6.

[0273] At the same time, because the data voltage Vdata supplied to the first data link line DLL1 is supplied to the first pixel PX1 and the fourth pixel PX4, the data voltage Vdata may be the data voltage Vdata corresponding to the red light emitting element. Because the data voltage Vdata supplied to the second data link line DLL2 is supplied to the second pixel PX2 and the fifth pixel PX5, the data voltage Vdata may be the data voltage Vdata corresponding to the green light emitting element. Because the data voltage Vdata supplied to the third data link line DLL3 is supplied to the third pixel PX3 and the sixth pixel PX6, the data voltage Vdata may be the data voltage Vdata corresponding to the blue light emitting element.

[0274] As described above, the data distribution circuit MUX can distribute the data voltage Vdata output by the output buffer of the data driving circuit DD to the plurality of data lines DL in a time-division manner, wherein the number of the output buffers is half the number of the data lines DL (i.e., the number of pixel columns). Therefore, the number of components included in the data driving circuit DD can be reduced, and the data driving circuit DD can be simplified.

[0275] The illumination inspection unit AP can inspect the plurality of pixels PX disposed in the display area AA for abnormal operation before shipment of the display device 100. To this end, the illumination inspection unit AP may include: a first illumination inspection unit AP1 configured to provide a first pattern illumination inspection signal SSs and a second pattern illumination inspection signal SPs corresponding to a first selection signal Ss and a second selection signal Ps to the plurality of pixels PX; and a second illumination inspection unit AP2 configured to provide a data illumination inspection signal DS corresponding to a data voltage Vdata to the plurality of pixels PX.

[0276] The first lighting check part AP1 may include a first mode lighting check switch SST1 and a second mode lighting check switch SST2.

[0277] The first pattern lighting check switch SST1 can electrically connect the first connection line CLL1 to the first pattern lighting check signal line provided with the first pattern lighting check signal SSs corresponding to the first select signal Ss in response to the first lighting check control signal APS1. In this case, the first pattern lighting check signal SSs can be provided to the first select signal line SSL1 via the first connection line CLL1 and the first select signal pattern SSP1 through the first pattern lighting check signal line. Therefore, the first pattern lighting check signal SSs can be provided to the first transistor T1 included in each of the plurality of pixels PX arranged in the display area AA.

[0278] The second pattern lighting check switch SST2 can electrically connect the second connection line CLL2 to the second pattern lighting check signal line provided with the second pattern lighting check signal SPs corresponding to the second select signal Ps in response to the first lighting check control signal APS1. In this case, the second pattern lighting check signal SPs can be provided to the second select signal line SSL2 via the second connection line CLL2 and the second select signal pattern SSP2 through the second pattern lighting check signal line. Therefore, the second pattern lighting check signal SPs can be provided to the second transistor T2 included in each of the plurality of pixels PX arranged in the display area AA.

[0279] The first illumination inspection part AP1 may inspect whether the first and second transistors T1 and T2 of each of the plurality of pixels PX provided in the display area AA operate abnormally and whether the first and second light emitting elements ED1 and ED2 emit light before shipment of the display device 100 .

[0280] The second illumination check part AP2 may include a first data illumination check switch LT1 , a second data illumination check switch LT2 , and a third data illumination check switch LT3 .

[0281] The first data lighting check switch LT1 may electrically connect the first data link line DLL1 to the first data lighting check signal line supplied with the first data lighting check signal DS1 in response to the second lighting check control signal APS2. In this case, the first data lighting check signal DS1 may be supplied to the first data link line DLL1.

[0282] The second data lighting check switch LT2 may electrically connect the second data link line DLL2 to the second data lighting check signal line provided with the second data lighting check signal DS2 in response to the second lighting check control signal APS2. In this case, the second data lighting check signal DS2 may be provided to the second data link line DLL2.

[0283] The third data lighting check switch LT3 can electrically connect the third data link line DLL3 to the third data lighting check signal line provided with the third data lighting check signal DS3 in response to the second lighting check control signal APS2. In this case, the third data lighting check signal DS3 can be provided to the third data link line DLL3.

[0284] In addition, the data distribution circuit MUX may operate as described above and distribute the data illumination inspection signal DS to the plurality of data lines DL in a time-division manner during operation of the second illumination inspection part AP2 , for example, during an illumination inspection period of the display device 100 .

[0285] For example, the first data link line DLL1, the second data link line DLL2 and the third data link line DLL3 can be respectively connected to the first data line DL1, the second data line DL2 and the third data line DL3 in the section where the first distribution control signal MS1 has the on level, and the first data link line DLL1, the second data line DLL2 and the third data line DL3 can be respectively connected to the fourth data line DL4, the fifth data line DL5 and the sixth data line DL6 in the section where the second distribution control signal MS2 has the on level.

[0286] At the same time, because the first data link line DLL1 provides the data voltage Vdata to the first pixel PX1 and the fourth pixel PX4, the first data lighting check signal DS1 provided to the first data link line DLL1 by the operation of the first data lighting check switch LT1 can be substantially the same as the data voltage Vdata corresponding to the red light emitting element. Because the second data link line DLL2 provides the data voltage Vdata to the second pixel PX2 and the fifth pixel PX5, the second data lighting check signal DS2 provided to the second data link line DLL2 by the operation of the second data lighting check switch LT2 can be substantially the same as the data voltage Vdata corresponding to the green light emitting element. Because the third data link line DLL3 provides the data voltage Vdata to the third pixel PX3 and the sixth pixel PX6, the third data lighting check signal DS3 provided to the third data link line DLL3 by the operation of the third data lighting check switch LT3 can be substantially the same as the data voltage Vdata corresponding to the blue light emitting element.

[0287] The second illumination inspection part AP2 may inspect whether each of the plurality of pixels PX provided in the display area AA operates abnormally before shipment of the display device 100 .

[0288] At the same time, as described above, since the lighting inspection pad portion that supplies the data lighting inspection signal and the pattern lighting inspection signal to the plurality of lighting inspection switches included in the lighting inspection portion AP is removed after the lighting inspection is performed on the display device 100, the lighting inspection portion AP does not operate when the display device 100 is operated after normal shipment of the display device 100. That is, when the display device 100 is operated after normal shipment of the display device 100, all of the plurality of pattern lighting inspection switches SST1 and SST2 included in the first lighting inspection portion AP1 and the plurality of data lighting inspection switches LT1, LT2, and LT3 included in the second lighting inspection portion AP2 can be kept in an on state and not operated.

[0289] The anti-static portion ESD may discharge static electricity applied to the plurality of data lines DL and / or the plurality of selection signal lines SSL1 and SSL2 , thereby protecting the plurality of data lines DL and / or the plurality of selection signal lines SSL1 and SSL2 from static electricity.

[0290] For example, the anti-static portion ESD may include a plurality of first anti-static portions ESD1 respectively connected to the plurality of connection lines CLL1 and CLL2 supplied with the selection signal and a plurality of second anti-static portions ESD2 respectively connected to the plurality of data link lines DLL.

[0291] A plurality of first antistatic parts ESD1 may each include a first antistatic element D1 and a second antistatic element D2, wherein the first antistatic element D1 and the second antistatic element D2 are connected in series with each other and are arranged between a first voltage line VL1 provided with a first voltage VGH at a high level and a second voltage line VL2 provided with a second voltage VGL at a low level. For example, the first voltage VGH may have a voltage level higher than the second voltage VGL. For example, the first voltage VGH and the high potential power voltage VDD may have substantially the same voltage level, and the second voltage VGL and the low potential power voltage VSS may have substantially the same voltage level. However, this specification is not limited to this. According to an embodiment, the second voltage line VL2 provided with the second voltage VGL may be electrically connected to a low potential power line or a second power pattern PP2 provided with a low potential power voltage VSS. However, this specification is not limited to this.

[0292] The first anti-static element D1 may be connected between the first voltage line VL1 and a connection line, such as the first connection line CLL1 or the second connection line CLL2. For example, the first anti-static element D1 may be a diode. However, the present invention is not limited thereto.

[0293] The second anti-static element D2 may be connected between the second voltage line VL2 and a connection line, such as the first connection line CLL1 or the second connection line CLL2. For example, the second anti-static element D2 may be a diode. However, the present invention is not limited thereto.

[0294] Therefore, the first anti-static element D1 and the second anti-static element D2 can protect the first selection signal line SSL1 connected to the first connection line CLL1 and the second selection signal line SSL2 connected to the second connection line CLL2 from the influence of static electricity by discharging static electricity applied to the connection lines, such as the first connection line CLL1 and the second connection line CLL2 provided with selection signals, to the second voltage line VL2 provided with the second voltage VGL at a low level.

[0295] The plurality of second anti-static parts ESD2 may each include a third anti-static element D3 and a fourth anti-static element D4, which are connected in series to each other and arranged between a first voltage line VL1 provided with a first voltage VGH at a high level and a second voltage line VL2 provided with a second voltage VGL at a low level.

[0296] The third anti-static element D3 may be connected between the first voltage line VL1 and any one of the plurality of data link lines DLL, such as the first data link line DLL1, the second data link line DLL2, or the third data link line DLL3. For example, the third anti-static element D3 may be a diode. However, this specification is not limited thereto.

[0297] The fourth anti-static element D4 may be connected between the second voltage line VL2 and any one of the plurality of data link lines DLL, such as the first data link line DLL1, the second data link line DLL2, or the third data link line DLL3. For example, the fourth anti-static element D4 may be a diode. However, this specification is not limited thereto.

[0298] Therefore, the third anti-static element D3 and the fourth anti-static element D4 can protect the plurality of data lines DL connected to the plurality of data link lines DLL from static electricity by discharging static electricity applied to the plurality of data link lines DLL supplied with the data voltage Vdata to the second voltage line VL2 supplied with the second voltage VGL at a low level.

[0299] Figure 11 is a top plan view of a display device according to another embodiment of the present specification.

[0300] at the same time, Figure 11 The diagram shows the connection relationship between the first selection signal line SSL1_1 and the second selection signal line SSL2_1. Figure 9 Therefore, in order to avoid repeated description, reference is made to Figure 11 The description will focus on the differences from the above-described embodiment.

[0301] Reference Figure 11 The display device 200 may include a substrate 110, a gate driving circuit GD, a plurality of pad portions PAD1 and PAD2, a plurality of power patterns PP1, PP2, and PP3, a data distribution circuit MUX, an anti-static portion ESD, an illumination inspection portion AP, a first selection signal pattern SSP1, a second selection signal pattern SSP2, and various types of signal lines.

[0302] The plurality of first selection signal lines SSL1_1 and the plurality of second selection signal lines SSL2_1 may each be disposed to extend from the non-display area NA to the display area AA.

[0303] The plurality of first selection signal lines SSL1_1 may include a plurality of first-first selection signal lines SSL1a_1 electrically connected to the first-first selection signal pattern SSP1a, a plurality of first-second selection signal lines SSL1b_1 electrically connected to the first-second selection signal pattern SSP1b, a plurality of first-third selection signal lines SSL1c_1 electrically connected to the first-third selection signal pattern SSP1c, and a plurality of first-fourth selection signal lines SSL1d_1 electrically connected to the first-fourth selection signal pattern SSP1d.

[0304] For example, one end of each of the plurality of first-first selection signal lines SSL1a_1 may be connected to a first-first selection signal pattern SSP1a that supplies a first selection signal Ss to the first area A1. Furthermore, the plurality of first-first selection signal lines SSL1a_1 may extend in both the first direction X and the second direction Y, connected to a plurality of pixels PX arranged in a plurality of pixel rows in the first area A1, and supplying the first selection signal Ss. Therefore, the number of first-first selection signal lines SSL1a_1 may be equal to the number of pixel rows in the display area AA. In this case, because all of the plurality of first-first selection signal lines SSL1a_1 are connected to the first-first selection signal pattern SSP1a that supplies the first selection signal Ss to the first area A1, the same first selection signal Ss may be supplied to the plurality of pixels PX arranged in the first area A1.

[0305] Furthermore, one end of each of the plurality of first-second selection signal lines SSL1b_1 may be connected to a first-second selection signal pattern SSP1b that supplies a first selection signal Ss to the second area A2. Furthermore, the plurality of first-second selection signal lines SSL1b_1 may extend in the first direction X and the second direction Y, connected to a plurality of pixels PX arranged in a plurality of pixel rows in the second area A2, and supplying the first selection signal Ss. Therefore, the number of first-second selection signal lines SSL1b_1 may be equal to the number of pixel rows in the display area AA. In this case, because all of the plurality of first-second selection signal lines SSL1b_1 are connected to the first-second selection signal pattern SSP1b that supplies the first selection signal Ss to the second area A2, the same first selection signal Ss may be supplied to the plurality of pixels PX arranged in the first area A1.

[0306] Furthermore, one end of each of the plurality of first-third selection signal lines SSL1c_1 may be connected to a first-third selection signal pattern SSP1c supplied with a first selection signal Ss provided to the third area A3. Furthermore, the plurality of first-third selection signal lines SSL1c_1 may extend in the first direction X and the second direction Y, connected to a plurality of pixels PX arranged in a plurality of pixel rows in the third area A3, and supplying the first selection signal Ss. Therefore, the number of first-third selection signal lines SSL1c_1 may be equal to the number of pixel rows in the display area AA. In this case, because all of the plurality of first-third selection signal lines SSL1c_1 are connected to the first-third selection signal pattern SSP1c supplied with the first selection signal Ss provided to the third area A3, the same first selection signal Ss may be supplied to the plurality of pixels PX arranged in the third area A3.

[0307] Furthermore, one end of each of the plurality of first to fourth selection signal lines SSL1d_1 may be connected to a first to fourth selection signal pattern SSP1d supplied with a first selection signal Ss provided to the fourth area A4. Furthermore, the plurality of first to fourth selection signal lines SSL1d_1 may extend in the first direction X and the second direction Y, connected to a plurality of pixels PX arranged in a plurality of pixel rows in the fourth area A4, and supplying the first selection signal Ss. Therefore, the number of first to fourth selection signal lines SSL1d_1 may be equal to the number of pixel rows in the display area AA. In this case, because all of the plurality of first to fourth selection signal lines SSL1d_1 are connected to the first to fourth selection signal pattern SSP1d supplied with the first selection signal Ss provided to the fourth area A4, the same first selection signal Ss may be supplied to the plurality of pixels PX arranged in the fourth area A4.

[0308] The multiple second selection signal lines SSL2_1 may include a plurality of second-first selection signal lines SSL2a_1 electrically connected to the second-first selection signal pattern SSP2a, a plurality of second-second selection signal lines SSL2b_1 electrically connected to the second-second selection signal pattern SSP2b, a plurality of second-third selection signal lines SSL2c_1 electrically connected to the second-third selection signal pattern SSP2c, and a plurality of second-fourth selection signal lines SSL2d_1 electrically connected to the second-fourth selection signal pattern SSP2d.

[0309] For example, one end of each of the plurality of second-first selection signal lines SSL2a_1 may be connected to a second-first selection signal pattern SSP2a that provides a second selection signal Ps to the first area A1. Furthermore, the plurality of second-first selection signal lines SSL2a_1 may extend in the first direction X and the second direction Y, connected to a plurality of pixels PX arranged in a plurality of pixel rows in the first area A1, and provide the second selection signal Ps. Therefore, the number of second-first selection signal lines SSL2a_1 may be equal to the number of pixel rows in the display area AA. In this case, because all of the plurality of second-first selection signal lines SSL2a_1 are connected to the second-first selection signal pattern SSP2a that provides the second selection signal Ps to the first area A1, the same second selection signal Ps may be provided to the plurality of pixels PX arranged in the first area A1.

[0310] Furthermore, one end of each of the plurality of second-second selection signal lines SSL2b_1 may be connected to a second-second selection signal pattern SSP2b supplied with a second selection signal Ps for the second area A2. Furthermore, the plurality of second-second selection signal lines SSL2b_1 may extend in the first direction X and the second direction Y, connected to a plurality of pixels PX arranged in a plurality of pixel rows in the second area A2, and supplying the second selection signal Ps. Therefore, the number of second-second selection signal lines SSL2b_1 may be equal to the number of pixel rows in the display area AA. In this case, because all of the plurality of second-second selection signal lines SSL2b_1 are connected to the second-second selection signal pattern SSP2b supplied with the second selection signal Ps for the second area A2, the same second selection signal Ps may be supplied to the plurality of pixels PX arranged in the first area A1.

[0311] Furthermore, one end of each of the plurality of second-third selection signal lines SSL2c_1 may be connected to a second-third selection signal pattern SSP2c supplied with a second selection signal Ps provided to the third area A3. Furthermore, the plurality of second-third selection signal lines SSL2c_1 may extend in the first direction X and the second direction Y, connected to a plurality of pixels PX arranged in a plurality of pixel rows in the third area A3, and supply the second selection signal Ps. Therefore, the number of second selection signal lines SSL2c_1 may be equal to the number of pixel rows in the display area AA. In this case, because all of the plurality of second-third selection signal lines SSL2c_1 are connected to the second-third selection signal pattern SSP2c supplied with the second selection signal Ps provided to the third area A3, the same second selection signal Ps may be supplied to the plurality of pixels PX arranged in the third area A3.

[0312] Furthermore, one end of each of the plurality of second-fourth selection signal lines SSL2d_1 may be connected to a second-fourth selection signal pattern SSP2d supplied with a second selection signal Ps provided to the fourth area A4. Furthermore, the plurality of second-fourth selection signal lines SSL2d_1 may extend in the first direction X and the second direction Y, connected to a plurality of pixels PX arranged in a plurality of pixel rows in the fourth area A4, and supplying the second selection signal Ps. Therefore, the number of second-fourth selection signal lines SSL2d_1 may be equal to the number of pixel rows in the display area AA. In this case, because all of the plurality of second-fourth selection signal lines SSL2d_1 are connected to the second-fourth selection signal pattern SSP2d supplied with the second selection signal Ps provided to the fourth area A4, the same second selection signal Ps may be supplied to the plurality of pixels PX arranged in the fourth area A4.

[0313] As described above, the first and second selection signals Ss and Ps may be independently provided to the plurality of areas A1, A2, A3, and A4 of the display area AA, so that driving modes of the plurality of areas A1, A2, A3, and A4 may be independently controlled.

[0314] In addition, compared with the case where a single selection signal line for providing selection signals, such as a single first selection signal line and a single second selection signal line, is set in multiple areas A1, A2, A3 and A4, the display device 200 according to the embodiment of the present specification includes multiple first selection signal lines SSL1_1 configured to provide the first selection signal Ss to different lines of each of the pixel rows in each of the multiple areas A1, A2, A3 and A4, and multiple second selection signal lines SSL2_1 configured to provide the second selection signal Ps to different lines of each of the pixel rows in each of the multiple areas A1, A2, A3 and A4, so that the resistance of the multiple selection signal lines SSL1_1 and SSL2_1 can be further reduced, and the RC delay that may occur on the multiple selection signal lines SSL1 and SSL2 can be more effectively improved.

[0315] Exemplary embodiments of the present disclosure may also be described as follows:

[0316] According to one aspect of the present disclosure, a display device is provided. The display device includes: a substrate including a display area and a non-display area arranged to surround the display area; a plurality of pixels arranged in the display area of the substrate; a pad portion arranged in the non-display area of the substrate and supplied with a selection signal; a connection line arranged in the non-display area of the substrate, extending along a first direction, and connected to the pad portion; a selection signal pattern arranged in the non-display area of the substrate, extending in a second direction different from the first direction, and connected to the connection line; and a selection signal line arranged to extend from the non-display area of the substrate to the display area, connected to the selection signal pattern, and configured to provide the selection signal supplied from the pad portion to the plurality of pixels.

[0317] The selection signal line may include: a main line extending in the first direction; and a plurality of auxiliary lines branched from the main line and extending in the second direction.

[0318] A plurality of auxiliary lines may be provided for each of a plurality of pixel rows in the display area.

[0319] A width of the selection signal pattern in the first direction may be greater than a width of the selection signal line.

[0320] The selection signal pattern may include a metal material.

[0321] Each of the multiple pixels may include: a first transistor; a first light-emitting element, which is configured to emit light by a first driving current supplied from the first transistor; a second transistor; and a second light-emitting element, which is configured to emit light by a second driving current supplied from the second transistor and emit light having the same color as the light emitted from the first light-emitting element.

[0322] The selection signal line may include a first selection signal line configured to provide a first selection signal to the first transistor; and a second selection signal line configured to provide a second selection signal to the second transistor.

[0323] The selection signal pattern may include a first selection signal pattern connected to a first selection signal line; and a second selection signal pattern connected to a second selection signal line.

[0324] The first selection signal pattern and the second selection signal pattern may be disposed adjacent to each other in the first direction.

[0325] The connection line may include a first connection line configured to receive a first selection signal from the pad portion and connected to a first selection signal pattern; and a second connection line configured to receive a second selection signal from the pad portion and connected to a second selection signal pattern.

[0326] Each of the plurality of pixels may further include: a first optical member configured to refract light from the first light emitting element; and a second optical member configured to refract light from the second light emitting element and having a shape different from that of the first optical member.

[0327] The display device may further include: an illumination inspection portion, which is arranged in the non-display area and connected to the connecting line, wherein the illumination inspection portion may include at least one mode illumination inspection switch, and the at least one mode illumination inspection switch is configured to provide a mode illumination inspection signal to the connecting line in response to the illumination inspection control signal.

[0328] The display device may further include: an antistatic portion, which is arranged in the non-display area and connected to the connecting line, wherein the antistatic portion may include a first antistatic element and a second antistatic element, the first antistatic element and the second antistatic element are connected in series between a first voltage line provided with a first voltage and a second voltage line provided with a second voltage lower than the first voltage.

[0329] According to another aspect of the present disclosure, a display device is provided. The display device includes: a substrate including a display area and a non-display area arranged to surround the display area; a plurality of pixels arranged in the display area of the substrate; a pad portion arranged in the non-display area of the substrate and supplied with a selection signal; a connection line arranged in the non-display area of the substrate, extending along a first direction, and connected to the pad portion; a selection signal pattern arranged in the non-display area of the substrate, extending in a second direction different from the first direction, and connected to the connection line; and a plurality of selection signal lines arranged to extend from the non-display area of the substrate to the display area, connected to the selection signal pattern, and configured to provide the selection signal supplied from the pad portion to the plurality of pixels, wherein the plurality of selection signal lines are provided for each pixel row in the display area.

[0330] The plurality of selection signal lines may extend in the first direction and the second direction.

[0331] A width of the selection signal pattern in the first direction may be greater than a width of each of the plurality of selection signal lines.

[0332] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all aspects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the appended claims, and all technical concepts within their equivalent scope should be interpreted as falling within the scope of the present disclosure.

Claims

1. A display device comprising: a substrate including a display area and a non-display area disposed to surround the display area; a plurality of pixels, the plurality of pixels being arranged in the display area of the substrate; a pad portion provided in the non-display area of the substrate and supplied with a selection signal; a connecting line, the connecting line being provided in the non-display area of the substrate, extending along a first direction, and connected to the pad portion; a selection signal pattern, the selection signal pattern being provided in the non-display area of the substrate, extending in a second direction different from the first direction, and connected to the connection line; as well as A selection signal line is provided to extend from the non-display area to the display area of the substrate, is connected to the selection signal pattern, and is configured to provide the plurality of pixels with the selection signal supplied from the pad portion.

2. The display device according to claim 1, wherein The selection signal line includes: a main line extending in the first direction; and A plurality of auxiliary lines branch from the main line and extend along the second direction.

3. The display device according to claim 2, wherein: The plurality of auxiliary lines are provided for each of a plurality of pixel rows in the display area.

4. The display device according to claim 1, wherein A width of the selection signal pattern in the first direction is greater than a width of the selection signal line.

5. The display device according to claim 1, wherein The selection signal pattern includes a metal material. The display device according to claim 1 , wherein: Each of the plurality of pixels comprises: a first transistor; a first light emitting element configured to emit light by a first drive current supplied from the first transistor; a second transistor; and a second light emitting element configured to emit light by a second driving current supplied from the second transistor and emit light having the same color as the light emitted from the first light emitting element.

7. The display device according to claim 6, wherein: The selection signal line includes: a first selection signal line configured to provide a first selection signal to the first transistor; and A second selection signal line is configured to provide a second selection signal to the second transistor.

8. The display device according to claim 7, wherein: The selection signal pattern includes: a first selection signal pattern connected to the first selection signal line; and A second selection signal pattern is connected to the second selection signal line.

9. The display device according to claim 8, wherein The first selection signal pattern and the second selection signal pattern are disposed adjacent to each other in the first direction.

10. The display device according to claim 8, wherein The connecting line includes: a first connection line configured to receive the first selection signal from the pad portion and be connected to the first selection signal pattern; and A second connection line is configured to receive the second selection signal from the pad portion and be connected to the second selection signal pattern.

11. The display device according to claim 6, wherein Each of the plurality of pixels further comprises: a first optical member configured to refract light from the first light emitting element; and a second optical member configured to refract light from the second light emitting element and having a shape different from that of the first optical member.

12. The display device according to claim 1, further comprising: an illumination inspection portion disposed in the non-display area and connected to the connection line; The lighting inspection section includes at least one mode lighting inspection switch, and the at least one mode lighting inspection switch is configured to provide a mode lighting inspection signal to the connection line in response to a lighting inspection control signal.

13. The display device according to claim 1, further comprising: an antistatic portion disposed in the non-display area and connected to the connection line; The anti-static part includes a first anti-static element and a second anti-static element, which are connected in series between a first voltage line provided with a first voltage and a second voltage line provided with a second voltage lower than the first voltage.

14. A display device comprising: a substrate including a display area and a non-display area disposed to surround the display area; a plurality of pixels, the plurality of pixels being arranged in the display area of the substrate; a pad portion provided in the non-display area of the substrate and supplied with a selection signal; a connecting line, the connecting line being provided in the non-display area of the substrate, extending along a first direction, and connected to the pad portion; a selection signal pattern, the selection signal pattern being provided in the non-display area of the substrate, extending in a second direction different from the first direction, and connected to the connection line; as well as a plurality of selection signal lines provided to extend from the non-display area to the display area of the substrate, connected to the selection signal pattern, and configured to supply the selection signal supplied from the pad portion to the plurality of pixels, The plurality of selection signal lines are provided for each pixel row in the display area.

15. The display device according to claim 14, wherein The plurality of selection signal lines extend in the first direction and the second direction.

16. The display device according to claim 14, wherein: A width of the selection signal pattern in the first direction is greater than a width of each of the plurality of selection signal lines.

17. A display device comprising a display area and a non-display area arranged to surround the display area, wherein: The display area includes a plurality of pixels; Each of the plurality of pixels comprises: a first light-emitting element, said first light-emitting element emitting light of a first color, a first optical member disposed on the first light emitting element to provide a first viewing angle range; a first transistor for supplying a first drive current for emitting light to the first light emitting element; a second light-emitting element, which emits light of the first color; a second optical member disposed on the second light emitting element to provide a second viewing angle range wider than the first viewing angle range, and a second transistor for supplying a second drive current for emitting light from the second transistor to the second light emitting element; The first transistor and the second transistor are controlled by different selection signal lines.

18. The display device according to claim 17, wherein: The display area includes a plurality of sub-display areas arranged along a second direction; The non-display area includes a plurality of selection signal pattern pairs corresponding to the plurality of sub-display areas; The first selection signal pattern and the second selection signal pattern in each of the plurality of selection signal pattern pairs are separated from each other along a first direction perpendicular to the second direction; and For a first selection signal pattern pair among the plurality of selection signal pattern pairs and pixels in a first sub-display area corresponding to the first selection signal pattern pair, The first selection signal pattern in the pair of first selection signal patterns is configured to receive a first selection signal and be connected to the first transistor of the pixel via a first selection signal line to control whether the first light-emitting element of the pixel emits light based on the first selection signal; and The second selection signal pattern in the first selection signal pattern pair is configured to receive a second selection signal and is connected to the second transistor of the pixel via a second selection signal line to control whether the second light emitting element of the pixel emits light based on the second selection signal.

19. A display device comprising a display area and a non-display area arranged to surround the display area, comprising: a plurality of pixels, the plurality of pixels being arranged in the display area; a pad portion disposed in the non-display area and configured to receive a selection signal; a selection signal pattern disposed in the non-display area and connected to the pad portion; as well as A selection signal line is provided, wherein the selection signal line connects the selection signal pattern and the plurality of pixels to provide the selection signal to the plurality of pixels.

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