Apparatus and method for managing data integrity of read and write operations

Abstract

The embodiment of the invention relates to equipment and a method for managing data integrity of read and write operations. A computing device for verifying data integrity is provided that includes a memory controller configured to receive a plurality of raw data blocks. Each raw data block has an associated initial CRC value. The memory controller then segments and recombines the received data blocks into logical blocks, and computes a new logical block CRC value for each logical block. The logical block is transmitted to the storage device along with its corresponding new logical block CRC value, and the logical block is written to a non-volatile memory of the storage device in a write operation. After the write operation, a combined CRC value for the logical block and a combined CRC value for the original data block are calculated, and the combined CRC values are compared. The memory controller determines whether the combined CRC values match. When they match, the memory controller generates a verification response that verifies the integrity of the write operation.

Description

Technical Field

[0001] The present disclosure relates to the field of computers, and in particular to reading and writing operations on storage devices. Background Art

[0002] In computing, data integrity during read and write operations on storage devices is crucial in the design of storage systems. Preserving data without corruption or alteration is crucial, as any instance of data corruption can lead to significant operational and financial consequences. Despite the importance of data integrity, achieving absolute protection against data corruption is extremely challenging, primarily due to software and hardware issues. Summary of the Invention

[0003] In view of the above, a computing device for managing data integrity is provided. The computing device includes a memory controller configured to receive a plurality of original data blocks. Each original data block has an associated initial CRC value. The memory controller then segments and reassembles the received data blocks into logical blocks and generates a new logical block CRC value for each logical block. The logical blocks are transmitted to a storage device along with their corresponding new logical block CRC values, and the logical blocks are written to the non-volatile memory of the storage device during a write operation. After the write operation, the memory controller calculates a combined CRC value for the logical blocks and a combined CRC value for the original data blocks, and compares the combined CRC values. The memory controller determines whether the combined CRC values ​​match. In response to determining that the combined CRC values ​​match, the memory controller generates a verification response to verify the integrity of the write operation.

[0004] This summary is provided to introduce a series of concepts that are further described below in the detailed description in a simplified form. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. Furthermore, the claimed subject matter is not limited to implementations that solve any or all disadvantages noted in any part of this disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 A schematic diagram of a computing system for managing data integrity of write operations according to examples of the present disclosure is shown.

[0006] Figure 2 A schematic diagram of a computing system for managing data integrity of read operations according to an example of the present disclosure is shown.

[0007] Figure 3 is a flow chart of a first method for managing data integrity of write operations according to an example embodiment of the present disclosure.

[0008] Figure 4 is a flow chart of a first method for managing data integrity of a read operation according to an example embodiment of the present disclosure.

[0009] Figure 5 An example computing environment for the present disclosure is shown. DETAILED DESCRIPTION

[0010] In view of the above problems, the present disclosure describes a device and method for managing data integrity of data blocks written to a non-volatile memory of a storage device.

[0011] Software components, from applications and drivers to operating systems, can inadvertently cause memory corruption. In direct memory access (DMA) technology, widely used in contemporary memory systems, data transfers through a DMA engine (a hardware module) bypass traditional processor operations. As a result, several software-based methods for memory address space protection are rendered ineffective. Faults in software or hardware resulting in incorrect addresses can cause data to be transferred to unexpected locations, making the debugging process particularly challenging because the processor does not perform these transfers. In addition, dynamic random access memory (DRAM) is prone to a low probability of unexpected bit flips, which can cause data corruption.

[0012] In the storage industry, cyclic redundancy checks (CRCs) are the primary method for checking data integrity. CRC protection allows applications to verify the data payload and its corresponding CRC at any given time to ensure consistency. When a CRC mismatch occurs, data corruption is indicated.

[0013] However, implementing CRC protection faces several challenges. During data transmission or storage, gaps may exist in the data path, creating windows of vulnerability where data corruption may occur. Furthermore, using processing hardware to calculate CRC values ​​consumes significant processing resources.

[0014] refer to Figure 1 , computing system 10 includes a host computing device 12 that includes a memory controller 14 configured to receive a plurality of raw data blocks to write to storage device 102. In this example, four raw data blocks 18a through 18d are initially received. Each raw data block has an associated initial CRC value. The first block 18a is 5KB in size and includes an associated CRC value of CRC 0. The second block 18b is 3KB in size and includes an associated CRC value of CRC 1. The third block 18c is 9KB in size and includes an associated CRC value of CRC 2. The fourth block 18d is 3KB of padding and includes an associated CRC value of CRC 3.

[0015] The CRC value is calculated using a CRC algorithm, which works by treating the data packet to be transmitted or stored as a large polynomial represented by binary numbers. The data is divided by a predetermined fixed binary divisor, called the generator polynomial. The remainder of this division, which is the CRC value, is then appended to the data.

[0016] To perform read and write operations, the memory controller 14 may implement the Non-Volatile Memory Express (NVMe) protocol, which is used for operation of solid-state drives (SSDs) utilizing a PCIe interface. Alternatively, the memory controller 14 may implement other interfaces including SATA (Serial ATA) or SAS (Serial Attached SCSI). The memory controller 14 may also be implemented in enterprise storage solutions, including RAID (Redundant Array of Independent Disks) systems and Network Attached Storage (NAS) units.

[0017] After receiving the original data blocks 18a-18d, the memory controller 14 segments and / or reassembles the data blocks 18a-18d into logical blocks 20a-20e suitable for writing to the storage device 102. Before reassembling the data blocks 18a-18d into the logical blocks 20a-20e, the memory controller 14 may segment the data blocks 18a-18d into different sizes. In this example, a first block 18a of 5KB is segmented into a first segment of 4KB, which is merged into a first logical block 20a, and a segment of 1KB is merged into a second logical block 20b. A second data block 18b of 3KB is segmented into a third segment of 3KB, which is merged into a second logical block 20b, and a fourth segment of 8KB is merged into a third logical block 20c. The 9KB third data block 18c is divided into a 4KB fifth segment, which is merged into the third logical block 20c. The 4KB sixth segment is merged into the fourth logical block 20d, and the 1KB seventh segment is merged into the fifth logical block 20e. The 3KB-16 padded eighth segment from the fourth data block 18d is merged into the fifth logical block 20e.

[0018] It should be understood that no CRC check is performed before segmentation. In other words, no CRC value is calculated for each data block 18a to 18d to verify data integrity before generating logic blocks 20a to 20e. Therefore, memory controller 14 omits the CRC check that is conventionally performed before segmentation.

[0019] The memory controller 14 then calculates a new logical block CRC value and appends it to each logical block 20a to 20e after segmentation and reassembly, performing a single-block CRC calculation on each logical block 20a to 20e. In this example, logical block (LB) CRC 0 is calculated and appended to the first logical block 20a, LB CRC 1 is calculated and appended to the second logical block 20b, LB CRC 2 is calculated and appended to the third logical block 20c, LB CRC 3 is calculated and appended to the fourth logical block 20d, and LB CRC 4 is calculated and appended to the fifth logical block 20e. It should be understood that this is the only step in which the memory controller 14 performs a single-block CRC calculation during a write operation.

[0020] The memory controller 14 transmits the data blocks 20a-20e along with their CRC values ​​via the data bus 16 to the storage device 102 in a write command 36. In accordance with the write command 36, the memory controller 14 writes the logic blocks 20a-20e to the non-volatile memory 108 of the storage device 102.

[0021] The storage device 102 includes a processing circuit 104, firmware 106, and a data bus 110 coupled to the processing circuit 104 and a non-volatile memory 108. The processing circuit 104 can be configured to execute a write program to receive a write command 36 and execute the write command 36 on a given area of ​​the non-volatile memory 108. The processing circuit 104 is a microprocessor, which may include an application-specific integrated circuit (ASIC). The firmware 106 can be configured as permanent software programmed into a read-only memory of the storage device 102. In a specific example, the storage device 102 can be a rack-mounted storage platform including various solid-state drives.

[0022] Upon successful completion of the write operation, the storage device 102 sends a write confirmation 38, which can be a completion queue entry that includes details about the completed operation, such as a success status and any relevant identifiers. In Non-Volatile Memory Express (NVMe) and other high-performance storage interfaces, a completion queue entry consists of multiple Dwords, one or more of which can include a write confirmation 38 that includes information about the status and results of the executed write command 36. For example, the write confirmation 38 can take the form of a specific bit set within the first Dword (Dword 0) or the fourth Dword (Dword 3) that indicates a command-specific status, including a completion status and a stage bit that indicates whether the entry is a new one. The completion status can indicate the success of the write operation, the type of error encountered, or other information about the completion of the write operation.

[0023] After writing the logical blocks 20 a - 20 e to the non-volatile memory 108 of the storage device 102 , the memory controller 14 then receives a write confirmation 38 from the storage device 102 .

[0024] The memory controller 14 then combines the CRC values ​​for each of the logic blocks 20 a to 20 e to calculate a combined LB CRC value 22. Furthermore, the memory controller 14 combines the CRC values ​​for each of the original data blocks 18 a to 18 d to calculate a combined data CRC value 24. The combination of CRC values ​​may be performed by initially virtually concatenating the data blocks, respecting their order. The CRC for this concatenated virtual data block is calculated using the same CRC algorithm and polynomial as used to generate the CRC values ​​for the original data blocks 18 a to 18 d, the logic blocks 20 a to 20 e, and the combined CRC values ​​22, 24.

[0025] The memory controller 14 then compares the LB CRC value 22 with the combined data CRC value 24 and determines whether the two CRC values ​​match. In response to determining that the two CRC values ​​match, the memory controller 14 generates and outputs a verification response 40 indicating that the integrity of the write operation is verified. In response to determining that the two CRC values ​​22, 24 do not match, the memory controller 14 generates and outputs a verification response 40 warning that the integrity of the write operation is suspected to be lost.

[0026] refer to Figure 2 , details a read operation in which the computing device 12 reads logic blocks 20 c through 20 e from the non-volatile memory 108 of the storage device 102. The memory controller 14 initiates the read process by identifying specific logic blocks 20 c through 20 e to be retrieved from the non-volatile memory 108 of the storage device 102. This identification is based on the current data requirements of the computing system 10, which may be influenced by user requests, application requirements, or system processes.

[0027] Once the target logical blocks 20c to 20e are identified, the memory controller 14 issues a read command 42 to the storage device 102. The command includes the address or identifier of the logical blocks 20c to 20e to be read. The read command 42 is transmitted via the data bus 16, which connects the memory controller 14 to the storage device 102. For example, in an NVMe device, the data bus 16 can be a PCIe bus.

[0028] Upon receiving the read command 42, the storage device 102 locates the designated logical blocks 20 c through 20 e within its non-volatile memory 108. The processing circuit 104 may be configured to execute a read program to receive the read command 42 and execute the read command 42 on a given area of ​​the non-volatile memory 108. The storage device 102 then reads these logical blocks 20 c through 20 e in preparation for transmitting them back to the memory controller 14.

[0029] The storage device 102 sends the retrieved logical blocks 20c-20e back to the memory controller 14 via the data bus 110. This transmission includes not only the original data or segments from the logical blocks, but also the LB CRC values ​​used to verify the integrity of the data.

[0030] The storage device 102 sends the logical blocks 20c to 20e along with a read confirmation 44 to the memory controller 14. The read confirmation 44 may include details about the success of the read operation, such as the operation status and any errors encountered. The read confirmation 44 ensures that the data has been correctly and completely retrieved from the non-volatile memory.

[0031] In response to receiving the logical blocks 20c-20e and the read acknowledgement 44, the memory controller 14 performs a data integrity check. The memory controller 14 first strips the CRC value from each read logical block 20c-20e, thereby separating the original data or data segments from the logical block CRC value.

[0032] Memory controller 14 calculates a CRC value for the first segment of the first logical block 20c read. In this specific example, the first logical block read is block 20c, and its first segment is an 8B segment. Memory controller 14 applies a CRC algorithm to the 8B segment to determine its CRC value.

[0033] Similarly, the memory controller 14 calculates the CRC value of the last segment of the last logical block 20e read, excluding the CRC value. In this case, the last segment is the 3KB-20 pad from the logical block 20e. The memory controller 14 applies the CRC algorithm to the 3KB-20 pad to determine its CRC value.

[0034] The memory controller 14 then combines all other segments from all read logical blocks 20c to 20e (excluding the first segment 8B and the last segment 3KB-20 padding). In this example, these segments include 4KB-12, 4KB-4, and 1KB+16. The memory controller 14 calculates a CRC value for this combined set of intermediate segments.

[0035] The memory controller 14 combines the three CRC values ​​(from the first segment, the combined middle segment, and the last segment) to calculate a final combined segment CRC value 46 that represents the overall data integrity of all segments across logical blocks 20c through 20e.

[0036] At the same time, the memory controller 14 also combines the original CRC values ​​LB CRC2 , LB CRC 3 , LB CRC 4 appended to all logical blocks 20 c to 20 e read from the storage device 102 to generate a combined CRC value 48 .

[0037] The memory controller 14 then compares the combined segment CRC value 46 with the combined CRC value 48 and determines whether the two CRC values ​​match. In response to determining that the two CRC values ​​match, the memory controller 14 generates and outputs a verification response 40 indicating that the integrity of the read operation has been verified. This response 40 indicates that the data integrity of the read logical blocks 20 c to 20 e has been successfully verified, thereby confirming that the retrieved data is accurate and has not been altered. In response to determining that the two CRC values ​​46, 48 do not match, the memory controller 14 generates and outputs a verification response 40 warning that the integrity of the read operation is suspected to be lost.

[0038] Therefore, by carefully calculating and comparing CRC values ​​at different stages of the data reading process, the memory controller 14 can accurately confirm the reliability and accuracy of the data 20 c to 20 e retrieved from the storage device 102 .

[0039] After confirming the integrity of the read logic blocks 20c-20e, memory controller 14 makes the retrieved logic blocks 20c-20e available to computing device 12. This may involve placing the data into system memory or passing it directly to the requesting application or process.

[0040] It should be understood that during the read process, the memory controller 14 does not recalculate the appended CRC value for each logical block 20 c to 20 e read. For example, the memory controller 14 does not recalculate the CRC value LB CRC2 for logical block 20 c by recalculating the CRC value for the combined segments 8B and 4KB-12 in logical block 20 c. For example, for logical block 20 c, the memory controller 14 does not recalculate the CRC value for the combined segments 8B and 4KB-12 and then compare that CRC value to the LB CRC 2 value that was already appended to logical block 20 c when the memory controller 14 read the logical block 20 c.

[0041] Figure 3 A flow chart of a computerized first method 200 for managing data integrity of a write operation to write data to a non-volatile memory of a storage device is shown. The first method 200 may be performed in the above Figure 1The system is shown as being implemented on a computing system 10 that includes processing circuitry configured to implement a memory controller and associated memory. Alternatively, other suitable computing hardware and software may be used.

[0042] At 202, the method includes receiving a plurality of raw data blocks, each raw data block having an associated initial CRC value. At 204, the method includes segmenting and reassembling the received raw data blocks into logical blocks. At 206, the method includes calculating a new logical block CRC value for each logical block. At 208, the method includes transmitting the logical blocks along with their corresponding new logical block CRC values ​​to a storage device. At 210, the method includes writing the logical blocks to a non-volatile memory of the storage device in a write operation. At 212, the method includes calculating a combined CRC value for the logical blocks and a combined CRC value for the raw data blocks.

[0043] At 214, the method includes comparing the combined CRC values. At 216, the method includes determining whether the combined CRC values ​​match. At 218, the method includes generating a verification response verifying the integrity of the write operation in response to determining that the combined CRC values ​​match. At 220, the method includes outputting the verification response. At 222, the method includes generating a verification response in response to determining that the combined CRC values ​​do not match, warning of a suspected loss of integrity of the write operation. At 224, the method includes outputting the generated verification response.

[0044] Figure 4 A flow chart of a second computerized method 300 for managing data integrity of a read operation that reads data from a non-volatile memory of a storage device is shown. The second method 300 may be described in the above Figure 2 The system is shown as being implemented on a computing system 10 that includes processing circuitry configured to implement a memory controller and associated memory. Alternatively, other suitable computing hardware and software may be used.

[0045] At 302, the method includes identifying a specific logical block to be retrieved from a non-volatile memory of a storage device. At 304, the method includes issuing a read command to the storage device. At 306, the method includes receiving the logical block from the storage device. At 308, the method includes separating segments of the logical block from logical block CRC values. At 310, the method includes calculating a first CRC value for a first segment of a first logical block read. At 312, the method includes calculating a second CRC value for a last segment of a last logical block read. At 314, the method includes calculating a third CRC value that is a combination of all other CRC values ​​for the read logical blocks.

[0046] At 316, the method includes combining the first CRC value, the second CRC value, and the third CRC value to calculate a combined segment CRC value. At 318, the method includes combining the CRC values ​​appended to all original CRC values ​​of the read logical block to generate a combined CRC value. At 320, the method includes comparing the combined CRC value to the combined segment CRC value.

[0047] At 322, the method includes determining whether the combined CRC values ​​match. At 324, the method includes generating a verification response verifying the integrity of the read operation in response to determining that the combined CRC values ​​match. At 326, the method includes outputting the verification response. At 328, the method includes generating a verification response in response to determining that the combined CRC values ​​do not match, warning of a suspected loss of integrity of the read operation. At 330, the method includes outputting the generated verification response.

[0048] The above-described systems, devices, and methods enhance data integrity in storage systems by providing a reliable mechanism for verifying data integrity during read and write operations on storage devices. After segmenting the original data blocks into logical blocks for write operations, redundant CRC calculations are minimized and end-to-end data protection is ensured, thereby ensuring high reliability and accuracy during data transmission and storage.

[0049] In some embodiments, the methods and processes described herein may be associated with a computing system of one or more computing devices. In particular, such methods and processes may be implemented as computer applications or services, application programming interfaces (APIs), libraries, and / or other computer program products.

[0050] Figure 5 A non-limiting embodiment of a computing system 400 is schematically shown that can implement one or more of the above methods and processes. The computing system 400 is shown in simplified form. The computing system 400 can embody the above and Figure 1 and Figure 2 Components of computing system 400 may be included in one or more personal computers, server computers, tablet computers, home entertainment computers, network computing devices, video gaming devices, mobile computing devices, mobile communication devices (e.g., smartphones), and / or other computing devices, as well as wearable computing devices (such as smart watches and head-mounted augmented reality devices).

[0051] The computing system 400 includes a processing circuit 402, a volatile memory 404, and a non-volatile storage device 406. The computing system 400 may optionally include a display subsystem 408, an input subsystem 410, a communication subsystem 412, and / or Figure 5 Other components not shown.

[0052] The processing circuitry 402 typically includes one or more logical processors, which are physical devices configured to execute instructions. For example, a logical processor may be configured to execute instructions that are part of one or more applications, programs, routines, libraries, objects, components, data structures, or other logical constructs. Such instructions may be implemented to perform a task, implement a data type, transform the state of one or more components, achieve a technical effect, or otherwise obtain a desired result.

[0053] The logical processor may include one or more physical processors configured to execute software instructions. Additionally or alternatively, the logical processor may include one or more hardware logic circuits or firmware devices configured to execute hardware-implemented logic or firmware instructions. The processor of the processing circuit 402 may be single-core or multi-core, and the instructions executed thereon may be configured for sequential, parallel and / or distributed processing. The various components of the processing circuit may optionally be distributed in two or more separate devices, which may be remotely located and / or configured for coordinated processing. For example, various aspects of the computing system disclosed herein may be virtualized and executed by a remotely accessible networked computing device configured in a cloud computing configuration. In this case, it will be understood that these virtualized aspects run on different physical logical processors of various different machines. These different physical logical processors of different machines will be understood to be included together in the processing circuit 402.

[0054] The non-volatile storage device 406 includes one or more physical devices configured to hold instructions executable by processing circuitry to implement the methods and processes described herein. When implementing such methods and processes, the state of the non-volatile storage device 406 may be transformed, such as holding different data.

[0055] The non-volatile storage device 406 may include a removable and / or built-in physical device. The non-volatile storage device 406 may include optical memory, semiconductor memory, and / or magnetic memory, or other mass storage device technologies. The non-volatile storage device 406 may include a non-volatile, dynamic, static, read / write, read-only, sequential access, location addressable, file addressable, and / or content addressable device. It should be understood that the non-volatile storage device 406 is configured to retain instructions even when the non-volatile storage device 406 is powered off.

[0056] Volatile memory 404 may include physical devices including random access memory. Volatile memory 404 is typically used by processing circuitry 402 to temporarily store information during the processing of software instructions. It should be understood that when volatile memory 404 is powered off, volatile memory 404 typically does not continue to store instructions.

[0057] Aspects of the processing circuitry 402, volatile memory 404, and non-volatile storage device 406 may be integrated together into one or more hardware logic components. Such hardware logic components may include, for example, field programmable gate arrays (FPGAs), application specific integrated circuits (PASIC / ASICs), application specific standard products (PSSP / ASSPs), systems on chips (SOCs), and complex programmable logic devices (CPLDs).

[0058] The terms "module," "program," and "engine" may be used to describe aspects of computing system 400 that are typically implemented in software by a processor to perform a specific function using a portion of volatile memory that involves transforming processes to specifically configure the processor to perform the function. Thus, a module, program, or engine may be instantiated by executing instructions stored by non-volatile storage device 406 via processing circuitry 402 using a portion of volatile memory 404. It should be understood that different modules, programs, and / or engines may be instantiated from the same application, service, code block, object, library, routine, API, function, etc. Likewise, the same module, program, and / or engine may be instantiated by different applications, services, code blocks, objects, routines, APIs, functions, etc. The terms "module," "program," and "engine" may encompass individual or groups of executable files, data files, libraries, drivers, scripts, database records, and the like.

[0059] When included, the display subsystem 408 can be used to present a visual representation of the data stored by the non-volatile storage device 406. The visual representation can take the form of a graphical user interface (GUI). When the methods and processes described herein change the data stored by the non-volatile storage device and thus transform the state of the non-volatile storage device, the state of the display subsystem 408 can also be transformed to visually represent the changes in the underlying data. The display subsystem 408 can include one or more display devices utilizing almost any type of technology. Such a display device can be combined with the processing circuit 402, the volatile memory 404 and / or the non-volatile storage device 406 in a shared housing, or such a display device can be a peripheral display device.

[0060] When included, input subsystem 410 may include or interface with one or more user input devices, such as a keyboard, mouse, touch screen, camera, or microphone.

[0061] When included, the communication subsystem 412 can be configured to communicatively couple the various computing devices described herein to each other and to other devices. The communication subsystem 412 may include wired and / or wireless communication devices compatible with one or more different communication protocols. As non-limiting examples, the communication subsystem may be configured to communicate via a wired or wireless local or wide area network, a broadband cellular network, or the like. In some embodiments, the communication subsystem may allow the computing system 400 to send and / or receive messages to and / or from other devices via a network such as the Internet.

[0062] The following paragraphs provide additional support for the claims of the present application. One aspect provides a computing device for managing data integrity during a write operation, comprising a memory controller configured to receive a plurality of original data blocks, each original data block having an associated initial cyclic redundancy check (CRC) value; segment and reassemble the received original data blocks into logical blocks; calculate a new logical block CRC value for each logical block; transmit the logical blocks together with their corresponding new logical block CRC values ​​to a storage device; in a write operation, write the logical blocks to a non-volatile memory of the storage device; calculate a combined CRC value for the logical blocks and a combined CRC value for the original data blocks; compare the combined CRC values; determine whether the combined CRC values ​​match; and in response to determining that the combined CRC values ​​match, generate and output a verification response to verify the integrity of the write operation. In this regard, additionally or alternatively, the memory controller may perform a single block CRC calculation for only one step during the write operation. In this regard, additionally or alternatively, the memory controller may omit the CRC check before segmenting the data blocks. In this regard, additionally or alternatively, the memory controller may implement a non-volatile memory express (NVMe) protocol to perform the write operation. In this regard, additionally or alternatively, after writing the logical block to the non-volatile memory of the storage device, the memory controller may also receive a write confirmation from the storage device. In this regard, additionally or alternatively, the write confirmation may be a completion queue entry. In this regard, additionally or alternatively, the memory controller may combine the CRC values ​​of the logical block and the data block by virtually connecting the blocks in their original order and calculating the CRC of the connected virtual blocks. In this regard, additionally or alternatively, the memory controller may use the same CRC algorithm and polynomial to generate CRC values ​​for the original data block, the logical block, and the combined CRC value.

[0063] Another aspect provides a computing device for managing data integrity during a read operation, comprising a memory controller configured to identify a specific logical block to be retrieved from a non-volatile memory of a storage device; issue a read command to the storage device; receive the logical block from the storage device; separate segments of the logical block from a logical block cyclic redundancy check (CRC) value; calculate a first CRC value for a first segment of a first logical block read; calculate a second CRC value for a last segment of a last logical block read; calculate a third CRC value for a combination of all other segments from the read logical block; combine the first CRC value, the second CRC value, and the third CRC value to calculate a combined segment CRC value; combine the CRC values ​​appended to all original CRC values ​​of the read logical block to generate a combined CRC value; compare the combined CRC value to the combined segment CRC value; determine whether the two CRC values ​​match; and, in response to determining that the combined CRC value matches, generate a verification response verifying the integrity of the read operation. In this regard, the memory controller can additionally or alternatively combine the CRC values ​​of the logical blocks by virtually concatenating the blocks in their original order and calculating a CRC for the concatenated virtual blocks. In this regard, additionally or alternatively, the memory controller may use the same CRC algorithm and polynomial to generate the CRC value for the logical block and the combined CRC value. In this regard, additionally or alternatively, the memory controller may not recalculate the additional CRC value for each read logical block.

[0064] Another aspect provides a computational method for managing data integrity during a write operation, comprising receiving a plurality of original data blocks, each original data block having an associated initial cyclic redundancy check (CRC) value; segmenting and reassembling the received original data blocks into logical blocks; calculating a new logical block CRC value for each logical block; transmitting the logical blocks together with their corresponding new logical block CRC values ​​to a storage device; writing the logical blocks to a non-volatile memory of the storage device in a write operation; calculating a combined CRC value for the logical blocks and a combined CRC value for the original data blocks; comparing the combined CRC values; determining whether the combined CRC values ​​match; and generating and outputting a verification response verifying the integrity of the write operation in response to determining that the combined CRC values ​​match. In this regard, additionally or alternatively, a single-block CRC calculation is performed only for one step during the write operation. In this regard, additionally or alternatively, a CRC check can be omitted before segmenting the data blocks. In this regard, additionally or alternatively, a non-volatile memory express (NVMe) protocol can be implemented to perform the write operation. In this regard, additionally or alternatively, the method may further include receiving a write confirmation from the storage device after writing the logic block to the non-volatile memory of the storage device. In this regard, additionally or alternatively, the write confirmation may be a completion queue entry. In this regard, additionally or alternatively, the CRC values ​​for the logic block and the data block may be combined by virtually concatenating the blocks in their original order and calculating a CRC of the concatenated virtual blocks. In this regard, additionally or alternatively, the same CRC algorithm and polynomial may be used to generate the CRC values ​​for the original data block, the logic block, and the combined CRC value.

[0065] It should be understood that "and / or" as used herein is defined as an inclusive OR, as specified by the following truth table:

[0066] A B A∨B real real real real Fake real Fake real real Fake Fake Fake

[0067] It should be understood that the configuration and / or method described herein are exemplary in nature, and these specific embodiments or examples are not considered to be restrictive, because many variations are possible. The specific routines or methods described herein can represent one or more strategies in any number of processing strategies. Therefore, the various actions illustrated and / or described can be performed in the sequence illustrated and / or described, other sequences, in parallel or omitted. Likewise, the order of the above-mentioned process can be changed.

[0068] The subject matter of the present disclosure includes all novel and nonobvious combinations and subcombinations of the various processes, systems and configurations, and other features, functions, acts, and / or properties disclosed herein, as well as any and all equivalents thereof.

Claims

1. A computing device for managing data integrity during a write operation, comprising: Memory controller, configured as: receiving a plurality of original data blocks, each original data block having an associated initial cyclic redundancy check (CRC) value; Segmenting and reassembling the received original data blocks into logical blocks; Calculate a new logical block CRC value for each logical block; transmitting the logic block together with its corresponding new logic block CRC value to a storage device; In the write operation, the logic block is written to the non-volatile memory of the storage device; Calculating a combined CRC value for the logic block and a combined CRC value for the original data block; comparing the combined CRC values; determining whether the combined CRC values ​​match; and In response to determining that the combined CRC values ​​match, a verification response is generated and output, the verification response verifying the integrity of the write operation. 2 . The computing device of claim 1 , wherein the memory controller performs a single-block CRC calculation for only one step during the write operation. 3 . The computing device of claim 2 , wherein the memory controller omits a CRC check prior to the segmentation of the data block.

4. The computing device of claim 1 , wherein the memory controller implements a Non-Volatile Memory Express (NVMe) protocol to perform the write operation. 5 . The computing device of claim 1 , wherein the memory controller receives a write confirmation from the storage device after writing the logic block to the non-volatile memory of the storage device. The computing device of claim 5 , wherein the write acknowledgement is a completion queue entry. 7 . The computing device of claim 1 , wherein the memory controller combines the CRC values ​​of the logical block and the data block by virtually concatenating the blocks in their original order and calculating a CRC for the concatenated virtual blocks.

8. The computing device of claim 1, wherein the memory controller uses a same CRC algorithm and polynomial to generate CRC values ​​for the original data block, the logic block, and the combined CRC value.

9. A computing device for managing data integrity during a read operation, comprising: Memory controller, configured as: identifying a specific logical block to be retrieved from the non-volatile memory of the storage device; issuing a read command to the storage device; receiving the logic block from the storage device; Separating the segments of the logic block from the cyclic redundancy check (CRC) values ​​of the logic block; Calculating a first CRC value for the first segment of the read first logical block; Calculating a second CRC value for the last segment of the last logical block read; calculating a third CRC value for a combination of all other segments from the logical block that were read; combining the first CRC value, the second CRC value, and the third CRC value to calculate a combined segment CRC value; combining the CRC values ​​appended to all original CRC values ​​of the read logical block to generate a combined CRC value; comparing the combined CRC value with the combined segment CRC values; determining whether the two CRC values ​​match; and In response to determining that the combined CRC values ​​match, a verification response is generated, the verification response verifying the integrity of the read operation.

10. The computing device of claim 9, wherein the memory controller combines the CRC values ​​of the logical blocks by virtually connecting the blocks in their original order and calculating a CRC for the connected virtual blocks.

11. The computing device of claim 9, wherein the memory controller uses a same CRC algorithm and polynomial to generate CRC values ​​for the logic block and the combined CRC value.

12. The computing device of claim 9, wherein the memory controller does not recalculate additional CRC values ​​for each logical block read.

13. A computing method for managing data integrity during a write operation, comprising: receiving a plurality of original data blocks, each original data block having an associated initial cyclic redundancy check (CRC) value; Segmenting and reassembling the received original data blocks into logical blocks; Calculate a new logical block CRC value for each logical block; transmitting the logic block together with its corresponding new logic block CRC value to a storage device; In the write operation, the logic block is written to the non-volatile memory of the storage device; Calculating a combined CRC value for the logic block and a combined CRC value for the original data block; comparing the combined CRC values; determining whether the combined CRC values ​​match; and In response to determining that the combined CRC values ​​match, a verification response is generated and output, the verification response verifying the integrity of the write operation. The calculation method according to claim 13 , wherein a single block CRC calculation is performed only for one step during the write operation. The calculation method according to claim 14 , wherein a CRC check is omitted before the segmentation of the data block.

16. The computing method of claim 13, wherein a Non-Volatile Memory Express (NVMe) protocol is implemented to perform the write operation.

17. The calculation method according to claim 13, further comprising: After writing the logic block to the non-volatile memory of the storage device, a write confirmation is received from the storage device.

18. The computing method of claim 17, wherein the write acknowledgement is a completion queue entry.

19. The calculation method of claim 13, wherein the CRC values ​​of the logic block and the data block are combined by virtually connecting the blocks in their original order and calculating a CRC for the connected virtual blocks.

20. The calculation method of claim 13, wherein the same CRC algorithm and polynomial are used to generate CRC values ​​for the original data block, the logical block, and the combined CRC value.

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