Clock looping processing method and device

Abstract

The invention provides a clock looping processing method. The method comprises the following steps: receiving a clock synchronization message; obtaining path tracking information carried by the clock synchronization message; wherein the path tracking information comprises node identification information of each network node through which the clock synchronization message passes; and determining that the network node sending the clock synchronization message is an invalid clock source in response to the node identifier of the current network node which is included in the path tracking information. According to the invention, the formation of the clock loop can be prevented from the source, the robustness and stability of the clock synchronization network are improved, and the stability of the transmission frequency of the network equipment is ensured. The invention further provides electronic equipment, a computer readable storage medium and a computer program product.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technology, and in particular to a method and device for processing clock looping. Background Art

[0002] Clock synchronization is a critical mechanism in communication networks. By coordinating the time bases of different devices, it ensures the consistency and coordination of operations among nodes within the network. This serves as the basis for ensuring low-latency, high-reliability communication services.

[0003] However, due to the dynamic changes in communication networks, such as fiber interruptions, equipment failures, configuration change errors and many other factors, clock synchronization has a difficult problem to deal with, namely, clock loops. Clock loops can further cause many communication failures and affect the quality of network services. Related technologies have no effective solution to the clock loop problem. Summary of the Invention

[0004] The present disclosure provides a method and device for processing clock looping.

[0005] In a first aspect, an embodiment of the present disclosure provides a method for processing clock looping, including:

[0006] Receive clock synchronization messages;

[0007] Obtaining path tracing information carried by the clock synchronization message; wherein the path tracing information includes node identification information of each network node passed by the clock synchronization message;

[0008] In response to the path tracing information including the node identifier of the current network node itself, it is determined that the network node that sends the clock synchronization message is an invalid clock source.

[0009] In a second aspect, an embodiment of the present disclosure provides an electronic device, comprising a memory and a processor; the memory stores a computer program that can be executed by the processor, and the computer program implements the clock loop processing method when executed by the processor.

[0010] In a third aspect, an embodiment of the present disclosure provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the clock loop processing method is implemented.

[0011] In a fourth aspect, an embodiment of the present disclosure provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, it implements the clock loop processing method.

[0012] In the embodiment of the present disclosure, after the current network node receives a clock synchronization message, it obtains the node identification information of each network node through which the message passes by checking the path tracking information of the message. In addition, when the node identification information includes its own node identification, it determines that the network node that sends the clock synchronization message is an invalid clock source, thereby avoiding tracking the clock signal sent by itself from the source and solving the clock loop problem. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In the accompanying drawings of the embodiments of the present disclosure:

[0014] Figure 1 A schematic flow chart of the steps of a method for processing clock looping provided by an embodiment of the present disclosure;

[0015] Figure 2 A schematic diagram of the field format of path tracing information in a clock synchronization message in a clock loop processing method provided by an embodiment of the present disclosure;

[0016] Figure 3 A schematic diagram of another field format of the path tracing information in a clock synchronization message in a clock loop processing method provided by an embodiment of the present disclosure;

[0017] Figure 4 A schematic flow chart of another method for processing clock looping provided by an embodiment of the present disclosure;

[0018] Figure 5 A schematic flow chart of another method for processing clock looping provided by an embodiment of the present disclosure;

[0019] Figure 6 This is a diagram of a synchronization scenario where clock loops are likely to occur during clock synchronization.

[0020] Figure 7 This is a schematic diagram of a clock synchronization path before a failure occurs in one embodiment of the present disclosure;

[0021] Figure 8 This is a schematic diagram of a clock synchronization path after a failure occurs in one embodiment of the present disclosure;

[0022] Figure 9 This is a schematic diagram of a clock synchronization path before a failure occurs in another embodiment of the present disclosure;

[0023] Figure 10 This is a schematic diagram of a clock synchronization path after a failure occurs in another embodiment of the present disclosure;

[0024] Figure 11 This is a schematic diagram of a clock synchronization path before a failure occurs in another embodiment of the present disclosure;

[0025] Figure 12 This is a schematic diagram of a clock synchronization path after a failure occurs in another embodiment of the present disclosure;

[0026] Figure 13 A block diagram of the composition of a device for a clock loop processing method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] To enable those skilled in the art to better understand the technical solution of the present disclosure, the clock looping processing method and device provided by the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0028] The present disclosure will be described more fully hereinafter with reference to the accompanying drawings, but the illustrated embodiments may be embodied in different forms, and the present disclosure should not be construed as limited to the embodiments set forth below. Rather, these embodiments are provided so that the present disclosure will be thorough and complete and will fully understand the scope of the present disclosure to those skilled in the art.

[0029] The accompanying drawings of the embodiments of the present disclosure are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the detailed embodiments, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing the detailed embodiments with reference to the accompanying drawings.

[0030] The present disclosure may be described with reference to plan views and / or cross-sectional views by way of ideal schematic views of the present disclosure. Therefore, the exemplary illustrations may be modified according to manufacturing techniques and / or tolerances.

[0031] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0032] The terms used in this disclosure are only used to describe specific embodiments and are not intended to limit the disclosure. As used in this disclosure, the term "and / or" includes any and all combinations of one or more related enumerated items. As used in this disclosure, the singular forms "a" and "the" are also intended to include plural forms, unless the context clearly indicates otherwise. As used in this disclosure, the terms "comprising" and "made of" specify the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meanings as those commonly understood by those skilled in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined in this disclosure.

[0034] The present disclosure is not limited to the embodiments shown in the drawings, but includes modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings have schematic properties, and the shapes of the regions shown in the drawings illustrate the specific shapes of the regions of the elements, but are not intended to be limiting.

[0035] Technical terminology

[0036] In this disclosure, unless otherwise specified, the following technical terms should be understood as follows:

[0037] (1) Clock Synchronization:

[0038] Clock synchronization refers to the process of ensuring that the internal clocks of distributed network devices maintain frequency or phase consistency within a communications network. Frequency synchronization requires that all clocks run at the same rate, meaning they oscillate the same number of times per second, but their starting times may differ. Time synchronization (or phase synchronization) requires that device clocks not only have the same frequency but also closely match the absolute time they indicate, often with microsecond or even nanosecond accuracy. This process is crucial for network services that rely on precise timing, such as mobile base station handovers, financial transaction timestamping, distributed system event sequencing, and traditional time-division multiplexed voice service transmission. Lack of effective synchronization can lead to packet loss, timing disruptions, degraded service quality, and even service interruptions.

[0039] (2) Synchronous Ethernet (SyncE):

[0040] Synchronous Ethernet is a technical standard for implementing frequency synchronization at the Ethernet physical layer. Essentially, it extends the physical-layer frequency synchronization mechanisms used in traditional synchronous digital hierarchy (SDH) or optical networks to the Ethernet architecture. SyncE-enabled network devices extract a frequency reference from the upstream physical-layer signal at their receive ports and use this reference to lock their local clock oscillator using a phase-locked loop (PLL) mechanism. This precise frequency is then transmitted to downstream devices via the physical-layer signal at the device's transmit port. The core advantage of SyncE is that its synchronization mechanism is unaffected by network congestion or higher-layer protocol processing delays, providing highly stable and accurate frequency synchronization.

[0041] (3) Precision Time Protocol (PTP / IEEE 1588v2):

[0042] The Precision Time Protocol (PTP) is a network protocol standard for achieving high-precision time synchronization on packet-switched networks, such as IP-based Ethernet. The protocol exchanges specific messages carrying precise timestamps between a master and slave clocks, measures the message's transmission delay along the network path, and calculates the slave clock's time deviation and path delay relative to the master. The slave clock continuously adjusts its local time based on this calculation, ultimately achieving high synchronization with the master clock.

[0043] (4) Synchronization Status Message (SSM):

[0044] Synchronization Status Messages (SSMs) are a signaling mechanism that carries information about clock source quality levels within a synchronization network. Network devices use SSMs to announce the quality level of the clock signal they are currently tracking or generating. These quality levels follow standardized encodings, such as those defined in International Telecommunication Union (ITU) Telecommunication Standardization Sector recommendations. Downstream network devices receive SSMs from different paths and, based on a predefined selection algorithm, select the source with the highest quality level to determine the optimal clock source for tracking.

[0045] (5) Clock Ring:

[0046] Clock looping refers to an abnormal condition in a clock synchronization network, in which a network device eventually tracks its own clock signal, forming a closed, self-referencing synchronization loop. This condition typically stems from flawed network topology design or configuration errors. In a loop, lacking an external, high-precision reference source, the clock signal circulates solely within the loop and is regenerated by the devices. This results in cumulative drift in the clock frequency or phase of all devices within the loop, leading to a continuous degradation of synchronization accuracy and ultimately synchronization failure, severely impacting the normal operation of network services that rely on precise synchronization. Preventing clock looping is a core principle in the design and deployment of synchronous networks.

[0047] (6) Clock degradation:

[0048] Clock degradation refers to the process of proactively lowering the quality level of the SSM information carried in the clock signal transmitted by a network device when it detects that its primary clock source has failed or has significantly degraded. When a device loses a high-quality external reference source, it switches to a backup clock source, enters holdover mode (relying on local oscillator stability), or enters free-run mode. At this point, the device lowers the quality level of its output SSM to clearly indicate to downstream devices that the clock signal currently being provided is unreliable or of degraded quality. This mechanism is intended to prevent poor-quality clock signals from propagating across the network and being mistakenly selected, and to encourage downstream devices to select a better available clock source based on the SSM information.

[0049] (7) Clock is not available (Do Not Use, DNU):

[0050] Clock Unavailable is a specific synchronization status message quality level value that explicitly instructs receiving devices not to use clock signals from that direction as a reference source. DNU is a key mechanism for preventing clock loops. Its main application scenarios include: after a device selects the clock received on a certain port as the reference source, it immediately sends DNU on the opposite port to block potential loop paths; when the device itself does not have any available or quality-compliant clock sources, it declares DNU on all output ports; and network administrators can manually configure ports to send DNU to forcibly isolate specific clock paths. According to the protocol, receiving devices must ignore clock signals marked as DNU.

[0051] In some related technologies, the requirements for time and frequency synchronization accuracy are becoming increasingly stringent in current communication networks, especially with the evolution of new technologies such as 5G. Existing technologies mainly rely on technologies such as Synchronous Ethernet and Precision Time Protocol to ensure clock synchronization across the entire network.

[0052] However, existing technical solutions face several challenges in actual deployment and operation. First, the configuration of clock synchronization paths is complex. In large-scale network topologies, clock source selection and protection path planning rely heavily on manual configuration by network operators. This can introduce the risk of clock loops due to oversight or configuration errors.

[0053] Secondly, standard clock selection algorithms have limitations in certain network anomaly scenarios. Although the SSM-based algorithm defines priority source selection rules based on clock quality levels, when the network undergoes dynamic changes, such as fiber breaks or equipment failures, the automated clock source switching mechanism may inadvertently create clock loops, especially in complex topologies with multiple redundant protection paths.

[0054] Once a clock loop occurs, it can have serious consequences. The clock frequency within the loop rapidly degrades due to the continuous accumulation of errors, causing frequent up / down interruptions on network device ports and impacting service stability. For applications that rely on high-precision time synchronization, such as 5G base stations, clock frequency degradation can cause time synchronization deviations to exceed the tolerable range, potentially leading to serious failures such as base station outages.

[0055] Furthermore, due to the potential risk of clock loops, network designers often adopt a conservative strategy when deploying clock protection paths, making it difficult to deploy multiple effective backup clock paths simultaneously. This reduces network redundancy and reliability. If the primary clock source fails, some network nodes may become "clock islands" due to the lack of a backup clock source.

[0056] It can be seen that the existing technology lacks a mechanism that can reliably detect and break clock loops when the network changes dynamically.

[0057] First, refer to Figure 1 The present disclosure provides a method for processing clock loops, which is applied to a current network node. The network node may be a router, a switch, or other electronic device in a network with clock synchronization capabilities. The present disclosure does not limit this method. The method includes the following steps:

[0058] Step 110: Receive a clock synchronization message.

[0059] The clock synchronization message may be a data message transmitted between network nodes for synchronizing frequency or time. For example, the clock synchronization message may be a message carrying Synchronization Status Message (SSM) information in Synchronous Ethernet (SyncE), or a Sync or Announce message in the IEEE 1588v2 protocol. This disclosure is not limited to this.

[0060] Step 120: Acquire path tracing information carried by the clock synchronization message; wherein the path tracing information includes node identification information of each network node passed by the clock synchronization message.

[0061] In the disclosed embodiments, path tracing information can be represented by a data structure attached to a clock synchronization message. This data structure dynamically records the node identification information of a series of network nodes that the clock synchronization message passes through after being sent from the source. In other words, the path tracing information represents the path history of the clock synchronization message. Each node identification information is an identifier that uniquely identifies the network node in the network and is unique within the network.

[0062] Step 130: In response to the path tracing information including the node identifier of the current network node, determine that the network node that sends the clock synchronization message is an invalid clock source.

[0063] The invalid clock source refers to a clock source that is determined by the current network node to not be used for synchronization. In this embodiment, it refers to a source that is determined to be invalid in order to avoid forming a clock loop.

[0064] In this step, the current network node checks the path tracing information carried in the received clock synchronization message to determine whether the message has passed through it. If its node identification information is found, it determines that tracing the clock synchronization message will form a clock loop. Therefore, the network node that sent the clock synchronization message is considered an invalid clock source to avoid loops.

[0065] Illustratively, in one embodiment of the present disclosure, the current network node performs clock ringing processing through the following steps:

[0066] ① Receiving and monitoring

[0067] One or more ports of the current network node listens to and receives clock synchronization messages from upstream or adjacent nodes.

[0068] ②Information extraction

[0069] After receiving a clock synchronization message, the processor or dedicated hardware logic of the current network node parses the clock synchronization message and extracts path tracking information from it. This information usually contains a list of one or more node identifiers.

[0070] ③Self-inspection and comparison

[0071] The node compares its pre-stored node identification information with each node identification in the path tracking information list.

[0072] ④ Loop determination and processing

[0073] Case 1 (Loop Detected): If, during the comparison process, a matching entry is found in the path tracing information list with the node's own ID, the node determines that tracing the peer network node (or corresponding port) that sent the clock synchronization message would result in a clock loop. In this case, the node identifies the peer network node (or corresponding port) that sent the message as an invalid clock source and may refuse to follow the source-synchronized clock.

[0074] Case 2 (no loop detected): If no node identifier of the node itself is found after comparing the entire list, it is considered that the path from the clock source is currently loop-free and can be used as a valid alternative clock source.

[0075] In the disclosed embodiments, each network node is equipped with the ability to proactively perform loop self-detection, enabling it to identify "clock looping" signals. This node-independent detection mechanism can block loops at the point of formation, preventing them from continuing to propagate and causing wider network impact. Clearly, the methods of the disclosed embodiments help resolve clock looping issues caused by factors such as abnormal network switching or configuration errors, thereby improving the robustness and stability of clock synchronization networks.

[0076] In some embodiments of the present disclosure, the path tracing information further includes a hop count, where the hop count is used to indicate the number of network nodes that the clock synchronization message has passed through.

[0077] This embodiment expands the functionality of the path tracing information. Based on the node identification information, a "hop count" is added to quantify the path length. The hop count represents the total number of network nodes that the clock synchronization message has passed from the initial source to the current network node.

[0078] In one embodiment, when a network node, acting as a clock source, first generates a clock synchronization message carrying path tracing information, it can set the initial hop count to 0 or 1. When any intermediate network node in the network receives the message, completes loop detection, and does not find its own identity, if it decides to select this clock and forward it downstream, it will perform the following two related actions:

[0079] First, the node identification information is updated. Specifically, the node identification information is appended to the existing node identification information in the path tracing information. Then, the current network node updates the hop count, that is, the hop count in the message is increased by 1.

[0080] For example, a message with an initial hop count of 1 becomes 2 after being forwarded by the first intermediate node; after being forwarded by the second intermediate node, the hop count becomes 3, and so on.

[0081] In the disclosed embodiments, adding "hop count" provides network management with intuitive, quantitative data on the length of clock synchronization paths, facilitating network monitoring and troubleshooting. Hop count can also serve as an auxiliary criterion in clock source selection algorithms. For example, among multiple valid clock sources of the same quality level, a node may prioritize paths with fewer hops, as this typically results in shorter transmission delays and smaller cumulative errors.

[0082] In some embodiments of the present disclosure, the path tracing information may be encapsulated in a preset field of the clock synchronization message. Encapsulating the path tracing information in the preset field can better ensure that the clock loop processing method of the present disclosure has better compatibility and scalability.

[0083] There are many specific implementation methods. For example, the path tracking information can be encapsulated in a preset field in TLV (Type-Length-Value) format. In one embodiment;

[0084] A new Type value can be set to represent path tracing information, with the "Length" field specifying the data length and the Value field storing the specific node ID list and hop count. The TLV field can be appended to the end of the standard clock message. Legacy devices that do not recognize this TLV type can ignore it without affecting their normal operation.

[0085] In other embodiments of the present disclosure, path tracing information can also be encapsulated in preset fields using reserved fields or optional headers. For example, in some communication protocols, the message format may reserve some reserved fields or define optional extension headers. Therefore, when implementing the embodiments of the present disclosure, these preset extension spaces can be used to carry path tracing information. The embodiments of the present disclosure only provide two exemplary implementations, and those skilled in the art will understand that the embodiments of the present disclosure are not limited to these.

[0086] It can be seen that the embodiments of the present disclosure help improve the deployability and backward compatibility of the solution by encapsulating path tracing information in a preset field of the clock synchronization message. Specifically, by encapsulating the newly added information in an independent preset field such as a TLV field, this can be achieved without modifying the existing message body structure, for example, without modifying protocols such as SyncE or 1588v2. This means that devices that support this method can coexist with legacy devices that do not support it in the same network, and the network can be upgraded smoothly and gradually, thereby ensuring the practical feasibility of the technical solution.

[0087] In some embodiments of the present disclosure, the node identification information is flexibly selected according to the specific architecture and management mode of the network. For example, the node identification information can be the MAC address of the network node, the IP address of the network node, or the node clock identification configured by the user for the network node. The specific description is as follows:

[0088] MAC address is the media access control address, which is a hardware address fixed on the network interface card. It works at the data link layer and is suitable for node identification in an Ethernet switching environment.

[0089] An IP address is an Internet Protocol address, a logical address at the network layer. In a routing environment spanning multiple subnets, an IP address can be used as a node identifier.

[0090] For example, referring to Figure 2 , the node identification information can be a MAC address, Figure 2A schematic diagram showing the field format of path tracing information in a clock synchronization message is shown.

[0091] Among them, the node identifier of network node 1 is 00:1A:2B:3C:4D:0A, the node identifier of network node 2 is 00:1A:2B:3C:4D:0B, ..., the node identifier of network node N is 00:1A:2B:3C:4D:17, and the number of hops passed by the clock synchronization message is n.

[0092] For example, referring to Figure 3 , the node identification information is the node clock identification configured by the user for the network node, Figure 2 A schematic diagram showing the field format of path tracing information in a clock synchronization message is shown.

[0093] The node identifier of network node 1 is 00 00 00 0A, the node identifier of network node 2 is 00 00000B, ..., the node identifier of network node N is 00 00 00 17, and the number of hops passed by the clock synchronization message is n.

[0094] The node clock identifier configured for a network node is an identifier that is manually configured by the network administrator or automatically assigned by the network management system. This method is decoupled from the physical address or network address of the device, providing management flexibility.

[0095] It is understandable to those skilled in the art that various device identification methods involving data link layer, network layer, and user customization may be adopted, and the embodiments of the present disclosure do not limit the specific form of the node identification information.

[0096] In a specific network deployment of an embodiment of the present disclosure, all network nodes participating in clock synchronization should agree to use the same type of node identifier to ensure the effectiveness of the comparison.

[0097] The node identifiers in the disclosed embodiments can cover several types of identifiers, including MAC addresses, IP addresses, and configurable IDs, ensuring that the loop detection logic of this method can find appropriate identity identifiers to implement, whether in a Layer 2 switching network, a Layer 3 routing network, or a dedicated network with special management requirements, and can adapt to a variety of network environments.

[0098] Reference Figure 4 , Figure 4 A flowchart of another method for processing clock looping provided in an embodiment of the present disclosure includes the following steps:

[0099] Step 410, receiving a clock synchronization message;

[0100] Step 420: Acquire path tracing information carried by the clock synchronization message; wherein the path tracing information includes node identification information of each network node passed by the clock synchronization message;

[0101] Step 430, determining whether the path tracing information includes the node identifier of the current network node itself;

[0102] Step 440A: If yes, determine that the network node that sends the clock synchronization message is an invalid clock source.

[0103] Step 440B: If not, perform clock synchronization based on the clock synchronization message.

[0104] In this example, steps 410 to 440A are similar to the implementation of steps 110 to 130 in the aforementioned embodiment, and the relevant parts can be referred to the aforementioned description.

[0105] This disclosed embodiment adds an operation 440B, parallel to step 440A, to handle clock synchronization when the path tracing information does not include the current network node's own node identifier. In other words, while step 430 determines a "loop" for clock synchronization, step 440B represents a "non-loop" process: if the current network node confirms that the received clock message path does not include itself, it follows the normal clock synchronization process.

[0106] More specifically, after the current network node completes the self-check and comparison of the path tracing information, it can perform the following operations:

[0107] ① If the node does not find its own node ID, it determines that the clock source is loop-free on the current path;

[0108] ②Then, the “loopless” clock source is considered as a candidate valid clock source;

[0109] ③ The current network node will compare it with all other candidate valid clock sources in its standard clock source selection algorithm (for example, based on SSM quality level, priority, etc.);

[0110] ④ Ultimately, the node will select a valid clock source to track and synchronize with, and update its own local clock based on this source.

[0111] It can be seen from this embodiment that the loop detection mechanism is a mechanism for handling abnormal situations and will not interfere with the normal clock synchronization function. This ensures that the clock synchronization system can operate stably during most of the time when the network is loop-free.

[0112] Reference Figure 5 , Figure 5 A flowchart of another method for processing clock looping provided in an embodiment of the present disclosure includes the following steps:

[0113] Step 510, receiving a clock synchronization message;

[0114] Step 520: Acquire path tracing information carried by the clock synchronization message; wherein the path tracing information includes node identification information of each network node passed by the clock synchronization message;

[0115] Step 530: In response to the path tracing information including the node identifier of the current network node, determining that the network node that sends the clock synchronization message is an invalid clock source;

[0116] Step 540: triggering the current network node to reselect an available valid clock source;

[0117] Step 550: Determine whether the current network node has an available valid clock source;

[0118] In the embodiment of the present disclosure, when all neighboring nodes of the current network node send target messages, it is determined that the current network node has no available valid clock source.

[0119] Among them, the target message can be target synchronization status information, which is used to indicate that the clock signal of the network node sending the information is prohibited from being used as a clock source. For example, in the SSM mechanism, if the other party's SSM message is not received within 5 seconds, the line clock signal SSM is considered to be DNU; on the other hand, the target message can also be a clock synchronization message carrying the identification information of the current network node.

[0120] Step 560A: If not, perform clock degradation processing on the current network node.

[0121] Clock degradation refers to a state in which a network node, after losing all valid external clock references, proactively lowers the quality of its broadcast clock. For example, in SyncE, a node might send SSM messages with the lowest quality level, such as DNU, or enter holdover mode.

[0122] Step 560B: If yes, track available valid clock sources.

[0123] As can be seen, this embodiment exemplifies a further exception handling process. Specifically, when a network node determines a source is invalid and no other valid clock source is available, the node should proactively downgrade the clock to prevent the fault from spreading. Of course, if a valid clock source exists, switching can be sufficient.

[0124] More specifically, the current network node can handle exceptions through the following steps:

[0125] ① Determine invalid source

[0126] The current network node first marks a clock source forming a loop as invalid according to steps 510 to 530.

[0127] In this example, steps 510 to 530 are similar to the implementation of steps 110 to 130 in the aforementioned embodiment, and the relevant parts can be referred to the aforementioned description.

[0128] ②Evaluate available sources

[0129] The node then checks all other potential clock sources. The conditions for a node to be judged as "no valid clock source available" may include one or more of the following:

[0130] For example, the path tracing information of clock messages received by all other ports also includes the current node's own identification.

[0131] For example, the neighboring node of the other port is sending DNU (clock unavailable) information.

[0132] In some embodiments, when the quality levels of all remaining clock sources are lower than the availability threshold set by the system, it may also be determined that there is no available valid clock source.

[0133] ③ Triggering degradation

[0134] Once it is confirmed that there is no valid clock source available, the node triggers clock degradation processing. It adjusts the clock synchronization message it sends to the downstream node and clearly indicates in the message that its clock quality has degraded.

[0135] The disclosed embodiments include a fault isolation step for clock degradation. When a network node loses its valid upstream reference due to a loop, without degradation, it may continue to broadcast a seemingly "high-quality" clock signal downstream based on its unstable internal crystal oscillator, potentially causing incorrect frequency or time information to propagate across the network. By actively degrading, the network node can notify all downstream devices not to use it as a reference, thereby localizing the fault, helping to prevent the spread of loop faults and ensuring overall network stability.

[0136] In one embodiment of the present disclosure, if the target network node that the current network node is tracking for clock synchronization is degraded, it is possible to switch to an available valid clock source according to the clock priority.

[0137] More specifically, in the process of the current network node tracking its target network node, the following processing may be performed:

[0138] ① Perception degradation

[0139] The current network node continuously receives clock synchronization messages from the target network node. When it detects a change in the clock quality level information in the message, indicating that the target node has entered a degraded state (for example, receiving a DNU signal), it can remove the target network node from its current valid clock source.

[0140] ②Reselect source

[0141] The current network node then triggers a new clock source selection process.

[0142] ③Switch by priority

[0143] The node queries its pre-configured clock source priority list and checks the backup clock sources in the list in descending order.

[0144] ④Switch to available valid source

[0145] The backup clock source with the highest priority and the current status of "Available" and "Valid" is selected, and the system locks on this source for clock synchronization. "Available" and "Valid" here must include at least "No ring formed".

[0146] Similarly, if the downstream network node of the current network node, that is, the tracking node that tracks the current network node, senses that the clock of its target node (that is, the current network node) has degraded, it will also perform the above-mentioned steps of reselecting the source, switching according to priority, and switching to an available valid source.

[0147] As can be seen, this embodiment includes an automatic network recovery mechanism after a localized fault occurs, establishing a "fault detection → fault isolation → fault recovery" processing chain, enabling the network to self-repair after a loop fault. Through a priority-based switching strategy, the network can reestablish legitimate clock synchronization paths in an orderly manner. This helps ensure the convergence speed and ultimate stability of the network during dynamic changes.

[0148] The following further describes an embodiment of the disclosed clock loop processing method.

[0149] First, combine Figure 6 , further explains a synchronization scenario where clock loops are likely to occur.

[0150] Nodes A and B use two pairs of optical fibers for clock extraction and user clock protection. Nodes A and D use one pair of optical fibers for clock extraction and clock protection.

[0151] The standard SSM clock synchronization algorithm specifies that the clock source selection order is: blocking / locking > forced switching > alarm > clock level > manual switching > priority. Meanwhile, when a downstream device tracks the clock of an upstream device, it will return a DNU (Drawing Unavailable) signal.

[0152] Clock deployment in the network strictly relies on engineering and maintenance personnel. In complex networking scenarios, configuration errors are inevitable. At the same time, to increase clock protection paths, network clock deployment may involve configuring clock pullback of neighboring network elements, or configuring clock pullback between neighboring network elements using two pairs of optical fibers.

[0153] At this time, the master clock server in the network sends the G.811 clock to the outside. If the clock server degrades, or a fiber break occurs in the network, a clock alarm occurs, or the user changes the clock, it will trigger a network clock switch, which is likely to trigger a clock loop. Figure 6 As shown: a clock loop is caused between ABA network elements, or a clock loop is caused between ABCDA network elements. Figure 6 The arrows in the figure indicate the direction of clock configuration extraction, and ① / ② / ③ indicate the clock configuration priority.

[0154] [Example 1]

[0155] In this embodiment, the network topology includes network nodes A, B, C, and D. Node A initially tracks a master clock server. Node A initially tracks a master clock server.

[0156] In this embodiment, the node identification information uses a MAC address.

[0157] For example,

[0158] The MAC address of node A is: 00:1A:2B:3C:4D:0A.

[0159] The MAC address of node B is: 00:1A:2B:3C:4D:0B,

[0160] The MAC address of node C is: 00:1A:2B:3C:4D:0C,

[0161] The MAC address of node D is: 00:1A:2B:3C:4D:0D.

[0162] like Figure 2 As shown in the figure, the clock message tail is extended to add the TLV field. The node number n in the TLV field represents the number of hops for clock transmission. The value of n increases by 1 for each additional hop.

[0163] In a stable state, the clock signal flows from the master clock server to A, and then sequentially passes through nodes B, C, and D. When node D sends a clock synchronization message to its downstream, the message's path tracing information includes a hop count field (n=4) and a list of the MAC addresses of nodes A, B, C, and D.

[0164] For example, Figure 7 As shown in the figure, after node A chooses to track the clock of the master clock server, the message sent by node A to all downstream nodes is:

[0165] Ethernet message header + clock message + 01 + 00 1A 2B 3C 4D 0A;

[0166] Similarly, after node D chooses to track the clock of node C, the message sent by node D to all downstream nodes is:

[0167] Ethernet packet header + clock packet + 04 + 00 1A 2B 3C 4D 0A + 00 1A 2B 3C 4D 0B + 00 1A 2B3C 4D 0C + 00 1A 2B 3C 4D 0D.

[0168] When the network fiber is disconnected or the clock quality is degraded between node A and the master clock server, Figure 8 shown.

[0169] Node A loses its primary clock source, triggering a clock source switch. Node A's backup clock source might include the clock from downstream node D, via a physical backhaul link. Node A receives the clock synchronization message from node D and extracts the path tracing information. Because node D's clock originally originated from node A, the path information necessarily includes node A's own MAC address.

[0170] Node A then identifies the existence of its own MAC address by checking the path tracing information, and thus determines that the clock source from node D is an invalid clock source because it will form a clock loop of A→B→C→D→A.

[0171] On the other hand, since node B is tracking the clock of node A, node A receives a clock message from node B containing DNU (clock unavailable), so node A is not allowed to track the clock of node B either.

[0172] From the above analysis, it can be seen that node A has no other clock to choose from, so the clock degradation of node A is triggered, and the original clock information passing through node A in the network disappears.

[0173] Next, downstream node B detects that the clock of node A, which it is tracking, has degraded. This event triggers node B to switch clock sources according to its preset clock priority list. Node B switches to a reliable backup clock server and stops sending DNU back to A. Node A then switches its clock to tracking node B.

[0174] It can be understood that the clock synchronization network successfully avoids clock loops and quickly converges to a new stable state through the spontaneous detection, isolation, and recovery process of this embodiment.

[0175] Supplementary explanation, adaptively, in Figure 7 and Figure 8 In the figure, the solid arrow indicates the clock synchronization direction, the dotted arrow indicates the backup clock synchronization direction, and ① / ② / ③ indicate the clock configuration priority.

[0176] [Example 2]

[0177] This embodiment adopts a linear topology similar to that of Embodiment 1, but two DNUs are configured between nodes A and B.

[0178] As in Example 1, in this embodiment, the network topology includes network nodes A, B, C, and D. Node A initially tracks a master clock server. Node A initially tracks a master clock server.

[0179] In this embodiment, the node identification information uses a MAC address.

[0180] For example,

[0181] The MAC address of node A is: 00:1A:2B:3C:4D:0A.

[0182] The MAC address of node B is: 00:1A:2B:3C:4D:0B,

[0183] The MAC address of node C is: 00:1A:2B:3C:4D:0C.

[0184] The MAC address of node D is: 00:1A:2B:3C:4D:0D.

[0185] like Figure 2 As shown in the figure, the clock message tail is extended to add the TLV field. The node number n in the TLV field represents the number of hops for clock transmission. The value of n increases by 1 for each additional hop.

[0186] After a stable clock transmission path is formed, such as Figure 9 As shown:

[0187] After node A chooses to track the clock source server's clock, the message it sends to all downstream nodes should be:

[0188] Ethernet message header + clock message + 01 + 00 1A 2B 3C 4D 0A;

[0189] Similarly, after node D chooses to track the clock of node C, the message sent by node D to all downstream nodes should be:

[0190] Ethernet packet header + clock packet + 04 + 00 1A 2B 3C 4D 0A + 00 1A 2B 3C 4D 0B + 00 1A 2B3C 4D 0C + 00 1A 2B 3C 4D 0D.

[0191] When the network fiber is disconnected or the clock quality is degraded between node A and the master clock server, Figure 10 shown.

[0192] Node A detects that the master clock server's clock is lost or degraded, triggering a clock switch based on the source selection criteria. At this point, Node B is synchronizing with Node A's clock. The clock sent by Node B carries Node A's MAC information, making Node A's second-priority clock unavailable and prohibiting Node A from tracking Node B's clock. Simultaneously, Node A receives a clock from Node D, which also carries Node A's MAC information. This leaves Node A with no other clocks to choose from, triggering clock degradation. The original clock information passing through NE A in the network disappears. Node B then discovers that its own clock has degraded and switches to tracking the backup clock server with the second-priority clock. The clock information sent to NE A no longer carries Node A's MAC address, and Node A's clock switches to tracking Node B via the second-priority clock.

[0193] In other words, Node A evaluates not only the clock from Node D but also the clock from Node B. Because Node B is currently tracking Node A, the clock message it sends back to Node A also carries path tracing information containing Node A's own MAC address. Therefore, Node A determines that the clock sources from both Node B and Node D are invalid.

[0194] As can be seen, the method disclosed herein does not rely solely on the sending and receiving of DNU messages, but instead makes decisions by directly examining the path information in the message content. This makes the loop detection mechanism more reliable and robust, effectively preventing loops even in the event of improper DNU configuration or failure.

[0195] Supplementary explanation, adaptively, in Figure 9 and Figure 10 In the figure, the solid arrow indicates the clock synchronization direction, the dotted arrow indicates the backup clock synchronization direction, and ① / ② / ③ indicate the clock configuration priority.

[0196] [Example 3]

[0197] In this embodiment, the network topology includes network nodes A, B, C, and D. Node A initially tracks a master clock server.

[0198] In this embodiment, the node identification information uses a configuration identifier. For example, the network administrator configures a globally unique node clock ID for each node.

[0199] For example,

[0200] The configuration identifier of node A is: 00 00 00 0A,

[0201] The configuration identifier of node B is: 00 00 00 0B,

[0202] The configuration identifier of node C is: 00 00 00 0C,

[0203] The configuration identifier of node D is: 00 00 00 0D.

[0204] like Figure 3 As shown in the figure, the clock message tail is extended to add the TLV field. The node number n in the TLV field represents the number of hops for clock transmission. The value of n increases by 1 for each additional hop.

[0205] In a stable state, the clock signal flows from the master clock server to A, and then sequentially passes through nodes B, C, and D. When node D sends a clock synchronization message to its downstream, the message's path tracing information includes a hop count field (n=4) and a list of the configuration identifiers of nodes A, B, C, and D.

[0206] For example, Figure 7 As shown in the figure, after node A chooses to track the clock of the master clock server, the message sent by node A to all downstream nodes is:

[0207] Ethernet message header + clock message + 01 + 00 00 00 0A;

[0208] Similarly, after node D chooses to track the clock of node C, the message sent by node D to all downstream nodes is:

[0209] Ethernet packet header + clock packet + 04 + 00 00 00 0A + 00 00 00 0B + 00 00 00 0C + 00 00000D.

[0210] When the network fiber is disconnected or the clock quality is degraded between node A and the master clock server, Figure 8 shown.

[0211] Node A loses its primary clock source, triggering a clock source switch. Node A's backup clock source might include the clock from downstream node D, via a physical backhaul link. Node A receives a clock synchronization message from node D and extracts the path tracing information. Because node D's clock originally originated from node A, the path information necessarily includes node A's configuration identifier.

[0212] Therefore, node A identifies the existence of its own configuration identifier by checking the path tracing information, and thus determines that the clock source from node D is an invalid clock source because it will form a clock loop of A→B→C→D→A.

[0213] On the other hand, since node B is tracking the clock of node A, node A receives a clock message from node B containing DNU (clock unavailable), so node A is not allowed to track the clock of node B either.

[0214] From the above analysis, it can be seen that node A has no other clock to choose from, so the clock degradation of node A is triggered, and the original clock information passing through node A in the network disappears.

[0215] Next, downstream node B detects that the clock of node A, which it is tracking, has degraded. This event triggers node B to switch clock sources according to its preset clock priority list. Node B switches to a reliable backup clock server and stops sending DNU back to A. Node A then switches its clock to tracking node B.

[0216] It can be understood that the clock synchronization network successfully avoids clock loops and quickly converges to a new stable state through the spontaneous detection, isolation, and recovery process of this embodiment.

[0217] It can be seen that the network topology and failure scenarios of this embodiment are the same as those of Example 1. The difference is that the nodes in the network do not use MAC addresses as identification. Instead, the network administrator configures a globally unique node clock ID for each node. Furthermore, it can be seen that the embodiment of the present disclosure has good universality. Its loop breaking logic does not rely on specific hardware addresses and can flexibly adapt to different network management requirements through software configuration.

[0218] [Example 4]

[0219] Compared to Examples 1, 2, and 3, this example is a more complex network. Its schematic network topology includes nine network nodes: A, B, C, D, E, F, G, H, and I. Node A initially tracks a master clock server.

[0220] In this embodiment, the node identification information uses a MAC address.

[0221] For example,

[0222] The MAC address of node A is: 00:1A:2B:3C:4D:0A.

[0223] The MAC address of node B is: 00:1A:2B:3C:4D:0B,

[0224] The MAC address of node C is: 00:1A:2B:3C:4D:0C.

[0225] ...and so on

[0226] The MAC address of node H is: 00:1A:2B:3C:4D:11,

[0227] The MAC address of node 1 is: 00:1A:2B:3C:4D:12.

[0228] like Figure 2 As shown in the figure, the clock message tail is extended to add the TLV field. The node number n in the TLV field represents the number of hops for clock transmission. The value of n increases by 1 for each additional hop.

[0229] After a stable clock transmission path is formed, such as Figure 11 As shown:

[0230] After node E chooses to track node F's clock, the message it sends to node D should be:

[0231] Ethernet packet header + clock packet + 08 + 00 1A 2B 3C 4D 0A + 00 1A 2B 3C 4D 0B + 00 1A 2B 3C 4D 0C + 00 1A 2B 3C 4D 12 + 00 1A 2B 3C 4D 11 + 00 1A 2B 3C 4D 10 + 00 1A 2B 3C 4D 0F + 00 1A 2B 3C 4D 0E.

[0232] When the main clock path of node C is disconnected or the clock quality is degraded, Figure 12 shown.

[0233] Node C detects a fiber break (node ​​C's priority 1 clock is lost). Node D then sends a DNU to node C. Node C has no available clock source, and node C degrades.

[0234] Node D discovers that the priority 1 clock has degraded and starts tracking the priority 2 clock from network element E. The clock sent by node D to node C carries node C's MAC address, so node C cannot track the priority 2 clock from network element D. Node C remains in the degraded state.

[0235] Until node E degrades, that is, the second-priority clock received by node D degrades, node D tracks node A through the third-priority clock, and node C tracks node D through the second-priority clock, and the clocks reach a stable state.

[0236] As can be seen, through a series of distributed, locally informed decisions, this embodiment ultimately leads the network to a stable, loop-free path. For example, node D eventually switches to tracking node A, which has a lower priority but a legitimate path. Once node D's clock stabilizes, node C can safely switch to tracking node D, and the clock synchronization of the entire network ultimately reaches a new, loop-free, stable state. This embodiment fully demonstrates that the disclosed embodiments can make correct decisions in a complex chain reaction involving multiple nodes and multiple paths, guiding the network to achieve spontaneous convergence.

[0237] Supplementary explanation, schematically, in Figure 11 and Figure 12 In the figure, the solid arrow indicates the clock synchronization direction, the dotted arrow indicates the backup clock synchronization direction, and ① / ② / ③ indicate the clock configuration priority.

[0238] In a second aspect, the disclosed embodiment provides an electronic device, referring to Figure 13 , which includes a memory and a processor; the memory stores a computer program that can be executed by the processor, and when the computer program is executed by the processor, it implements any of the clock loop processing methods described above.

[0239] In a third aspect, the disclosed embodiment provides a computer-readable medium having a computer program stored thereon, wherein the computer program, when executed by the processor, implements any one of the aforementioned methods and devices for processing clock looping.

[0240] In a fourth aspect, the disclosed embodiments provide a computer program product, comprising a computer program, which, when executed by the processor, implements any one of the aforementioned methods and devices for processing clock looping.

[0241] Among them, the processor is a device with data processing capabilities, including but not limited to the central processing unit (CPU); the memory is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically such as SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and flash memory (FLASH); the I / O interface (read-write interface) is connected between the processor and the memory, which can realize information exchange between the memory and the processor, including but not limited to the data bus (Bus), etc.

[0242] Those skilled in the art will appreciate that all or some of the steps, systems, and functional modules / units in the apparatus disclosed above may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0243] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation.

[0244] Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit (CPU), a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As is well known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH) or other disk storage; compact disc (CD-ROM), digital versatile disc (DVD) or other optical disc storage; magnetic cassettes, tapes, disk storage or other magnetic storage; any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, as is well known to those skilled in the art, communication media typically embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0245] The present disclosure has disclosed example embodiments, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly indicated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A method for processing clock looping, characterized in that: include: Receive clock synchronization messages; Obtaining path tracing information carried by the clock synchronization message; wherein the path tracing information includes node identification information of each network node passed by the clock synchronization message; In response to the path tracing information including the node identifier of the current network node itself, it is determined that the network node that sends the clock synchronization message is an invalid clock source.

2. The processing method according to claim 1, wherein The path tracing information further includes a hop count, where the hop count is used to indicate the number of network nodes that the clock synchronization message has passed through.

3. The processing method according to claim 1 or 2, wherein: The path tracing information is encapsulated in a preset field of the clock synchronization message.

4. The processing method according to claim 1, wherein: The node identification information is one of the following: The MAC address of the network node; The IP address of the network node; The node clock identifier configured for the network node.

5. The processing method according to claim 1, wherein: After obtaining the path tracing information carried by the clock synchronization message, the method further includes: In response to the path tracing information not including the node identifier of the current network node itself, clock synchronization is performed based on the clock synchronization message.

6. The processing method according to claim 1, wherein: After determining that the network node sending the clock synchronization message is an invalid clock source, the method further includes: Triggering the current network node to reselect an available valid clock source; In response to the current network node having no available valid clock source, performing clock degradation processing on the current network node; In which, in response to the target message sent by all adjacent nodes of the current network node, it is determined that the current network node has no available valid clock source; the target message includes target synchronization status information or a clock synchronization message carrying the identification information of the current network node, and the target synchronization status information is used to indicate that the clock signal of the network node sending the information is prohibited from being used as a clock source.

7. The processing method according to claim 1, wherein: The method further comprises: In response to the target network node performing clock degradation processing, switching to an available valid clock source according to the clock priority; The target network node is a tracking network node for clock synchronization of the current network node.

8. An electronic device comprising a memory and a processor; the memory stores a computer program that can be executed by the processor, and when the computer program is executed by the processor, it implements the clock loop processing method described in any one of claims 1 to 7.

9. A computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the clock loop processing method according to any one of claims 1 to 7 is implemented.

10. A computer program product comprising a computer program, wherein when the computer program is executed by a processor, the clock looping processing method according to any one of claims 1 to 7 is implemented.

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