Bandwidth scheduling method and related device

Abstract

The invention provides a bandwidth scheduling method and a related device, which are used for guaranteeing rapid transmission of high-priority data. The method comprises the following steps: determining a to-be-transmitted data packet corresponding to at least one transmission node; based on packet header information of each to-be-transmitted data packet, obtaining a time delay requirement of each to-be-transmitted data packet, the packet header information comprising a time delay requirement and a data packet identifier of the corresponding data packet; obtaining first bandwidth state information, wherein the bandwidth state information is used for reflecting the load condition of each transmission node in a first time period; determining a first bandwidth scheduling scheme based on the delay requirement of each to-be-transmitted data packet and the first bandwidth state information; and transmitting the to-be-transmitted data packet based on the first bandwidth scheduling scheme.

Description

Technical Field

[0001] The present application relates to the field of data processing, and in particular to a bandwidth scheduling method and related devices. Background Art

[0002] In recent years, with the advancement of chip technology and the increasing demand for system integration, heterogeneous integration and multi-core heterogeneous computing have gradually become mainstream architectures. The open-source RISC-V architecture, based on the principles of reduced instruction set computing (RISC-V), has attracted widespread attention in various application scenarios due to its openness and modularity. In the context of chiplet technology, achieving system-level integration (i.e., die-to-die interfaces) through efficient interconnection between different chip modules (die) has become a key means of improving overall system performance and reducing power consumption.

[0003] However, traditional die-to-die interfaces have shortcomings in bandwidth, latency, and protocol complexity, and cannot fully meet the requirements of next-generation high-performance computing systems. Summary of the Invention

[0004] The embodiments of the present application provide a bandwidth scheduling method and related devices for better determining an adaptive transmission scheme based on the transmission requirements of data packets to ensure the rapid transmission of high-priority data.

[0005] In a first aspect, an embodiment of the present application provides a bandwidth scheduling method, the method comprising:

[0006] Determine a data packet to be transmitted corresponding to at least one transmission node; obtain a delay requirement for each data packet to be transmitted based on packet header information of each data packet to be transmitted, wherein the packet header information includes the delay requirement and data packet identifier of the corresponding data packet; obtain first bandwidth status information, wherein the bandwidth status information is used to reflect the load status of each transmission node in a first time period; determine a first bandwidth scheduling scheme based on the delay requirement of each data packet to be transmitted and the first bandwidth status information; and transmit the data packet to be transmitted based on the first bandwidth scheduling scheme.

[0007] Through the above method, the embodiment of the present application optimizes the data packet structure and introduces the delay requirements of the data packets, so that in actual scheduling, based on the acquired bandwidth status information and combined with the delay requirements of the data packets, a scheduling plan can be determined more accurately and efficiently, effectively reducing the data packet processing and queuing delays, and ensuring that high-priority, delay-sensitive tasks can be responded to quickly.

[0008] As an example, the at least one transmission node described in the embodiment of the present application can be a node that needs to perform data transmission in a RISC-V heterogeneous integration system.

[0009] Through this method, the embodiment of the present application provides a RISC-V heterogeneous integration scenario, which can greatly improve the efficiency and real-time performance of data transmission in a multi-core heterogeneous system.

[0010] As an example, the first bandwidth status information in an embodiment of the present application may include but is not limited to the available bandwidth information of the first time period (such as the current time period), the load status of each transmission node in the first time period, the bandwidth allocation status of each transmission node in the first time period, and one or more other information.

[0011] As an example, in order to design a bandwidth scheduling scheme for high-demand data packets in a more targeted manner, the embodiment of the present application can determine a key transmission data packet from the multiple data packets to be transmitted corresponding to the at least one transmission node based on the packet header information of the data packet; thereby determining the first bandwidth scheduling scheme for the key transmission data packet based on the delay requirement of the key transmission data packet.

[0012] As an example, an embodiment of the present application can prioritize the transmission of key transmission data packets based on a first bandwidth scheduling scheme, and after completing the transmission of the key transmission data packets, perform the transmission of non-key transmission data packets. The transmission of non-key transmission data packets can be based on an existing transmission scheme or on a scheme provided by the present application, such as determining a bandwidth scheduling scheme for non-key transmission data packets based on the latency requirements of the non-key transmission data packets and the current bandwidth status information.

[0013] In one possible design, transmitting the to-be-transmitted data packet based on the first bandwidth scheduling scheme includes:

[0014] Based on the first bandwidth scheduling scheme, bandwidths allocated to different nodes among the at least one transmission node are determined; and based on the bandwidths allocated to different transmission nodes, data packets to be transmitted corresponding to different transmission nodes are transmitted in parallel.

[0015] In one possible design, transmitting the to-be-transmitted data packet based on the first bandwidth scheduling scheme includes:

[0016] Determining, based on the first bandwidth scheduling scheme, a bandwidth allocated to a first node among the at least one transmission node;

[0017] Based on the bandwidth allocated by the first node, the data packets to be transmitted corresponding to the first node are transmitted in sequence; or, if the bandwidth allocated by the first node meets the transmission requirements of all data packets to be transmitted corresponding to the first node, all data packets to be transmitted corresponding to the first node are transmitted in parallel; or, if the bandwidth allocated by the first node meets the transmission requirements of part of the data packets to be transmitted corresponding to the first node, based on the latency requirements of the data packets to be transmitted, data packets to be transmitted with low latency requirements are transmitted first.

[0018] In one possible design, transmitting the to-be-transmitted data packet based on the first bandwidth scheduling scheme includes:

[0019] When the data packet to be transmitted is transmitted based on the first bandwidth scheduling scheme, the first bandwidth scheduling scheme is dynamically updated according to the transmission status of the data packet to be transmitted.

[0020] In one possible design, the method further includes:

[0021] Based on the first bandwidth status information, predict the load of each node in a second time period; based on the load of each transmission node in the second time period, determine a second bandwidth scheduling scheme; based on the second bandwidth scheduling scheme, perform data transmission in the second time period.

[0022] In one possible design, determining a first bandwidth scheduling scheme based on a latency requirement of each data packet to be transmitted and the first bandwidth state information includes:

[0023] Based on the processing time of each data packet to be transmitted in each processing stage, the packet processing delay of each data packet to be transmitted is determined; based on the arrival rate of each data packet to be transmitted and the service rate, the queuing waiting delay of each data packet to be transmitted is determined; according to the transmission link status corresponding to each data packet to be transmitted, the data transmission delay of each data packet to be transmitted is determined; based on the packet processing delay, the queuing waiting delay, and the data transmission delay, a first delay corresponding to each data packet to be transmitted is obtained; and based on the first delay corresponding to each data packet to be transmitted and the corresponding delay requirement, a first bandwidth scheduling scheme is determined.

[0024] In one possible design, determining the packet processing delay of each packet to be transmitted based on the processing time of each packet to be transmitted in each processing stage includes:

[0025] The processing time of each data packet to be transmitted in each processing stage is tracked and recorded by a hardware timer, and the processing time of each processing stage is analyzed in combination with a delay model to obtain the data packet processing delay of each data packet to be transmitted.

[0026] As an example, the delay model described in the embodiment of the present application can be obtained by training based on processing information of various stages of a large number of data packets.

[0027] As an example, the packet processing latency described in the embodiments of the present application may refer to the time from when a packet enters a system to when it is processed by the system. For example, the packet processing latency is estimated by calculating the delays in various steps of the packet processing in the processor, including the time from receiving the packet, parsing the packet header, to transmitting the data, etc., which is not limited here.

[0028] In one possible design, the transmission link status corresponding to each data packet to be transmitted includes one or more of the transmission time between the source and destination ends of the transmission link, the bandwidth information of the transmission link, or the delay information of the transmission link.

[0029] In one possible design, the packet header information further includes a priority for data packet transmission; and determining the first bandwidth scheduling scheme based on the latency requirement of each data packet to be transmitted and the first bandwidth state information includes:

[0030] Based on the delay requirement of each data packet to be transmitted and the first delay of each data packet to be transmitted, determine the first transmission priority among multiple data packets to be transmitted; based on the first transmission priority, update the priority in the header information of each data packet; based on the priority in the header information of each data packet to be transmitted and the first bandwidth status information, determine the first bandwidth scheduling scheme.

[0031] In one possible design, the packet header information further includes a priority for data packet transmission; and determining the first bandwidth scheduling scheme based on the latency requirement of each data packet to be transmitted and the first bandwidth state information includes:

[0032] Based on the delay requirement of each data packet to be transmitted and the first delay of each data packet to be transmitted, a first data packet is determined from the data packets to be transmitted, where the first data packet is a data packet among the data packets to be transmitted whose first delay does not meet the corresponding delay requirement; a first transmission channel is determined based on the first bandwidth state information, and the first data packet is transmitted based on the first transmission channel.

[0033] In one possible design, the first transmission priority is used to ensure that the first delay corresponding to a first threshold number or a first threshold proportion of data packets to be transmitted meets the corresponding delay requirement.

[0034] As an example, in the embodiment of the present application, the first transmission channel may be the optimal route.

[0035] As an example, in the embodiment of the present application, the first threshold ratio may be 100%.

[0036] As an example, the optimal route in the embodiment of the present application may be a preset route dedicated to executing the transmission of the first data packet.

[0037] As an example, the first transmission channel in the embodiment of the present application may occupy a bandwidth of a second threshold ratio of the current available bandwidth; or the bandwidth of the first transmission channel in the embodiment of the present application is a fixed bandwidth, specifically a bandwidth of a second threshold amount.

[0038] As an example, an embodiment of the present application can determine a first transmission priority among multiple data packets to be transmitted based on the delay requirement of each data packet to be transmitted, the first delay of each data packet to be transmitted, and the first bandwidth status information; based on the first transmission priority, update the priority in the header information of each data packet; and perform data packet transmission based on the priority in the header information of each data packet to be transmitted.

[0039] In one possible design, determining a first bandwidth scheduling scheme based on a latency requirement of each data packet to be transmitted and the first bandwidth state information includes:

[0040] When a first delay corresponding to a first data packet does not meet the delay requirement of the first data packet, the priority level in the header information of the first data packet is increased; the first data packet is any data packet in the data packets to be transmitted.

[0041] In one possible design, determining a first transmission channel based on the first bandwidth state information, and transmitting the first data packet based on the first transmission channel further includes:

[0042] The first data packet is transmitted through the first transmission channel and hardware acceleration.

[0043] In one possible design, determining a first bandwidth scheduling scheme based on a latency requirement of each data packet to be transmitted and the first bandwidth state information includes:

[0044] Obtain data flow information of each transmission node among the at least one transmission node; determine the bandwidth allocated to each transmission node based on the data flow information of each transmission node, the bandwidth allocation weight corresponding to each transmission node, and the first bandwidth status information; determine the first bandwidth scheduling scheme based on the bandwidth allocated to each transmission node and each data packet to be transmitted.

[0045] In one possible design, the method further includes:

[0046] Collect data flow information of each transmission node in real time; generate a real-time data flow map based on the data flow information of each transmission node; and dynamically update the first bandwidth scheduling solution based on the real-time data flow map.

[0047] As an example, the embodiment of the present application can predict the data traffic map of the future time period based on the data traffic map, and thus obtain the bandwidth scheduling plan corresponding to the future time period based on the data traffic map of the future time period.

[0048] In one possible design, the method further includes:

[0049] After the second data packet is transmitted, a check code included in the header information of the second data packet is obtained, where the check code is used to check whether an error occurs during the transmission of the second data packet, and the second data packet is any data packet among the data packets to be transmitted; after determining that the second data packet has a transmission error based on the check code, the second data packet is retransmitted through a second transmission channel; wherein the second transmission channel is a preset low-latency transmission channel, which is used to perform data packet retransmission.

[0050] Through the above method, the embodiments of the present application use a lightweight error checking mechanism to achieve rapid error detection and recovery during data transmission, effectively reducing the instability caused by transmission errors and ensuring the continued stable operation of the system under high load conditions. Therefore, the present invention achieves significant optimization in data transmission and bandwidth management, and meets the needs of multi-core heterogeneous computing platforms for high concurrency and low latency transmission through a low-latency protocol and adaptive scheduling mechanism.

[0051] In one possible design, the method further includes:

[0052] Obtain the synchronization signal corresponding to each transmission node; determine the delay compensation between each transmission node through an adaptive delay compensation algorithm based on the synchronization signal corresponding to each transmission node; and adjust the clock deviation of each transmission node based on the delay compensation between each transmission node.

[0053] Through the above method, the embodiment of the present application adopts distributed clock synchronization technology to achieve precise clock alignment between modules, effectively reducing the instability factors caused by clock deviation, and ensuring the continuous and stable operation of the system under high load conditions.

[0054] In a second aspect, an embodiment of the present application provides a bandwidth scheduling method, the method comprising:

[0055] Receive a data packet sent by a master node based on a first bandwidth scheduling scheme; the first bandwidth scheduling scheme is determined by the master node based on the delay requirement in the packet header information of each data packet to be transmitted and first bandwidth status information, and the bandwidth status information is used to reflect the load status of each transmission node in the first time period.

[0056] As an example, the master node described in the embodiment of the present application can be a node responsible for transmission scheduling in a RISC-V heterogeneous integration system.

[0057] In one possible design, the method further includes:

[0058] Obtain its own data flow information; and send the data flow information to the master node.

[0059] In one possible design, the method further includes:

[0060] Sending its own synchronization signal to the master node; receiving the delay compensation determined by the master node based on the synchronization signal; and adjusting its own clock deviation based on the delay compensation.

[0061] In a third aspect, an embodiment of the present application provides a bandwidth scheduling device, comprising a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor executes the method in the first aspect and any design thereof.

[0062] In a fourth aspect, an embodiment of the present application provides a bandwidth scheduling system, which is used to execute the method in the above-mentioned first aspect and any design thereof.

[0063] In a fifth aspect, an embodiment of the present application provides a bandwidth scheduling device, including:

[0064] a processing module configured to determine a data packet to be transmitted corresponding to at least one transmission node; obtain a latency requirement for each data packet to be transmitted based on packet header information of each data packet to be transmitted, wherein the packet header information includes the latency requirement for the corresponding data packet and a data packet identifier; obtain first bandwidth status information, wherein the bandwidth status information is used to reflect the load status of each transmission node in a first time period; and determine a first bandwidth scheduling scheme based on the latency requirement for each data packet to be transmitted and the first bandwidth status information;

[0065] A transceiver module is configured to transmit the data packet to be transmitted using the first bandwidth scheduling scheme. In one possible design, the processing module is specifically configured to:

[0066] Based on the first bandwidth scheduling scheme, bandwidths allocated to different transmission nodes among the at least one transmission node are determined; and based on the bandwidths allocated to different transmission nodes, data packets to be transmitted corresponding to different transmission nodes are transmitted in parallel.

[0067] In one possible design, the processing module is specifically used to:

[0068] Determining, based on the first bandwidth scheduling scheme, a bandwidth allocated to a first node among the at least one transmission node;

[0069] Based on the bandwidth allocated by the first node, the data packets to be transmitted corresponding to the first node are transmitted in sequence; or, if the bandwidth allocated by the first node meets the transmission requirements of all data packets to be transmitted corresponding to the first node, all data packets to be transmitted corresponding to the first node are transmitted in parallel; or, if the bandwidth allocated by the first node meets the transmission requirements of part of the data packets to be transmitted corresponding to the first node, based on the latency requirements of the data packets to be transmitted, data packets to be transmitted with low latency requirements are transmitted first.

[0070] In one possible design, the processing module is specifically used to:

[0071] When the data packet to be transmitted is transmitted based on the first bandwidth scheduling scheme, the first bandwidth scheduling scheme is dynamically updated according to the transmission status of the data packet to be transmitted.

[0072] In one possible design, the processing module is also used to:

[0073] Based on the first bandwidth status information, predict the load of each node in a second time period; based on the load of each node in the second time period, determine a second bandwidth scheduling scheme; based on the second bandwidth scheduling scheme, perform data transmission in the second time period.

[0074] In one possible design, the processing module is specifically used to:

[0075] Based on the processing time of each data packet to be transmitted in each processing stage, the packet processing delay of each data packet to be transmitted is determined; based on the arrival rate of each data packet to be transmitted and the service rate, the queuing waiting delay of each data packet to be transmitted is determined; according to the transmission link status corresponding to each data packet to be transmitted, the data transmission delay of each data packet to be transmitted is determined; based on the packet processing delay, the queuing waiting delay, and the data transmission delay, a first delay corresponding to each data packet to be transmitted is obtained; and based on the first delay corresponding to each data packet to be transmitted and the corresponding delay requirement, a first bandwidth scheduling scheme is determined.

[0076] In one possible design, the processing module is specifically used to:

[0077] The processing time of each data packet to be transmitted in each processing stage is tracked and recorded by a hardware timer, and the processing time of each processing stage is analyzed in combination with a delay model to obtain the data packet processing delay of each data packet to be transmitted.

[0078] In one possible design, the transmission link status corresponding to each data packet to be transmitted includes one or more of the transmission time between the source and destination ends of the transmission link, the bandwidth information of the transmission link, or the delay information of the transmission link.

[0079] In one possible design, the processing module is specifically used to:

[0080] Based on the delay requirement of each data packet to be transmitted and the first delay of each data packet to be transmitted, determine the first transmission priority among multiple data packets to be transmitted; based on the first transmission priority, update the priority in the header information of each data packet; based on the priority in the header information of each data packet to be transmitted and the first bandwidth status information, determine the first bandwidth scheduling scheme.

[0081] In one possible design, the processing module is specifically used to:

[0082] Based on the delay requirement of each data packet to be transmitted and the first delay of each data packet to be transmitted, a first data packet is determined from the data packets to be transmitted, where the first data packet is a data packet among the data packets to be transmitted whose first delay does not meet the corresponding delay requirement; a first transmission channel is determined based on the first bandwidth state information, and the first data packet is transmitted based on the first transmission channel.

[0083] In one possible design, the first transmission priority is used to ensure that the first delay corresponding to a first threshold number or a first threshold proportion of data packets to be transmitted meets the corresponding delay requirement.

[0084] In one possible design, the processing module is specifically used to:

[0085] Based on the delay requirement of each data packet to be transmitted, the first delay of each data packet to be transmitted and the first bandwidth status information, a first transmission priority among multiple data packets to be transmitted is determined; based on the first transmission priority, the priority in the header information of each data packet is updated; and data packet transmission is performed based on the priority in the header information of each data packet to be transmitted.

[0086] In one possible design, the processing module is specifically used to:

[0087] When a first delay corresponding to a first data packet does not meet the delay requirement of the first data packet, the priority level in the header information of the first data packet is increased; the first data packet is any data packet in the data packets to be transmitted.

[0088] In one possible design, the processing module is also used to:

[0089] The first data packet is transmitted through the first transmission channel and hardware acceleration.

[0090] In one possible design, the processing module is specifically used to:

[0091] Obtain data flow information of each transmission node; determine the bandwidth allocated to each transmission node based on the data flow information of each transmission node, the bandwidth allocation weight corresponding to each transmission node, and the first bandwidth status information; determine the first bandwidth scheduling scheme based on the bandwidth allocated to each transmission node and each data packet to be transmitted.

[0092] In one possible design, the processing module is also used to:

[0093] Collect data flow information of each transmission node in real time; generate a real-time data flow map based on the data flow information of each transmission node; and dynamically update the first bandwidth scheduling solution based on the real-time data flow map.

[0094] In one possible design, the processing module is also used to:

[0095] After the second data packet is transmitted, a check code included in the header information of the second data packet is obtained, where the check code is used to check whether an error occurs during the transmission of the second data packet, and the second data packet is any data packet among the data packets to be transmitted; after determining that the second data packet has a transmission error based on the check code, the second data packet is retransmitted through a second transmission channel; wherein the second transmission channel is a preset low-latency transmission channel, which is used to perform data packet retransmission.

[0096] In one possible design, the processing module is also used to:

[0097] Obtain the synchronization signal corresponding to each transmission node; determine the delay compensation between each transmission node through an adaptive delay compensation algorithm based on the synchronization signal corresponding to each transmission node; and adjust the clock deviation of each transmission node based on the delay compensation between each transmission node.

[0098] In a sixth aspect, an embodiment of the present application provides a bandwidth scheduling device, including:

[0099] A transceiver module is configured to receive data packets sent by a master node based on a first bandwidth scheduling scheme; the first bandwidth scheduling scheme is determined by the master node based on the delay requirement in the packet header information of each data packet to be transmitted and first bandwidth status information, wherein the bandwidth status information is used to reflect the load status of each node in the first time period.

[0100] As an example, the master node described in the embodiment of the present application can be a node responsible for transmission scheduling in a RISC-V heterogeneous integration system.

[0101] In one possible design, the bandwidth scheduling apparatus further includes:

[0102] The processing module is used to obtain its own data flow information; and send the data flow information to the master node through the transceiver module.

[0103] In one possible design, the processing module is further configured to:

[0104] The module sends its own synchronization signal to the master node through the transceiver module; receives the delay compensation determined by the master node based on the synchronization signal; and adjusts its own clock deviation based on the delay compensation.

[0105] In the seventh aspect, an embodiment of the present application provides a computer-readable storage medium, which includes a computer program. When the computer program is run on an electronic device, the computer program is used to enable the electronic device to execute the method in the first aspect and any design thereof; or, execute the method in the second aspect and any design thereof.

[0106] In an eighth aspect, an embodiment of the present application provides a computer program product, comprising a computer program, wherein the computer program is stored in a computer-readable storage medium; when a processor of an electronic device reads the computer program from the computer-readable storage medium, the processor executes the method as in the first aspect and any design thereof; or, executes the method as in the second aspect and any design thereof.

[0107] In the ninth aspect, an embodiment of the present application provides a chip, which includes a computer program and a processor, and the chip is used to execute the method in the first aspect and any design thereof; or, to execute the method in the second aspect and any design thereof.

[0108] In addition, the technical effects brought about by the second to ninth aspects and any of their designs can refer to the technical effects brought about by the different design methods in the first aspect, and will not be repeated here.

[0109] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. The purposes and other advantages of the present application can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0110] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0111] Figure 1A schematic diagram of a system architecture provided in an embodiment of the present application;

[0112] Figure 2 Another system architecture diagram provided for an embodiment of the present application;

[0113] Figure 3 Another system architecture diagram provided for an embodiment of the present application;

[0114] Figure 4 A schematic diagram of a bandwidth scheduling method provided in an embodiment of the present application;

[0115] Figure 5 A schematic diagram of a data packet configuration provided in an embodiment of the present application;

[0116] Figure 6 A schematic diagram of a dynamic bandwidth allocation process provided in an embodiment of the present application;

[0117] Figure 7 A schematic diagram of the structure of a bandwidth scheduling device provided in an embodiment of the present application;

[0118] Figure 8 A schematic diagram of the structure of another bandwidth scheduling device provided in an embodiment of the present application;

[0119] Figure 9 A schematic diagram of the hardware structure of a computing device according to an embodiment of the present application. DETAILED DESCRIPTION

[0120] To facilitate understanding by those skilled in the art, some terms involved in this application are explained below.

[0121] (1) RISC-V heterogeneous system:

[0122] The RISC-V heterogeneous system described in the embodiments of this application may refer to a computing system based on the RISC-V instruction set architecture (ISA) and composed of different types of processor cores or hardware acceleration units, with diversified computing units and customized hardware expansion capabilities. These components can have different instruction sets, microarchitectures, or functional divisions, and work together to improve energy efficiency, performance, or flexibility.

[0123] Exemplarily, the RISC-V heterogeneous system includes diverse processor cores, such as general-purpose CPUs (such as high-performance RISC-V cores and low-power embedded cores) and specialized processors (such as GPUs, NPUs, DSPs, etc.). In addition, the RISC-V heterogeneous system can have unified memory or distributed memory.

[0124] (2)die-to-die interface:

[0125] In the embodiments of the present application, the die-to-die interface is a functional block that provides a data interface between two chip dies in the same package. It establishes and maintains the link during chip operation and provides a standardized parallel interface to the internal interconnect structure for the application program.

[0126] (3) M / M / 1 queue model:

[0127] The M / M / 1 queue model in the embodiment of the present application is a queue theory model used to describe the queuing process of a data packet entering a single service node.

[0128] It should be noted that the acquisition, storage, use, and processing of data in the embodiments of this application comply with the relevant provisions of national laws and regulations.

[0129] In the embodiments of this application, the term "and / or" describes the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0130] The application scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. It is known to those skilled in the art that, with the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are equally applicable to similar technical problems. In the description of the present application, unless otherwise specified, the meaning of "multiple" is two or more. In the description of the embodiments of the present application, words such as "first" and "second" are only used to distinguish the purpose of description, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

[0131] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application. In the financial field, in order to effectively ensure the healthy and upward development of the financial system, it is often necessary to identify and deal with bad financial behaviors, such as cash-out transactions such as converting credit lines into cash through illegal means.

[0132] In recent years, with the advancement of chip technology and the increasing demand for system integration, heterogeneous integration and multi-core heterogeneous computing have gradually become mainstream architectures. The RISC-V architecture, with its openness and modularity, has attracted widespread attention in various application scenarios. In the context of chiplet technology, achieving system-level integration through efficient interconnection between different chip modules has become a key means of improving overall system performance and reducing power consumption. However, traditional die-to-die interfaces have limitations in bandwidth, latency, and protocol complexity, and cannot fully meet the requirements of next-generation high-performance computing systems.

[0133] For example, related technologies often face bandwidth bottlenecks and latency issues. For example, traditional die-to-die interfaces often use fixed bandwidth designs, making it difficult to cope with the dynamically changing bandwidth requirements of different computing tasks. Furthermore, complex transmission protocols lead to high communication latency, impacting overall system performance. Furthermore, related technologies also face issues such as a lack of adaptive mechanisms in interface protocols. For example, current interface protocols fail to fully leverage the advantages of RISC-V multi-core heterogeneous systems in heterogeneous computing scenarios, lacking optimized solutions for dynamic bandwidth allocation and low-latency data transmission based on task load.

[0134] Therefore, there is an urgent need for an efficient and convenient bandwidth scheduling method to better guarantee the requirements of high-performance computing systems.

[0135] Based on this, the embodiment of the present application provides a bandwidth scheduling method and related devices, which significantly reduce transmission latency by introducing a new low-latency protocol at the data transmission level and optimizing the data packet structure and transmission scheduling. In addition, based on the heterogeneous integration characteristics of RISC-V, the embodiment of the present application adopts a dynamic bandwidth scheduling algorithm to achieve flexible allocation of bandwidth between different dies to meet the parallel requirements of multi-core heterogeneous computing. Among them, the method and the device are based on the same inventive concept. Since the principles of solving the problems of the method and the device are similar, the implementation of the device and the method can refer to each other, and the repeated parts will not be repeated.

[0136] The bandwidth scheduling method in the embodiment of the present application can be implemented by software, hardware, or a combination of software and hardware. The following takes an electronic device as an example to introduce the bandwidth scheduling method in the embodiment of the present application.

[0137] To better illustrate the embodiments of this application, this application is applicable to a wide range of scenarios, including but not limited to high-performance computing (HPC) scenarios, artificial intelligence (AI), and machine learning scenarios. For example, on a massively parallel computing platform, an optimized die-to-die interface can achieve low-latency data exchange and high-bandwidth resource scheduling, improving overall computing efficiency. Another example is heterogeneous computing platforms that require real-time data exchange for tasks such as data preprocessing and deep neural network training. An optimized interface will effectively improve training speed and response speed.

[0138] The system application scenario implemented in this application can be a multi-chiplet system architecture using heterogeneous integration, where each chiplet integrates a RISC-V-based processing core and a dedicated acceleration unit, and high-speed, low-latency data transmission is achieved between different chiplets through an optimized die-to-die interface. The system in the embodiment of this application implements hardware and software collaborative design at the hardware and software levels to ensure efficient and synchronized transmission between modules.

[0139] The present application embodiment provides a bandwidth scheduling system, see Figure 1 As shown, the bandwidth scheduling system provided by the present application can be a schematic diagram of the overall system architecture based on RISC-V heterogeneous integration. The multi-core heterogeneous system 100 includes multiple chiplets, each chiplet can contain processing units with different functions, and multiple chiplets can communicate with each other. For example, the multi-core heterogeneous system 100 includes chiplet 110 and chiplet 120, wherein the chiplet 110 and chiplet 120 are connected to a data interconnection network 130. The data interconnection network 130 has a low-latency, high-bandwidth interface.

[0140] Chiplet 110 is responsible for task scheduling (such as allocating image frames to accelerators, etc.) and running lightweight algorithms.

[0141] As an example, the chiplet 110 described in the embodiment of the present application can be a RISC-V core group, which has functions such as general computing and control, parallel processing and load balancing, as well as scalability and customization. For example, the RISC-V core group described in the embodiment of the present application is based on the open source RISC-V instruction set, and is composed of multiple central processing unit (CPU) cores, which are responsible for performing general computing tasks (such as operating system scheduling, logic control, task distribution, etc.), and are flexible and programmable. The multi-core cluster improves system throughput through parallel processing, such as multi-threaded task allocation or distributed computing (such as edge servers, real-time data processing). The open source nature of RISC-V allows the core group to be customized according to demand (such as increasing or decreasing the number of cores, extending the instruction set), and adapting to different scenarios (low-power embedded or high-performance computing).

[0142] Chiplet120 is used for related operations.

[0143] As an example, the chiplet 120 described in the embodiment of the present application can be a dedicated accelerator with functions such as efficiently executing target computing tasks, optimizing energy efficiency, and unloading the main processor load. For example, the dedicated accelerator described in the embodiment of the present application can design hardware modules for computationally intensive tasks (such as AI reasoning, cryptography, and image processing), and achieve efficiency far exceeding that of a general-purpose CPU through algorithm solidification or hardware optimization. The dedicated accelerator can also significantly reduce power consumption by reducing general instruction decoding overhead and customizing data paths. In addition, the dedicated accelerator can also divert time-consuming tasks (such as encryption and decryption) from the RISC-V core group to release CPU resources.

[0144] The data interconnection network 130 is used to transmit sensor data from the memory to the embedded neural processing unit (NPU) with high bandwidth, and return the results to the CPU.

[0145] As an example, the data interconnection network 130 described in the embodiment of the present application has functions such as high-speed communication between components, low latency and high bandwidth, and resource coordination and consistency management. For example, the data interconnection network 130 described in the embodiment of the present application can connect core groups, accelerators, memory and I / O through an on-chip network (network operations center, NoC), a bus protocol (anced extensible interface, AXI) or a cross switch to ensure efficient data flow. The data interconnection network can also avoid performance bottlenecks caused by data blockage (such as weight data transmission between accelerators and memory in AI chips), and support cache consistency protocols (such as CXL) and dynamic priority scheduling (such as quality of service (QoS) mechanism) to ensure the collaborative work of multi-core / multi-accelerators.

[0146] In some implementations, the interface described above in the embodiments of the present application is customized in design, capable of dynamically scheduling bandwidth according to real-time needs, and using a low-latency transmission protocol to ensure rapid transmission of critical data.

[0147] This embodiment of the application provides another bandwidth scheduling system, see Figure 2 As shown, the bandwidth scheduling system 200 may include a master node 210 and at least one transmission node 220. The master node 210 is used to perform bandwidth scheduling and allocation; the transmission node 220 is used to send and receive related information, such as data packets.

[0148] As an example, the bandwidth scheduling system 200 in the embodiment of the present application can also be as follows Figure 3 As shown in (a), each transmission node may be provided with a bandwidth monitoring module 221 for monitoring and collecting data flow information of the transmission node; the master node may be provided with a bandwidth scheduling control module 211 for executing bandwidth scheduling allocation. Optionally, the bandwidth monitoring module may be implemented by sensors and monitoring circuits within each transmission node. Optionally, after obtaining data flow information of the transmission node, the bandwidth monitoring module may transmit the relevant information in real time to the bandwidth scheduling control module in the master node, so that the bandwidth scheduling control module can adjust bandwidth allocation based on the obtained relevant information.

[0149] As an example, the bandwidth scheduling system 200 in the embodiment of the present application can also be as follows Figure 3As shown in (b) of FIG. 1 , the master node may be internally provided with a bandwidth scheduling control module 211 for executing bandwidth scheduling and allocation. The master node may also be internally provided with a bandwidth monitoring module 212 for monitoring and collecting data flow information, etc., from each transmission node. Optionally, the bandwidth monitoring module may be connected to each transmission node and, using sensors and monitoring circuits, acquire data flow information, etc., from each transmission node. The acquired information is then transmitted in real time to the bandwidth scheduling control module in the master node, enabling the bandwidth scheduling control module to adjust bandwidth allocation based on the acquired information.

[0150] It should be noted that the above Figures 1 to 3 The system architecture described is only an example of the system architecture of this application and does not constitute a limitation on the embodiments of this application. For example, the embodiments of this application can be used to Figures 1 to 3 The system architecture described above can be adaptively adjusted or integrated to obtain other system architectures applicable to the embodiments of the present application.

[0151] like Figure 4 As shown, it is a schematic flow chart of a bandwidth scheduling method provided in an embodiment of the present application. The method can be applied to a bandwidth scheduling device, such as being applied to interactive execution between multiple nodes in the above-mentioned system. The specific process may include the following steps:

[0152] S401: Determine a data packet to be transmitted corresponding to at least one transmission node.

[0153] As an example, the data packets to be transmitted determined in the above S401 of the embodiment of the present application can be all the data packets to be transmitted in the entire system, or can be part of the data packets to be transmitted in the entire system. For example, the data packets to be transmitted determined in the above S401 can be key transmission data packets among all the data packets to be transmitted in the entire system. The key transmission data packets and non-key transmission data packets can be divided based on various methods such as the type of data packet, the delay requirement of the data packet, the importance of the data packet, etc., which are not limited here.

[0154] For example, in order to design a bandwidth scheduling scheme for high-demand data packets in a more targeted manner, an embodiment of the present application can determine a key transmission data packet from the multiple data packets to be transmitted corresponding to the at least one transmission node based on the packet header information of each data packet to be transmitted. For example, a data packet with a delay requirement less than a threshold A is determined as a key transmission data packet, thereby more specifically determining the first bandwidth scheduling scheme based on the key transmission data packet.

[0155] Optionally, an embodiment of the present application can prioritize the transmission of key transmission data packets based on the first bandwidth scheduling scheme, and after completing the transmission of the key transmission data packets, the transmission of non-key data packets can be performed. The transmission of non-key data packets can be based on an existing transmission scheme or on the scheme provided by the present application, such as determining the bandwidth scheduling scheme for non-key data packets based on the latency requirements of the non-key data packets and the current bandwidth status information.

[0156] S402 : Acquire a delay requirement of each data packet to be transmitted based on the packet header information of each data packet to be transmitted, wherein the packet header information includes the delay requirement of the corresponding data packet and a data packet identifier.

[0157] As an example, the packet header information described in the embodiment of the present application may also include the priority of the data packet, check code and other information, which is not limited here.

[0158] As an example, the priority in the packet header information described in the embodiment of the present application can be adaptively adjusted based on the delay requirement of the data packet to which it belongs, the actual transmission situation of the data packet to which it belongs, and / or the predicted transmission situation of the data packet to which it belongs, so that the delay requirement of the data packet can be better met when transmission is based on priority.

[0159] S403: Acquire first bandwidth status information, where the bandwidth status information is used to reflect the load status of each transmission node in a first time period.

[0160] In some implementations, the embodiments of the present application may construct a bandwidth monitoring module based on sensors, monitoring circuits and other devices in the system, thereby obtaining the first bandwidth status information based on the bandwidth monitoring module.

[0161] As an example, the first bandwidth status information in an embodiment of the present application may include but is not limited to the available bandwidth information of the first time period (such as the current time period), the load status of each transmission node in the first time period, the bandwidth allocation status of each transmission node in the first time period, and one or more other information.

[0162] As an example, the first bandwidth status information in the embodiment of the present application can be presented in the form of a data traffic map. For example, the embodiment of the present application can collect data traffic information of each transmission node in real time; based on the data traffic information of each transmission node, a real-time data traffic map is generated, and the first bandwidth scheduling scheme is dynamically updated based on the real-time data traffic map.

[0163] As an example, the embodiment of the present application can also predict the data traffic map of the future time period based on the data traffic map, and thus obtain the bandwidth scheduling plan corresponding to the future time period based on the data traffic map of the future time period.

[0164] S404: Determine a first bandwidth scheduling solution based on the delay requirement of each data packet to be transmitted and the first bandwidth status information.

[0165] Since the header information of the data packet to be transmitted in the embodiment of the present application includes the delay requirement, it is possible to determine whether the current transmission conditions meet the delay requirements of the data packet to be transmitted based on the current transmission scenario. Among them, the embodiment of the present application can divide the overall first delay for the completion of the transmission of the data packet, for example, into three parts: data packet processing delay, data packet queuing waiting delay and data packet transmission delay. Among them, the first delay of the data packet described in the embodiment of the present application can refer to the time from the data packet entering the system to the time it is processed by the system. For example, the data packet processing delay is estimated by calculating the delay of each step of the data packet in the processor, including the time from receiving the data packet, parsing the header, to transmitting the data, etc., which is not limited here. It can be understood that the division method of the first delay in the embodiment of the present application is only listed as one embodiment of the present application, and any other division method belongs to the scope of protection of this application.

[0166] As an example, an embodiment of the present application can determine the packet processing delay of each packet to be transmitted based on the processing time of each packet to be transmitted in each processing stage; determine the queuing waiting delay of each packet to be transmitted based on the arrival rate of each packet to be transmitted and the service rate; and determine the data transmission delay of each packet to be transmitted based on the transmission link status corresponding to each packet to be transmitted. The transmission link status corresponding to each packet to be transmitted includes one or more of the transmission time between the source and destination ends of the transmission link, the bandwidth information of the transmission link, or the delay information of the transmission link.

[0167] Optionally, embodiments of the present application can track and record the processing time of each data packet to be transmitted at each processing stage using a hardware timer, and analyze the processing time of each processing stage in combination with a delay model to obtain the data packet processing delay of each data packet to be transmitted. The delay model described in embodiments of the present application can be trained based on processing information of a large number of data packets at each stage.

[0168] After obtaining the packet processing delay, the queuing delay, and the data transmission delay of the target data packet through the above content, a first delay corresponding to each data packet to be transmitted can be obtained based on the packet processing delay, the queuing delay, and the data transmission delay. For example, in embodiments of the present application, the packet processing delay, the queuing delay, and the data transmission delay can be added together to obtain the first delay corresponding to the data packet.

[0169] Since the first delay of the data packet needs to meet the corresponding delay requirement, the embodiment of the present application can determine the first bandwidth scheduling scheme based on the first delay corresponding to the data packet and the delay requirement, specifically but not limited to the following methods:

[0170] Method 1: An embodiment of the present application can determine the first transmission priority among multiple data packets to be transmitted based on the delay requirement of each data packet to be transmitted and the first delay of each data packet to be transmitted; based on the first transmission priority, update the priority in the header information of each data packet; based on the priority in the header information of each data packet to be transmitted and the first bandwidth status information, determine the first bandwidth scheduling scheme.

[0171] As an example, the first transmission priority is used to ensure that a first delay corresponding to a first threshold number or a first threshold ratio of data packets to be transmitted meets a corresponding delay requirement. Optionally, the first threshold ratio in this embodiment of the application can be 100%.

[0172] Exemplarily, when a first delay corresponding to a first data packet does not meet the delay requirement of the first data packet, the priority level in the header information of the first data packet is increased; the first data packet is any data packet among the data packets to be transmitted.

[0173] Method 2: An embodiment of the present application can determine a first data packet from the data packets to be transmitted based on the delay requirement of each data packet to be transmitted and the first delay of each data packet to be transmitted, where the first data packet is a data packet among the data packets to be transmitted whose first delay does not meet the corresponding delay requirement; determine a first transmission channel based on the first bandwidth status information, and transmit the first data packet based on the first transmission channel.

[0174] As an example, the first transmission channel in the embodiment of the present application may be an optimal route. Optionally, the optimal route in the embodiment of the present application may be a preset route specifically used for transmitting the first data packet.

[0175] As an example, the first transmission channel in the embodiment of the present application may occupy a bandwidth of a second threshold ratio of the current available bandwidth; or the bandwidth of the first transmission channel in the embodiment of the present application is a fixed bandwidth, specifically a bandwidth of a second threshold amount.

[0176] Furthermore, in order to better ensure the transmission of the first data packet, the embodiment of the present application can transmit the first data packet through the first transmission channel and hardware acceleration.

[0177] Method 3: The embodiment of the present application can determine the first transmission priority among multiple data packets to be transmitted based on the delay requirement of each data packet to be transmitted, the first delay of each data packet to be transmitted, and the first bandwidth status information; based on the first transmission priority, update the priority in the header information of each data packet; and perform data packet transmission based on the priority in the header information of each data packet to be transmitted.

[0178] Method 3 differs from Method 1 in that it already considers the first bandwidth status information when determining the first transmission priority among multiple data packets to be transmitted, making the determined first transmission priority more consistent with the current bandwidth status. Method 1, on the other hand, after determining the first transmission priority, further considers the bandwidth scheduling solution based on the first transmission priority and the first bandwidth status information. In specific applications, the choice of these methods can be based on the actual scenario.

[0179] It should be noted that the above-mentioned methods 1 to 3 are only listed as examples of the embodiments of the present application and do not constitute a limitation on the embodiments of the present application. For example, the present application can also be put into practical application by combining multiple methods in the above-mentioned methods 1 to 3.

[0180] In some implementations, when determining the first bandwidth scheduling scheme, the embodiments of the present application also need to consider the bandwidth allocated to the node corresponding to the data packet to be transmitted. Exemplarily, when determining the first bandwidth scheduling scheme based on the latency requirement of each data packet to be transmitted and the first bandwidth status information, the embodiments of the present application can obtain the data flow information of each transmission node in the at least one transmission node; determine the bandwidth allocated to each transmission node based on the data flow information of each transmission node, the bandwidth allocation weight corresponding to each transmission node, and the first bandwidth status information; and determine the first bandwidth scheduling scheme based on the bandwidth allocated to each transmission node and each data packet to be transmitted.

[0181] Next, we will continue with the embodiment of this application Figure 4 The process described.

[0182] S405: Transmit the data packet to be transmitted based on the first bandwidth scheduling scheme.

[0183] In the embodiment of the present application, when transmitting the data packet to be transmitted based on the first bandwidth scheduling scheme, there may be multiple transmission scenarios, which are not limited to the following:

[0184] Transmission mode 1: Based on the first bandwidth scheduling scheme, determine the bandwidth allocated to different nodes among the at least one transmission node; based on the bandwidth allocated to different transmission nodes, transmit the data packets to be transmitted corresponding to different transmission nodes in parallel.

[0185] Transmission mode 2: Based on the first bandwidth scheduling scheme, determine the bandwidth allocated to the first node among the at least one transmission node; based on the bandwidth allocated by the first node, transmit the data packets to be transmitted corresponding to the first node in sequence.

[0186] Transmission mode 3: Based on the first bandwidth scheduling scheme, determine the bandwidth allocated to the first node among the at least one transmission node; if the bandwidth allocated by the first node meets the transmission requirements of all data packets to be transmitted corresponding to the first node, transmit all data packets to be transmitted corresponding to the first node in parallel.

[0187] Transmission mode 4: Based on the first bandwidth scheduling scheme, determine the bandwidth allocated to the first node among the at least one transmission node; if the bandwidth allocated by the first node meets the transmission requirements of the part of the data packets to be transmitted corresponding to the first node, based on the delay requirements of the data packets to be transmitted, give priority to transmitting the data packets to be transmitted with low delay requirements.

[0188] Transmission mode 5: When transmitting the data packet to be transmitted based on the first bandwidth scheduling scheme, the first bandwidth scheduling scheme is dynamically updated according to the transmission status of the data packet to be transmitted.

[0189] In some implementations, the embodiments of the present application may also predict the load conditions of each node in a second time period based on the first bandwidth status information; determine a second bandwidth scheduling scheme based on the load conditions of each transmission node in the second time period; and perform data transmission in the second time period based on the second bandwidth scheduling scheme.

[0190] Furthermore, in an embodiment of the present application, after the second data packet is transmitted, a check code included in the header information of the second data packet is obtained, and the check code is used to check whether an error occurs during the transmission of the second data packet, where the second data packet is any data packet among the data packets to be transmitted; after determining that the second data packet has a transmission error based on the check code, the second data packet is retransmitted through a second transmission channel; wherein, the second transmission channel is a preset low-latency transmission channel for performing data packet retransmission.

[0191] As an example, an embodiment of the present application can obtain the synchronization signal corresponding to each transmission node; based on the synchronization signal corresponding to each transmission node, determine the delay compensation between each transmission node through an adaptive delay compensation algorithm; based on the delay compensation between each transmission node, adjust the clock deviation of each transmission node.

[0192] Through the above-mentioned method, the embodiments of the present application effectively reduce packet processing and queuing delays by optimizing the packet structure, introducing a preemptive scheduling algorithm, and a real-time dynamic bandwidth allocation mechanism, ensuring rapid response for high-priority, latency-sensitive tasks. Compared with traditional fixed bandwidth and first-in, first-out (FIFO) scheduling methods, this solution can flexibly adjust bandwidth allocation based on actual load, thereby significantly improving the efficiency and real-time performance of data transmission in multi-core heterogeneous systems. In addition, the embodiments of the present application use distributed clock synchronization technology and a lightweight error checking mechanism to achieve precise clock alignment between modules and rapid error detection and recovery during data transmission. This not only reduces instability caused by clock deviation and transmission errors, but also ensures continuous and stable operation of the system under high load conditions. Therefore, the present invention achieves significant optimization in data transmission and bandwidth management. Through a low-latency protocol and adaptive scheduling mechanism, it meets the high-concurrency, low-latency transmission requirements of multi-core heterogeneous computing platforms. At the same time, the distributed clock synchronization and error checking mechanism effectively improves the reliability and stability of the system. Overall, this solution provides a more efficient, flexible, and reliable solution for high-performance computing, artificial intelligence, edge computing, and other fields, with broad application prospects and market competitiveness.

[0193] In order to better introduce the embodiments of the present application, the following details of the embodiments of the present application are described in detail based on different application scenario examples, which are not limited to the following examples:

[0194] Example 1: Configuring a low-latency transmission protocol.

[0195] To reduce data transmission latency, the present application improves the traditional data packet structure and transmission scheduling algorithm, thereby configuring a low-latency transmission protocol that better meets transmission requirements. The present application can configure the low-latency transmission protocol based on, but not limited to, the following two configuration methods.

[0196] Configuration method 1: Data packet structure optimization.

[0197] In some implementations, a data packet in an embodiment of the present application may include a data packet header and a data payload. The data packet header is used to store control information for data packet transmission, i.e., the data packet header contains metadata required for network transmission, and its main function is to ensure that data can be correctly routed, transmitted, and processed. The data packet payload is the valid data portion actually transmitted in the data packet, i.e., the content that the upper layer protocol or user needs to transmit.

[0198] like Figure 5 As shown, the embodiment of the present application provides an optimized data packet structure:

[0199] (1) The header of the data packet in the embodiment of the present application is configured to have a first fixed length.

[0200] As an example, the embodiment of the present application may determine the first fixed length based on the type of the data packet according to a mapping relationship between a specific data packet type and the first fixed length.

[0201] The embodiment of the present application configures the header of the data packet to a fixed length, which helps to quickly parse and reduce processing delays.

[0202] (2) The header of the data packet in the embodiment of the present application includes but is not limited to fields such as the data packet identification, the priority of the data packet, the delay requirement of the data packet, and the check code of the data packet.

[0203] The packet identifier is used to identify fragments of the same packet, ensuring that the receiver can correctly reassemble the fragmented packets. The packet check code is used to detect whether a bit error occurs during the transmission of the packet (such as data corruption caused by noise, hardware failure, etc.).

[0204] The delay requirement of the data packet is used to indicate the conditions that the transmission delay of the data packet needs to meet during transmission. The delay requirement includes but is not limited to one or more of the data packet processing delay, queuing delay, and data transmission delay.

[0205] As an example, the latency requirement for the packet header in the embodiments of the present application can be an overall latency requirement, that is, it does not distinguish between packet processing delay, queuing delay, and data transmission delay. For example, if the latency requirement for the header of Packet 1 is Delay A, then if the overall latency of Packet 1, including the packet processing delay, queuing delay, and data transmission delay, does not exceed Delay A, the latency requirement is met.

[0206] As another example, the delay requirements of the data packet header in the embodiment of the present application can be expressed based on different delay types, that is, different bits can be occupied according to different delay types. For example, the packet processing delay, queuing waiting delay, data transmission delay, etc. can correspond to different fields respectively. The number of bits of each field depends on the delay range that needs to be represented. For example, the packet processing delay A, queuing waiting delay B, and data transmission delay C in the header of packet 1, then the packet processing delay of packet 1 needs to meet the packet processing delay A, the queuing waiting delay of packet 1 needs to meet the queuing waiting delay B, and the data transmission delay of packet 1 needs to meet the data transmission delay C. The priority of the data packet is used to indicate the priority information of the data packet relative to other data packets during transmission.

[0207] As an example, when two data packets have the same priority, embodiments of the present application can further determine the data packet that needs to be scheduled first based on the latency requirements of the two data packets. When two data packets have the same latency requirements, embodiments of the present application can further determine the data packet that needs to be scheduled first based on the priorities of the two data packets. When the priorities and latency requirements of the two data packets are different, the data packet that needs to be scheduled first can be determined based on the actual scheduling policy.

[0208] Furthermore, the embodiment of the present application can adjust the priority of the data packet based on the delay requirement of the data packet, so that the transmission delay of the data packet in actual transmission (ie, the first delay mentioned above) meets the delay requirement.

[0209] (3) The data payload of the data packet in the embodiment of the present application is configured as a variable-length data segment.

[0210] As an example, embodiments of the present application can adjust the data payload of the data packet based on the target application scenario according to the mapping relationship between the application scenario and the data payload. For example, in large-scale parallel computing, a larger data payload may be required to transmit a large amount of data, while in real-time task processing, a smaller data payload may be used to reduce processing latency.

[0211] The embodiments of the present application configure the packet header to a fixed length, facilitating rapid parsing and reducing processing delays. By configuring the data payload of the packet to a variable length, the size of the data block can be better modulated according to specific application scenarios, ensuring transmission flexibility while reducing the overhead caused by redundant fields.

[0212] Configuration method 2: Transmission scheduling algorithm optimization.

[0213] In some implementations, the embodiments of the present application introduce a preemptive scheduling algorithm based on a priority queue to pre-schedule delay-sensitive data packets, thereby better ensuring that high-priority data can obtain a transmission channel first.

[0214] As an example, the embodiment of the present application can be the first delay T corresponding to the data packet total For example, the first time delay T in the embodiment of the present application is total It can be decomposed into the following formula 1:

[0215] T total =T proc +T queue +T trans Formula 1

[0216] Among them, T proc is the packet processing delay, T queue is the waiting time in queue, Ttrans The data transmission delay.

[0217] In some implementations, the embodiments of the present application may adopt a preemptive scheduling strategy to reduce the queuing delay of data packets, reduce data transmission delay through optimal routing and hardware acceleration, etc., which are not limited here.

[0218] For example, assuming that the embodiment of the present application adopts the M / M / 1 queue model, the queuing delay T queue It can be determined by the following formula 2:

[0219]

[0220] Where λ is the packet arrival rate and μ is the service rate.

[0221] It is understandable that the embodiments of the present application may also adopt other queue models (such as M / M / c or M / G / 1, etc.), and different queue waiting delay calculation formulas may be configured for different queue models.

[0222] After obtaining the above-mentioned data packet processing delay, queuing waiting delay, data transmission delay and other related delays, the embodiment of the present application can achieve rapid scheduling of high-real-time data packets by adjusting the priority weights based on the above-mentioned related delays and specific delay requirements.

[0223] Example 2: Dynamic bandwidth adaptive scheduling configuration.

[0224] The embodiments of this application address the dynamic changes in heterogeneous computing loads by proposing real-time bandwidth monitoring and adaptive allocation strategies to achieve intelligent bandwidth scheduling between different chiplets. The embodiments of this application can perform dynamic bandwidth adaptive scheduling based on, but not limited to, the following three configurations.

[0225] Configuration method 1: Configure the real-time bandwidth monitoring module.

[0226] The embodiment of the present application can collect data flow information of each chiplet in real time through built-in sensors and monitoring circuits to form a data flow map, thereby better providing a real-time basis for bandwidth scheduling.

[0227] Configuration method 2: Configure a dynamic bandwidth allocation algorithm.

[0228] The bandwidth scheduling control module (located in the master node, or main processor, etc.) of the embodiment of the present application can obtain the real-time data flow D of each chiplet based on the bandwidth monitoring module. i , based on the real-time data traffic D of each chiplet i Preset weight ω i Dynamic bandwidth allocation is performed. The allocation formula can be found in the following formula 3:

[0229]

[0230] Among them, B total Denotes the total available bandwidth, D i is the real-time data traffic of the i-th chiplet, ω i is the weight parameter of the i-th chiplet.

[0231] Configuration method 3: Configure software and hardware collaborative design.

[0232] The bandwidth allocation algorithm in this embodiment of the application can be implemented in hardware through a dedicated bandwidth scheduling control module to ensure that scheduling delays are minimized, while dynamically adjusting resource allocation in conjunction with software. Through this module, the system can flexibly respond to load changes, improving overall bandwidth utilization and system performance.

[0233] like Figure 6 As shown, it is a schematic diagram of a process for dynamically performing bandwidth scheduling based on the above-mentioned dynamic bandwidth adaptive scheduling configuration provided by an embodiment of the present application, which may include the following steps:

[0234] S601: Based on the bandwidth monitoring module, obtain a first data traffic map corresponding to at least one transmission node.

[0235] As an example, the bandwidth monitoring module described in the embodiment of the present application includes a built-in sensor and a monitoring circuit.

[0236] S602: Determine to execute a first bandwidth scheduling solution based on at least one first data traffic map and a preset dynamic bandwidth allocation algorithm.

[0237] As an example, an embodiment of the present application applies the above formula 3 to determine the bandwidth allocated to each transmission node based on the preset weight corresponding to each transmission node and the first data traffic map, thereby obtaining the first bandwidth scheduling scheme based on the bandwidth allocated to all transmission nodes.

[0238] S603: The bandwidth scheduling control module performs bandwidth scheduling based on the first bandwidth scheduling solution.

[0239] S604: Each transmission node interface obtains the corresponding allocated bandwidth.

[0240] Example 3: Configuring distributed clock synchronization and error checking mechanisms.

[0241] In a multi-chiplet system, data synchronization and error control are key to ensuring low-latency transmission. To this end, the present application embodiment can adopt but is not limited to the following two configurations:

[0242] Configuration method 1: Distributed clock synchronization technology.

[0243] As an example, embodiments of the present application may employ a distributed clock synchronization solution, where each chiplet achieves clock alignment through a dedicated synchronization signal (such as a synchronization pulse or synchronization frame), ensuring that each chiplet shares a unified time reference. Specifically, embodiments of the present application may utilize an adaptive delay compensation algorithm to automatically adjust the clock deviation of each chiplet, reducing the risk of data errors caused by clock differences.

[0244] Configuration method 2: Lightweight error checking and fast retransmission mechanism.

[0245] As an example, embodiments of the present application introduce a checksum into the packet header to detect errors in real time during packet transmission. For example, the number of error packets is typically determined by an error detection mechanism in hardware or data transmission protocols (such as a cyclic redundancy check (CRC) check). When an error occurs during the transmission of a packet, the number of detected error packets is recorded and a fast retransmit mechanism is triggered.

[0246] As an example, the bit error rate calculation formula provided in the embodiment of the present application can be shown in the following formula 4:

[0247]

[0248] Among them, N error is the number of error packets, N total The total number of transmitted packets.

[0249] As an example, when an error is detected in an embodiment of the present application, a dedicated low-latency channel can be used to quickly trigger a retransmission mechanism to shorten the error recovery time.

[0250] This solution effectively reduces delay fluctuations caused by clock deviation and transmission errors, and improves the reliability and real-time performance of the overall system.

[0251] In the embodiment of the present application, bandwidth scheduling can be performed by applying one of the solutions in Examples 1 to 3 above alone according to actual conditions, or by combining any two or three of the solutions in Examples 1 to 3 above according to actual conditions, which is not limited here.

[0252] Based on the same inventive concept, an electronic device is also provided in the embodiment of the present application. The electronic device can perform the steps or operations in the bandwidth scheduling method provided in any of the above embodiments and can achieve the same technical effects, which will not be described in detail here. In this embodiment, the structure of the electronic device can be as follows: Figure 7As shown, it includes a memory 701 , a communication module 703 and one or more processors 702 .

[0253] Memory 701 is used to store computer programs executed by processor 702. Memory 701 may mainly include a program storage area and a data storage area. The program storage area may store an operating system and programs required for running instant messaging functions, while the data storage area may store various instant messaging messages and operating instruction sets.

[0254] Memory 701 may be a volatile memory, such as random-access memory (RAM); a non-volatile memory, such as read-only memory, flash memory, a hard disk drive (HDD), or a solid-state drive (SSD); or any other medium capable of carrying or storing a desired computer program in the form of instructions or data structures and accessible by a computer, but is not limited thereto. Memory 701 may be a combination of the above memories.

[0255] The processor 702 may include one or more central processing units (CPUs) or digital processing units, etc. The processor 702 is configured to implement the above-mentioned bandwidth scheduling method when calling the computer program stored in the memory 701 .

[0256] The communication module 704 is used to communicate with electronic devices and other servers.

[0257] The specific connection medium between the memory 701, the communication module 703 and the processor 702 is not limited in the embodiment of the present application. Figure 7 In the embodiment, the memory 701 and the processor 702 are connected via a bus 704. Figure 7 The connections between the other components are shown in bold lines, which are only for illustration and are not intended to be limiting. The bus 704 can be divided into an address bus, a data bus, a control bus, etc. For ease of description, Figure 7 The diagram shows a single thick line, but this does not indicate that there is only one bus or one type of bus.

[0258] The memory 701 stores a computer storage medium, which stores computer-executable instructions for implementing the bandwidth scheduling method of the embodiment of the present application. The processor 702 is configured to execute the bandwidth scheduling method.

[0259] Based on the same inventive concept, an embodiment of the present application provides another bandwidth scheduling device 800 .

[0260] Figure 8 This is a schematic diagram of the structure of a bandwidth scheduling device provided in an embodiment of the present application. Figure 8 As shown, in one possible scenario, the device includes:

[0261] Processing module 801 is configured to determine a data packet to be transmitted corresponding to at least one transmission node; obtain a latency requirement for each data packet to be transmitted based on header information of each data packet to be transmitted, wherein the header information includes the latency requirement of the corresponding data packet and a data packet identifier; obtain first bandwidth status information, wherein the bandwidth status information is used to reflect the load status of each transmission node in a first time period; and determine a first bandwidth scheduling scheme based on the latency requirement of each data packet to be transmitted and the first bandwidth status information.

[0262] The transceiver module 802 is configured to transmit the data packet to be transmitted using the first bandwidth scheduling solution.

[0263] In one possible design, the processing module 801 is specifically configured to:

[0264] Based on the first bandwidth scheduling scheme, bandwidths allocated to different transmission nodes among the at least one transmission node are determined; and based on the bandwidths allocated to different transmission nodes, data packets to be transmitted corresponding to different transmission nodes are transmitted in parallel.

[0265] In one possible design, the processing module 801 is specifically configured to:

[0266] Determining, based on the first bandwidth scheduling scheme, a bandwidth allocated to a first node among the at least one transmission node;

[0267] Based on the bandwidth allocated by the first node, the data packets to be transmitted corresponding to the first node are transmitted in sequence; or, if the bandwidth allocated by the first node meets the transmission requirements of all data packets to be transmitted corresponding to the first node, all data packets to be transmitted corresponding to the first node are transmitted in parallel; or, if the bandwidth allocated by the first node meets the transmission requirements of part of the data packets to be transmitted corresponding to the first node, based on the latency requirements of the data packets to be transmitted, data packets to be transmitted with low latency requirements are transmitted first.

[0268] In one possible design, the processing module 801 is specifically configured to:

[0269] When the data packet to be transmitted is transmitted based on the first bandwidth scheduling scheme, the first bandwidth scheduling scheme is dynamically updated according to the transmission status of the data packet to be transmitted.

[0270] In one possible design, the processing module 801 is further configured to:

[0271] Based on the first bandwidth status information, predict the load of each node in a second time period; based on the load of each node in the second time period, determine a second bandwidth scheduling scheme; based on the second bandwidth scheduling scheme, perform data transmission in the second time period.

[0272] In one possible design, the processing module 801 is specifically configured to:

[0273] Based on the processing time of each data packet to be transmitted in each processing stage, the packet processing delay of each data packet to be transmitted is determined; based on the arrival rate of each data packet to be transmitted and the service rate, the queuing waiting delay of each data packet to be transmitted is determined; according to the transmission link status corresponding to each data packet to be transmitted, the data transmission delay of each data packet to be transmitted is determined; based on the packet processing delay, the queuing waiting delay, and the data transmission delay, a first delay corresponding to each data packet to be transmitted is obtained; and based on the first delay corresponding to each data packet to be transmitted and the corresponding delay requirement, a first bandwidth scheduling scheme is determined.

[0274] In one possible design, the processing module 801 is specifically configured to:

[0275] The processing time of each data packet to be transmitted in each processing stage is tracked and recorded by a hardware timer, and the processing time of each processing stage is analyzed in combination with a delay model to obtain the data packet processing delay of each data packet to be transmitted.

[0276] In one possible design, the transmission link status corresponding to each data packet to be transmitted includes one or more of the transmission time between the source and destination ends of the transmission link, the bandwidth information of the transmission link, or the delay information of the transmission link.

[0277] In one possible design, the processing module 801 is specifically configured to:

[0278] Based on the delay requirement of each data packet to be transmitted and the first delay of each data packet to be transmitted, determine the first transmission priority among multiple data packets to be transmitted; based on the first transmission priority, update the priority in the header information of each data packet; based on the priority in the header information of each data packet to be transmitted and the first bandwidth status information, determine the first bandwidth scheduling scheme.

[0279] In one possible design, the processing module 801 is specifically configured to:

[0280] Based on the delay requirement of each data packet to be transmitted and the first delay of each data packet to be transmitted, a first data packet is determined from the data packets to be transmitted, where the first data packet is a data packet among the data packets to be transmitted whose first delay does not meet the corresponding delay requirement; a first transmission channel is determined based on the first bandwidth state information, and the first data packet is transmitted based on the first transmission channel.

[0281] In one possible design, the first transmission priority is used to ensure that the first delay corresponding to a first threshold number or a first threshold proportion of data packets to be transmitted meets the corresponding delay requirement.

[0282] In one possible design, the processing module 801 is specifically configured to:

[0283] Based on the delay requirement of each data packet to be transmitted, the first delay of each data packet to be transmitted and the first bandwidth status information, a first transmission priority among multiple data packets to be transmitted is determined; based on the first transmission priority, the priority in the header information of each data packet is updated; and data packet transmission is performed based on the priority in the header information of each data packet to be transmitted.

[0284] In one possible design, the processing module 801 is specifically configured to:

[0285] When a first delay corresponding to a first data packet does not meet the delay requirement of the first data packet, the priority level in the header information of the first data packet is increased; the first data packet is any data packet in the data packets to be transmitted.

[0286] In one possible design, the processing module 801 is further configured to:

[0287] The first data packet is transmitted through the first transmission channel and hardware acceleration.

[0288] In one possible design, the processing module 801 is specifically configured to:

[0289] Obtain data flow information of each transmission node; determine the bandwidth allocated to each transmission node based on the data flow information of each transmission node, the bandwidth allocation weight corresponding to each transmission node, and the first bandwidth status information; determine the first bandwidth scheduling scheme based on the bandwidth allocated to each transmission node and each data packet to be transmitted.

[0290] In one possible design, the processing module 801 is further configured to:

[0291] Collect data flow information of each transmission node in real time; generate a real-time data flow map based on the data flow information of each transmission node; and dynamically update the first bandwidth scheduling solution based on the real-time data flow map.

[0292] In one possible design, the processing module 801 is further configured to:

[0293] After the second data packet is transmitted, a check code included in the header information of the second data packet is obtained, where the check code is used to check whether an error occurs during the transmission of the second data packet, and the second data packet is any data packet among the data packets to be transmitted; after determining that the second data packet has a transmission error based on the check code, the second data packet is retransmitted through a second transmission channel; wherein the second transmission channel is a preset low-latency transmission channel, which is used to perform data packet retransmission.

[0294] In one possible design, the processing module 801 is further configured to:

[0295] Obtain the synchronization signal corresponding to each transmission node; determine the delay compensation between each transmission node through an adaptive delay compensation algorithm based on the synchronization signal corresponding to each transmission node; and adjust the clock deviation of each transmission node based on the delay compensation between each transmission node.

[0296] In another possible scenario, the device includes:

[0297] The transceiver module 802 is used to receive data packets sent by the master node based on a first bandwidth scheduling scheme; the first bandwidth scheduling scheme is determined by the master node based on the delay requirement in the packet header information of each data packet to be transmitted and the first bandwidth status information, and the bandwidth status information is used to reflect the load status of each node in the first time period.

[0298] In one possible design, the bandwidth scheduling apparatus further includes:

[0299] The processing module 801 is used to obtain its own data flow information; and send the data flow information to the master node through the transceiver module.

[0300] In one possible design, the processing module 801 is further configured to:

[0301] The module sends its own synchronization signal to the master node through the transceiver module; receives the delay compensation determined by the master node based on the synchronization signal; and adjusts its own clock deviation based on the delay compensation.

[0302] Based on the same inventive concept, embodiments of the present application provide a computer-readable storage medium, a computer program product comprising: computer program code. When the computer program code is executed on a computer, it causes the computer to execute any of the bandwidth scheduling methods discussed above. Because the principles underlying the problem solved by the computer-readable storage medium are similar to those of the bandwidth scheduling method, the implementation of the computer-readable storage medium can be referred to as the implementation of the method, and any repetitions will be omitted.

[0303] Refer to the following Figure 9 hereinafter, a computing device 900 according to this embodiment of the present application is described. Figure 9 The computing device 900 is merely an example and should not limit the functions and scope of use of the embodiments of the present application.

[0304] like Figure 9 The computing device 900 is implemented as a general-purpose computing device. Components of the computing device 900 may include, but are not limited to, the at least one processing unit 901 described above, the at least one storage unit 902 described above, and a bus 903 connecting various system components (including the storage unit 902 and the processing unit 901).

[0305] Bus 903 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, and a processor or local bus using any of a variety of bus architectures.

[0306] The storage unit 902 may include a readable medium in the form of a volatile memory, such as a random access memory (RAM) 921 and / or a cache memory 922 , and may further include a read-only memory (ROM) 923 .

[0307] The storage unit 902 may also include a program / utility 925 having a set (at least one) of program modules 924, such program modules 924 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0308] The computing device 900 may also communicate with one or more external devices 904 (e.g., a keyboard, a pointing device, etc.), one or more devices that enable a user to interact with the computing device 900, and / or any device that enables the computing device 900 to communicate with one or more other computing devices (e.g., a router, a modem, etc.). Such communication may be performed via an input / output (I / O) interface 905. Furthermore, the computing device 900 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) via a network adapter 906. Figure 9 As shown, network adapter 906 communicates with other modules used in computing device 900 via bus 903. It should be understood that, although not shown in the figure, other hardware and / or software modules can be used in conjunction with computing device 900, including but not limited to microcode, device drivers, redundant processors, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0309] Based on the same inventive concept, an embodiment of the present application also provides a bandwidth scheduling system, which may include the aforementioned master node and transmission node.

[0310] The present application also provides a computer program product. The methods described herein can be implemented in whole or in part using software, hardware, firmware, or any combination thereof. When implemented using software, they can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described herein are performed in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user device, a core network device, an OAM, or other programmable device.

[0311] The computer-readable storage medium can be implemented as a computer program product, that is, an embodiment of the present application further provides a computer-readable storage medium, which includes a computer program. When the computer program is executed by a processor, it implements any of the above-mentioned bandwidth scheduling methods.

[0312] The computer program or instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer program or instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired or wireless method. The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium, such as a floppy disk, a hard disk, or a magnetic tape; an optical medium, such as a digital video disk; or a semiconductor medium, such as a solid-state drive. The computer-readable storage medium may be a volatile or non-volatile storage medium, or may include both volatile and non-volatile types of storage media.

[0313] In the embodiments provided in the present application above, the methods provided in the embodiments of the present application are introduced from the perspective of an electronic device as an execution subject. In order to implement the various functions in the methods provided in the embodiments of the present application above, the electronic device may include a hardware structure and / or a software module, and implement the above functions in the form of a hardware structure, a software module, or a hardware structure plus a software module. Whether a function of the above functions is executed in the form of a hardware structure, a software module, or a hardware structure plus a software module depends on the specific application and design constraints of the technical solution.

[0314] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0315] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A bandwidth scheduling method, characterized in that: The method comprises: Determine a data packet to be transmitted corresponding to at least one transmission node; Obtaining a delay requirement for each data packet to be transmitted based on packet header information of each data packet to be transmitted, wherein the packet header information includes the delay requirement for the corresponding data packet and a data packet identifier; Acquire first bandwidth status information, where the bandwidth status information is used to reflect the load status of each transmission node in the first time period; Determining a first bandwidth scheduling scheme based on a delay requirement of each data packet to be transmitted and the first bandwidth state information; The data packet to be transmitted is transmitted based on the first bandwidth scheduling scheme.

2. The method according to claim 1, characterized in that The determining a first bandwidth scheduling scheme based on the delay requirement of each data packet to be transmitted and the first bandwidth state information includes: determining a packet processing delay of each packet to be transmitted based on a processing time of each packet to be transmitted in each processing stage; Determine the queuing delay of each data packet to be transmitted based on the arrival rate of each data packet to be transmitted and the service rate; Determine the data transmission delay of each data packet to be transmitted based on the transmission link status corresponding to each data packet to be transmitted; Obtaining a first delay corresponding to each data packet to be transmitted based on the data packet processing delay, the queuing waiting delay, and the data transmission delay; A first bandwidth scheduling solution is determined based on a first delay corresponding to each to-be-transmitted data packet and a corresponding delay requirement.

3. The method according to claim 2, characterized in that The packet header information also includes the priority of data packet transmission; The determining a first bandwidth scheduling scheme based on the delay requirement of each data packet to be transmitted and the first bandwidth state information includes: Determining a first transmission priority among a plurality of data packets to be transmitted based on a delay requirement of each data packet to be transmitted and a first delay of each data packet to be transmitted; updating a priority in the header information of each data packet based on the first transmission priority; determining a first bandwidth scheduling scheme based on the priority in the header information of each data packet to be transmitted and the first bandwidth status information; and / or, Based on the delay requirement of each data packet to be transmitted and the first delay of each data packet to be transmitted, a first data packet is determined from the data packets to be transmitted, where the first data packet is a data packet among the data packets to be transmitted whose first delay does not meet the corresponding delay requirement; a first transmission channel is determined based on the first bandwidth state information, and the first data packet is transmitted based on the first transmission channel.

4. The method according to any one of claims 1 to 3, characterized in that The determining a first bandwidth scheduling scheme based on the delay requirement of each data packet to be transmitted and the first bandwidth state information includes: Obtaining data flow information of each transmission node in the at least one transmission node; Determine the bandwidth allocated to each transmission node based on the data flow information of each transmission node, the bandwidth allocation weight corresponding to each transmission node, and the first bandwidth status information; The first bandwidth scheduling scheme is determined based on the bandwidth allocated to each transmission node and each data packet to be transmitted.

5. The method according to any one of claims 1 to 3, characterized in that The method further comprises: Collect data flow information of each transmission node in real time; Generate real-time data traffic graph based on the data traffic information of each transmission node; Based on the real-time data traffic map, the first bandwidth scheduling solution is dynamically updated.

6. The method according to any one of claims 1 to 3, characterized in that The method further comprises: After the second data packet is transmitted, obtaining a check code included in the header information of the second data packet, the check code being used to check whether an error occurs during the transmission of the second data packet, where the second data packet is any data packet among the data packets to be transmitted; After determining, based on the check code, that the second data packet is transmitted incorrectly, retransmitting the second data packet through a second transmission channel; The second transmission channel is a preset low-latency transmission channel used to perform data packet retransmission.

7. The method according to any one of claims 1 to 3, characterized in that The method further comprises: Obtain the synchronization signal corresponding to each transmission node; Based on the synchronization signal corresponding to each transmission node, the delay compensation between each transmission node is determined by an adaptive delay compensation algorithm; Based on the delay compensation between each transmission node, the clock deviation of each transmission node is adjusted.

8. A transaction identification device, characterized in that: The method comprises a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor is enabled to perform the steps of any one of the methods of claims 1 to 7.

9. A transaction identification device, characterized in that: include: A processing module, configured to determine a data packet to be transmitted corresponding to at least one transmission node; Obtaining, based on header information of each data packet to be transmitted, a delay requirement of each data packet to be transmitted, the header information including the delay requirement of the corresponding data packet and a data packet identifier; obtaining first bandwidth status information, the bandwidth status information being used to reflect a load condition of each transmission node in a first time period; and determining a first bandwidth scheduling scheme based on the delay requirement of each data packet to be transmitted and the first bandwidth status information; The transceiver module is configured to transmit the data packet to be transmitted using the first bandwidth scheduling scheme.

10. A computer-readable storage medium, characterized in that The method comprises a computer program. When the computer program is run on an electronic device, the computer program is used to enable the electronic device to execute the steps of any one of the methods of claims 1 to 7.

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