Processor performance optimization method and apparatus, electronic device, and storage medium

Abstract

The application discloses a processor performance optimization method and device, electronic equipment and storage medium, which can solve the problems that the performance of the processor cannot be analyzed from multiple angles and the performance of the processor cannot be accurately and effectively optimized. Real-time running data of a target processor is acquired, the real-time running data including hardware perception information, software perception information and load information; multi-dimensional feature extraction is performed on the running data to obtain target load features, the target load features including a cache miss rate and / or a branch prediction error rate; an optimization strategy corresponding to the target load features is determined according to the target load features and a target performance optimization strategy model; the target performance optimization strategy model is obtained through model training in advance; and the performance of the target processor is optimized through the optimization strategy, so that the cache miss rate and / or the branch prediction error rate are reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of processor optimization, and particularly relates to a processor performance optimization method and device, electronic equipment and a storage medium. BACKGROUND

[0002] Traditional performance optimization of a processor mostly relies on artificial experience to preset parameters for optimization, and in a dynamic load change scenario, the adaptability is poor. In addition, the traditional scheme mostly only focuses on the influence of a PMC event on performance, and cannot analyze the performance of the processor from multiple angles, so the performance of the processor cannot be accurately and effectively optimized. SUMMARY

[0003] The present application provides a processor performance optimization method and device, electronic equipment and a storage medium to at least solve the problem that the performance of the processor cannot be analyzed from multiple angles and the performance of the processor cannot be accurately and effectively optimized.

[0004] The present application provides a processor performance optimization method, comprising: obtaining real-time running data of a target processor, wherein the real-time running data comprises hardware perception information, software perception information and load information;

[0005] Multi-dimensional feature extraction is performed on the running data to obtain target load features, wherein the target load features comprise a cache miss rate and / or a branch prediction error rate;

[0006] According to the target load features and a target performance optimization strategy model, an optimization strategy corresponding to the target load features is determined, wherein the target performance optimization strategy model is obtained through model training in advance;

[0007] The target processor is optimized through the optimization strategy to reduce the cache miss rate and / or the branch prediction error rate.

[0008] The present application also provides a processor performance optimization device, comprising: an acquisition module configured to obtain real-time running data of a target processor, wherein the real-time running data comprises hardware perception information, software perception information and load information;

[0009] A processing module is configured to perform multi-dimensional feature extraction on the running data to obtain target load features, wherein the target load features comprise a cache miss rate and / or a branch prediction error rate;

[0010] The processing module is further configured to determine an optimization strategy corresponding to the target load features according to the target load features and a target performance optimization strategy model, wherein the target performance optimization strategy model is obtained through model training in advance;

[0011] The processing module is further configured to perform performance optimization on the target processor by using the optimization strategy, so as to reduce the cache miss rate and / or the branch prediction error rate.

[0012] The application further provides an electronic device, comprising a memory configured to store a computer program, and a processor configured to execute the computer program to implement the steps of any of the processor performance optimization methods.

[0013] The application further provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps of any of the processor performance optimization methods.

[0014] The application further provides a computer program product, comprising a computer program, and the computer program is executed by a processor to implement the steps of any of the processor performance optimization methods.

[0015] According to the application, real-time running data of a target processor is acquired, the real-time running data comprising hardware perception information, software perception information and load information; multi-dimensional feature extraction is performed on the running data to obtain target load features, the target load features comprising a cache miss rate and / or a branch prediction error rate; an optimization strategy corresponding to the target load features is determined according to the target load features and a target performance optimization strategy model, the target performance optimization strategy model being obtained by model training in advance; and performance optimization is performed on the target processor by using the optimization strategy, so as to reduce the cache miss rate and / or the branch prediction error rate. In this scheme, running data of a processor is acquired from multiple angles, and then multi-dimensional features are extracted to input a pre-trained model, so that an optimization strategy that best matches a current load running scenario can be obtained, thereby effectively improving the optimization effect of the processor. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the application, the drawings required in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort.

[0017] Figure 1 A flowchart of a processor performance optimization method provided by an embodiment of the application Figure 1 ;

[0018] Figure 2 A flowchart of a processor performance optimization method provided by an embodiment of the application Figure 2 ;

[0019] Figure 3 A structural diagram of a processor performance optimization device provided by an embodiment of the application

[0020] Figure 4 A structural diagram of an electronic device is provided in the embodiments of the present application. DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, but not all embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0022] It should be noted that, in the description of the present application, the terms “comprising”, “containing” or any other variants thereof are intended to cover non-exclusive containing, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The terms “first”, “second” and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0023] It should be noted that, in the embodiments of the present application, the words “exemplary” or “for example” are used to represent an example, illustration or description. Any embodiment or design scheme described as “exemplary” or “for example” in the embodiments of the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the words “exemplary” or “for example” are intended to present the relevant concept in a specific manner.

[0024] The traditional method relies on manual experience to preset the compilation parameters (such as -march / -mtune of the multi-language and cross-platform compiler suite (GNU Compiler Collection, GCC)), which cannot adapt to the changes of dynamic load characteristics; the existing tools (such as perf / Likwid) only collect limited power and platform management controller (Power Management Controller, PMC) events, lack of correlation analysis of instruction stream micro characteristics and system layer behaviors; the existing solutions mostly focus on the improvement of the number of cycle instructions (Instructions Per Second, IPS), ignoring the balance of multiple targets such as power consumption / temperature / tail delay; the optimization scheme based on offline analysis needs several hours to generate a report, which cannot meet the real-time tuning requirements; therefore, it is necessary to solve the performance loss problem of the processor when running the SPEC CPU and other compute-intensive loads due to hardware resource contention, mismatch of compilation parameters, and rigid running time strategy.

[0025] To solve all or part of the above technical problems, an embodiment of the present application provides a processor performance optimization method and device, electronic equipment and storage medium, real-time running data of a target processor is obtained, the real-time running data including hardware perception information, software perception information and load information; multi-dimensional feature extraction is performed on the running data to obtain target load features, the target load features including cache miss rate and / or branch prediction error rate; an optimization strategy corresponding to the target load features is determined according to the target load features and a target performance optimization strategy model, the target performance optimization strategy model being obtained through model training in advance; and the target processor is optimized through the optimization strategy to reduce the cache miss rate and / or the branch prediction error rate. In this scheme, running data of the processor is obtained from multiple angles, and then multi-dimensional features are extracted to input a pre-trained model, so that the optimization strategy most matching the current load running scenario can be obtained, thereby effectively improving the processor optimization effect.

[0026] In order for those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0027] As shown in Figure 1 , Figure 1 The flowchart of the processor performance optimization method provided by the embodiments of the present application can include the following steps:

[0028] 101. Real-time running data of a target processor is obtained.

[0029] In the embodiments of the present application, the target processor is a processor that needs to be monitored and optimized for performance, and the real-time running data can specifically include hardware perception information, software perception information and load information, and the real-time running data can specifically constitute a three-dimensional perception matrix.

[0030] In some embodiments, the hardware perception information can specifically include an event set and an instruction stream quantity heat map. Specifically, a preset event can be collected according to a preset sampling frequency to obtain the event set; and an instruction stream quantity heat map can be collected through an instruction stream sampling technology.

[0031] It should be noted that based on the Intel PT instruction stream sampling technology, the PMC events of the CPU can be deeply mined according to a preset sampling frequency (for example, 10 ms is collected once), such as the triggering condition L1D_PREFETCH_TRIGGER of the CPU L1 data cache prefetch, the execution stall period CYCLE_ACTIVITY.STALLS_LDM_PENDING caused by the memory load instruction waiting for data and other unusual events. In addition, based on the Intel PT (ProcessorTrace) instruction stream sampling technology, the IPC heat map can be captured according to the preset sampling frequency (for example, 10 ms is collected once), and the IPC heat map can specifically describe the resource occupation of each cache and load of the CPU.

[0032] In some embodiments, the software awareness information specifically can include compiler optimization markers and kernel behavior information. Specifically, the system running file can be parsed to obtain the compiler optimization markers, and the processor running process can be monitored to obtain the kernel behavior information.

[0033] It should be noted that the ELF binary file can be dynamically parsed to obtain the compiler optimization markers. The ELF binary file is a standard binary file format widely used in Unix-like systems (such as Linux, FreeBSD, Android, etc.), used to store executable programs, object files, shared libraries and core dump files. That is, the ELF binary file can be automatically generated and continuously updated during the running process of the CPU, and the compiler optimization markers can be directly read from the ELF binary file, such as __attribute__((optimize("O3"))). The compiler optimization markers can be related to different compilation directions and loads, such as focusing more on energy efficiency, or focusing more on performance or focusing more on security redundancy. In addition, the eBPF can be used to dynamically load and safely execute sandboxed programs to track the kernel behavior of the process in real time, including scheduling delay, memory allocation mode, etc. At the same time, the kernel behavior can be network filtered and performance analyzed, etc. The eBPF (extended Berkeley Packet Filter) is a revolutionary technology in the Linux kernel, which allows users to safely and efficiently run custom programs in the kernel without modifying the kernel code or loading kernel modules.

[0034] In some embodiments, the load information specifically can include instruction mix variance and cache distribution characteristics. Specifically, the instruction distribution of multiple types of instructions can be calculated to obtain the instruction mix variance, and a cache access matrix can be constructed to obtain the cache distribution characteristics.

[0035] It should be noted that, by analyzing the instruction execution characteristics of the IMF program instruction execution characteristics, the dynamic distribution of different instruction types (such as AVX512 vector instructions, branch instructions, memory access instructions, etc.) is focused on, the sliding window variance of the instruction type proportion is calculated, and the instruction mixing degree variance is obtained. In the running process of the CPU, many instructions are in circulation at the same time. In order to count the distribution and dynamic circulation of various types of instructions, a preset window can be used for sliding to calculate the instruction dynamic distribution variance. In addition, an L3 cache access mode matrix can be constructed to identify the access mode of the program during running, so as to identify the spatial distribution and time locality characteristics.

[0036] In some embodiments, the running data of the target processor can also include other parameters, which are not limited in the embodiments of the present application.

[0037] 102. Multi-dimensional feature extraction is performed on the running data to obtain target load characteristics.

[0038] In the embodiments of the present application, after obtaining the running data of the target processor, the running data needs to be analyzed. In order to improve the comprehensiveness of the processor characteristics, the running characteristics can be extracted from multiple dimensions to obtain target load characteristics, which at least include cache miss rate and / or branch prediction error rate.

[0039] It should be noted that the cache miss rate can be used to describe the error rate of CPU data pre-reading in cache. That is, when the CPU is running, the load is constantly updated. In order to improve the data processing efficiency, the data that may be called can be pre-read before the load and placed in the cache. If the load indeed needs to use the pre-read called data, it is considered that the pre-reading is correct. If the load does not need to use the pre-read called data, it is considered that the pre-reading is incorrect, and the number of pre-reading errors is recorded to calculate the cache miss rate in combination with the total number of pre-reading. The cache miss rate can be used to monitor the L1 / L2 cache efficiency. High miss rate triggers prefetch or NUMA rebinding. Specifically, it can be combined with "unit operation cache pre-reading error number miss number (MPO)" to identify whether the current is a memory intensive stage. The miss number corresponding to the memory intensive stage is higher, and the corresponding cache miss rate is also higher.

[0040] It should be noted that during the running of the CPU, multiple processes can be run simultaneously, and multiple instructions can also be executed simultaneously. In this case, when the data is called, it needs to flow to the corresponding process or instruction. Each process or instruction can be considered as a branch. If the branch to which the data flows is incorrect, the process or instruction execution can fail. Therefore, the number of errors in branch prediction of the data can be counted, so as to calculate the branch prediction error rate in combination with the total number of branch predictions. The branch prediction error rate can affect the efficiency of the instruction pipeline. A high error rate needs to adjust the CPU frequency or the instruction mix degree. Frequency adjustment can alleviate the pipeline stall caused by prediction errors.

[0041] It should be noted that the cache miss rate and / or the branch prediction error rate can be calculated by extracting features from the running data.

[0042] In some embodiments, the target load features can further include an IPC and an instruction mix variance. The IPC (instructions per cycle) can reflect the CPU computing efficiency. A high value indicates a computing-intensive stage, and a low value can encounter a memory bottleneck or a branch prediction error. The IPC value can be obtained by periodically sampling (such as 3 seconds / time) the Linux kernel tool perf. The instruction mix variance quantifies the volatility of the distribution of instruction types (such as integer / floating point / vector instructions). A high variance suggests that the execution strategy needs to be dynamically adjusted.

[0043] 103. Determine the optimization strategy corresponding to the target load features according to the target load features and the target performance optimization strategy model.

[0044] In the embodiments of the present application, the target performance optimization strategy model is obtained by model training in advance. The target load features are input into the target performance optimization strategy model, so as to obtain the optimization strategy corresponding to the target load features output by the target performance optimization strategy model. The optimization strategy can be considered as the strategy that optimizes the performance of the target processor in the current scenario.

[0045] 104. Perform performance optimization on the target processor through the optimization strategy, so as to reduce the cache miss rate and / or the branch prediction error rate.

[0046] In the embodiments of the present application, after the optimization strategy is determined, the optimization strategy can be executed on the target processor to optimize the performance of the target processor through the optimization strategy, so as to reduce the cache miss rate and / or the branch prediction error rate, and achieve the effect of performance optimization.

[0047] In the embodiment of the present application, real-time running data of the target processor is obtained, the real-time running data including hardware perception information, software perception information and load information; multi-dimensional feature extraction is performed on the running data to obtain target load features, the target load features including cache miss rate and / or branch prediction error rate; an optimization strategy corresponding to the target load features is determined according to the target load features and a target performance optimization strategy model, the target performance optimization strategy model being obtained through model training in advance; and the target processor is optimized through the optimization strategy to reduce the cache miss rate and / or the branch prediction error rate. In this scheme, the running data of the processor is obtained from multiple angles, and then multi-dimensional features are extracted to input a pre-trained model, so that the optimization strategy that best matches the current load running scenario can be obtained, thereby effectively improving the optimization effect of the processor.

[0048] As shown in Figure 2 , Figure 2 Another flowchart of the processor performance optimization method provided by the embodiment of the present application can include the following steps:

[0049] 201. Obtain real-time running data of a target processor.

[0050] In the embodiment of the present application, for the description of step 201, please refer to the detailed description of step 101 in the above embodiment, and the embodiment of the present application will not be repeated here.

[0051] 202. Extract features from the running data through a time series convolution network to obtain time series features.

[0052] In the embodiment of the present application, when extracting features from the running data, a neural network model can be used, which can integrate multiple neural network modules, including a time series convolution network (TCN), a graph attention network (GAT) and a cross-attention layer (CrossAttention), etc. The above neural network modules are used to extract features from the running data from multiple dimensions.

[0053] It should be noted that the time series convolution network can be mainly used to extract time series features, so the time series features of the running data can be extracted through the time series convolution network to obtain the time series features.

[0054] Among them, the Temporal Convolutional Network (TCN) is a deep learning model based on the Convolutional Neural Network (CNN) architecture. It is optimized for processing sequential data and achieves efficient time series modeling through causal and dilated convolutions. It has demonstrated superior performance compared to traditional Recurrent Neural Networks (RNNs) in multiple fields. TCN transforms the two-dimensional convolution of traditional CNNs into one-dimensional convolutions, directly operating on time series data. Its core concept is to extract local temporal features by sliding the convolution kernel along the time axis, and to expand the receptive field by stacking layers to capture long-term dependencies. Unlike RNNs, TCNs do not require recursive computation and naturally support parallel training, significantly improving computational efficiency.

[0055] In some embodiments, this can be specifically implemented through the code: self.temporal_conv = TemporalConvNet(input_dim=512), where input_dim=512 indicates that the feature dimension of the input running data is 512.

[0056] In some embodiments, the neural network model may be initialized before feature extraction, which can be achieved through code:

[0057] class WorkloadClassifier(nn.Module);

[0058] def __init__(self);

[0059] """Initialize the neural network model""";

[0060] super().__init__().

[0061] 203. Convert the timing features into a graph structure to obtain a program control flow graph.

[0062] In an embodiment of the present application, after obtaining the timing features of the operating data, the graph features can also be extracted. The graph features are reflected by the program control flow graph, so the timing features can be converted into a graph structure to obtain the program control flow graph.

[0063] In some embodiments, converting the timing features into a graph structure (such as a program control flow graph, CFG) requires analyzing the control flow logic in the program and abstracting the basic blocks, branches, loops, etc. structures into nodes and edges in the graph. The concept of nodes and edges are included in the program control flow graph (CFG), the nodes can represent basic blocks, i.e. a set of sequentially executed instructions, the entry is unique, the exit is unique (except for the last instruction without jump), the edges can represent control flow transitions (such as branches, jumps, function calls, etc.), wherein the edges include directed edges and special edges, the directed edges represent the direction of the control flow (such as if-else, loops), and the special edges include exception handling, function return, etc.

[0064] The step of converting the timing features into a graph structure can include extracting basic blocks, constructing control flow edges, and processing special structures, wherein extracting basic blocks includes: based on the intermediate representation of the program (such as assembly, LLVM IR, source code), identifying a continuous instruction sequence until a jump instruction (such as jmp, br), a conditional branch (such as if, switch) or a function call is encountered, the last instruction of each basic block determines the subsequent control flow (such as goto target or next instruction); constructing control flow edges includes: sequential flow, branch flow, loop flow and function call, the sequential flow refers to the last instruction of the basic block A without jump, adding edge A → next basic block; the branch flow refers to conditional branch (such as if (cond) goto L1; else goto L2;): adding edges A → L1 and A → L2; the loop flow refers to that the loop head (such as while condition) can be pointed to by multiple basic blocks (back edge); the explicit call in the function call includes adding call → function entry and function return → instruction after call, and the implicit control flow (such as exception) needs to be handled additionally. Processing special structures includes: identifying back edges (edges from loop body to loop head), marking loop structure; unreachable code: deleting basic blocks without predecessors (unless it is an entry point); multiple exits: such as return or exit to terminate the control flow.

[0065] 204, feature extraction on the program control flow graph by the graph attention network to obtain graph features.

[0066] In the embodiments of the present application, after obtaining the program control flow graph, the graph features in the program control flow graph can be extracted, and here the graph attention network can be used to extract the features of the program control flow graph to obtain the graph features.

[0067] Among them, the graph attention network is a graph neural network model based on the attention mechanism. It aims to capture complex dependencies in graph-structured data by dynamically calculating the attention weights between nodes. It is suitable for tasks such as node classification, link prediction, image segmentation, and recommendation systems. The core idea of ​​GAT is to calculate the attention coefficient at each node to determine the importance between the node and its neighboring nodes. This attention mechanism enables the model to assign different weights to the relationships between different nodes, thereby better capturing the local structure and global information in the graph data. The GAT model usually consists of multiple attention heads, each of which can learn different attention weights, and finally aggregate the outputs of multiple heads. This multi-head attention mechanism helps to improve the representation and generalization capabilities of the model.

[0068] In some embodiments, this can be specifically implemented through the code: self.gnn = GAT(in_features=64, hidden_features=128), indicating that the input feature dimension is 64 and the hidden layer feature dimension is 128.

[0069] 205. The time series features and graph features are fused through the cross attention mechanism to obtain the target load features.

[0070] In an embodiment of the present application, after obtaining the time series features and the graph features, the time series features and the graph features can be fused, which can be achieved through a cross-attention mechanism, so that the target load features are obtained after fusion.

[0071] Among them, the cross-attention mechanism is a variant of the attention mechanism, mainly used to model the interactive relationship between two different sequences or features. It is widely used in natural language processing (NLP), computer vision (CV), and multimodal tasks, and can dynamically capture the dependencies between different inputs. Compared with self-attention, which processes the relationship between elements within a single sequence (such as the encoder in the Transformer), cross-attention can process the relationship between two different sequences (such as combining the encoder output with the current decoder state in the Transformer decoder). The goal of the cross-attention mechanism is to highlight the relevant parts of the two sequences and suppress the irrelevant parts through dynamic weight allocation. You can first prepare the input and obtain sequence A (such as encoder output): shape is (L_A, d_model); sequence B (such as the current state of the decoder): shape is (L_B, d_model); then you can use linear transformation to map the input to the query (Q), key (K), value (V) space: then perform attention weight calculation, calculate the similarity (dot product or scaled dot product) between the query (Q) and the key (K), and obtain the weight matrix α, shape is (L_B, L_A); finally, perform weighted summation, multiply the weight matrix α by the value (V) to get the output.

[0072] In some embodiments, the above can be implemented by codes as follows:

[0073] self.fusion_layer = CrossAttention(embed_dim=256);

[0074] def forward(self, pmc_data, cfg_graph).

[0075] In summary, the running data is subjected to feature extraction to obtain target load features, which can be represented as follows:

[0076] # Extract time sequence features;

[0077] time_feat = self.temporal_conv(pmc_data);

[0078] # Extract graph structure features;

[0079] graph_feat = self.gnn(cfg_graph);

[0080] # Fuse time sequence and graph features and return the result;

[0081] return self.fusion_layer(time_feat, graph_feat).

[0082] In the embodiments of the present application, the time sequence features and the graph features of the running data are extracted by the neural network module, and then fused, so that the running features of the target processor can be mined from multiple angles, and the matching degree of the optimization strategy can be better guaranteed.

[0083] 206、Obtain running sample data of a sample processor.

[0084] In the embodiments of the present application, in the process of training the target performance optimization strategy model, a large amount of sample data can be obtained, i.e., the running sample data of a sample processor, which can be similar to the running data and include hardware perception information, software perception information and load information, etc. Here, the sample processor can be a processor that can normally run, and the sample processor can run in various actual scenarios, so that the target performance optimization strategy model obtained by running has strong generalization ability.

[0085] 207、Train the preset model by using the running sample data to obtain the target performance optimization strategy model.

[0086] In the embodiments of the present application, after obtaining the running sample data, the model training can be performed, the preset model is trained through the running sample data, and the model obtained after the training is the target performance optimization strategy model.

[0087] In the embodiments of the present application, the model is trained in advance through the sample running data, which can improve the accuracy of the target performance optimization strategy model and enable the model to conform to multiple scenarios and multiple types of processors, thereby improving the generalization ability and optimization strategy decision-making ability.

[0088] In some embodiments, the preset model is trained through the running sample data to obtain the target performance optimization strategy model, which can specifically include: training the preset model through the running sample data to obtain the target performance optimization strategy model, which can specifically include: performing feature extraction on the running sample data to obtain target load sample features; performing performance optimization on the sample processor through a plurality of preset optimization strategies, and recording the sample performance evaluation value of the sample processor corresponding to each optimization strategy; determining the optimization strategy with the highest sample performance evaluation value as the sample optimization strategy; and training the preset model through the target load sample features and the sample optimization strategy to obtain the target performance optimization strategy model.

[0089] It should be noted that, since the model will perform feature extraction on the running data in the actual application process, and input the features into the target performance optimization strategy model to obtain the output result, the running sample data can also be subjected to feature extraction to obtain target load sample features. Here, the process of feature extraction on the running sample data is the same as the process of feature extraction on the running data described above, and will not be repeated.

[0090] After obtaining the cache miss rate and / or branch prediction error rate included in the target load sample features, the sample processor can be subjected to performance optimization through a plurality of optimization strategies, and the sample optimization strategy with the best performance optimization effect on the current sample processor can be selected therefrom. Thus, the preset model is trained according to the target load sample features and the sample optimization strategy, thereby obtaining the target performance optimization strategy model.

[0091] It should be noted that the optimization strategy can include: adjusting the CPU frequency (0.1 GHz step), rebinding the NUMA node, injecting the pre-read instruction, adjusting the L2 prefetch distance, and the like. Different parameter values set in each strategy can also be considered as different optimization strategies. After the sample processor is subjected to performance optimization through a plurality of optimization strategies, the optimization effect can be evaluated through the sample performance evaluation value. The sample performance evaluation value can be understood as a reward function, which is related to the processor speed change amount, the power consumption change amount, and the instruction delay time change amount, and can be specifically represented by the following formula:

[0092]

[0093] wherein, is a sample performance evaluation value, is a processor speed change amount, is a power consumption change amount, is an instruction delay duration change amount, , and are weight values, which can be set and adjusted by themselves, such as: may be related to the current IPC and the target SLA, may be related to the machine room PUE and the real-time electricity price, etc.

[0094] In some embodiments, in the case of target load characteristics including IPC, cache miss rate, branch prediction error rate, and instruction mix variance, the target load characteristics are optimized by adjusting the CPU frequency (0.1 GHz step), rebinding the NUMA node, injecting pre-read instructions, adjusting the L2 prefetch distance, and other optimization strategies. During the optimization process, the numerical value of the sample performance evaluation value is also constantly increasing until it is higher than a certain threshold and gradually stable.

[0095] In the embodiments of the present application, during the model training process, the sample performance evaluation value of each optimization strategy is calculated. The higher the sample performance evaluation value, the better the processor optimization effect. Therefore, by selecting the optimal optimization strategy through the sample performance evaluation value to perform model training, the output accuracy of the target performance optimization strategy model and the effectiveness of the target processor performance optimization can be maximized.

[0096] In some embodiments, the optimization strategy with the highest sample performance evaluation value is determined as the sample optimization strategy, which can specifically include: determining the optimization strategy with the highest sample performance evaluation value and the power consumption index not exceeding the preset thermodynamic constraint as the sample optimization strategy.

[0097] When evaluating the processor performance, a thermodynamic constraint needs to be introduced, that is, the temperature, power consumption, and other thermodynamic parameters of the processor also need to have certain constraint conditions. Specifically, the thermodynamic constraint Tjmax = f (Power, CFD heat dissipation coefficient) can be defined, and the CFD heat dissipation coefficient can be a fixed coefficient value. Specifically, Power*CFD heat dissipation coefficient<MaxTJunction, Power can be understood as a real-time power consumption value, and MaxTJunction can be understood as a maximum power consumption value corresponding to a maximum temperature value. That is, the maximum power consumption of the processor during the optimization process cannot exceed the maximum power consumption value corresponding to the maximum temperature value.

[0098] In the embodiment of the present application, in the model training process, the thermodynamic constraint is also considered, that is, when the processor performance is continuously improved, the value of the thermodynamic parameter should also be controlled not to be too high, which effectively ensures the running safety of the target processor and improves the output accuracy of the target performance optimization strategy model.

[0099] In some embodiments, the sample processor is optimized in performance by a plurality of preset optimization strategies, and the sample performance evaluation value of the sample processor corresponding to each optimization strategy is recorded, which can specifically include: optimizing the sample processor in performance by a plurality of preset optimization strategies, adjusting the data of each optimization strategy by a nonlinear optimizer, and recording the sample performance evaluation value of the sample processor corresponding to each optimization strategy.

[0100] It should be noted that the specific data of the optimization strategy can also be adjusted by itself in the process of optimizing the performance of the sample processor, which can be realized by a nonlinear optimizer. The nonlinear optimizer adopts an improved multi-objective Bayesian optimization (MOBO) algorithm and a kernel function to adapt to a non-smooth parameter space.

[0101] The multi-objective Bayesian optimization (MOBO) algorithm is an intelligent algorithm for solving multi-objective optimization problems. It combines the Bayesian optimization framework and the multi-objective optimization strategy, and can efficiently find a set of Pareto optimal solutions that balance multiple objectives in the case of complex objective functions and high evaluation cost. Bayesian optimization constructs a probabilistic proxy model of the objective function (such as Gaussian process), balances exploration and utilization by combining acquisition functions (such as expected improvement, upper confidence bound), and gradually approaches the global optimal solution. The core idea is to update the knowledge of the objective function using historical observation data to avoid unnecessary sampling. In the multi-objective scenario, the objective function is expanded from a single value to a vector (such as optimizing accuracy, computational efficiency, energy consumption, etc. at the same time). MOBO needs to handle the trade-off between objectives, rather than a single optimal solution. Its goal is to find a set of Pareto optimal solutions through iterative sampling, that is, to improve any solution set without compromising other objectives. Through the Pareto frontier and the acquisition function, MOBO can explicitly handle the trade-off between objectives, avoid the subjectivity of manually setting weights, and provide more comprehensive optimization results.

[0102] In some embodiments, the code can be implemented as follows:

[0103] function [optimal_params] = MOBO_optimize();

[0104] bayesopt(@ObjectiveFunction, ParameterSpace;

[0105] 'AcquisitionFunction', 'EI' ;

[0106] 'Constraints', constraint;

[0107] 'KernelFunction','matern52') ;

[0108] End.

[0109] In the embodiments of the present application, the optimization strategy adjustment is performed by introducing a nonlinear optimizer, and the improved MOBO algorithm and kernel function are adopted to adapt to the non-smooth parameter space, so that the data adjustment of the optimization strategy is more smooth, and the normal operation of the processor is not affected.

[0110] 208. Determine the optimization strategy corresponding to the target load characteristics according to the target load characteristics and the target performance optimization strategy model.

[0111] 209. Perform performance optimization on the target processor through the optimization strategy.

[0112] In the embodiments of the present application, for the description of steps 208-209, please refer to the detailed description of steps 103-104 in the above embodiments, and the embodiments of the present application will not be repeated here.

[0113] 210. Real-time acquire the performance evaluation parameter of the target processor.

[0114] In the embodiments of the present application, in the process of performing performance optimization on the target processor through the optimization strategy, the performance evaluation parameter of the target processor can also be detected, so as to judge whether the current optimization strategy is effective. The performance evaluation parameter can at least include: power consumption parameter, operation speed parameter and delay parameter, that is, current power consumption value, operation speed and delay time length.

[0115] 211. Determine the performance evaluation score of the target processor according to the performance evaluation parameter.

[0116] In the embodiments of the present application, the performance evaluation score here can be understood as the reward function mentioned in the foregoing, that is:

[0117]

[0118] Wherein, is the sample performance evaluation value, is the processor speed change amount, is the power consumption change amount, is the instruction delay time length change amount, , and are weight values, respectively,

[0119] That is, the performance evaluation parameter can be collected, and the change amount of the performance evaluation parameter is calculated in a period of time, and then the reward function is brought in to obtain the performance evaluation score R.

[0120] 212、If the performance evaluation score is higher than the preset score value, it is determined that the optimization strategy is an effective strategy, and the performance optimization of the target processor is continuously performed through the optimization strategy.

[0121] In the embodiments of the present application, in the process of performing performance optimization on the target processor, the performance evaluation score will theoretically gradually increase, and the higher the performance evaluation score, the better the performance of the target processor. Therefore, the preset score value can be set in advance, and the performance evaluation score and the preset score value are compared. If the performance evaluation score is higher than the preset score value, it means that the current optimization strategy is effective for the target processor, and then the performance optimization of the target processor can be continuously performed through the optimization strategy.

[0122] In the embodiments of the present application, in the process of optimizing the target processor, the performance evaluation score obtained by calculation can be used to judge whether the current optimization strategy is suitable and whether there is a performance optimization effect. In this way, the accuracy of the model output can be detected, and appropriate decisions can be made in a timely manner.

[0123] In some embodiments, when the running parameters of the target processor are obtained, the preset sampling frequency of the preset event can be dynamically adjusted, and the preset sampling frequency can be related to IPC and thermodynamic constraints. If the IPC change amount is greater than a preset proportion (for example: 5%), the preset sampling frequency can be 1 kHz; if the temperature is greater than the difference between the thermodynamic constraint value and 10°C (i.e. temperature > thermodynamic constraint value - 10°C), the Turbo frequency reduction detection mode is started; if the IPC change amount is less than or equal to the preset proportion, and the temperature is less than or equal to the difference between the thermodynamic constraint value and 10°C, the 200 Hz reference sampling is maintained.

[0124] In some embodiments, in the entire process of performance optimization of the target processor, a real-time feedback control loop can be constructed, that is, the optimization strategy is continuously adjusted through real-time running parameters, and then the optimization performance is evaluated through the performance evaluation score to adjust the optimization strategy.

[0125] In some embodiments, metadata markers (such as llvm.loop.unroll.disable) are inserted in the compilation phase to describe the cache hit rate; and when L1 cache contention is detected during running, the optimization code is regenerated through JIT, and the runtime features are fed back to the machine learning optimizer (ML-guided Compiler) of the compiler for model training.

[0126] In some embodiments, when a high-density floating-point operation event is detected during the 503.bwaves_r startup phase, an AVX-512 frequency adjustment strategy is activated to avoid frequency reduction due to overheating; and a __builtin_prefetch instruction template is inserted to prefetch adaptive data steps.

[0127] In some embodiments, when an L2 cache miss rate > 15% event occurs, the L2 prefetcher is adjusted by MSR 0x1A4 (set bits 54:55 to '10' to enable enhanced mode); and the process binding core strategy is dynamically modified to migrate memory-intensive threads to a near-memory NUMA node.

[0128] In some embodiments, when an instruction mix degree variance sudden increase (IMF_σ>0.25) event is detected, a control flow graph real-time analysis is triggered to identify a hot loop body; and a JIT compiler is called to generate SIMD optimized code (using the VPMASKMOV instruction).

[0129] In some embodiments, when a policy switching event is completed within 10ms, the Uncore frequency is adjusted by the WRMSR instruction; and the C-state policy is updated to limit the deepest sleep state to C3.

[0130] Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software and the necessary general hardware platform, of course, it can also be realized by hardware, but in many cases the former is a better embodiment.

[0131] As shown in Figure 3 The embodiments of the present application also provide a processor performance optimization device, which can include:

[0132] The acquisition module 301 is configured to acquire real-time running data of a target processor, and the real-time running data includes hardware perception information, software perception information, and load information.

[0133] The processing module 302 is configured to perform multi-dimensional feature extraction on the running data to obtain target load features, and the target load features include cache miss rate and / or branch prediction error rate.

[0134] The processing module 302 is further configured to determine an optimization strategy corresponding to the target load features according to the target load features and a target performance optimization strategy model, and the target performance optimization strategy model is obtained by model training in advance.

[0135] The processing module 302 is further configured to perform performance optimization on the target processor by using the optimization strategy, so as to reduce the cache miss rate and / or the branch prediction error rate.

[0136] In some embodiments, the obtaining module 301 is further configured to obtain the performance evaluation parameter of the target processor in real time, and the performance evaluation parameter at least includes a power consumption parameter, an operation speed parameter and a delay parameter.

[0137] The processing module 302 is further configured to determine the performance evaluation score of the target processor according to the performance evaluation parameter.

[0138] The processing module 302 is further configured to determine that the optimization strategy is an effective strategy if the performance evaluation score is higher than a preset score, and continuously perform performance optimization on the target processor by using the optimization strategy.

[0139] In some embodiments, the obtaining module 301 is further configured to obtain the running sample data of the sample processor.

[0140] The processing module 302 is further configured to train the preset model by using the running sample data, so as to obtain the target performance optimization strategy model.

[0141] In some embodiments, the processing module 302 is specifically configured to perform feature extraction on the running sample data, so as to obtain the target load sample feature.

[0142] The processing module 302 is specifically configured to perform performance optimization on the sample processor by using a plurality of preset optimization strategies respectively, and record the sample performance evaluation value of the sample processor corresponding to each optimization strategy.

[0143] The processing module 302 is specifically configured to determine the optimization strategy with the highest sample performance evaluation value as the sample optimization strategy.

[0144] The processing module 302 is specifically configured to train the preset model by using the target load sample feature and the sample optimization strategy, so as to obtain the target performance optimization strategy model.

[0145] In some embodiments, the processing module 302 is specifically configured to determine the optimization strategy with the highest sample performance evaluation value and the power consumption index not exceeding a preset thermodynamic constraint as the sample optimization strategy.

[0146] In some embodiments, the processing module 302 is specifically configured to perform performance optimization on the sample processor by using a plurality of preset optimization strategies respectively, adjust the data of each optimization strategy by using a nonlinear optimizer, and record the sample performance evaluation value of the sample processor corresponding to each optimization strategy.

[0147] In some embodiments, the processing module 302 is specifically configured to perform feature extraction on the running data by using a time sequence convolution network, so as to obtain time sequence features.

[0148] The processing module 302 is specifically configured to convert the timing features into a graph structure to obtain a program control flow graph;

[0149] Processing module 302 is specifically used to extract features from the program control flow graph through a graph attention network to obtain graph features;

[0150] The processing module 302 is specifically used to fuse the time series features and the graph features through the cross attention mechanism to obtain the target load features.

[0151] In the embodiments of the present application, the description of the features in the embodiments corresponding to the processor performance optimization device can refer to the relevant description of the embodiments corresponding to the processor performance optimization method, and will not be repeated here.

[0152] like Figure 4 As shown, an embodiment of the present application further provides an electronic device, including a memory 401 and a processor 402, wherein the memory 401 stores a computer program, and the processor 402 is configured to run the computer program to execute the steps in any of the above-mentioned processor performance optimization method embodiments.

[0153] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above-mentioned processor performance optimization method embodiments when running.

[0154] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0155] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of any of the above-mentioned processor performance optimization method embodiments are implemented.

[0156] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned processor performance optimization method embodiments are implemented.

[0157] Those skilled in the art will further realize that the mere concepts, teachings, and embodiments described herein are merely meant to provide an enabling description of the applications and are not intended to limit the scope of the applications. Therefore, embodiments or examples described herein are not meant to be limiting, but merely to aid in the understanding of the overall more complete disclosure of the applications. Accordingly, those skilled in the art will recognize that modifications and variations of the more complete description herein can be resorted to without departing from the spirit and scope of the applications. Therefore, it is intended that the applications encompass all such modifications and variations as fall within the scope of the applications. All articles, patents, and other publications that have been cited herein are incorporated herein by reference for the teachings relevant to the sentence and / or paragraph in which the article, patent, and / or publication is mentioned.

[0158] The process monitoring of the storage system provided by the application is described in detail above. The principles and implementation manners of the application are described by applying specific examples herein. The above description of the examples is only used to help understand the method of the application and its core idea. It should be noted that, for those skilled in the art, some improvements and modifications can be made to the application without departing from the principles of the application. These improvements and modifications also fall within the protection scope of the claims of the application.

Claims

1. A method for optimizing processor performance, characterized in that: The method comprises: Acquiring real-time operating data of a target processor, the real-time operating data including hardware perception information, software perception information, and load information, the hardware perception information including at least an event set consisting of preset events, and a preset sampling frequency for collecting the preset events being dynamically adjusted based on a change in the number of instructions per cycle and thermodynamic constraints; Performing multi-dimensional feature extraction on the operating data to obtain target load features, the target load features including: number of cycle instructions, cache miss rate, branch prediction error rate, and instruction mix variance; Determining an optimization strategy corresponding to the target load characteristics based on the target load characteristics and the target performance optimization strategy model; the target performance optimization strategy model is obtained in advance through model training, and the optimization strategy includes at least one of adjusting processor frequency, rebinding non-uniform memory access nodes, injecting pre-read instructions, and adjusting pre-fetch distance; Optimizing the performance of the target processor by using the optimization strategy so as to reduce a cache miss rate and / or a branch prediction error rate; Acquiring performance evaluation parameters of the target processor in real time, wherein the performance evaluation parameters include at least: power consumption parameters, operation speed parameters, and delay parameters; Determining a performance evaluation score of the target processor according to the performance evaluation parameters, wherein the performance evaluation score is determined by weighted summation based on a change in operation speed, a change in power consumption, a change in instruction delay duration, and corresponding weight values; If the performance evaluation score is higher than a preset score, the optimization strategy is determined to be a valid strategy, and the performance of the target processor is continuously optimized using the optimization strategy.

2. The method according to claim 1, characterized in that Before determining the optimization strategy of the target processor according to the target load characteristics and the target performance optimization strategy model, the method further includes: Obtaining running sample data of the sample processor; The preset model is trained using the running sample data to obtain the target performance optimization strategy model.

3. The method according to claim 2, characterized in that The step of training a preset model using the running sample data to obtain the target performance optimization strategy model includes: Performing feature extraction on the running sample data to obtain target load sample features; Optimizing the performance of the sample processors using a plurality of preset optimization strategies, and recording the sample performance evaluation value of the sample processors corresponding to each optimization strategy; Determine the optimization strategy with the highest sample performance evaluation value as the sample optimization strategy; The preset model is trained using the target load sample characteristics and the sample optimization strategy to obtain the target performance optimization strategy model.

4. The method according to claim 3, characterized in that Determining the optimization strategy with the highest sample performance evaluation value as the sample optimization strategy includes: The optimization strategy with the highest sample performance evaluation value and a power consumption index not exceeding a preset thermodynamic constraint is determined as the sample optimization strategy.

5. The method according to claim 3, characterized in that The performing performance optimization on the sample processors respectively by using a plurality of preset optimization strategies, and recording the sample performance evaluation value of the sample processor corresponding to each optimization strategy, includes: The performance of the sample processor is optimized respectively by using a plurality of preset optimization strategies, the data of each optimization strategy is adjusted by a nonlinear optimizer, and the sample performance evaluation value of the sample processor corresponding to each optimization strategy is recorded.

6. The method according to claim 1, characterized in that The performing multi-dimensional feature extraction on the operating data to obtain target load features includes: Extracting features from the operating data using a temporal convolutional network to obtain temporal features; Converting the timing features into a graph structure to obtain a program control flow graph; Extract features from the program control flow graph through a graph attention network to obtain graph features; The time series features and the graph features are fused through a cross-attention mechanism to obtain the target load features.

7. A processor performance optimization device, characterized in that: The device comprises: an acquisition module, configured to acquire real-time operating data of a target processor, the real-time operating data including hardware perception information, software perception information, and load information, the hardware perception information including at least an event set consisting of preset events, and a preset sampling frequency for collecting the preset events being dynamically adjusted based on a change in the number of cycle instructions and thermodynamic constraints; a processing module, configured to perform multi-dimensional feature extraction on the operating data to obtain target load features, wherein the target load features include: number of cycle instructions, cache miss rate, branch prediction error rate, and instruction mix variance; The processing module is further configured to determine an optimization strategy corresponding to the target load characteristics based on the target load characteristics and a target performance optimization strategy model; the target performance optimization strategy model is obtained in advance through model training, and the optimization strategy includes at least one of adjusting processor frequency, rebinding non-uniform memory access nodes, injecting pre-read instructions, and adjusting pre-fetch distance; The processing module is further configured to optimize the performance of the target processor using the optimization strategy so as to reduce a cache miss rate and / or a branch prediction error rate; The acquisition module is further configured to acquire performance evaluation parameters of the target processor in real time, wherein the performance evaluation parameters include at least power consumption parameters, operation speed parameters, and delay parameters; The processing module is further configured to determine a performance evaluation score of the target processor based on the performance evaluation parameters, wherein the performance evaluation score is determined by weighted summation of a change in operation speed, a change in power consumption, a change in instruction delay duration, and corresponding weight values ​​thereof; The processing module is further configured to determine that the optimization strategy is a valid strategy if the performance evaluation score is higher than a preset score, and to continue to optimize the performance of the target processor using the optimization strategy.

8. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the processor performance optimization method according to any one of claims 1 to 6 when executing the computer program.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the processor performance optimization method according to any one of claims 1 to 6 are implemented.

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