Multi-band finely adjustable wide-tuning range digitally controlled oscillators, phase-locked loops and chips

Abstract

This invention relates to a multi-band finely tunable, wide-tuning-range numerically controlled oscillator, phase-locked loop, and chip. The numerically controlled oscillator includes n differential operational amplifier delay units, 2n array tuning circuits, and one digital-to-analog converter; the n differential operational amplifier delay units are cascaded, and the output V at the end of the cascade is... out +、V out - and the input V at the cascade start end in +、V in The positive and negative terminals of the circuit are reversed to form a ring structure; any one differential operational amplifier delay unit is connected to two array tuning circuits; a digital-to-analog converter is used to provide control voltage to the array tuning circuits. This invention significantly reduces oscillator phase noise through the combination of a tail current source and capacitor filtering, while simultaneously enabling a wide tuning range by adjusting the operating state of the array tuning circuits. The digital-to-analog converter achieves 256-bit fine-level voltage control, allowing for significantly precise operation of the output frequency, thus meeting the higher resolution requirements of a fully digital phase-locked loop.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a multi-band finely adjustable digitally controlled oscillator, phase-locked loop, and chip. Background Technology

[0002] In recent years, with the rapid development of wireless communication and the increasing demand for low-cost, low-power, and high-performance radio frequency transceivers, all-digital phase-locked loops (ADPLLs) have become increasingly important. Digital radio frequency (RF) uses digital circuits to implement RF circuit functions. Compared to traditional RF circuits, digital circuits offer more precise transistor size control and higher circuit integration, thus effectively reducing chip area and cost. Furthermore, digital circuits offer greater configurability and process portability. Based on these advantages, ADPLLs, as a crucial component of digital RF transceivers, have become a research hotspot in recent years.

[0003] Digitally controlled oscillators (DCOs) have wide applications in mobile communications, wireless smart terminals, and other fields. Currently, oscillators mainly use analog oscillators, which suffer from high power consumption, high cost, low portability, and susceptibility to digital signals in the circuit. In recent years, with the continuous reduction of power supply voltage, the digital implementation of oscillators has gradually become a trend. A digitally controlled oscillator consists of a capacitor array and a control circuit, and frequency tuning is achieved by changing the tuning capacitor through a control word. Currently, oscillators improve performance through inductor or mutual inductance tuning, but these oscillators, relying solely on inductor or mutual inductance adjustment, fail to meet the resolution and tuning range requirements of modern communications. Therefore, a digitally controlled oscillator with high bandwidth, high resolution, and low phase noise is indispensable. Summary of the Invention

[0004] Therefore, it is necessary to address the problem that existing oscillators, which rely on a single inductor or mutual inductance adjustment, fail to meet the resolution and tuning range requirements of modern communication. A multi-band, finely adjustable, wide-tuning-range digitally controlled oscillator, phase-locked loop, and chip are required.

[0005] In a first aspect, the present invention proposes a multi-band finely adjustable wide-tuning numerically controlled oscillator, which includes: n differential operational amplifier delay units, 2n array tuning circuits, and 1 digital-to-analog converter; n≥2.

[0006] The differential operational amplifier delay unit includes: two resistors R D1 ~R D2 Two NMOS transistors, M1 and M2; R D1R D2 One end of each is connected to the power supply terminal V. DD ;R D1 The other end is connected to the drain of M1 and serves as the positive output terminal V. out +; The gate of M1 serves as the positive input terminal V in +;R D2 The other end is connected to the drain of M2 and serves as the negative output terminal V. out -; The gate of M2 is connected as the negative input terminal V. in -; The source-level connection current source I of M1 and M2 SS .

[0007] n differential operational amplifier delay units are cascaded together, and the output V at the end of the cascade is... out +、V out - and the input V at the beginning of the cascade in +、V in - The positive and negative ends are reversed to form a ring structure.

[0008] Any one differential operational amplifier delay unit is connected to two array tuning circuits, with one array tuning circuit connected to the drain of M1 of the differential operational amplifier delay unit and the other array tuning circuit connected to the drain of M2 of the differential operational amplifier delay unit.

[0009] The digital-to-analog converter is used to provide control voltage V to the array tuning circuit. ctrl The array tuning circuit is used to coarsely adjust the frequency based on the external control signal group sel, and based on V... ctrl To fine-tune the frequency.

[0010] In a second aspect, the present invention proposes an all-digital phase-locked loop, which includes the multi-band finely tunable, wide-tuning-range digitally controlled oscillator described in the first aspect.

[0011] Thirdly, the present invention also proposes a chip with a wide tuning range and finely adjustable multi-band frequency band, which is packaged from the numerically controlled oscillator with a wide tuning range and finely adjustable multi-band frequency band described in the first aspect. The chip with a wide tuning range and finely adjustable multi-band frequency band includes the following pins: one power supply pin, one ground pin, one current pin, one reference pin, K first signal pins, and Q second signal pins.

[0012] The power supply pin is used to connect to V. DD The ground pin is used to connect to V. SS The current pin is used to connect I. SS The reference pin is used to connect V. ref The K first signal pins are connected to the array tuning circuit, which is used to receive K signals from sel1 to sel2 respectively. KThe Q second signal pins are connected to the digital-to-analog converter, which are used to receive Q DCW1 to DCW1 signals respectively. Q .

[0013] The beneficial effects of this invention are as follows:

[0014] This invention significantly reduces oscillator phase noise by combining a tail current source and capacitor filtering. At the same time, it enables the circuit to have a wide tuning range by adjusting the operating state of the array tuning circuit. It achieves 256-bit fine-level voltage control through a digital-to-analog converter, and can more effectively control the capacitance of the varactor tube. It can significantly and accurately operate the output frequency, thereby meeting the higher resolution requirements of the all-digital phase-locked loop. Furthermore, it can operate in all-digital phase-locked loop circuits, significantly improving the application range of the all-digital phase-locked loop frequency. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is an overall structural diagram of the CNC oscillator with a wide tuning range and multiple frequency bands that can be finely adjusted in this embodiment;

[0017] Figure 2 This is a structural diagram of the differential operational amplifier delay unit in this embodiment;

[0018] Figure 3 This is a structural diagram of the digital-to-analog converter in this embodiment;

[0019] Figure 4 This is a structural diagram of the array tuning circuit in this embodiment;

[0020] Figure 5 This is a simulation diagram of the phase noise of the numerically controlled oscillator in this embodiment and the comparative example;

[0021] Figure 6 This is a simulation diagram of the output frequency tuning range of the numerically controlled oscillator and the comparative example in this embodiment. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0024] This invention provides a multi-band, finely tunable, wide-tuning-range digitally controlled oscillator, mainly comprising three parts: a differential operational amplifier delay unit, an array tuning circuit, and a digital-to-analog converter. The differential operational amplifier delay unit, through positive and negative feedback loops, introduces phase delay and resistance amplification gain, enabling the oscillator to generate continuous oscillation output and lower phase noise, forming the main body of the oscillator. The array tuning circuit controls different switch schedules according to an external control signal group sel, achieving significant changes in its capacitance to expand the tuning range. The digital-to-analog converter precisely adjusts its output voltage V using the input digital code. ctrl This allows for smaller capacitance changes in the array tuning circuit, thereby achieving higher resolution.

[0025] Please refer to Figure 1 In this embodiment, the multi-band finely tunable, wide-tuning-range digitally controlled oscillator includes four differential operational amplifier delay units, eight array tuning circuits, and a digital-to-analog converter. Each differential operational amplifier delay unit is connected to two array tuning circuits. The structure of the three parts will be described in detail below:

[0026] I. Differential operational amplifier delay unit.

[0027] In this embodiment, four differential operational amplifier delay units are cascaded. The positive output V of the first three differential operational amplifier delay units... out + and positive input V in +, Negative output V out - and negative input V in - Connection. The last stage is connected in reverse to the delay unit of the first stage differential operational amplifier, that is, the positive output V out + and negative input V in - Negative output V out - and positive input V inThe + connection achieves the phase reversal requirement, enabling continuous oscillation. Furthermore, the four-stage cascade of differential operational amplifiers helps generate multiple well-defined output phases. Specifically, the four-stage loop can produce eight phases with a phase separation of 45°, improving the overall speed and frequency tuning range.

[0028] Furthermore, the differential operational amplifier delay unit comprises a pair of matched MMOS transistors forming the differential input, followed by a cross-coupled resistive load circuit connected between the power supply and the NMOS differential input pair to establish the necessary feedback. Each operational amplifier delay unit contributes a specific phase shift, determined by the device's transconductance, load capacitance, and bias current. Theoretically, to satisfy the closed-loop startup condition, each stage of the delay unit should provide at least 60° of phase shift. Once the accumulated phase shift reaches 360° (or an integer multiple thereof), the loop satisfies the Barkhausen criterion, enabling oscillation and thus outputting a stable oscillation frequency waveform. A differential ring oscillator with tail current can be viewed as two coupled single-ended ring oscillators synchronized by mutual source injection from the input transistor pair. In this configuration, one NMOS transistor acts as a source follower, while the other operates in common-gate mode, allowing one ring oscillator to inject current into the other. To effectively synchronize these two single-ended loops while maintaining different oscillation modes, the injection must be sufficiently strong, requiring the use of a high-impedance tail device; therefore, a current mirror is also incorporated.

[0029] Specifically, such as Figure 2 As shown, taking the first differential operational amplifier delay unit as an example, it includes: two resistors R D1 ~R D2 Two NMOS transistors M1-M2, and a filter capacitor C. tail The source of M1 is connected to the current source I. SS The output terminal and the positive input V of the gate receiving the differential signal. in +, Drain passes through R D1 Connect to power supply terminal V DD And M1 and R D1 The positive terminal of the differential signal output by the node between them outputs V. out +. The source level of M2 is connected to the source level of M1, and they are both connected to I. SS The output terminal of M2. The gate of M2 is connected to the negative input V of the differential signal. in - Drain through R D2 Connect to power supply terminal V DD And M2 and R D2 The negative terminal of the differential signal output between the nodes outputs V. out -. C tailOne end is connected to the source of M2 and the source of M1, and the other end is grounded. The second, third, and fourth differential operational amplifier delay units have the same structure as the first differential operational amplifier delay unit. The two NMOS transistors M3-M4 in the second differential operational amplifier delay unit, the two NMOS transistors M5-M6 in the third differential operational amplifier delay unit, and the two NMOS transistors M7-M8 in the fourth differential operational amplifier delay unit have the same connection structure as M1-M2. It should be noted that the positive and negative terminals of the fourth differential operational amplifier delay unit are reversed compared to the first differential operational amplifier delay unit. These MOS transistors form multiple differential pairs with the same structure. Each differential pair is connected to the current source I through its source. ss The gate receives the differential input signal, and the drain is connected to a resistor to output a differential output signal. Together, they form a digital ring oscillator circuit, whose oscillation frequency is shown below:

[0030]

[0031] In the formula, g m C represents the transconductance of the NMOS transistor in the delay unit of the differential operational amplifier. eq R is the equivalent capacitance of the delay unit circuit in a differential operational amplifier, including parasitic capacitance. D R in the delay unit of the differential operational amplifier D1 R D1 The resistance.

[0032] In addition, the current mirror connected to each differential operational amplifier delay unit is used to provide I SS The current mirror includes two NMOS transistors, M9 and M1. 10 M9, M 10 The gates are connected and a bias current I is applied. bias The source of M9 is grounded, and its drain is connected to the source of M1. 10 Source grounding, drain connection I bias This forms a current mirror, providing It for the delay unit of the differential operational amplifier. SS This allows for the adjustment of circuit gain and delay.

[0033] The gain formula is as follows:

[0034]

[0035] In the formula, I tail This is the tail current value. V ov The overdrive voltage is the gate-source voltage of the MOSFET minus the threshold voltage.

[0036] The delay formula is as follows:

[0037]

[0038] II. Digital-to-analog converter.

[0039] In this embodiment, the digital-to-analog converter controls the conduction or cutoff of the MOSFETs by inputting an 8-bit binary code connected to the gates of the NMOS and PMOS transistors. Additionally, a reference voltage is connected to the drain of the PMOS transistor to provide a pull-up voltage when it is on. The reference voltage V is adjusted according to the proportion of the input binary code to the total binary code. ref The proportional adjustment uses an NMOS transistor as a pull-down device to selectively connect the node to ground voltage V based on the input digital code. SS PMOS transistors are used as V ref The pull-up device is activated, causing the output V of the digital-to-analog converter to work. ctrl The voltage is regulated by connecting to an array tuning circuit. Each digital bit controls a switch that determines whether the corresponding current path contributes to the final output. A network of resistors ensures that each bit receives a current proportional to its binary weight. This circuit, based on the principle of current division, ensures accurate and monotonic output voltage scaling for fine-tuning of the frequency. Figure 3 As shown, the digital-to-analog converter includes one NMOS transistor MN0, one resistor R0, Q resistors R, and Q+1 control unit. The control unit is used to receive control signals DCW1 to DCW1. Q To control V ctrl The qth control unit includes: one NMOS transistor MN q 1 PMOS transistor MP q 1 resistor R q q∈[1,Q]. Specifically, the digital-to-analog converter in this embodiment includes: one NMOS transistor MN0, one resistor R0, seven resistors R, and eight control units. The source of MN0 is connected to ground voltage V. SS Gate connection V DD Seven resistors R are connected in series, one end of which is connected to the drain of MN0 through R0, and the other end outputs V. ctrl Simultaneously, each node at both ends of R is connected to a control unit. These eight control units receive control signals DCW1 to DCW8 to control V. ctrl Taking the first control unit as an example, it includes one NMOS transistor MN1, one PMOS transistor MP1, and one resistor R1. The eight control units have the same structure, thus there are a total of eight NMOS transistors MN1-MN8, eight PMOS transistors MP1-MP8, and eight resistors R1-R8 (the resistance values ​​of R1-R8 and R0 are all twice that of R). The source terminals of MN1-MN8 are connected to V... SSThe gates of MN1 to MN8 are connected to DCW1 to DCW8 respectively (i.e., MN1 is connected to DCW1, MN2 is connected to DCW2, and so on). DCW1 to DCW8 control the conduction and cutoff of MN1 to MN8. The drains of MN1 to MN8 are connected to one end of R1 to R8 respectively (i.e., MN1 is connected to R1, MN2 is connected to R2, and so on). Simultaneously, the drains of MN1 to MN8 are also connected to the sources of MP1 to MP8 respectively (i.e., MN1 is connected to MP1, MN2 is connected to MP2, and so on). The drains of MP1 to MP8 are connected to the reference voltage V. ref The gate and the corresponding DCW1 to DCW8 are connected respectively. Overall, these MOSFETs are connected to the power supply, reference voltage, resistor, and control signal through their source, gate, and drain. The on / off state of the MOSFETs is controlled by DCW1 to DCW8, thereby affecting the output V of the digital-to-analog converter. ctrl This allows for precise adjustment of the control voltage of the varactor transistors in the array tuning circuit. ctrl The control can be based on the following formula:

[0040]

[0041] In the formula, b q This represents the q-th control signal DCW. q The state is either 0 or 1.

[0042] III. Array Tuning Circuit.

[0043] Each differential operational amplifier delay unit is connected to two array tuning circuits, meaning there are a total of eight array tuning circuits in this embodiment. The array tuning circuits are connected between the resistor and the drain of the NMOS transistor in the corresponding differential operational amplifier delay unit; that is, one of the array tuning circuits is connected to R... D1 Between M1, another array tuning circuit is connected to R. D2 Between M1 and M2, both sides have the same symmetrical structure. For example... Figure 4 As shown, taking one of the array tuning circuits as an example, it includes: a K-level capacitor array, and one capacitor C. var0 The input connection of the K-level capacitor array is V. ctrl The output VZ of the K-level capacitor array out Connect C var0 C var0 Connected to the delay unit of the differential operational amplifier. The k-th stage capacitor array includes 2 k-1 A variable capacitance layer, which receives one external control signal sel. k k∈[1,K]. sel1~sel KThe capacitor array is configured as a 4-stage array. Each sel consists of 4-bit digital control signals sel1 to sel4. One sel... k This system is used to control the connection or disconnection of a capacitor array, thereby adjusting the total capacitance. The four-stage capacitor array consists of 1, 2, 4, and 8 varactor transistor layers sequentially. Each varactor transistor layer has the same structure, including one NMOS transistor MN9 and two varactor transistors C. var1 ~C var2 V ctrl Through C var1 Connect the drain of MN9, through C var2 The source of MN9 is connected to the capacitor used for fine-tuning the array tuning circuit. The source of MN9 is connected to the output terminal VZ. out The gate of MN9 is connected to the external control signal group sel. k and subject to sel k Control, participates in the 4-bit coarse adjustment control function, enabling C var1 C var2 Capacitors connected in parallel or disconnected to coarsely adjust the array tuning circuit. Wherein, C var1 C var2 It can be constructed using an NMOS transistor. Shorting the source and drain of the NMOS transistor and controlling it with an external control voltage allows it to act as a buffer capacitor in the circuit, resulting in a smoother frequency output. Furthermore, C... var1 C var2 The capacitance varies with V ctrl It exhibits a non-linear change. Specifically, when V ctrl As the voltage increases, the capacitance increases from approximately 0.6 fF to 1.4 fF. Its voltage-dependent characteristic is expressed by the following equation:

[0044]

[0045] In the formula, C ox This is the capacitance of the oxide layer. V FB Φ is the flat-band voltage. Φ is the Fermi potential, which is a doping and structure-related parameter. From this, we can see that C var1 C var2 The average voltage on it is approximately equal to VZ out Subtract V ctrl The common-mode level at V. Therefore, when V ctrl When the voltage changes, the pressure drop (VZ) across the variable capacitance tube out -V ctrl This corresponding change, in turn, alters the overall capacitance. This modulation behavior facilitates fine frequency tuning. When used in conjunction with a coarse-tuning capacitor array, an even wider tuning range can be achieved.

[0046] In another embodiment, a fully digital phase-locked loop is also proposed, which includes a digitally controlled oscillator with a wide tuning range and multi-band fine-tuning capability as described in the above embodiments.

[0047] In another embodiment, a chip with a wide tuning range and multiple frequency bands is also proposed, which is packaged from the numerically controlled oscillator with a wide tuning range and multiple frequency bands as described above. The chip with a wide tuning range and multiple frequency bands as described above has the following pins: one power supply pin, one ground pin, one current pin, one reference pin, K first signal pins, and Q second signal pins.

[0048] The power supply pin is used to connect to V. DD The ground pin is used to connect to V. SS The current pin is used to connect I. SS The reference pin is used to connect V. ref The K first signal pins are connected to the array tuning circuit, which is used to receive K signals from sel1 to sel2 respectively. K The Q second signal pins are connected to the digital-to-analog converter, which are used to receive Q DCW1 to DCW1 signals respectively. Q .

[0049] To verify the advantages of this invention, a ring oscillator presented at the 2024 ICICM conference (Z. Ding, J. Zhang, A. Guo and L. Yin, “Design of a Novel Low-Power Differential Ring Voltage Controlled Oscillator,” 2024 9th International Conference on Integrated Circuits and Microsystems (ICICM), Wuhan, China, 2024, pp. 473-478) was selected as a comparative example for simulation. The results are as follows. Figure 5 , Figure 6 As shown. By Figure 5 As can be seen, the horizontal X-axis represents the offset frequency, using a logarithmic scale, ranging from 1 kHz to 10 MHz, used to measure the frequency offset relative to the carrier frequency. The vertical Y-axis represents the phase noise, ranging from 0 dBc / Hz to -140 dBc / Hz, used to quantify the noise characteristics of the signal phase; the lower the value, the lower the phase noise and the better the signal quality. Regarding phase noise, at 1 MHz, the oscillator of this invention has a phase noise of -103.7 dBc / Hz, while the comparative example has -93.1 dBc / Hz. The phase noise of this invention is reduced by 10.6 dBc / Hz compared to the comparative example.

[0050] Figure 6 In the diagram, the blue curve represents the results of this invention, and the red curve represents the results of comparative examples. Figure 6 As can be seen, the horizontal X-axis represents the DCO input code, ranging from 0 to 255, which is the variable controlling the DCO frequency. The vertical Y-axis represents the DCO frequency, ranging from 0.5 GHz to 3.0 GHz, used to display the oscillation frequency of the DCO output under different input codes. Each blue curve corresponds to a different 4-bit binary digital control code (from 4'b 0000 to 4'b 1111). As the DCO input code increases, the DCO frequency represented by each blue curve shows an upward or downward trend, indicating that the input code has a regulating effect on the DCO frequency. Two important DCO gain coefficients K are marked on the blue curves. DCO = 1.56MHz / LSB, indicating that under the corresponding conditions, the DCO frequency changes by 1.56MHz for each least significant bit changed. K DCO =0.91MHz / LSB, meaning that for every LSB changed, the DCO frequency changes by 0.91MHz. Figure 6 This invention demonstrates the tuning range and resolution of a ring numerically controlled oscillator structure with fine-tunable multi-band low phase noise and a wide tuning range. The tuning range of this invention is 0.6-2.7 GHz, compared to 0.9-2.6 GHz for the comparative example. Clearly, this invention has a wider tuning range and more levels of controlled tuning curves, enabling better control of the output frequency and higher resolution.

[0051] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0052] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A multi-band fine-tunable wide tuning range digitally controlled oscillator, characterized by, It includes: n differential operational amplifier delay unit, 2n array tuning circuit, 1 digital analog converter;N≥2; The differential operational amplifier delay unit comprises two resistors R D1 ~R D2 , two NMOS transistors M1~M2; one end of R D1 , R D2 is connected to the power supply end V DD +; the other end of R D1 is connected to the drain of M1 and serves as the output positive end V out +; the gate of M1 serves as the input positive end V in +; the other end of R D2 is connected to the drain of M2 and serves as the output negative end V out -; the gate of M2 serves as the input negative end V in -; the source of M1 and M2 is connected to the current source I SS ; n differential operational amplifier delay unit cascades, and the output V out +, V out - and the input V in +, V in - of the head end of the cascade are connected reversely to form a ring structure; Any one differential operational amplifier delay unit is connected with two array tuning circuits, and one of the array tuning circuits is connected to the drain of M1 of the differential operational amplifier delay unit, and the other array tuning circuit is connected to the drain of M2 of the differential operational amplifier delay unit; The digital-to-analog converter is used to provide control voltage V to the array tuning circuit. ctrl The array tuning circuit is used to coarsely adjust the frequency based on the external control signal group sel, and based on V... ctrl To fine-tune the frequency; wherein, the array tuning circuit includes: a K-level capacitor array, and one capacitor C. var0 Input connection V of the K-level capacitor array ctrl The output VZ of the K-level capacitor array out Connect C var0 The k-th stage capacitor array includes 2 k-1 A variable capacitance layer, which receives one external control signal sel. k ;k∈[1,K];sel1~sel K Composed of sel.

2. The multi-band fine-tunable wide tuning range digitally controlled oscillator of claim 1, wherein, The varactor tube layer in the kth-stage capacitor array comprises 1 NMOS tube MN9, 2 varactor tubes C var1 ~C var2 ; V ctrl through C var1 the drain of MN9, through C var2 the source of MN9, for fine tuning the capacitance of the array tuning circuit; the source of MN9 is connected to the output VZ out ; the gate of MN9 is connected to the external control signal group sel k , for connecting C var1 , C var2 in parallel or disconnecting them for coarse tuning the capacitance of the array tuning circuit.

3. The multi-band fine-tunable wide tuning range digitally controlled oscillator of claim 1, wherein, I SS includes: 2 NMOS tubes M9~M 10 ; M9, M 10 The gate of M9 is connected with bias current I bias ; the source of M9 is grounded, and the drain is connected with the source of M1; the source of M 10 is grounded, and the drain is connected with I bias .

4. The multi-band fine-tunable wide tuning range digitally controlled oscillator of claim 1, wherein, The differential operational amplifier delay unit further comprises a filtering capacitor C tail ; one end of C tail is connected to the source of M2 and the source of M1, and the other end is grounded.

5. The multi-band fine-tunable wide tuning range digitally controlled oscillator of claim 1, wherein, The digital analog converter comprises: one NMOS tube MN0, one resistor R0, Q resistors R, Q+1 control units. Wherein, Q R series, one end through R0 connects MN0 drain, the other end outputs V ctrl ; MN0 source stage connects ground voltage V SS , gate connects V DD ; Each R both ends node connects 1 control unit; Control unit is used for receiving control signal DCW1~DCW Q To control V ctrl .

6. The multi-band fine-tunable wide tuning range digitally controlled oscillator of claim 5, wherein, The qth control unit comprises: 1 NMOS transistor MN q , 1 PMOS transistor MP q , 1 resistor R q ; q ∈ [1, Q] Among them, MN q MP q Gate connection control signal DCW q MN q The drain and MP q Source-level connections; MN q Source-level connection V SS ;MP q The drain is connected to the reference voltage V. ref ;R q One end is connected to MN q The drain of one end is connected to the node of R, and the other end is connected to R.

7. The multi-band fine-tunable wide tuning range digitally controlled oscillator of claim 1, wherein, The differential operational amplifier delay unit is provided with four.

8. An all-digital phase-locked loop, characterized by It comprises the multi-band fine-tunable wide tuning range digital controlled oscillator of any one of claims 1 to 7.

9. A multi-band fine-tuneable wide tuning range chip, characterized in that, It is packaged by the multi-band fine-tunable wide tuning range digital controlled oscillator of any one of claims 1 to 7;The pins of the multi-band fine-tunable wide tuning range chip include: 1 power supply end pin for connecting V DD ; 1 ground pin for connecting V SS ; 1 current pin for connecting I SS ; 1 reference pin for connecting V ref ; K first signal pins, which are connected with the array tuning circuit; which are respectively used for receiving K sel1 ~ selK signals K ; Q second signal pins, which are connected with the digital-analog converter; which are respectively used for receiving Q DCW1~DCW Q .

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