Large-scale phased array multi-channel partition beam control method and device based on FPGA and storage medium

Abstract

The invention discloses a large-scale phased array multi-channel partition beam control method and device based on an FPGA and a storage medium. The method comprises the steps that a control instruction of an antenna control unit is acquired; analyzing the control instruction which is verified to be correct, judging an instruction type according to an analysis result, when the instruction type is a beam switching instruction, determining a beam control parameter in the instruction, and calculating a base code of the phased-array antenna according to the beam control parameter; the array elements of the phased-array antenna are divided into a plurality of areas, according to the base codes and the position coordinates of the array elements, the wave control codes of the array elements are calculated in parallel by adopting a multi-channel partitioning method, and the wave control codes are normalized and then written into a beam forming chip in parallel; and after the operation is completed, a corresponding response instruction is sent to the antenna control unit. The method has the advantages of being high in beam switching speed, small in resource consumption and good in universality, an array can form a sparse array in the mode of sending a control instruction, and therefore side lobes are restrained, and power consumption is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of large-scale two-dimensional phased array antenna control, and in particular to a large-scale phased array multi-channel partitioned beam control method, device and storage medium based on FPGA. Background Art

[0002] Phased array antennas are an advanced antenna technology that dynamically adjusts beam pointing by controlling the phase differences between individual radiating elements in the array. Compared to traditional mechanically scanned antennas, phased array antennas offer fast beam switching, high pointing accuracy, and strong anti-interference capabilities. They are widely used in radar systems, satellite communications, 5G / 6G mobile communications, and electronic countermeasures. Beam steering technology is a crucial component of phased array antennas, directly impacting beam switching time and pointing accuracy.

[0003] Currently, common beam steering methods are designed using DSP or FPGA architectures. DSP architectures offer the advantages of low cost and simple implementation, but the beam steering code is calculated serially, resulting in long beam switching times and inadequate for large-scale phased array antennas. FPGA architectures can calculate the beam steering code for each array element in parallel, enabling faster beam switching and suitable for large-scale phased array antennas. However, current FPGA architectures still use a single-channel serial method to calculate the beam steering code for each array element, which is difficult to meet real-time requirements. Using a multi-channel, fully parallel method to calculate the beam steering code for each array element significantly improves beam steering code calculation speed, but the hardware and software resources consumed also increase exponentially. Furthermore, traditional two-dimensional phased array systems are prone to false alarms or interference in high sidelobe conditions, compromising target detection. While amplitude weighting is effective for sidelobe suppression, it is complex and results in significant gain loss.

[0004] Therefore, it is necessary to provide a large-scale phased array multi-channel partitioned beam control method, device and storage medium based on FPGA, which can divide the phased array antenna elements into multiple areas according to the array element position coordinates, quickly process the beam control code of each element through parallel computing, and use sidelobe suppression instructions to make the phased array antenna close the channels of some elements, thereby improving the control accuracy of the phased array system, optimizing the response speed, and reducing the sidelobe level. It is suitable for application scenarios of large-scale phased array antennas requiring high performance and high reliability. Summary of the Invention

[0005] In view of this, the present invention provides a large-scale phased array multi-channel partitioned beam steering method based on FPGA, which is used to solve the technical problems in the prior art such as large FPGA resource consumption, slow beam control code calculation speed and poor versatility.

[0006] In order to achieve the above technical objectives, the present invention adopts the following technical solutions:

[0007] In a first aspect, the present invention provides a large-scale phased array multi-channel partitioned beam steering method based on FPGA, comprising:

[0008] Obtain control instructions from the antenna control unit and verify the control instructions;

[0009] Parse the verified control instructions and determine the instruction type based on the parsing result. If the instruction type is a beam switching instruction, determine the beam control parameters in the instruction and calculate the base code of the phased array antenna based on the beam control parameters.

[0010] The elements of the phased array antenna are divided into multiple regions. Based on the base code and the position coordinates of each element, a multi-channel partitioning method is used to parallelly calculate the beam control code of each element. The beam control code is normalized and then written into the beamforming chip in parallel to achieve rapid phase arrangement.

[0011] After the operation corresponding to the control instruction is completed, the corresponding response instruction is sent to the antenna control unit in a serial transmission manner.

[0012] Furthermore, the beam control parameters in the instruction include at least scanning angle, azimuth angle and frequency word information;

[0013] The formula for calculating the phased array antenna base code based on the beam steering parameters is:

[0014]

[0015]

[0016] in, Phased array antenna Axis direction base code, Phased array antenna Axis direction base code, Phased array antenna Axis element spacing, Phased array antenna Axle spacing, is the scanning angle, is the azimuth, is the frequency, is the speed of light, is the bit width using virtual bit technology.

[0017] Furthermore, the array elements of the phased array antenna are divided into multiple regions. Based on the base code and the position coordinates of each array element, a multi-channel partitioning method is used to parallelly calculate the wave control code of each array element, including:

[0018] According to the physical position relationship between antenna elements and beamforming chips, the antenna array is divided into Each area is controlled by a SPI interface with multiple beamforming chips;

[0019] According to the antenna left-hand, right-hand polarization mode and frequency word information, the corresponding phase compensation code is read from the external FLASH and stored in the FPGA RAM;

[0020] Will Base code in axis direction , Base code in axis direction , phase compensation code for each partition Parallel Input Partition channels;

[0021] Input the coordinates of each partition antenna array element serially Partition channels, each partition is calculated by two multipliers 、 The value of

[0022] Use adders to calculate the original wave control code of each partition antenna array element ;

[0023] Normalize the original wave control code, intercept the valid bits, and obtain the final wave control code ;

[0024] The beam control codes of each partition are framed according to the beamforming chip protocol format and transmitted in parallel. The data is written into the beamforming chip through the SPI interface to complete the rapid phase arrangement.

[0025] Furthermore, the calculation formula of the multi-channel partition wave control code is as follows:

[0026]

[0027] in, Phased array antenna The wave control code of each array element in each partition, , for a phased array antenna with M rows and N columns, For the array element Axis coordinates, For the array element Axis coordinates, Phased array antenna Axis direction base code, Phased array antenna Axis direction base code, is the phase compensation code after phased array antenna calibration.

[0028] Furthermore, the instruction types include:

[0029] Beam switching commands, used for beam pointing control of phased array antennas, including scan angle, azimuth angle, and frequency fields;

[0030] Polarization switching instructions are used to configure the polarization mode of the phased array antenna;

[0031] RF switch command, used to control the RF switch of the beamforming chip;

[0032] The sidelobe suppression command is used to shut down some elements of the phased array antenna to form a sparse array, thereby reducing the sidelobe level and the power consumption of the phased array antenna.

[0033] Temperature query command, used to query the temperature information of the phased array antenna and monitor the antenna temperature in real time;

[0034] The power query command is used to query the power information of the phased array antenna and monitor the antenna power in real time.

[0035] Furthermore, when the instruction type is a sidelobe suppression instruction, performing a sidelobe suppression operation includes:

[0036] The corresponding antenna array elements are turned off by issuing radio frequency switch instructions, so that the phased array antenna forms a sparse array; the sparse array includes a cut-angle array and a sparse array based on a genetic algorithm.

[0037] Furthermore, the control instruction is framed using a preset frame format;

[0038] The preset frame format includes a frame header, a frame length, a frame type, a frame data, and a check bit.

[0039] In a second aspect, the present invention further provides a large-scale phased array multi-channel partitioned beam control device based on FPGA, comprising:

[0040] The command receiving module is used to obtain the control command of the antenna control unit and verify the control command;

[0041] The instruction parsing module is used to parse the control instructions that have been verified to be correct and determine the instruction type based on the parsing results;

[0042] The beam control code calculation module, when the instruction type is a beam switching instruction, is used to determine the beam control parameters in the instruction and calculate the base code of the phased array antenna based on the beam control parameters. The array elements of the phased array antenna are divided into multiple areas. Based on the base code and the position coordinates of each array element, a multi-channel partitioning method is used to parallelly calculate the beam control code of each array element. The beam control code is normalized and then written into the beamforming chip in parallel to complete rapid phase arrangement.

[0043] The instruction response module is used to send the corresponding response instruction to the antenna control unit in a serial transmission manner after the operation corresponding to the control instruction is completed.

[0044] Furthermore, the beam control code calculation module includes a base code calculation module; the base code calculation module is used to determine the beam control parameters in the instruction and calculate the base code of the phased array antenna according to the beam control parameters;

[0045] The base code calculation module includes a table lookup unit, a parallel calculation unit, a first direction base code calculation unit and a second direction base code calculation unit;

[0046] The table lookup unit is used to calculate the intermediate variables using a table lookup method;

[0047] The parallel computing unit is used to call the cordic IP core inside the FPGA to perform parallel computing;

[0048] The first direction base code calculation unit is used to calculate using two multipliers Axis direction base code;

[0049] The second direction base code calculation unit is used to calculate using two multipliers Axis direction base code.

[0050] In a third aspect, the present invention also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the FPGA-based large-scale phased array multi-channel partitioned beam control method described in any of the above technical solutions is implemented.

[0051] Compared with the existing technology, the FPGA-based large-scale phased array multi-channel partitioned beam steering method proposed in this invention has the following advantages:

[0052] First, the control instructions are received and verified to ensure that invalid or erroneous instructions are eliminated before execution, thereby ensuring the validity of the instructions. Second, the control instructions that have passed the verification are parsed to determine the instruction type. For beam switching instructions, the direction of the beam can be dynamically adjusted according to the instruction content, thereby improving the flexibility and accuracy of the operation. Third, the phased array antenna elements are divided into multiple regions, and the base code is calculated based on the position coordinates of the elements in each region and the beam control parameters. The parallel computing method is used to quickly process the beam control code of each element. By calculating the beam control code in parallel through multiple channels, the computing efficiency can be significantly improved, especially in large-scale array systems, which can achieve higher-speed beam control and rapid response. Finally, after completing the operation corresponding to the control instruction, a response instruction is sent to ensure that the control unit can obtain timely feedback on the system operation, thereby ensuring the correctness and real-time performance of the operation.

[0053] In addition, the present invention includes a wealth of control instructions, through which phased array antenna calibration, beam switching, polarization switching, temperature power and other information queries can be completed, making testing and debugging very convenient. The present invention uses sidelobe suppression instructions to close some antenna element channels of the phased array antenna to form a sparse array, which not only reduces the sidelobe level but also reduces antenna power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 A schematic flow chart of the FPGA-based large-scale phased array multi-channel partitioned beam steering method provided by the present invention;

[0055] Figure 2 The block diagram of the wave control code calculation module provided by the present invention;

[0056] Figure 3 A schematic diagram of the positional relationship between antenna elements and beam chips corresponding to one zone of the phased array antenna provided by the present invention;

[0057] Figure 4 A schematic diagram of the triangular cut-corner array provided by the present invention;

[0058] Figure 5 A schematic diagram of the frame format of the control instructions and response instructions provided by the present invention;

[0059] Figure 6 A schematic structural diagram of an embodiment of a large-scale phased array multi-channel partitioned beam steering device based on FPGA provided by the present invention;

[0060] Figure 7 This is a schematic diagram of the workflow of the FPGA-based large-scale phased array multi-channel partitioned beam control device provided by the present invention. DETAILED DESCRIPTION

[0061] The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, and are not used to limit the scope of the present invention.

[0062] See Figure 1 This embodiment provides a large-scale phased array multi-channel partitioned beam steering method based on FPGA, including:

[0063] Step S101: obtaining a control instruction from an antenna control unit and verifying the control instruction;

[0064] Step S102: Parse the verified control instruction and determine the instruction type based on the parsing result. If the instruction type is a beam switching instruction, determine the beam control parameters in the instruction and calculate the base code of the phased array antenna based on the beam control parameters.

[0065] Step S103: Divide the elements of the phased array antenna into multiple regions. Based on the base code and the position coordinates of each element, a multi-channel partitioning method is used to parallelly calculate the beam control code of each element. The beam control code is normalized and then written into the beamforming chip in parallel to complete rapid phase arrangement.

[0066] Step S104: After the operation corresponding to the control instruction is completed, the corresponding response instruction is sent to the antenna control unit in a serial transmission manner.

[0067] The FPGA-based large-scale phased array multi-channel partitioned beam control method provided in this embodiment first receives and verifies control instructions to ensure that invalid or erroneous instructions are eliminated before execution, thereby ensuring the validity of the instructions. Second, the control instructions that pass the verification are parsed to determine the instruction type. For beam switching instructions, the direction of the beam can be dynamically adjusted according to the instruction content, thereby improving the flexibility and accuracy of the operation. Third, the phased array antenna elements are divided into multiple regions, and the base code is calculated based on the position coordinates of the elements in each region and the beam control parameters. The beam control code of each element is quickly processed using a parallel computing method. The multi-channel parallel calculation of the beam control code can significantly improve computing efficiency, especially in large-scale array systems, and can achieve higher-speed beam control and rapid response. Finally, after completing the operation corresponding to the control instruction, a response instruction is sent to ensure that the control unit can obtain timely feedback on the system operation, thereby ensuring the correctness and real-time performance of the operation.

[0068] As a specific embodiment, in step S101, after comprehensively considering the accuracy and efficiency of detection, the data verification method is selected as CRC verification. If the verification is correct, the control instruction is parsed according to the frame format; if the verification fails, an error response instruction is returned.

[0069] Control instructions are messages containing specific operational requirements. In a specific embodiment, control instructions are framed using a fixed frame format, primarily consisting of a frame header, frame length, frame type, frame data, and checksums, and are sent serially using the SPI protocol. After a command is correctly received, the frame type field of the control instruction is parsed to determine the instruction type.

[0070] As a preferred embodiment, the instruction types include:

[0071] Beam switching commands, used for beam pointing control of phased array antennas, including scan angle, azimuth angle, and frequency fields;

[0072] Polarization switching instructions are used to configure the polarization mode of the phased array antenna;

[0073] RF switch command, used to control the RF switch of the beamforming chip;

[0074] The sidelobe suppression command is used to shut down some elements of the phased array antenna to form a sparse array, thereby reducing the sidelobe level and the power consumption of the phased array antenna.

[0075] Temperature query command, used to query the temperature information of the phased array antenna and monitor the antenna temperature in real time;

[0076] The power query command is used to query the power information of the phased array antenna and monitor the antenna power in real time.

[0077] As a preferred embodiment, in step S102, if the instruction type is a beam switching instruction, the beam control parameters in the instruction need to be parsed. The beam control parameters in the instruction include at least scanning angle, azimuth angle and frequency word information;

[0078] The formula for calculating the phased array antenna base code based on the beam steering parameters is:

[0079]

[0080]

[0081] in, Phased array antenna Axis direction base code, Phased array antenna Axis direction base code, Phased array antenna Axis element spacing, Phased array antenna Axle spacing, is the scanning angle, is the azimuth, is the frequency, is the speed of light, is the bit width using virtual bit technology.

[0082] As a specific embodiment, in practice, the block diagram of the wave control code calculation module is as follows: Figure 2 As shown, in order to save multiplier resources, the table lookup method is used to calculate and The value of the scan angle can be obtained by calling the cordic IP core , the sine of the azimuth and cosine ; From multiplier 1 we can get * The value of can be obtained by multiplier 3 * The value of; by multiplier 2 we can get The value of can be obtained by multiplier 4 The value of .

[0083] In practice, the base code calculation steps include:

[0084] Step 1: Calculate separately using the table lookup method 、 ;

[0085] Step 2: Call the FPGA internal cordic IP core for parallel computing 、 、 ;

[0086] Step 3: Use multiplier 1 and multiplier 2 to calculate Axis direction base code ;

[0087] Step 4: Use multipliers 3 and 4 to calculate Axis direction base code .

[0088] As a preferred embodiment, in step S103, as Figure 3 As shown in the figure, the array elements of the phased array antenna are divided into multiple regions. According to the base code and the position coordinates of each array element, the wave control code of each array element is calculated in parallel using a multi-channel partitioning method, including:

[0089] According to the physical position relationship between antenna elements and beamforming chips, the antenna array is divided into Each area is controlled by a SPI interface with multiple beamforming chips;

[0090] According to the antenna left-hand, right-hand polarization mode and frequency word information, the corresponding phase compensation code is read from the external FLASH and stored in the FPGA RAM;

[0091] Will Base code in axis direction , Base code in axis direction , phase compensation code for each partition Parallel Input Partition channels;

[0092] Input the coordinates of each partition antenna array element serially Partition channels, each partition is calculated by two multipliers 、 The value of

[0093] Use adders to calculate the original wave control code of each partition antenna array element ;

[0094] Normalize the original wave control code, intercept the valid bits, and obtain the final wave control code ;

[0095] The beam control codes of each partition are framed according to the beamforming chip protocol format and transmitted in parallel. The data is written into the beamforming chip through the SPI interface to complete the rapid phase arrangement.

[0096] As a preferred embodiment, the calculation formula of the multi-channel partition wave control code is as follows:

[0097]

[0098] in, Phased array antenna The wave control code of each array element in each partition, , for a phased array antenna with M rows and N columns, For the array element Axis coordinates, For the array element Axis coordinates, Phased array antenna Axis direction base code, Phased array antenna Axis direction base code, is the phase compensation code after phased array antenna calibration.

[0099] As a preferred embodiment, when the instruction type is a sidelobe suppression instruction, performing a sidelobe suppression operation includes:

[0100] The corresponding antenna array elements are turned off by issuing radio frequency switch instructions, so that the phased array antenna forms a sparse array; the sparse array includes a cut-angle array and a sparse array based on a genetic algorithm.

[0101] Specifically, the antenna control unit sends a control instruction, and after the frame type field determines that it is a sidelobe suppression instruction, it performs a sidelobe suppression operation and shuts down the corresponding antenna array element by sending an RF switch instruction, so that the phased array antenna forms a sparse array. Common sparse arrays include angle-cut arrays and sparse arrays based on genetic algorithms. They can reduce the sidelobe level and power consumption without significantly reducing the antenna gain and beam bandwidth, and are simple to implement.

[0102] like Figure 4 As shown, the RF channels of some edge arrays are closed, so that the phased array antenna forms a triangular truncated array, thereby reducing the sidelobe level and power consumption.

[0103] As a specific embodiment, in step S104, the response instruction is returned to the antenna control unit, specifically:

[0104] After the control instruction classification operation is completed, the corresponding response instruction is framed and then sent to the antenna control unit in a serial manner, mainly including the following response instructions:

[0105] Beam switching response command, responding to the beam switching command, beam switching is completed;

[0106] Polarization switching response instruction, responding to the polarization switching instruction, and polarization switching is completed;

[0107] RF switch response command, respond to RF switch command, RF switch is completed;

[0108] Sidelobe suppression response instruction, responding to the sidelobe suppression instruction, and sidelobe suppression is completed;

[0109] Temperature query response command, respond to the temperature query command, the temperature query is completed;

[0110] Power query response command, respond to the power query command, and the power query is completed.

[0111] The frame format of the response command is as follows: Figure 5 As shown, after the classification operation is completed, framing is performed and sent serially to the antenna control unit according to the SPI protocol; if the beam switching instruction operation is completed, the beam switching response instruction is returned to indicate that the beam switching has been completed; if the temperature query instruction operation is completed, the temperature query response instruction is returned to obtain the temperature information.

[0112] Example 2

[0113] like Figure 6 As shown, an embodiment of the present invention further provides a large-scale phased array multi-channel partitioned beam control device 600 based on FPGA, comprising:

[0114] The instruction receiving module 601 is used to obtain the control instruction of the antenna control unit and verify the control instruction;

[0115] The instruction parsing module 602 is used to parse the control instruction that has been verified to be correct and determine the instruction type based on the parsing result;

[0116] The beam control code calculation module 603, when the instruction type is a beam switching instruction, is used to determine the beam control parameters in the instruction and calculate the base code of the phased array antenna based on the beam control parameters. The array elements of the phased array antenna are divided into multiple regions. Based on the base code and the position coordinates of each array element, a multi-channel partitioning method is used to parallelly calculate the beam control code of each array element. The beam control code is normalized and then written into the beamforming chip in parallel to complete rapid phase arrangement.

[0117] The instruction response module 604 is used to send the corresponding response instruction to the antenna control unit in a serial transmission manner after the operation corresponding to the control instruction is completed.

[0118] In some embodiments, as Figure 7As shown, the instruction receiving module receives the serial control instructions issued by the antenna control unit according to the SPI interface protocol, identifies the frame header, and performs CRC check on each byte in sequence. After the check is correct, the control instruction is sent to the instruction parsing module. The instruction parsing module determines the current instruction type by looking up the frame type field of the instruction, parses the required fields, and sends it to the classification operation module for processing. Common instruction types include beam switching instructions, polarization switching instructions, RF switching instructions, sidelobe suppression instructions, temperature query instructions, power query instructions, etc. The classification operation module performs different operations based on the instruction type. If the current instruction is a temperature query instruction, the phased array temperature query operation is executed; if the current instruction is a beam switching instruction, the parsed scanning angle, azimuth angle, and frequency word are sent to the wave control code calculation module. The wave control code calculation module first calculates the base code of the phased array antenna. Given the coordinates of each array element, multi-channel partitioning is used to calculate the wave control code of each array element and outputs them in parallel. The beamforming control code is written into the beamforming chip for pointing control. After the classification operation is completed, the command response module needs to provide a corresponding response. It frames the response command according to the response command frame format and sends it to the command transmission module. The command transmission module transmits the response command serially to the antenna control unit using the SPI interface protocol.

[0119] As a preferred embodiment, the beam control code calculation module includes a base code calculation module; the base code calculation module is used to determine the beam control parameters in the instruction and calculate the base code of the phased array antenna according to the beam control parameters;

[0120] The base code calculation module includes a table lookup unit, a parallel calculation unit, a first direction base code calculation unit and a second direction base code calculation unit;

[0121] The table lookup unit is used to calculate the intermediate variables using a table lookup;

[0122] The parallel computing unit is used to call the cordic IP core inside the FPGA to perform parallel computing;

[0123] The first direction base code calculation unit is used to calculate using two multipliers Axis direction base code;

[0124] The second direction base code calculation unit is used to calculate using two multipliers Axis direction base code.

[0125] As a specific embodiment, after completing the base code calculation, use The channel partitions calculate the wave control code of the phased array antenna; each channel contains two multipliers and one adder to complete Then perform normalization to control the result of the wave control code between 0-360°, intercept the effective 6-bit width, and parallel Please refer to Figure 2 , this embodiment adopts Figure 2 The method to calculate the wave control code is as follows: If a fully parallel method is used, at least 5 multipliers are required for each path, which is a total of multipliers. That is, assuming The fully parallel approach requires 80 multipliers, while the method of the present invention only requires 36 multipliers, reducing multiplier resources by 55%. However, the wave control code calculation time of this method is basically the same as that of the fully parallel approach. Although the single-channel wave control code calculation method consumes the least resources, it is also the slowest. For large-scale phased array antennas (the number of array elements in this embodiment is 4096), the single-channel consumes more clocks than the method of the present invention. The method of this embodiment ,but When the clock is 50 MHz, the wave control code calculation time of a single channel is 76.8 μs longer than that of the present embodiment.

[0126] From the above analysis, it can be seen that the device proposed in this embodiment can significantly reduce the use of multipliers while keeping the calculation time unchanged, save hardware resources, and avoid the calculation delay problem caused by the single-channel method.

[0127] Example 3

[0128] This embodiment also provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the FPGA-based large-scale phased array multi-channel partitioned beam control method described in any of the above technical solutions.

[0129] The computer-readable storage medium and computing device provided in the above-mentioned embodiments of the present invention can be implemented with reference to the specific description of the above-mentioned large-scale phased array multi-channel partitioned beam steering method based on FPGA according to the present invention, and have similar beneficial effects as the above-mentioned large-scale phased array multi-channel partitioned beam steering method based on FPGA, which will not be repeated here.

[0130] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with this technical field within the technical scope disclosed by the present invention should be covered by the scope of protection of the present invention.

Claims

1. A large-scale phased array multi-channel partitioned beam steering method based on FPGA, characterized in that: include: Obtain control instructions from the antenna control unit and verify the control instructions; Parse the verified control instructions and determine the instruction type based on the parsing result. If the instruction type is a beam switching instruction, determine the beam control parameters in the instruction and calculate the base code of the phased array antenna based on the beam control parameters. The elements of the phased array antenna are divided into multiple regions. Based on the base code and the position coordinates of each element, a multi-channel partitioning method is used to parallelly calculate the beam control code of each element. The beam control code is normalized and then written into the beamforming chip in parallel to achieve rapid phase arrangement. After the operation corresponding to the control instruction is completed, the corresponding response instruction is sent to the antenna control unit in a serial transmission manner.

2. The FPGA-based large-scale phased array multi-channel partitioned beam steering method according to claim 1, characterized in that: The beam control parameters in the instruction include at least scanning angle, azimuth angle and frequency word information; The formula for calculating the phased array antenna base code based on the beam steering parameters is: in, Phased array antenna Axis direction base code, Phased array antenna Axis direction base code, Phased array antenna Axis element spacing, Phased array antenna Axle spacing, is the scanning angle, is the azimuth, is the frequency, is the speed of light, is the bit width using virtual bit technology.

3. The FPGA-based large-scale phased array multi-channel partitioned beam steering method according to claim 2, characterized in that: The elements of the phased array antenna are divided into multiple regions. Based on the base code and the position coordinates of each element, a multi-channel partitioning method is used to parallelly calculate the wave control code of each element, including: According to the physical position relationship between antenna elements and beamforming chips, the antenna array is divided into regions, each of which consists of a Interface controls multiple beamforming chips; According to the antenna left-hand, right-hand polarization mode and frequency word information, the corresponding phase compensation code is read from the external FLASH and stored in the FPGA RAM; Will Base code in axis direction , Base code in axis direction , phase compensation code for each partition Parallel Input Partition channels; Input the coordinates of each partition antenna array element serially Partition channels, each partition is calculated by two multipliers 、 The value of Use adders to calculate the original wave control code of each partition antenna array element ; Normalize the original wave control code, intercept the valid bits, and obtain the final wave control code ; The beam control codes of each partition are framed according to the beamforming chip protocol format and transmitted in parallel. The data is written into the beamforming chip through the SPI interface to complete the rapid phase arrangement.

4. The FPGA-based large-scale phased array multi-channel partitioned beam steering method according to claim 3, characterized in that: The calculation formula of the multi-channel partition wave control code is as follows: in, Phased array antenna The wave control code of each array element in each partition, , for a phased array antenna with M rows and N columns, For the array element Axis coordinates, For the array element Axis coordinates, Phased array antenna Axis direction base code, Phased array antenna Axis direction base code, is the phase compensation code after phased array antenna calibration.

5. The FPGA-based large-scale phased array multi-channel partitioned beam steering method according to claim 1, characterized in that: The instruction types include: Beam switching commands, used for beam pointing control of phased array antennas, including scan angle, azimuth angle, and frequency fields; Polarization switching instructions are used to configure the polarization mode of the phased array antenna; RF switch command, used to control the RF switch of the beamforming chip; The sidelobe suppression command is used to shut down some elements of the phased array antenna to form a sparse array, thereby reducing the sidelobe level and the power consumption of the phased array antenna. Temperature query command, used to query the temperature information of the phased array antenna and monitor the antenna temperature in real time; The power query command is used to query the power information of the phased array antenna and monitor the antenna power in real time.

6. The FPGA-based large-scale phased array multi-channel partitioned beam steering method according to claim 5, characterized in that: When the instruction type is a sidelobe suppression instruction, performing a sidelobe suppression operation includes: The corresponding antenna array elements are turned off by issuing radio frequency switch instructions, so that the phased array antenna forms a sparse array; the sparse array includes a cut-angle array and a sparse array based on a genetic algorithm.

7. The FPGA-based large-scale phased array multi-channel partitioned beam steering method according to claim 1, characterized in that: The control instructions are framed using a preset frame format; The preset frame format includes a frame header, a frame length, a frame type, a frame data, and a check bit.

8. A large-scale phased array multi-channel partitioned beam control device based on FPGA, characterized in that: include: The command receiving module is used to obtain the control command of the antenna control unit and verify the control command; The instruction parsing module is used to parse the control instructions that have been verified to be correct and determine the instruction type based on the parsing results; The beam control code calculation module, when the instruction type is a beam switching instruction, is used to determine the beam control parameters in the instruction and calculate the base code of the phased array antenna based on the beam control parameters. The array elements of the phased array antenna are divided into multiple areas. Based on the base code and the position coordinates of each array element, a multi-channel partitioning method is used to parallelly calculate the beam control code of each array element. The beam control code is normalized and then written into the beamforming chip in parallel to complete rapid phase arrangement. The instruction response module is used to send the corresponding response instruction to the antenna control unit in a serial transmission manner after the operation corresponding to the control instruction is completed.

9. The FPGA-based large-scale phased array multi-channel partitioned beam control device according to claim 8, characterized in that: The beam control code calculation module includes a base code calculation module; the base code calculation module is used to determine the beam control parameters in the instruction and calculate the base code of the phased array antenna according to the beam control parameters; The base code calculation module includes a table lookup unit, a parallel calculation unit, a first direction base code calculation unit and a second direction base code calculation unit; The table lookup unit is used to calculate the intermediate variables using a table lookup method; The parallel computing unit is used to call the cordic IP core inside the FPGA to perform parallel computing; The first direction base code calculation unit is used to calculate using two multipliers Axis direction base code; The second direction base code calculation unit is used to calculate using two multipliers Axis direction base code.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the FPGA-based large-scale phased array multi-channel partitioned beam control method according to any one of claims 1 to 7 is implemented.

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