Display device, display panel and vehicle

Abstract

The invention discloses a display device, a display panel and a vehicle. A display device according to an exemplary embodiment of the present disclosure may include: a substrate including a display area and a non-display area; a first pad region disposed in the non-display region, and a second pad region disposed in the non-display region; an alignment mark disposed to be spaced apart from the first pad region; and a structure disposed adjacent to the alignment mark.

Description

Technical Field

[0001] Exemplary embodiments of the present disclosure relate to a display device, a display panel, and a vehicle, and more particularly, for example but not limited to, to a display device, a display panel, and a vehicle capable of preventing cracks from occurring or propagating in the display panel. Background Art

[0002] With the development of intelligent society, display devices for displaying images have been rapidly developed. Therefore, display devices are developing towards lightweight, ultra-thin appearance, excellent performance and low power consumption.

[0003] Various display devices, such as liquid crystal displays (LCDs), field emission displays (FEDs), and organic light emitting displays (OLEDs), have recently been widely used.

[0004] The description provided in the description of the background technology section should not be assumed to be prior art simply because it is mentioned in the description of the background technology section or is associated with the description of the background technology section. The description of the background technology section may include information describing one or more aspects of the subject technology, and the description in this section does not limit the present disclosure. Summary of the Invention

[0005] The inventors have recognized that a display device may include a display panel including a display area and a non-display area. A chip or a printed circuit board may be disposed in the non-display area of ​​the display panel. When the chip or printed circuit board is coupled to the display panel, a bonding process may be performed.

[0006] When performing the bonding process, cracks may appear in the display panel. When cracks appear, the cracks may propagate into the display panel, or moisture may penetrate along the cracks. In addition, the propagation of the cracks may damage various circuits.

[0007] Cracks in the display panel may reduce the reliability of the display device.

[0008] Exemplary embodiments of the present disclosure may provide a display device capable of preventing cracks from occurring or propagating in the display panel.

[0009] Exemplary embodiments of the present disclosure may provide a display device capable of preventing moisture from penetrating due to cracks.

[0010] Exemplary embodiments of the present disclosure may provide a display device capable of preventing various wirings from being damaged by cracks.

[0011] Exemplary embodiments of the present disclosure may provide a display device capable of alleviating a reduction in reliability of the display device due to cracks.

[0012] A display device according to an exemplary embodiment of the present disclosure may include: a substrate including a display area and a non-display area; a first pad area disposed in the non-display area; an alignment mark disposed to be spaced apart from the first pad area; and a structure disposed adjacent to the alignment mark.

[0013] A display device according to an exemplary embodiment of the present disclosure may include: a substrate including a display area and a non-display area; a plurality of insulating layers disposed on the substrate; a pad electrode disposed on the substrate and including a plurality of metal layers; an alignment mark disposed on the substrate and adjacent to the pad electrode; and a structure disposed on the substrate and including a plurality of metal layers. The structure may be disposed between the pad electrode and the alignment mark.

[0014] According to an exemplary embodiment of the present disclosure, a display panel is provided, which is provided with a display area and a non-display area, and includes: a first pad area, which is provided in the non-display area; an alignment mark, which is provided to be spaced apart from the first pad area; and a structure, which is provided to be adjacent to the alignment mark.

[0015] According to an exemplary embodiment of the present disclosure, a display panel is provided, which includes: a plurality of insulating layers; a pad electrode, which is arranged among the plurality of insulating layers and includes a plurality of metal layers; an alignment mark, which is arranged among the plurality of insulating layers and adjacent to the pad electrode; and a structure, which is arranged among the plurality of insulating layers and includes a plurality of metal layers, wherein the structure is arranged between the pad electrode and the alignment mark.

[0016] According to exemplary embodiments of the present disclosure, a display device with enhanced reliability may be provided.

[0017] According to exemplary embodiments of the present disclosure, it is possible to provide a display device capable of preventing cracks from occurring or propagating in a display panel by providing a structure in an insulating layer of the display panel.

[0018] According to exemplary embodiments of the present disclosure, a display device having enhanced resistance to moisture permeation by preventing cracks from occurring or propagating in a display panel may be provided.

[0019] According to exemplary embodiments of the present disclosure, a display device capable of preventing damage to various wirings by preventing cracks from occurring or propagating in a display panel may be provided.

[0020] According to exemplary embodiments of the present disclosure, it is possible to provide a display device capable of reducing power consumption by improving the service life of the display device by preventing cracks from occurring or propagating in a display panel.

[0021] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the inventive concept as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated into and constitute a part of the present disclosure. The accompanying drawings illustrate various aspects and embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. The above and other objects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0023] Figure 1 is a view showing a system configuration of a display device according to an exemplary embodiment of the present disclosure;

[0024] Figure 2 shows a display panel according to an exemplary embodiment of the present disclosure;

[0025] Figure 3 is an exemplary cross-sectional view illustrating a display panel according to an exemplary embodiment of the present disclosure;

[0026] Figure 4 is an exemplary plan view illustrating a display device according to an exemplary embodiment of the present disclosure;

[0027] Figure 5 It shows Figure 4 An exemplary view of region X;

[0028] Figure 6 It is along Figure 5 An exemplary cross-sectional view taken along line AB in FIG.

[0029] Figure 7 It shows Figure 4 An exemplary view of region X; and

[0030] Figure 8 It is along Figure 7 An exemplary cross-sectional view taken along line CD in FIG.

[0031] Throughout the drawings and detailed description, unless otherwise described, the same drawing reference numerals should be understood to refer to the same elements, features, and structures. The relative sizes and depictions of these elements may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0032] Reference will now be made in detail to embodiments of the present disclosure, examples of which may be illustrated in the accompanying drawings. The described progression of processing steps and / or operations is an example; however, the order of the steps and / or operations is not limited to that described herein and may be varied as is known in the art, except for steps and / or operations that must occur in a specific order. The names of the various elements used in the following explanation may have been selected solely for convenience in writing the specification and, therefore, may differ from the names used in the actual product.

[0033] In the following description of examples or embodiments of the present disclosure, reference will be made to the accompanying drawings, which show by way of illustration specific examples or embodiments that can be implemented, and in which the same reference numerals and symbols may be used to represent the same or similar parts even when the same or similar parts are shown in different figures from each other. In addition, in the following description of examples or embodiments of the present disclosure, detailed descriptions of well-known functions and components incorporated herein will be omitted when it is determined that the description may make the subject matter in some embodiments of the present disclosure quite unclear. Terms used herein such as "comprising", "having", "including", "containing", "constituting", "made of", "formed of", "composed of" are generally intended to allow for the addition of other parts unless these terms are used with the term "only". As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0034] The shapes, sizes, proportions, angles, quantities, etc. shown in the drawings for illustrating the embodiments of the present disclosure are for illustration purposes only and are not intended to limit the contents shown in the drawings. Where possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts. In the following description, detailed descriptions of techniques or configurations related to the present disclosure may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0035] The shapes, sizes, dimensions (e.g., length, width, height, thickness, radius, diameter, area, etc.), ratios, angles, quantities, etc. of the elements shown in the drawings for describing exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals generally represent the same elements.

[0036] The dimensions including size and thickness of the various components shown in the drawings are shown for ease of description, and the present disclosure is not limited to the size and thickness of the components shown, but it should be noted that the relative dimensions including relative size, position and thickness of the components shown in the various drawings submitted herein are part of the present disclosure.

[0037] When describing various embodiments of the present disclosure, when terms used for positional relationships are used, such as “on,” “over,” “above,” “under,” “below,” “beside,” “under,” “near,” “near,” “adjacent,” “on the side of,” or “close to,” at least one intermediate element may be present between two elements unless “immediately adjacent” or “directly” is used.

[0038] Spatially relative terms may be used herein, such as "below," "beneath," "under," "lower," "above," "upper," etc., to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that in addition to the orientation shown in the figures, spatially relative terms can also include different orientations of elements in use or operation. For example, if the elements in the figures are inverted, elements described as being "below" or "below" other elements or features will be oriented as being "above" other elements or features. Thus, the exemplary term "below" can include both below and above orientations. Similarly, the exemplary terms "above" or "above" can include both above and below orientations.

[0039] When an element or layer is referred to as being “on” another element or layer, the further layer or element may be directly on the other element or interposed between the two elements or layers.

[0040] Terms such as "first," "second," "A," "B," "(A)," or "(B)" may be used herein to describe elements of the present disclosure. Each of these terms is not used to define the nature, order, sequence, or quantity of the elements, but is only used to distinguish the corresponding element from other elements.

[0041] When it is mentioned that a first element is “connected or coupled”, “contacted or overlapped”, etc. with a second element, it should be understood that not only the first element may be “directly connected or coupled” or “directly contacted or overlapped” with the second element, but also a third element may be “interposed” between the first and second elements, or the first and second elements may be “connected or coupled”, “contacted or overlapped”, etc. with each other via a fourth element. Here, the second element may be included in at least one of the two or more elements that are “connected or coupled”, “contacted or overlapped”, etc. with each other.

[0042] When time relative terms (such as "after," "subsequently," "next," "before," etc.) are used to describe a process or operation of an element or configuration, or a flow or step in an operation, process, or manufacturing method, these terms may be used to describe non-sequential or non-sequential processes or operations unless the terms "directly" or "immediately" are used at the same time.

[0043] The term "at least one" should be understood to include all possible combinations that can be suggested from one or more related items. For example, "at least one of a first item, a second item, or a third item" can mean each of the first item, the second item, or the third item, and can also mean all possible combinations that can be suggested from two or more of the first item, the second item, and the third item.

[0044] In addition, when referring to any size, relative size, etc., it should be understood that the numerical value or corresponding information (e.g., level, range, etc.) of the element or feature includes tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no relevant description is specified. In addition, the term "may" fully includes all meanings of the term "can."

[0045] The term "device" as used herein may refer to a display device including a display panel and a driver for driving the display panel. Examples of display devices may include light-emitting elements, etc. In addition, examples of devices may include laptop computers, televisions, computer monitors, automotive devices, wearable devices, and automotive equipment devices, as well as complete electronic devices (or devices) or complete sets of devices (or devices) each including a light-emitting element as a complete product or final product, for example, mobile electronic devices such as smartphones or electronic tablets, but embodiments of the present disclosure are not limited thereto.

[0046] The various features of the various embodiments according to the present disclosure may be partially or completely joined or combined and technically related or operated in various ways, and the embodiments may be implemented independently or in combination.

[0047] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0048] In aspects of the present disclosure, for ease of description, source electrodes and drain electrodes are distinguished from each other. However, source electrodes and drain electrodes may be used interchangeably. A source electrode may be a drain electrode, and a drain electrode may be a source electrode. In addition, a source electrode in any aspect of the present disclosure may be a drain electrode in another aspect of the present disclosure, and a drain electrode in any aspect of the present disclosure may be a source electrode in another aspect of the present disclosure.

[0049] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the specification, when adding reference numerals to elements in each drawing, it should be noted that, whenever possible, the same reference numerals used to represent elements in other drawings are used for those elements. In addition, for ease of description, the dimensional ratios of the components shown in the drawings may differ from the actual dimensional ratios. That is, the dimensional ratios of the components shown in the drawings should not be interpreted as being the same as the dimensional ratios shown in the drawings.

[0050] Hereinafter, various embodiments of the present disclosure are described in detail with reference to the accompanying drawings.

[0051] Figure 1 is a view illustrating a system configuration of a display device according to an exemplary embodiment of the present disclosure.

[0052] Reference Figure 1 The display device 100 according to an exemplary embodiment of the present disclosure may include a display panel 110 and a display driving circuit as components for displaying an image. The display driving circuit may be a circuit for driving the display panel 110. The display driving circuit may include a data driving circuit 120, a gate driving circuit 130, and a controller 140, but the exemplary embodiments of the present disclosure are not limited thereto.

[0053] The display panel 110 may include a substrate 111 and a plurality of sub-pixels SP disposed on the substrate 111 .

[0054] The substrate 111 may include a display area (display region) AA capable of displaying an image and a non-display area (non-display region) NA located around or outside the display area AA.

[0055] A plurality of sub-pixels SP for image display may be provided in the display area AA. The non-display area NA may include a pad area PA (not shown) located at at least one side of the display area AA in a column direction.

[0056] In the display panel 110 according to an exemplary embodiment of the present disclosure, the non-display area NA can be very small. In the present disclosure, the non-display area NA can also be referred to as a "frame." For example, the non-display area NA can include a first non-display area, a second non-display area, a third non-display area, and a fourth non-display area. The first non-display area can be located outside the display area AA in the column direction. The second non-display area can be located outside the display area AA in the row direction. The third non-display area can be located outside the display area AA in the column direction and can be positioned opposite the first non-display area. The fourth non-display area can be located outside the display area AA in the row direction and can be positioned opposite the second non-display area. The first non-display area among the first to fourth non-display areas may include a pad area for connecting or bonding to a data driver circuit. Among the first to fourth non-display areas, the second to fourth non-display areas that do not include the pad area can have very small sizes, but exemplary embodiments of the present disclosure are not limited thereto.

[0057] As another example, the boundary area between the display area AA and the non-display area NA may be bent so that the non-display area NA may be positioned below the display area AA. In this case, when the user views the display area AA from the front, the non-display area NA displayed to the user may be unchanged or slightly changed, but exemplary embodiments of the present disclosure are not limited thereto.

[0058] Various types of signal lines for driving the plurality of sub-pixels SP may be provided on the substrate 111 of the display panel 110 .

[0059] The display device 100 according to the exemplary embodiment of the present disclosure may be a liquid crystal display device or a self-luminous display device in which the display panel 110 emits light by itself, but the exemplary embodiment of the present disclosure is not limited thereto. When the display device 100 according to the exemplary embodiment of the present disclosure is a self-luminous display device, each of the plurality of sub-pixels SP may include a light-emitting element.

[0060] For example, the display device 100 according to the exemplary embodiment of the present disclosure may be an organic light-emitting diode display device in which the light-emitting elements are implemented as organic light-emitting diodes (OLEDs). As another example, the display device 100 according to the exemplary embodiment of the present disclosure may be an inorganic light-emitting display device in which the light-emitting elements are implemented as light-emitting diodes based on inorganic materials. As another example, the display device 100 according to the exemplary embodiment of the present disclosure may be a quantum dot display device in which the light-emitting elements are implemented as quantum dots, which are self-luminous semiconductor crystals. As another example, the display device 100 according to the exemplary embodiment of the present disclosure may be a micro-LED display device or a mini-LED display device.

[0061] A plurality of sub-pixels SP is the smallest unit constituting a display area, and n sub-pixels SP form a pixel. Each of the plurality of sub-pixels SP can emit light having a different wavelength from one another. The plurality of sub-pixels SP can include a first sub-pixel, a second sub-pixel, and a third sub-pixel that emit light of different colors from one another. Each pixel P can be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for color rendering. Each pixel P can also include a white sub-pixel. The plurality of sub-pixels SP can be modified in various colors and configurations as needed. However, the present disclosure is not limited thereto.

[0062] For example, the plurality of sub-pixels SP may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, wherein the red sub-pixel, the green sub-pixel, and the blue sub-pixel may be arranged in a repeated manner. Alternatively, the plurality of sub-pixels SP may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, wherein the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel may be arranged in a repeated manner, or the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel may be arranged in a quadrilateral type. For example, the red sub-pixel, the blue sub-pixel, and the green sub-pixel may be arranged sequentially along the row direction, or the red sub-pixel, the blue sub-pixel, the green sub-pixel, and the white sub-pixel may be arranged sequentially along the row direction. However, in an embodiment of the present disclosure, the color type, arrangement type, and arrangement order of the sub-pixels are not limited, and may be configured in various forms according to luminous characteristics, device life, and device specifications.

[0063] Furthermore, subpixels may have different light-emitting areas depending on their light-emitting characteristics. For example, a subpixel emitting light of a color different from that of a blue subpixel may have a light-emitting area different from that of the blue subpixel. For example, a red subpixel, a blue subpixel, and a green subpixel, or a red subpixel, a blue subpixel, a white subpixel, and a green subpixel may each have a different light-emitting area.

[0064] The structure of each of the plurality of sub-pixels SP may vary depending on the type of the display device 100. For example, when the display device 100 is a self-luminous display device in which the sub-pixels SP emit light by themselves, each sub-pixel SP may include a self-luminous light-emitting element, one or more transistors, and one or more capacitors, but exemplary embodiments of the present disclosure are not limited thereto.

[0065] For example, the various types of signal lines may include a plurality of data lines DL transmitting data signals (also referred to as data voltages or image signals) and a plurality of gate lines GL transmitting gate signals (also referred to as scan signals).

[0066] The plurality of data lines DL and the plurality of gate lines GL may intersect each other. Each of the plurality of data lines DL may be arranged to extend in a column direction. Each of the plurality of gate lines GL may be arranged to extend in a row direction. According to an exemplary embodiment of the present disclosure, the column direction and the row direction may be opposite directions. In other words, depending on the viewpoint, the column direction may be the row direction, and depending on the viewpoint, the row direction may be the column direction. For ease of description, an example is described below in which each of the plurality of data lines DL is arranged in a column direction and each of the plurality of gate lines GL is arranged in a row direction, but the exemplary embodiment of the present disclosure is not limited thereto. For example, each of the plurality of data lines DL may be arranged in a row direction, and each of the plurality of gate lines GL may be arranged in a column direction. In an exemplary embodiment of the present disclosure, the angle between the row direction and the column direction may be 90 degrees, or may be an angle different from 90 degrees. In addition, in an exemplary embodiment of the present disclosure, the row direction may be referred to as a first direction, and the column direction may be referred to as a second direction. Alternatively, the column direction may be referred to as a first direction, and the row direction may be referred to as a second direction.

[0067] The data driving circuit 120 may be a circuit for driving a plurality of data lines DL. The data driving circuit 120 may output data signals to the plurality of data lines DL. The gate driving circuit 130 may be a circuit for driving a plurality of gate lines GL and may supply gate signals to the gate lines GL.

[0068] The data driving circuit 120 may receive digital image data DATA from the controller 140 and may convert the received image data DATA into analog data signals and output them to the plurality of data lines DL.

[0069] For example, the data driving circuit 120 may be connected to the display panel 110 through a tape automated bonding (TAB) method, or connected to a bonding pad of the display panel 110 through a chip on glass (COG) or chip on panel (COP) method, or may be implemented through a chip on film (COF) method and connected to the display panel 110, but exemplary embodiments of the present disclosure are not limited thereto.

[0070] The data driving circuit 120 may be connected to one side (e.g., the upper side or the lower side) of the display panel 110. As another example, depending on a driving scheme or a panel design scheme, the data driving circuit 120 may be connected to both sides (e.g., the upper side and the lower side) of the display panel 110, or to two or more of the four sides of the display panel 110.

[0071] The data driving circuit 120 may be connected outside the display area AA of the display panel 110 , but as another example, the data driving circuit 120 may be provided in the display area AA of the display panel 110 .

[0072] The gate driving circuit 130 is a circuit for driving the plurality of gate lines GL and may output gate signals to the plurality of gate lines GL.

[0073] The gate driving circuit 130 may receive a first gate voltage corresponding to an on-level voltage and a second gate voltage corresponding to an off-level voltage, and various gate driving control signals GCS, generate gate signals, and supply the generated gate signals to the plurality of gate lines GL.

[0074] In the display device 100 according to the exemplary embodiment of the present disclosure, the gate driving circuit 130 may be embedded in the display panel 110 in a gate-in-panel (GIP) type, but the exemplary embodiment of the present disclosure is not limited thereto. When the gate driving circuit 130 is a gate-in-panel type, the gate driving circuit 130 may be formed on the substrate 111 of the display panel 110 during the manufacturing process of the display panel 110.

[0075] For example, the gate driving circuit 130 may be disposed in the non-display area NDA of the display panel 110 .

[0076] As another example, the gate driving circuit 130 may be disposed in the display area AA of the display panel 110. For example, the gate driving circuit 130 may be disposed in a first partial area of ​​the display area AA (e.g., a left area or a right area of ​​the display area AA). As another example, the gate driving circuit 130 may be disposed in a first partial area of ​​the display area AA (e.g., a left area or a right area side of the display area AA) and a second partial area of ​​the display area AA (e.g., a right area or a left area of ​​the display area AA).

[0077] In the present disclosure, the gate driving circuit 130 embedded in the display panel 110 in an intra-panel gate type may also be referred to as an “intra-panel gate circuit.” The gate driving circuit 130 may be disposed on the substrate 111 or connected to the substrate 111 .

[0078] The controller 140 is a device for controlling the data driving circuit 120 and the gate driving circuit 130 and may control driving timings of the plurality of data lines DL and driving timings of the plurality of gate lines GL.

[0079] The controller 140 may supply a data driving control signal DCS to the data driving circuit 120 to control the data driving circuit 120 , and may supply a gate driving control signal GCS to the gate driving circuit 130 to control the gate driving circuit 130 .

[0080] The controller 140 may receive input image data from the host system 150 and supply image data DATA to the data driving circuit 120 based on the input image data.

[0081] The controller 140 may be implemented as a separate component from the data driving circuit 120, or the controller 140 and the data driving circuit 120 may be integrated into an integrated circuit (IC). However, the present disclosure is not limited thereto.

[0082] The controller 140 may be a timing controller for display technology, a control device that can perform other control functions as well as the functions of the timing controller, or a control device other than a timing controller, or may be a circuit in a control device. The controller 140 may be implemented as various circuits or electronic components, such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a processor, but is not limited thereto.

[0083] The controller 140 may be mounted on a printed circuit board or a flexible printed circuit, and may be electrically connected to the data driving circuit 120 and the gate driving circuit 130 through the printed circuit board or the flexible printed circuit.

[0084] The controller 140 can send signals to / receive signals from the data driver circuit 120 according to one or more predetermined interfaces. The interface may include, for example, a low voltage differential signaling (LVDS) interface, an embedded clock point-to-point interface (EPI), and a serial peripheral interface (SPI), but the exemplary embodiments of the present disclosure are not limited thereto. Similarly, the controller 140 can send signals to and receive signals from the gate driver circuit 130 via one or more predefined interfaces.

[0085] In order to provide a touch sensing function as well as an image display function, the display device 100 according to an exemplary embodiment of the present disclosure may include a touch sensor and a touch sensing circuit that can sense the touch sensor to detect whether a touch occurs through a touch object (such as a finger or a pen), or the position of the touch.

[0086] The touch sensing circuit may include a touch driving circuit that drives and senses the touch sensor and generates and outputs touch sensing data, and a touch controller that may detect occurrence of a touch or a touched position using the touch sensing data.

[0087] The touch sensor may include a plurality of touch electrodes and a plurality of touch lines for electrically connecting the plurality of touch electrodes and a touch driving circuit.

[0088] The touch sensor may be located outside the display panel 110 in the form of a touch panel, or it may be located inside the display panel 110. When the touch sensor is located outside the display panel 110 in the form of a touch panel, the touch sensor is an external type touch sensor. When the touch sensor is an external type touch sensor, the touch panel and the display panel 110 may be manufactured separately or may be combined during the assembly process. An external type touch panel may include a touch panel substrate and a plurality of touch electrodes on the touch panel substrate.

[0089] When the touch sensor exists inside the display panel 110 , the touch sensor may be formed on a substrate together with signal lines and electrodes related to display driving during a manufacturing process of the display panel 110 .

[0090] The touch driving circuit may supply a touch driving signal to at least one of the plurality of touch electrodes and may sense at least one of the plurality of touch electrodes to generate touch sensing data.

[0091] The touch sensing circuit may perform touch sensing in a self-capacitance sensing scheme or a mutual-capacitance sensing scheme.

[0092] When the touch sensing circuit performs touch sensing in a self-capacitance sensing scheme, the touch sensing circuit can perform touch sensing based on the capacitance between each touch electrode and the touch object (e.g., a finger or pen). According to the self-capacitance sensing scheme, each of the multiple touch electrodes can be used as both a driving touch electrode and a sensing touch electrode. The touch drive circuit can drive all or part of the multiple touch electrodes and can sense all or part of the multiple touch electrodes.

[0093] When the touch sensing circuit performs touch sensing using a mutual capacitance sensing scheme, the touch sensing circuit can perform touch sensing based on the capacitance between touch electrodes. According to the mutual capacitance sensing scheme, multiple touch electrodes are divided into drive touch electrodes and sense touch electrodes. The touch drive circuit can drive the drive touch electrodes and sense the sense touch electrodes.

[0094] The touch driving circuit and the touch controller included in the touch sensing circuit may be implemented as separate devices or as a single device. The touch driving circuit and the data driving circuit may be implemented as separate devices or as a single device.

[0095] The display device 100 may further include a power supply circuit for supplying various types of power to the display driver integrated circuit and / or the touch sensing circuit. The power supply circuit may supply a power supply voltage and various other voltages related to display driving to the display driver circuit or the display panel 110.

[0096] The display device 100 according to an exemplary embodiment of the present disclosure may be a mobile terminal such as a smartphone or a tablet, or a monitor or television (TV) of various sizes, but is not limited thereto and may be displays of various types and sizes capable of displaying information or images.

[0097] The display device 100 according to an exemplary embodiment of the present disclosure may further include electronic devices such as a camera (image sensor), a detection sensor, etc. For example, the detection sensor may be a sensor that detects an object or a human body by receiving light such as infrared rays, ultrasonic waves, or ultraviolet rays, but the exemplary embodiment of the present disclosure is not limited thereto.

[0098] Figure 2 is a view illustrating a display panel according to an exemplary embodiment of the present disclosure.

[0099] Reference Figure 2 The display panel 110 may include a substrate 111 provided with a plurality of sub-pixels SP and an encapsulation layer 200 on the substrate 111. The encapsulation layer 200 may also be referred to as an encapsulation substrate or an encapsulation portion.

[0100] Reference Figure 2 When the display device 100 according to the exemplary embodiment of the present disclosure is a self-luminous display device, each of the plurality of sub-pixels SP provided on the substrate 111 may include a light emitting element ED and a sub-pixel circuit SPC for driving the light emitting element ED.

[0101] Reference Figure 2 The sub-pixel circuit SPC may include a plurality of transistors and at least one capacitor for driving the light-emitting element ED, but exemplary embodiments of the present disclosure are not limited thereto. In the present disclosure, the sub-pixel circuit SPC may drive the light-emitting element ED by supplying a driving current to the light-emitting element ED at a predetermined timing. The light-emitting element ED may be driven by the driving current to emit light.

[0102] The plurality of transistors may include a driving transistor DT for driving the light emitting element ED and a scan transistor ST that is turned on or off according to a scan signal SC.

[0103] The driving transistor DT may supply a driving current to the light emitting element ED.

[0104] The scan transistor ST may be configured to control an electrical state of a corresponding node in the sub-pixel circuit SPC or to control a state or operation of the drive transistor DT.

[0105] The at least one capacitor may include a storage capacitor Cst for maintaining a constant voltage during a frame.

[0106] To drive the subpixel SP, a data signal VDATA as an image signal and a scan signal SC as a gate signal may be applied to the subpixel SP. In addition, to drive the subpixel SP, a common pixel driving voltage including a driving voltage VDD and a base voltage VSS may be applied to the subpixel SP.

[0107] The light emitting element ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE. The intermediate layer EL may be disposed between the pixel electrode PE and the common electrode CE.

[0108] For example, the pixel electrode PE may be an electrode provided in each sub-pixel SP, and the common electrode CE may be an electrode commonly provided in all sub-pixels SP. For example, the pixel electrode PE may be an anode, and the common electrode CE may be a cathode. As another example, the pixel electrode PE may be a cathode, and the common electrode CE may be an anode. For ease of description, an example is described in which the pixel electrode PE is an anode and the common electrode CE is a cathode.

[0109] When the light-emitting element ED is an organic light-emitting element, the intermediate layer EL may include a light-emitting layer EML, a first common intermediate layer COM1 located between the pixel electrode PE and the light-emitting layer EML, and a second common intermediate layer COM2 located between the light-emitting layer EML and the common electrode CE. The first common intermediate layer COM1 and the second common intermediate layer COM2 may be collectively referred to as a common intermediate layer EL_COM.

[0110] A light emitting layer EML may be provided for each sub-pixel SP. A common intermediate layer EL_COM may be commonly provided over the plurality of sub-pixels SP, but exemplary embodiments of the present disclosure are not limited thereto.

[0111] A light emitting layer EML may be provided for each light emitting region, and a common intermediate layer EL_COM may be provided across a plurality of light emitting regions and non-light emitting regions, but exemplary embodiments of the present disclosure are not limited thereto.

[0112] For example, the first common intermediate layer COM1 may include a hole injection layer HIL, an electron blocking layer EBL, and a hole transport layer HTL, but exemplary embodiments of the present disclosure are not limited thereto. The second common intermediate layer COM2 may include an electron transport layer ETL, a hole blocking layer HBL, and an electron injection layer EIL, but exemplary embodiments of the present disclosure are not limited thereto.

[0113] The hole injection layer can inject holes from the pixel electrode PE into the hole transport layer, and the hole transport layer can transport holes to the emission layer EML. The electron injection layer can inject electrons from the common electrode CE into the electron transport layer, and the electron transport layer can transport electrons to the emission layer EML.

[0114] For example, the common electrode CE can be electrically connected to a base voltage line VSSL. The base voltage VSS is a type of common pixel drive voltage that can be applied to the common electrode CE via the base voltage line VSSL. The pixel electrode PE can be electrically connected directly or indirectly (via another transistor) to the first node N1 of the drive transistor DT of each sub-pixel SP. In the present disclosure, the "base voltage VSS" may also be referred to as a "low-potential power voltage" or "low-potential voltage", and the "base voltage line VSSL" may also be referred to as a "low-potential power voltage line" or "low-potential voltage line".

[0115] Each light-emitting element ED may include a portion where the pixel electrode PE, the light-emitting layer in the intermediate layer LE, and the common electrode CE overlap. Each light-emitting element ED may form a predetermined light-emitting region. For example, the light-emitting region of each light-emitting element ED may include an overlapping region where the pixel electrode PE, the intermediate layer EL, and the common electrode CE overlap.

[0116] For example, the light-emitting element ED may be an organic light-emitting diode (OLED), an inorganic light-emitting diode (LED), a quantum dot light-emitting element, a micro-LED, or a mini-LED, but exemplary embodiments of the present disclosure are not limited thereto. For example, when the light-emitting element ED is an organic light-emitting diode (OLED), the intermediate layer EL of the light-emitting element ED may include an intermediate layer EL including an organic material.

[0117] The driving transistor DT may be a driving transistor for supplying a driving current to the light emitting element ED. The driving transistor DT may be connected between the driving voltage line VDDL and the light emitting element ED.

[0118] The driving transistor DT may include a first node N1, a second node N2, and a third node N3. The first node N1 may be electrically connected to the light emitting element ED, the second node N2 may receive a data signal VDATA, and the third node N3 may receive a driving voltage VDD from a driving voltage line VDDL. The driving transistor DT may be connected to the first node N1 and the third node N3.

[0119] In the driving transistor DT, the second node N2 may be a gate node, the first node N1 may be a source node or a drain node, and the third node N3 may be a drain node or a source node. Hereinafter, for convenience of description, an example is described in which the second node N2 may be a gate node, the first node N1 may be a source node, and the third node N3 may be a drain node in the driving transistor DT, but exemplary embodiments of the present disclosure are not limited thereto.

[0120] Figure 2The scan transistor ST shown included in the sub-pixel circuit SPC may be a switching transistor for transmitting the data signal VDATA, which is an image signal, to the second node N2, which is a gate node of the driving transistor DT.

[0121] The scan transistor ST can be controlled to be turned on and off by a scan signal SC, which is a gate signal applied via a scan line / scan signal line SCL, which is a type of gate line GL, to control electrical connection between the second node N2 of the drive transistor DT and the data line DL. A drain electrode or a source electrode of the scan transistor ST can be electrically connected to the data line DL, a source electrode or a drain electrode of the scan transistor ST can be electrically connected to the second node N2 of the drive transistor DT, and a gate electrode of the scan transistor ST can be electrically connected to the scan line / scan signal line SCL.

[0122] The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the driving transistor DT. The storage capacitor Cst may include a first capacitor electrode electrically connected to or corresponding to the first node N1 of the driving transistor DT, and a second capacitor electrode electrically connected to or corresponding to the second node N2 of the driving transistor DT.

[0123] The capacitor Cst may be an external capacitor intentionally designed outside the driving transistor DT, rather than a parasitic capacitor (eg, Cgs or Cgd) as an internal capacitor that may exist between the first and second nodes N1 and N2 of the driving transistor DT, but exemplary embodiments of the present disclosure are not limited thereto.

[0124] Each of the driving transistor DT and the scanning transistor ST may be an n-type transistor or a p-type transistor, but exemplary embodiments of the present disclosure are not limited thereto. For example, each of the driving transistor DT and the scanning transistor ST may be an n-type transistor or a p-type transistor.

[0125] The display panel 110 may have a top emission structure or a bottom emission structure.

[0126] When the display panel 110 has a top emission structure, at least a portion of the sub-pixel circuit SPC may vertically overlap at least a portion of the light emitting element ED, thereby increasing the area of ​​the light emitting region and the aperture ratio.

[0127] When the display panel 110 has a bottom emission structure, the sub-pixel circuit SPC may not overlap with the light emitting element ED in a vertical direction.

[0128] like Figure 2As shown, the sub-pixel circuit SPC may have a 2T (transistor) 1C (capacitor) structure including two transistors DT and ST and one capacitor Cst. In some cases, the sub-pixel circuit SPC may further include one or more transistors or one or more capacitors.

[0129] For example, the sub-pixel circuit SPC may have an 8T1C structure including eight transistors and one capacitor. As another example, the sub-pixel circuit SPC may have a 6T2C structure including six transistors and two capacitors. As another example, the sub-pixel circuit SPC may have a 7T1C structure including seven transistors and one capacitor. Exemplary embodiments of the present disclosure are not limited thereto.

[0130] The transistor may be a thin film transistor (TFT), and the active layer of the thin film transistor (TFT) may be formed of a semiconductor material, such as an oxide semiconductor, an amorphous semiconductor, or a polycrystalline semiconductor, but is not limited thereto.

[0131] Oxide semiconductor materials can have excellent effects in preventing leakage current and relatively cheap manufacturing costs. Oxide semiconductors can be made of metal oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn) and titanium (Ti) or combinations of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn) or titanium (Ti) and their oxides. Specifically, oxide semiconductors can include zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO) and indium gallium oxide (IGO), but are not limited thereto.

[0132] Polycrystalline semiconductor materials have a fast moving speed of carriers such as electrons and holes, and thus have high mobility, low power consumption, and excellent reliability. Polycrystalline semiconductors may be made of polycrystalline silicon (poly-Si), but are not limited thereto.

[0133] The amorphous semiconductor material may be made of amorphous silicon (a-Si), but is not limited thereto.

[0134] The type and number of gate lines or gate signals supplied to the subpixels SP may differ according to the structure of the subpixel circuit SPC. In addition, the type and number of common pixel driving voltages supplied to the subpixels SP may differ according to the structure of the subpixel circuit SPC.

[0135] Since the circuit elements in each sub-pixel SP (e.g., the light-emitting element ED implemented as an organic light-emitting diode (OLED) including an organic material) are susceptible to external moisture or oxygen, an encapsulation layer 200 may be provided on the display panel 110. The encapsulation layer 200 may prevent external moisture or oxygen from penetrating into the circuit elements (e.g., the light-emitting element ED). The encapsulation layer 200 may be configured in various forms so that the light-emitting element ED is not exposed to moisture or oxygen. For example, the encapsulation layer 200 may be composed of two or more layers in which organic films and inorganic films are alternately stacked, but exemplary embodiments of the present disclosure are not limited thereto.

[0136] Reference Figure 2 According to an exemplary embodiment of the present disclosure, a display device 100 may include: a touch sensor layer 210, which includes a plurality of sensor electrodes to sense a user's touch; a touch drive circuit 220, which is configured to sense the plurality of sensor electrodes; and a touch controller 230, which is configured to use the sensing result (touch sensing data) of the touch drive circuit 220 to determine whether there is a touch or touch coordinates.

[0137] The touch sensor layer 210 may be embedded in the display panel 110. For example, the touch sensor layer 210 may be provided on the encapsulation layer 200 in the display panel 110. The touch sensor layer 210 may be a touch portion.

[0138] The display panel 110 may further include a plurality of touch pads TP electrically connected to the touch driving circuit 220 and a plurality of touch routing lines for electrically connecting the plurality of sensor electrodes included in the touch sensor layer 210 to the plurality of touch pads TP connected to the touch driving circuit 220 .

[0139] Figure 3 is a cross-sectional view illustrating a display panel according to an exemplary embodiment of the present disclosure.

[0140] Reference Figure 3 , the display panel 110 according to the exemplary embodiment of the present disclosure may include a transistor part, a light emitting element part, and a packaging part, but the exemplary embodiment of the present disclosure is not limited thereto.

[0141] The substrate 111 may include a single layer or multiple layers. For example, the substrate may include a flexible polymer film. For example, the flexible polymer film may be made of any one of polyimide (PI), polyethylene terephthalate (PET), acrylonitrile butadiene styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polycarbonate (PC), polyethersulfone (PES), polyarylate (PAR), polysulfone (PSF), cyclic olefin copolymer (COC), triacetyl cellulose (TAC), polyvinyl alcohol (PVA) and polystyrene (PS), and the present disclosure is not limited thereto. When the substrate 111 includes multiple layers, the substrate 111 may include a first substrate 301, an intermediate layer 302 and a second substrate 303. The intermediate layer 302 may be positioned between the first substrate 301 and the second substrate 303. For example, each of the first substrate 301 and the second substrate 303 may be a polyimide (PI) layer, but exemplary embodiments of the present disclosure are not limited thereto. The intermediate layer 302 may be an inorganic insulating layer, but the exemplary embodiments of the present disclosure are not limited thereto. When charges are charged to the first substrate PI1 as a polyimide layer, the intermediate layer 302 may prevent the charges from affecting transistors provided on the second substrate 303 through the second substrate 303 as a polyimide layer.

[0142] In addition, the intermediate layer 302 can prevent moisture components from penetrating upwardly through the first substrate 301. For example, the intermediate layer 302 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof, or may be formed of a double layer of silicon oxide (SiO2) and silicon nitride (SiNx), but is not limited thereto.

[0143] The transistor part may include a substrate 111 , insulating layers 311 , 312 , 313 , 321 , 322 , and 323 on the substrate 111 , thin film transistors TFT1 and TFT2 , a storage capacitor Cst, and various electrodes or signal lines.

[0144] The thin film transistors TFT1 and TFT2 included in the transistor part may include a first thin film transistor TFT1 and a second thin film transistor TFT2 .

[0145] The first thin-film transistor TFT1 may include a first active layer ACT1, a first electrode E1a, a second electrode E1b, and a third electrode E1c. The first active layer ACT1 may be a first semiconductor layer, but exemplary embodiments of the present disclosure are not limited thereto. For example, the first active layer ACT1 may be formed of an oxide semiconductor, amorphous silicon, polycrystalline silicon, or low-temperature polycrystalline silicon (LTPS), but exemplary embodiments of the present disclosure are not limited thereto. The first thin-film transistor TFT1 may be implemented as a p-channel thin-film transistor or an n-channel thin-film transistor, but exemplary embodiments of the present disclosure are not limited thereto.

[0146] The first electrode E1a may be a gate electrode, the second electrode E1b may be a source electrode or a drain electrode, and the third electrode E1c may be a drain electrode or a source electrode. Hereinafter, for ease of description, the first electrode E1a is referred to as a first gate electrode E1a, the second electrode E1b is referred to as a first source electrode E1b, and the third electrode E1c is referred to as a first drain electrode E1c, but exemplary embodiments of the present disclosure are not limited thereto.

[0147] The second thin film transistor TFT2 may include a second active layer ACT2, a fourth electrode E2a, a fifth electrode E2b, and a sixth electrode E2c. The second active layer ACT2 may be a second semiconductor layer, but exemplary embodiments of the present disclosure are not limited thereto. For example, the second active layer ACT2 may be formed of an oxide semiconductor, amorphous silicon, polycrystalline silicon, or low-temperature polycrystalline silicon (LTPS), but exemplary embodiments of the present disclosure are not limited thereto. The second thin film transistor TFT2 may be implemented as a p-channel thin film transistor or an n-channel thin film transistor, but exemplary embodiments of the present disclosure are not limited thereto.

[0148] For example, one of the first thin film transistor TFT1 and the second thin film transistor TFT2 may include an oxide semiconductor as an active layer. As another example, one of the first thin film transistor TFT1 and the second thin film transistor TFT2 may use low-temperature polysilicon as an active layer. As another example, the first thin film transistor TFT1 and the second thin film transistor TFT2 may be configured with an oxide semiconductor as an active layer. As another example, the first thin film transistor TFT1 and the second thin film transistor TFT2 may be configured with low-temperature polysilicon as an active layer. As another example, in the first thin film transistor TFT1 and the second thin film transistor TFT2, the drive transistor DT may be configured with an oxide semiconductor as an active layer, and the scan transistor ST may be configured with low-temperature polysilicon as an active layer. As another example, in the first thin film transistor TFT1 and the second thin film transistor TFT2, the drive transistor DT may be configured with low-temperature polysilicon as an active layer, and the scan transistor ST may be configured with an oxide semiconductor as an active layer. As another example, the transistors included in the gate-in-panel (GIP) type gate drive circuit 130 may be configured with an oxide semiconductor or low-temperature polysilicon as an active layer. As another example, all transistors configured on the substrate 111 and transistors included in the gate driving circuit 130 of a gate in panel (GIP) type may be configured with an oxide semiconductor as an active layer.

[0149] The fourth electrode E2a may be a gate electrode, the fifth electrode E2b may be a source electrode or a drain electrode, and the sixth electrode E2c may be a drain electrode or a source electrode. Hereinafter, for ease of description, the fourth electrode E2a is referred to as a second gate electrode E2a, the fifth electrode E2b is referred to as a second source electrode E2b, and the sixth electrode E2c is referred to as a second drain electrode E2c. However, exemplary embodiments of the present disclosure are not limited thereto.

[0150] The second active layer ACT2 of the second thin film transistor TFT2 may be located at a higher position from the substrate 111 than the first active layer ACT1 of the first thin film transistor TFT1 .

[0151] The first buffer layer 311 may be disposed below the first active layer ACT1 of the first thin film transistor TFT1, and the second buffer layer 321 may be disposed below the second active layer ACT2 of the second thin film transistor TFT2. For example, the first active layer ACT1 of the first thin film transistor TFT1 may be positioned on the first buffer layer 311, and the second active layer ACT2 of the second thin film transistor TFT2 may be positioned on the second buffer layer 321. The second buffer layer 321 may be positioned higher than the first buffer layer 311.

[0152] For example, the first buffer layer 311 may be formed by a single-layer or multi-layer inorganic film. For example, the single-layer inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multi-layer inorganic film may be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto. However, depending on the structure or characteristics of the display device, the first buffer layer 311 may not be included.

[0153] For example, the second buffer layer 321 may be formed by a single-layer or multi-layer inorganic film. For example, the single-layer inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multi-layer inorganic film may be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto. However, depending on the structure or characteristics of the display device, the second buffer layer 321 may not be included.

[0154] The storage capacitor Cst may be provided in various metal layers in the display panel 110. For example, the storage capacitor Cst may include a first capacitor electrode CAPE1 and a second capacitor electrode CAPE2.

[0155] The light emitting element portion may include a plurality of light emitting elements ED disposed on at least one planarization layer 331 and 332. Each of the plurality of light emitting elements ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE. However, the present disclosure is not limited thereto.

[0156] The encapsulation portion may include an encapsulation layer 200 located on the plurality of light emitting elements ED. The encapsulation layer 200 may be a single layer or multiple layers, but the exemplary embodiments of the present disclosure are not limited thereto. In addition to the encapsulation layer 200, the encapsulation portion may further include a dam DAM.

[0157] In the following, reference is made to Figure 3 The structure of the display panel 110 according to an exemplary embodiment of the present disclosure, for example, a vertical structure, is described in more detail.

[0158] Reference Figure 3 , a first buffer layer 311 may be provided on the substrate 111. The first buffer layer 311 may be a single layer or a plurality of layers, but exemplary embodiments of the present disclosure are not limited thereto. When the first buffer layer 311 includes a plurality of layers, the first buffer layer 311 may include a first sub-buffer layer 311a and a second sub-buffer layer 311b.

[0159] The first active layer ACT1 of the first thin film transistor TFT1 may be disposed on the first buffer layer 311. The first active layer ACT1 may include a channel region in which a channel is formed, a source connection region on one side of the channel region, and a drain connection region on the other side of the channel region.

[0160] The first insulating layer 312 may be disposed on the first active layer ACT1 of the first thin film transistor TFT1. The first gate electrode E1a of the first thin film transistor TFT1 may be disposed on the first insulating layer 312. The second insulating layer 313 may be disposed on the first gate electrode E1a of the first thin film transistor TFT1. The first insulating layer 312 may be a gate insulating layer, but exemplary embodiments of the present disclosure are not limited thereto. The first insulating layer 312 may be formed as a single layer made of an inorganic material or as a multilayer made of different inorganic materials. For example, the first insulating layer 312 may be formed as a single layer of any one of a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, and a silicon oxynitride (SiON) film, or as a multilayer thereof. For example, the first insulating layer 312 may be formed by a single layer or multiple layers of an inorganic film. For example, the single layer of the inorganic film may be a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a silicon oxynitride (SiON) film, and the multilayer inorganic film may be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of silicon oxynitride (SiON) film and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto. The second insulating layer 313 may be an interlayer insulating layer, but the exemplary embodiments of the present disclosure are not limited thereto. The second insulating layer 313 may be formed as a single layer made of an inorganic material or as a multilayer made of different inorganic materials. For example, the second insulating layer 313 may be formed as a single layer of any one of a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, and a silicon oxynitride (SiON) film, or as a multilayer thereof. For example, the second insulating layer 313 can be formed by a single-layer or multi-layer inorganic film. For example, the single-layer inorganic film can be a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a silicon oxynitride (SiON) film, and the multi-layer inorganic film can be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of silicon oxynitride (SiON) film and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto.

[0161] The second buffer layer 321 may be disposed on the second insulating layer 313 .

[0162] The second active layer ACT2 of the second thin film transistor TFT2 may be disposed on the second buffer layer 321. The second active layer ACT2 may include a channel region in which a channel is formed, a source connection region on one side of the channel region, and a drain connection region on the other side of the channel region.

[0163] The third insulating layer 322 may be provided on the second active layer ACT2 of the second thin film transistor TFT2. A second gate electrode E2a of the second thin film transistor TFT2 may be provided. A fourth insulating layer 323 may be provided on the second gate electrode E2a of the second thin film transistor TFT2. The third insulating layer 322 may be a gate insulating layer, but the exemplary embodiments of the present disclosure are not limited thereto. The third insulating layer 322 may be formed as a single layer made of an inorganic material or as a multilayer made of different inorganic materials. For example, the third insulating layer 322 may be formed as a single layer of any one of a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, and a silicon oxynitride (SiON) film, or as a multilayer thereof. For example, the third insulating layer 322 may be formed by a single layer or multiple layers of an inorganic film. For example, the single layer of the inorganic film may be a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a silicon oxynitride (SiON) film, and the multilayer inorganic film may be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of silicon oxynitride (SiON) film and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto. The fourth insulating layer 323 may be an interlayer insulating layer, but the exemplary embodiments of the present disclosure are not limited thereto. The fourth insulating layer 323 may be formed as a single layer made of an inorganic material or as a multilayer made of different inorganic materials. For example, the fourth insulating layer 323 may be formed as a single layer of any one of a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, and a silicon oxynitride (SiON) film, or as a multilayer thereof. For example, the fourth insulating layer 323 can be formed by a single-layer or multi-layer inorganic film. For example, the single-layer inorganic film can be a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a silicon oxynitride (SiON) film, and the multi-layer inorganic film can be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of silicon oxynitride (SiON) film and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto.

[0164] The first source electrode E1 b and the first drain electrode E1 c of the first thin film transistor TFT1 , and the second source electrode E2 b and the second drain electrode E2 c of the second thin film transistor TFT2 may be disposed on the fourth insulating layer 323 .

[0165] The first source electrode E1b and the first drain electrode E1c of the first thin film transistor TFT1 may be respectively connected to the source connection region and the drain connection region of the first active layer ACT1 through the holes of the fourth insulating layer 323 , the third insulating layer 322 , the second buffer layer 321 , the second insulating layer 313 and the first insulating layer 312 .

[0166] The second source electrode E2 b and the second drain electrode E2 c of the second thin film transistor TFT2 may be connected to the source connection region and the drain connection region of the second active layer ACT2 through the holes of the fourth insulating layer 323 and the third insulating layer 322 , respectively.

[0167] The first source electrode E1b and the first drain electrode E1c of the first thin film transistor TFT1, and the second source electrode E2b and the second drain electrode E2c of the second thin film transistor TFT2 may include a first metal and may be provided in a first metal layer. Here, the first metal and the first metal layer may be referred to as a first source-drain metal and a first source-drain metal layer.

[0168] For example, refer to Figure 3 The storage capacitor Cst may be formed of a first capacitor electrode CAPE1 and a second capacitor electrode CAPE2. In some cases, the storage capacitor Cst may be formed of three or more capacitor electrodes. In some cases, the storage capacitor Cst may have a form in which two or more capacitors are connected in parallel.

[0169] Each of the first capacitor electrode CAPE1 and the second capacitor electrode CAPE2 may be disposed on various metal layers provided in the display panel 110 .

[0170] For example, the first capacitor electrode CAPE1 may include the same first gate metal as the first gate electrode E1a of the first thin-film transistor TFT1 on the first insulating layer 312 and may be provided in the first gate metal layer, but exemplary embodiments of the present disclosure are not limited thereto. For example, the first capacitor electrode CAPE1 and the first gate electrode E1a of the first thin-film transistor TFT1 may be formed on different layers; for example, the first capacitor electrode CAPE1 and the first gate electrode E1a of the first thin-film transistor TFT1 may include different materials.

[0171] For example, the second capacitor electrode CAPE2 may be disposed on the second insulating layer 313 .

[0172] The second source electrode E2 b of the second thin film transistor TFT2 may be electrically connected to the second capacitor electrode CAPE2 through the hole of the fourth insulating layer 323 , the third insulating layer 322 , and the second buffer layer 321 .

[0173] For example, the first thin film transistor TFT1 may be Figure 2 The scanning transistor ST, and the second thin film transistor TFT2 may be Figure 2 The driving transistor DT.

[0174] The transistor portion may further include metal layers MP1 and MP2. For example, the first metal layer MP1 may be disposed between the first sub-buffer layer 311a and the second sub-buffer layer 311b included in the first buffer layer 311, but exemplary embodiments of the present disclosure are not limited thereto. The second metal layer MP2 may include the same first gate metal as the first gate electrode E1a of the first thin-film transistor TFT1 and may be disposed in the first gate metal layer, but exemplary embodiments of the present disclosure are not limited thereto. For example, the second metal layer MP2 and the first gate electrode E1a of the first thin-film transistor TFT1 may be formed on different layers; for example, the second metal layer MP2 and the first gate electrode E1a of the first thin-film transistor TFT1 may include different materials. The first metal layer MP1 may be a first metal pattern, and the second metal layer MP2 may be a second metal pattern, but exemplary embodiments of the present disclosure are not limited thereto. Furthermore, the first metal layer MP1 and the second metal layer MP2 may include the same or different materials.

[0175] Each of the first metal layer MP1 and the second metal layer MP2 may be disposed in the display area AA or the non-display area NA.

[0176] Reference Figure 3 The transistor portion may further include a first shield metal BSM1 disposed on the substrate 111. The first shield metal BSM1 may overlap the first active layer ACT1 of the first thin-film transistor TFT1. The first shield metal BSM1 may be disposed below the first active layer ACT1 of the first thin-film transistor TFT1. For example, the first shield metal BSM1 may be disposed between the substrate 111 and the first buffer layer 311, or between the first sub-buffer layer 311a and the second sub-buffer layer 311b.

[0177] The transistor portion may further include a second barrier metal BSM2 disposed on the substrate 111. The second barrier metal BSM2 may overlap with the second active layer ACT2 of the second thin film transistor TFT2. The second barrier metal BSM2 may be disposed under the second active layer ACT2 of the second thin film transistor TFT2.

[0178] For example, the second barrier metal BSM2 may be disposed in a metal layer between the second insulating layer 313 and the second buffer layer 321. The second barrier metal BSM2 may be disposed in the same metal layer as the second capacitor electrode CAPE2, but exemplary embodiments of the present disclosure are not limited thereto.

[0179] As another example, the second barrier metal BSM2 may be provided in the same first gate metal layer as the first gate electrode E1a of the first thin film transistor TFT1. Figure 3The transistor portion may further include a common drive voltage layer CVP to which a common drive voltage is applied. For example, the common drive voltage applied to the common drive voltage layer CVP may also be referred to as a power signal and may be a drive voltage VDD or a base voltage VSS. The drive voltage VDD may be referred to as a high-potential power supply voltage (a high-potential power supply signal or a high-potential voltage), and the base voltage VSS may be referred to as a low-potential power supply voltage (a low-potential power supply signal or a low-potential voltage).

[0180] The common driving voltage layer CVP may be disposed in the display area AA or the non-display area NA.

[0181] At least one planarization layer may be provided on the first thin film transistor TFT1 and the second thin film transistor TFT2. Figure 3 In the example, two planarization layers 331 and 332 are provided on the first and second thin film transistors TFT1 and TFT2. In some cases, three or more planarization layers may be provided on the first and second thin film transistors TFT1 and TFT2, but exemplary embodiments of the present disclosure are not limited thereto.

[0182] Reference Figure 3 The first planarization layer 331 may be disposed on the first source electrode E1b and the first drain electrode E1c of the first thin-film transistor TFT1, and the second source electrode E2b and the second drain electrode E2c of the second thin-film transistor TFT2. For example, the first planarization layer 331 may be disposed on the first thin-film transistor TFT1 and the second thin-film transistor TFT2. For example, the first planarization layer 331 may be disposed to cover both the first thin-film transistor TFT1 and the second thin-film transistor TFT2.

[0183] Reference Figure 3 A relay electrode RE may be provided on the first planarization layer 115 a . The relay electrode RE may electrically connect the second source electrode E2 b of the second thin film transistor TFT2 to the pixel electrode PE.

[0184] The relay electrode RE may be electrically connected to the second source electrode E2b of the second thin film transistor TFT2 through the hole of the first planarization layer 331. The second source electrode E2b of the second thin film transistor TFT2 may be electrically connected to the second capacitor electrode CAPE2 of the storage capacitor Cst.

[0185] The relay electrode RE may be provided in a second metal layer on the first planarization layer 331 and may include a second metal. The second metal and the second metal layer may be referred to as a second source-drain metal and a second source-drain metal layer.

[0186] The second planarization layer 332 may be disposed on the relay electrode RE.

[0187] Reference Figure 3 The light emitting element portion may be disposed on the second planarization layer 332. A light emitting element ED may be formed on the second planarization layer 332. The light emitting element ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE. A light emitting region of the light emitting element ED may be formed in a region where the pixel electrode PE, the intermediate layer EL, and the common electrode CE overlap and contact each other.

[0188] The pixel electrode PE may be disposed on the second planarization layer 332. The pixel electrode PE may be electrically connected to the relay electrode RE through the hole of the second planarization layer 332.

[0189] A bank 333 may be provided on the pixel electrode PE. The bank 333 may be provided at the boundary between the multiple sub-pixels SP and suppress color mixing of the light beams from the multiple sub-pixels SP. The bank 333 may cover the edge of the pixel electrode PE and may be formed to expose a portion of the pixel electrode PE. Thus, the bank 333 can prevent current from concentrating at the end of the pixel electrode PE, thereby preventing degradation of luminous efficiency. The opening of the bank 333 may expose a portion of the pixel electrode PE to form a light-emitting area. For example, the opening of the bank 333 may overlap a portion of the pixel electrode PE. The bank 333 may be formed of a material including black pigment or an organic material such as benzocyclobutene resin, polyimide resin, acrylic resin, or photosensitive polymer, but exemplary embodiments of the present disclosure are not limited thereto. When the bank 333 is formed of a material including black pigment, black dye, or the like, it may be a black bank. When the bank 333 is formed of a material including black pigment or black dye, it can block external light or light reflected from the outside, thereby further enhancing the brightness of the display device.

[0190] The intermediate layer EL of the light emitting element ED may be disposed on the bank 333 and a portion of the pixel electrode PE. The common electrode CE may be disposed on the intermediate layer EL.

[0191] Reference Figure 3 The encapsulation portion may be provided on the light emitting element portion and may be positioned on the common electrode CE. The encapsulation portion may include an encapsulation layer 200 formed on the common electrode CE.

[0192] The encapsulation layer 200 can prevent moisture or oxygen from penetrating into the light-emitting element ED. For example, the encapsulation layer 200 can prevent moisture or oxygen from penetrating into the organic material included in the intermediate layer EL of the light-emitting element ED. The encapsulation layer 200 can be formed of a single layer or a plurality of layers, but the exemplary embodiments of the present disclosure are not limited thereto.

[0193] For example, refer to Figure 3The encapsulation layer 200 may include a first encapsulation layer 341, a second encapsulation layer 342, and a third encapsulation layer 343, but exemplary embodiments of the present disclosure are not limited thereto. For example, the first encapsulation layer 341 and the third encapsulation layer 343 may include an inorganic layer, and the second encapsulation layer 342 may include an organic layer, but exemplary embodiments of the present disclosure are not limited thereto.

[0194] The first encapsulation layer 341 and the third encapsulation layer 343 may be formed of an inorganic insulating material capable of low temperature deposition, such as silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiON), or aluminum oxide (Al2O3). Since the first encapsulation layer 341 and the third encapsulation layer 343 are deposited in a low-temperature atmosphere, the light-emitting element ED, which is weak to high-temperature atmospheres, can be prevented from being damaged during the deposition process of the first encapsulation layer 341 and the third encapsulation layer 343.

[0195] The second encapsulation layer 342 may have a buffering function for reducing stress between layers caused by bending of the display device and may flatten steps between layers. The second encapsulation layer 342 may be formed on the substrate formed with the first encapsulation layer 341 using a non-photosensitive organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyethylene, or silicon oxycarbide (SiOC), or a photosensitive organic insulating material such as photoacryl, but is not limited thereto.

[0196] Alternatively, the encapsulation layer 200 may include a first inorganic encapsulation layer, a first organic encapsulation layer, a second inorganic encapsulation layer, a second organic encapsulation layer, and a third inorganic encapsulation layer that are sequentially stacked.

[0197] The first inorganic encapsulation layer, the second inorganic encapsulation layer, and the third inorganic encapsulation layer can be used to block the penetration of moisture or oxygen. The first inorganic encapsulation layer, the second inorganic encapsulation layer, and the third inorganic encapsulation layer can be made of an inorganic material, for example, an inorganic material such as silicon nitride (SiNx), silicon oxide (SiOx), or aluminum oxide (AlOx). However, the present disclosure is not limited thereto.

[0198] The first organic encapsulation layer is disposed between the first inorganic encapsulation layer and the second inorganic encapsulation layer, and the second organic encapsulation layer is disposed between the second inorganic encapsulation layer and the third inorganic encapsulation layer. The first organic encapsulation layer and the second organic encapsulation layer may each have a thickness greater than that of each of the first inorganic encapsulation layer, the second inorganic encapsulation layer, and the third inorganic encapsulation layer so as to adsorb or block particles that may be generated during the process of manufacturing the display device. The first organic encapsulation layer and the second organic encapsulation layer may fill cracks that may be formed in the first inorganic encapsulation layer and the second inorganic encapsulation layer. The first organic encapsulation layer and the second organic encapsulation layer may flatten the upper portion of the first inorganic encapsulation layer and the upper portion of the second inorganic encapsulation layer by covering the particles on the first inorganic encapsulation layer and the second inorganic encapsulation layer, respectively. For example, the first organic encapsulation layer may flatten the upper portion of the first inorganic encapsulation layer by covering the particles on the first inorganic encapsulation layer. For example, the second organic encapsulation layer may flatten the upper portion of the second inorganic encapsulation layer by covering the particles on the second inorganic encapsulation layer. The first organic encapsulation layer and the second organic encapsulation layer may be made of an organic material, and for example, epoxy polymers, acrylic polymers, etc. may be used. However, the present disclosure is not limited thereto.

[0199] In addition, the encapsulation layer 200 is not limited to three or five layers, and for example, may include n layers (where n is an integer greater than 3) in which inorganic encapsulation layers and organic encapsulation layers are alternately stacked.

[0200] The display panel 110 according to an exemplary embodiment of the present disclosure may have a built-in touch sensor. In this case, the display panel 110 according to an exemplary embodiment of the present disclosure may include a touch sensor layer 210 formed on the encapsulation layer 200. The touch sensor layer 210 may be a touch portion.

[0201] Reference Figure 3 The touch sensor layer 210 may include a plurality of touch electrodes TE, and may include a sensor metal TSM and a bridge metal BRG to form the plurality of touch electrodes TE. In an exemplary embodiment of the present disclosure, the sensor metal TSM may be referred to as a sensor metal layer TSM, and the bridge metal BRG may be referred to as a bridge metal layer BRG.

[0202] The touch sensor layer 210 may further include insulating layers such as a buffer layer 351 on the encapsulation layer 200, an interlayer insulating layer 352 on the buffer layer 351, and a protective layer 353 on the interlayer insulating layer 352. Here, the buffer layer 351 may be omitted.

[0203] The bridge metal BRG may be disposed between the buffer layer 351 and the interlayer insulating layer 352 . The sensor metal TSM may be disposed between the interlayer insulating layer 352 and the protection layer 353 .

[0204] Each of the plurality of touch electrodes TE may be formed of a sensor metal TSM. Each of the plurality of touch electrodes TE may be a mesh type electrode having a plurality of openings, but exemplary embodiments of the present disclosure are not limited thereto.

[0205] The plurality of touch electrodes TE may include a first touch electrode TE1 and a second touch electrode TE2. The sensor metal TSM included in the first touch electrode TE1 may be electrically connected by a bridge metal BRG. For example, the sensor metal TSM spaced apart from each other may be electrically connected by a bridge metal BRG to form one first touch electrode TE1.

[0206] A bridge metal BRG may be provided on the buffer layer 351. An interlayer insulating layer 352 may be provided on the bridge metal BRG. A sensor metal TSM may be provided on the interlayer insulating layer 352. A portion of the sensor metal TSM may be connected to a corresponding bridge metal BRG through a hole of the interlayer insulating layer 352.

[0207] Reference Figure 3 , the sensor metal TSM and the bridge metal BRG may be disposed so as not to overlap with the light emitting element ED. The sensor metal TSM and the bridge metal BRG may overlap with the bank 333. However, the present disclosure is not limited thereto.

[0208] A plurality of sensor metals TSM may constitute a touch electrode TE. A plurality of sensor metals TSM may be arranged in a grid form and electrically connected to each other. A portion of the sensor metal TSM may be electrically connected to another portion of the sensor metal TSM via a bridge metal BRG to constitute a touch electrode TE.

[0209] The protection layer 353 may be disposed on the sensor metal TSM and the bridge metal BRG. The protection layer 353 may be disposed to cover both the sensor metal TSM and the bridge metal BRG.

[0210] Reference Figure 3 The touch line TL may electrically connect the touch electrode TE and the touch pad TP. The touch line TL may be formed of at least one of a sensor metal TSM and a bridge metal BRG, but exemplary embodiments of the present disclosure are not limited thereto. For example, the touch line TL may be formed of a material different from the sensor metal TSM and the bridge metal BRG.

[0211] When the display panel 110 is a touch sensor embedded type, the touch line TL may extend along the outer slope SLP_ENCAP of the encapsulation layer 200 and may extend beyond the upper portion of the dam DAM to reach the pad TP in the non-display area NA.

[0212] Figure 4is an exemplary plan view illustrating a display device 100 according to an exemplary embodiment of the present disclosure.

[0213] Reference Figure 4 , the substrate 111 may include a display area AA and a non-display area NA.

[0214] The display area AA may display an image through a plurality of sub-pixels SP.

[0215] The non-display area NA may be located around the display area AA, or may partially or completely surround the display area AA. The non-display area NA may be an area adjacent to the display area AA. Furthermore, the non-display area NA may be an area adjacent to the display area AA and configured to surround the display area AA. However, the present disclosure is not limited thereto.

[0216] For example, the non-display area NA may include a first non-display area located outside the display area AA along a first direction, a second non-display area located outside the display area AA along a second direction intersecting the first direction, a third non-display area located outside the display area AA along a direction opposite to the first direction, and a fourth non-display area located outside the display area AA along a direction opposite to the second direction.

[0217] For another example, the boundary area between the display area AA and the non-display area NA may be curved so that the non-display area NA is located below the display area. In this case, when a user views the display device from the front, little or no non-display area NA may be visible to the user.

[0218] The non-display area NA may include a bending area BA and a pad area PA. The bending area BA may be provided on one side of the display area AA. The pad area PA may be provided on one side of the bending area BA. The bending area BA may be an area where the substrate 111 can be bent. The bending area BA may be positioned between the data driving circuit 120 and the display area AA.

[0219] The data driving circuit 120 and the gate driving circuits 130 a and 130 b may be disposed in the non-display area NA.

[0220] The data driving circuit 120 may be provided in the form of a chip on panel (COP) on the substrate 111. The data driving circuit 120 may be electrically connected to the display panel 110 through the data lines DL.

[0221] The gate drive circuits 130a and 130b may be disposed on the substrate 111. The gate drive circuits 130a and 130b may be of a GIP type disposed within the display panel. The gate drive circuits 130a and 130b may be disposed on the substrate 111 at the left and right ends of the display area AA. For example, the gate drive circuit 130a may be disposed on the substrate 111 at the left end of the display area AA, while the gate drive circuit 130b may be disposed on the substrate 111 at the right end of the display area AA. For example, the gate drive circuit 130a may be disposed on the substrate 111 at the right end of the display area AA, while the gate drive circuit 130b may be disposed on the substrate 111 at the left end of the display area AA. For example, both the gate drive circuits 130a and 130b may be disposed on the substrate 111 at the left or right end of the display area AA. However, exemplary embodiments of the present disclosure are not limited thereto.

[0222] The gate driving circuits 130a and 130b may be electrically connected to the sub-pixels disposed in the display area AA through the gate lines GL. A plurality of gate lines GL may be disposed to cross a plurality of data lines DL, but exemplary embodiments of the present disclosure are not limited thereto.

[0223] The plurality of gate lines GL may be scan signal lines SCL, sensing signal lines SENL, and emission control lines ECL.

[0224] When the gate line GL is a scanning signal line SCL, the scanning signal line SCL can be connected to Figure 2 The gate nodes of the scan transistors ST shown are electrically connected.

[0225] When the gate line GL is a sensing signal line SENL, the sensing signal line SENL may be electrically connected to a gate node of a sensing transistor. The sensing transistor may include a gate electrode. Figure 2 In the sub-pixel SP shown, the sensing transistor may be electrically connected to the first node N1.

[0226] When the gate line GL is the emission control line ECL, the emission control line ECL may be electrically connected to a gate node of the emission control transistor. When the sub-pixel SP is formed of 7T1C, 8T1C, etc., the emission control transistor may be included in the sub-pixel SP.

[0227] The display controller 140 may be provided on a printed circuit board PCB. The display controller 140 may control the data driving circuit 120 and the gate driving circuits 130 a and 130 b. The printed circuit board PCB may be coupled to one end of the substrate 111.

[0228] Figure 5 It shows Figure 4 An exemplary view of region X, Figure 6 It is along Figure 5An exemplary cross-sectional view taken along line AB in FIG.

[0229] Reference Figure 5 , the pad area PA of the display panel 110 may include a first pad area 400 provided in the non-display area NA and bonded to the data drive circuit 120, and a second pad area 430 provided in the non-display area NA and bonded to the flexible printed circuit. The first pad area 400 may be provided between the display area AA and the second pad area 430. The first pad area 400 may be an area provided in the non-display area NA and bonded to (or attached to) the data drive circuit 120. The first pad area 400 may be a drive circuit bonding pad area or a drive circuit attachment area, but exemplary embodiments of the present disclosure are not limited thereto. The second pad area 430 may be an area provided in the non-display area NA and bonded to (or attached to) the flexible printed circuit. The second pad area 430 may be a film bonding pad area or a film attachment area, but exemplary embodiments of the present disclosure are not limited thereto.

[0230] Reference Figure 5 , the pad area PA of the display panel 110 may include the first pad region 400 and the alignment key 440 disposed to be spaced apart from the first pad region 400 .

[0231] In the first pad region 400, pad electrodes 411 and 421 for inputting or outputting signals for driving the display panel 110 may be provided. The first pad region 400 may include a first sub-pad region 410 and a second sub-pad region 420. The first sub-pad region 410 may be provided between the display region AA and the second sub-pad region 420.

[0232] A pad electrode 411 for input / output of a signal for driving the display panel may be provided in the first sub-pad region 410. A pad electrode 421 for output or input of a signal for driving the display panel may be provided in the second sub-pad region 420.

[0233] The alignment mark 440 may be provided to be spaced apart from the first pad region 400 in the row direction, but the exemplary embodiments of the present disclosure are not limited thereto. In the process of bonding the data driving circuit 120 and the display panel 110, the alignment mark 440 may be used as an identification mark for identifying the position of the data driving circuit 120 or aligning the data driving circuit 120 and the display panel 110.

[0234] The alignment mark 440 may include a first alignment mark 441 and a second alignment mark 442. The first alignment mark 441 may be disposed to be spaced apart from the first sub-pad region 410. The second alignment mark 442 may be disposed to be spaced apart from the second sub-pad region 420. The alignment mark 440 may include a third alignment mark 443 disposed between the first alignment mark 441 and the second alignment mark 442.

[0235] Reference Figure 5 , a film pad electrode 431 for driving a signal input / output of the display panel may be provided in the second pad region 430 .

[0236] Reference Figure 5 , may include a data driving circuit 120 bonded (or attached) to the first pad region 400. The data driving circuit 120 may be disposed to overlap the first pad region 400 and the alignment mark 440. The alignment mark 440 may be disposed inside an edge of the data driving circuit 120, but exemplary embodiments of the present disclosure are not limited thereto.

[0237] Reference Figure 5 and Figure 6 , the pad area PA of the display panel 110 may be provided on the substrate 111. The pad area PA may include an insulating layer 450, pad electrodes 411 and 412, and an alignment key 440.

[0238] The insulating layer 450 may be provided with a plurality of insulating layers and may be provided on the substrate 111. The insulating layer 450 may be a layer including an inorganic material.

[0239] The insulating layer 450 may include a first insulating layer 451, a second insulating layer 452, a third insulating layer 453, a fourth insulating layer 454, and a fifth insulating layer 455, but exemplary embodiments of the present disclosure are not limited thereto. The first insulating layer 451, the second insulating layer 452, the third insulating layer 453, the fourth insulating layer 454, and the fifth insulating layer 455 may be inorganic insulating layers, but exemplary embodiments of the present disclosure are not limited thereto.

[0240] The first insulating layer 451 may be provided on the substrate 111. The second insulating layer 452 may be provided on the first insulating layer 451. The third insulating layer 453 may be provided on the second insulating layer 452. The fourth insulating layer 454 may be provided on the third insulating layer 453. The fifth insulating layer 455 may be provided on the fourth insulating layer 454. For example, the first insulating layer 451, the second insulating layer 452, the third insulating layer 453, the fourth insulating layer 454, and the fifth insulating layer 455 may be formed as a single layer or a multilayer of any one of a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, and a silicon oxynitride (SiON) film. However, the present disclosure is not limited thereto.

[0241] For example, the first insulating layer 451 may serve as a buffer layer corresponding to Figure 3 The first buffer layer 311 in the embodiment of the present disclosure is not limited thereto. The second insulating layer 452 may serve as an interlayer insulating layer corresponding to Figure 3 The second insulating layer 313 in the embodiment of the present disclosure is not limited thereto. The third insulating layer 453 may serve as an interlayer insulating layer corresponding to Figure 3 The fourth insulating layer 323 in the embodiment of the present disclosure is not limited thereto. The fourth insulating layer 454 may serve as a buffer layer corresponding to Figure 3 The buffer layer 351 in the embodiment of the present disclosure is not limited thereto. The fifth insulating layer 455 may serve as an interlayer insulating layer corresponding to Figure 3 The interlayer insulating layer 352 is formed in the embodiment of the present invention, but exemplary embodiments of the present disclosure are not limited thereto.

[0242] Reference Figure 5 and Figure 6 , a link line LL may be provided on the first insulating layer 451. The link line LL may be a line for transmitting a signal. For example, the link line LL may be a data line, a reference voltage line, etc., but exemplary embodiments of the present disclosure are not limited thereto.

[0243] Reference Figure 5 and Figure 6 , a pad electrode 411 may be provided on the substrate 111. The pad electrode 411 may be provided in the pad area PA of the insulating layer 450. The pad electrode 411 may include at least one metal layer. The pad electrode 411 may include a plurality of metal layers. The metal layer may include at least one metal layer.

[0244] The pad electrode 411 may include a first metal layer 411a, a second metal layer 411b, and a third metal layer 411c, but exemplary embodiments of the present disclosure are not limited thereto. The pad electrode 411 may be formed by disposing or stacking the first metal layer 411a, the second metal layer 411b, and the third metal layer 411c.

[0245] The first metal layer 411a may be disposed on the third insulating layer 453. The first metal layer 411a may be disposed to overlap with the link line LL. Figure 3The second electrode E1b and the third electrode E1c may be made of the same material, but the exemplary embodiments of the present disclosure are not limited thereto. For example, the first metal layer 411a may include a source electrode material and a drain electrode material, but the exemplary embodiments of the present disclosure are not limited thereto. For example, when the second electrode E1b and the third electrode E1c are formed, the first metal layer 411a may be formed together, but the exemplary embodiments of the present disclosure are not limited thereto. The first metal layer 411a may also include the same material as the source electrode material and the drain electrode material. Figure 3 The second electrode E1b and the third electrode E1c are made of different materials.

[0246] The second metal layer 411b may be disposed on the first metal layer 411a. For example, the second metal layer 411b may be disposed to cover the first metal layer 411a. The second metal layer 411b may be formed of Figure 3 The relay electrode RE is formed of the same material as the relay electrode RE, but the exemplary embodiment of the present disclosure is not limited thereto. When the relay electrode RE is formed, the second metal layer 411b may be formed together, but the exemplary embodiment of the present disclosure is not limited thereto. The second metal layer 411b may also be made of the same material as the relay electrode RE. Figure 3 The relay electrodes RE are formed of different materials.

[0247] The third metal layer 411c may be disposed on the second metal layer 411b. For example, the third metal layer 411c may be formed of the same material as the touch electrode TE, but exemplary embodiments of the present disclosure are not limited thereto. When forming the touch electrode TE, the third metal layer 411c may be formed together, but exemplary embodiments of the present disclosure are not limited thereto. The third metal layer 411c may also be formed of a different material than the touch electrode TE. The third metal layer 411c may be disposed in the region where portions of the fourth insulating layer 454 and the fifth insulating layer 455 have been removed. For example, the third metal layer 411c may contact the second metal layer 411b through contact holes formed in the fourth insulating layer 454 and the fifth insulating layer 455.

[0248] Reference Figure 5 and Figure 6 , alignment marks 440 may be provided on the substrate 111. The alignment marks 440 may include a first alignment mark 441, a second alignment mark 442, and a third alignment mark 443, but exemplary embodiments of the present disclosure are not limited thereto. The cross-sectional structures of the first alignment mark 441, the second alignment mark 442, and the third alignment mark 443 may be the same, but exemplary embodiments of the present disclosure are not limited thereto. Hereinafter, the first alignment mark 441 will be described.

[0249] The first alignment mark 441 may include an eighth metal layer 441 a and a first layer 441 b , but exemplary embodiments of the present disclosure are not limited thereto. The first alignment mark 441 may be formed by disposing or stacking the eighth metal layer 441 a and the first layer 441 b .

[0250] The eighth metal layer 441a may be provided on the third insulating layer 453. The eighth metal layer 441a may include the same material as the first metal layer 411a or the second metal layer 411b, but exemplary embodiments of the present disclosure are not limited thereto. For example, when forming the first metal layer 411a or the second metal layer 411b, the eighth metal layer 441a may be formed together, but exemplary embodiments of the present disclosure are not limited thereto.

[0251] The first layer 441b may be disposed on the eighth metal layer 441a. For example, the first layer 441b may be disposed to cover the eighth metal layer 441a. The first layer 441b may be formed of Figure 3 The first planarization layer 331 or the second planarization layer 332 is formed of the same material, but the exemplary embodiments of the present disclosure are not limited thereto. When forming the first planarization layer 331 or the second planarization layer 332, the first layer 441b may be formed together, but the exemplary embodiments of the present disclosure are not limited thereto.

[0252] Reference Figure 6 The pad electrode 411 has a structure in which a plurality of metal layers relatively thicker than the alignment mark 440 are provided or stacked, and a step difference in which the thickness of the pad electrode 411 is greater than that of the alignment mark 440 may occur.

[0253] The data driving circuit 120 may be disposed on the insulating layer 450 .

[0254] The data driving circuit 120 may be a circuit for driving a plurality of data lines DL. The data driving circuit 120 may include a first bump 471, a second bump 472, and a third bump 473, but exemplary embodiments of the present disclosure are not limited thereto. The data driving circuit 120 may include a plurality of bumps, but for ease of description, only the first bump 471, the second bump 472, and the third bump 473 are shown, but exemplary embodiments of the present disclosure are not limited thereto.

[0255] The first bump 471 may be a bump for signal transmission. The first bump 471 may be electrically connected to the pad electrode 411 so that the first bump 471 can supply a signal to the pad electrode 411. The data driving circuit 120 may include at least one first bump 471 electrically connected to the pad electrode 411.

[0256] The second bump 472 may not be connected to the pad electrode.The second bump 472 may be a dummy bump, but exemplary embodiments of the present disclosure are not limited thereto.

[0257] The third bump 473 may be a bump for fixing a position where the data driving circuit 120 is to be coupled to the insulating layer 450. The second bump 472 may be an alignment bump corresponding to the alignment mark 440, but exemplary embodiments of the present disclosure are not limited thereto.

[0258] The data driving circuit 120 may be connected to or coupled to the insulating layer 450 through a bonding process. The data driving circuit 120 may be attached to the pad area PA of the insulating layer 450 through an adhesive layer 460. For example, the adhesive layer 460 may be provided between the insulating layer 450 and the data driving circuit 120. The adhesive layer 460 may include conductive balls 461 and an adhesive 462, but exemplary embodiments of the present disclosure are not limited thereto.

[0259] The conductive ball 461 may have a core structure. In addition, the conductive ball 461 may have a core-shell structure including a core and a shell surrounding the core, but the exemplary embodiments of the present disclosure are not limited thereto. In the case of a core structure, the core may be formed of a metal material including at least one of gold (Au), silver (Ag), nickel (Ni), copper (Cu), lead (Pb), and platinum (Pt), but the exemplary embodiments of the present disclosure are not limited thereto. In the case of a core-shell structure, the core may be formed of a resin and the shell may be formed of a metal material including at least one of gold (Au), silver (Ag), nickel (Ni), copper (Cu), lead (Pb), and platinum (Pt), but the exemplary embodiments of the present disclosure are not limited thereto.

[0260] The adhesive 462 may be an acrylic or silicone adhesive, but exemplary embodiments of the present disclosure are not limited thereto. The adhesive 462 may be mixed with the conductive balls 461. The conductive balls 461 may be disposed between the pad electrode 411 and the first bump 471 to electrically connect the pad electrode 411 to the data driving circuit 120. The conductive balls 461 may smoothly transmit signals between the data driving circuit 120 and the pad electrode 411.

[0261] The substrate 111 and the data driving circuit 120 may undergo an attachment (or bonding) process while being pressed at a constant pressure so that the adhesive layer 460 can be evenly attached thereto. In this case, cracks may occur in the insulating layer 450 of the alignment mark 440, which is thinner than the pad electrode 411. The cracks may propagate around the insulating layer 450, thereby damaging the circuits arranged around the cracks. In addition, moisture may migrate along the cracks.

[0262] Figure 7 It shows Figure 4An exemplary view of region X, Figure 8 It is along Figure 7 An exemplary cross-sectional view taken along line CD in FIG.

[0263] Figure 7 and Figure 8 The contents of the substrate 111, pad electrode 411, insulating layer 450 and alignment mark 440 shown in FIG can be the same as Figure 5 and Figure 6 The contents of the substrate 111 , the pad electrode 411 , the insulating layer 450 , and the alignment mark 440 shown in FIG. 4 are the same or substantially the same, and thus redundant descriptions thereof may be omitted or briefly described.

[0264] Reference Figure 7 , the first pad area 400 , the structure 500 , and the alignment key 440 may be disposed in the pad area PA of the display panel 110 .

[0265] The structure 500 may be disposed adjacent to the alignment mark 440. A portion of the structure 500 may be disposed between the first pad region 400 and the alignment mark 440. The structure 500 may be a crack stopper, a crack protector, etc., but exemplary embodiments of the present disclosure are not limited thereto.

[0266] The structure 500 may have various shapes, but exemplary embodiments of the present disclosure are not limited thereto. The structure 500 may include a main structure and a substructure.

[0267] The main structures 511 and 521 may be disposed to surround the alignment mark 440. The main structures 511 and 521 may be continuously disposed while surrounding the alignment mark 440. For example, the main structures 511 and 521 may have a seamless closed loop shape, but exemplary embodiments of the present disclosure are not limited thereto.

[0268] Substructures 512, 513, 514, 522, and 523 may surround alignment mark 440 and may be configured to be disconnected or broken at certain portions. For example, substructures 512, 513, 514, 522, and 523 may have a shape that is disconnected at certain portions, but exemplary embodiments of the present disclosure are not limited thereto.

[0269] The structure 500 may include main structures 511 and 521 and substructures 512, 513, 514, 522, and 523. The main structures 511 and 521 may surround the alignment mark 440 and may be continuously provided. The substructures 512, 513, 514, 522, and 523 may surround the alignment mark 440 and may be provided to be disconnected or broken.

[0270] The substructures 512, 513, 514 may be disposed inside the main structure 511. In addition, the substructures 522 and 523 may be disposed outside the main structure 521.

[0271] Reference Figure 7 , the structure 500 may include a first structure 510 and a second structure 520 .

[0272] The first structure 510 may be disposed adjacent to the first alignment key 441. The second structure 520 may be disposed adjacent to the second alignment key 442.

[0273] The first structure 510 may include a first main structure and a first substructure. The first main structure may surround the first alignment mark 441 and may be continuously provided. The first substructure may surround the first alignment mark and may be provided to be disconnected or broken.

[0274] The first structure 510 may include a first main structure 511 and first substructures 512, 513, and 514. The first main structure 511 may surround the first alignment mark 441 and may be continuously provided. The first substructures 512, 513, and 514 may surround the first alignment mark 441 and may be provided to be disconnected or broken.

[0275] The second structure 520 may include a second main structure 521 and second substructures 522 and 523. The second main structure 521 may surround the second alignment mark 442 and may be continuously provided. The second substructures 522 and 523 may surround the second alignment mark 442 and may be provided to be disconnected or broken.

[0276] The first substructures 512, 513, 514 may be disposed inside the first main structure 511. In addition, the second substructures 522 and 523 may be disposed outside the second main structure 521.

[0277] The first substructure may be disposed outside the first main structure, and the second substructure may be disposed inside the second main structure, but exemplary embodiments of the present disclosure are not limited thereto.

[0278] Reference Figure 7 , may include pad electrodes 411 and 421 disposed in the first pad region 400. A portion of the structure 500 may be disposed between the pad electrodes 411 and 421 and the alignment key.

[0279] The pad electrodes 411 and 421 may include a plurality of pad electrodes arranged in a plurality of rows. The alignment mark 440 may be provided spaced apart from the outermost pad electrode provided at the end of at least one of the plurality of rows. A portion of the structure 500 may be provided between the outermost pad region and the alignment mark.

[0280] Reference Figure 7 , may include a data driving circuit 120 bonded (or attached) to the first pad region 400. The data driving circuit 120 may be disposed to overlap at least a portion of the first pad region 400, the alignment key 440, and the structure 500. For example, the data driving circuit 120 may be disposed on the display panel.

[0281] Reference Figure 7 and Figure 8 , the pad electrode 411, the alignment key 441, and the structure 511 may be disposed in the pad area PA of the display panel 110. The structure 511 may be disposed between the pad electrode 411 and the alignment key 441.

[0282] Reference Figure 8 The structure 511 may include at least one metal layer. The structure 511 may include multiple metal layers. The metal layer may include at least one metal layer.

[0283] The structure 511 may include a fourth metal layer 511a, a fifth metal layer 511b, a sixth metal layer 511c, and a seventh metal layer 511d. The structure 511 may be formed by disposing or stacking the fourth metal layer 511a, the fifth metal layer 511b, the sixth metal layer 511c, and the seventh metal layer 511d.

[0284] The fourth metal layer 511a may be provided on the substrate 111. The fourth metal layer 511a may include Figure 3 The fourth metal layer 511a may be formed together with the first shield metal BSM1, but the exemplary embodiment of the present disclosure is not limited thereto. For example, when the first shield metal BSM1 is formed, the fourth metal layer 511a may be formed together, but the exemplary embodiment of the present disclosure is not limited thereto. The fourth metal layer 511a may also include the same material as the first shield metal BSM1. Figure 3 The first shield metal BSM1 is of a different material.

[0285] The fifth metal layer 511b may be disposed on the fourth metal layer 511a. The fifth metal layer 511b may include the same material as the first metal layer 411a, but exemplary embodiments of the present disclosure are not limited thereto. For example, when the first metal layer 411a is formed, the fifth metal layer 511b may be formed together, but exemplary embodiments of the present disclosure are not limited thereto. The fifth metal layer 511b may also include a different material from the first metal layer 411a.

[0286] The sixth metal layer 511c may be disposed on the fifth metal layer 511b. For example, the sixth metal layer 511c may be disposed to cover the fifth metal layer 511b. The sixth metal layer 511c may include the same material as the second metal layer 411b, but exemplary embodiments of the present disclosure are not limited thereto. For example, when the second metal layer 411b is formed, the sixth metal layer 511c may be formed together, but exemplary embodiments of the present disclosure are not limited thereto. The sixth metal layer 511c may also include a different material from the second metal layer 411b.

[0287] The fifth metal layer 511b and the sixth metal layer 511c may be disposed in the region where a portion of the first insulating layer 451, the second insulating layer 452, and the third insulating layer 453 is removed. For example, the fifth metal layer 511b may contact the fourth metal layer 511a through a contact hole formed in the first insulating layer 451, the second insulating layer 452, and the third insulating layer 453.

[0288] The seventh metal layer 511d may be disposed on the sixth metal layer 511c. For example, the seventh metal layer 511d may be formed of the same material as the third metal layer 411c, but exemplary embodiments of the present disclosure are not limited thereto. When the third metal layer 411c is formed, the seventh metal layer 511d may be formed together, but exemplary embodiments of the present disclosure are not limited thereto. The seventh metal layer 511d may also be formed of a material different from that of the third metal layer 411c. The seventh metal layer 511d may be disposed in an area where portions of the fourth insulating layer 454 and the fifth insulating layer 455 are removed. For example, the seventh metal layer 511d may contact the sixth metal layer 511c through contact holes formed in the fourth insulating layer 454 and the fifth insulating layer 455.

[0289] For example, the structure 511 may be provided in a region where a portion of the first to fifth insulating layers 451 , 452 , 453 , 454 , and 455 is removed.

[0290] Structure 511 may be in an electrically floating state.

[0291] The thickness of the structure 511 may be greater than the thickness of the alignment key 441 and may be no greater than the thickness of the pad electrode 411. For example, the thickness of the structure 511 may correspond to the thickness of the pad electrode 411.

[0292] Reference Figure 8 , the data driving circuit 120 may include a first bump 471 , a second bump 472 , and a third bump 473 , but exemplary embodiments of the present disclosure are not limited thereto.

[0293] The first bump 471 may be electrically connected to the pad electrode 411. The second bump 472 may be disposed to overlap the alignment key 441. The third bump 473 may be disposed to overlap the structure 511.

[0294] Reference Figure 8 The structure 511 may be a structure in which a plurality of metal layers are disposed or stacked, and the plurality of metal layers may be disposed or stacked to have the same or substantially the same thickness as the pad electrode 411. When the thickness of the structure 511 is greater than the thickness of the alignment mark 441 and not greater than the thickness of the pad electrode 411, the third bump 473 and the structure 511 may maintain a gap between the substrate 111 and the data driving circuit 120 during the bonding process with the data driving circuit 120 to prevent cracks from occurring in the alignment mark 441.

[0295] According to the present disclosure, since the structure is formed between the first bump 471 and the second bump 472, during the process of attaching the data driving circuit 120 to the first bump 471 and the second bump 472, cracks in the insulating layer 450 can be prevented from occurring due to the thickness difference between the first bump 471 and the second bump 472. Therefore, cracks can be prevented from propagating to the pad region and the link line LL.

[0296] Exemplary embodiments of the present disclosure are described below.

[0297] A display device according to an exemplary embodiment of the present disclosure may include: a substrate including a display area and a non-display area; a first pad area disposed in the non-display area; an alignment mark disposed to be spaced apart from the first pad area; and a structure disposed adjacent to the alignment mark.

[0298] According to an exemplary embodiment of the present disclosure, the structure may surround the alignment mark and be continuously provided.

[0299] According to an exemplary embodiment of the present disclosure, the structure may surround the alignment mark and be provided to be disconnected.

[0300] According to an exemplary embodiment of the present disclosure, the structure may include a main structure disposed to surround the alignment mark and a sub-structure disposed to surround the alignment mark.

[0301] According to an exemplary embodiment of the present disclosure, the substructure may be disposed inside the main structure.

[0302] According to an exemplary embodiment of the present disclosure, the substructure may be provided outside the main structure.

[0303] According to an exemplary embodiment of the present disclosure, the first pad region may include a first sub-pad region and a second sub-pad region. The first sub-pad region may be disposed between the display region and the second sub-pad region.

[0304] According to an exemplary embodiment of the present disclosure, the alignment mark may include a first alignment mark disposed to be spaced apart from the first sub-pad region.The structure may include a first structure disposed adjacent to the first alignment mark.

[0305] According to an exemplary embodiment of the present disclosure, the alignment mark may include a second alignment mark disposed to be spaced apart from the second sub-pad region.The structure may include a second structure disposed adjacent to the second alignment mark.

[0306] According to an exemplary embodiment of the present disclosure, the first structure may include a first main structure disposed to surround the first alignment mark and a first sub-structure disposed to surround the first alignment mark.

[0307] According to an exemplary embodiment of the present disclosure, the second structure may include a second main structure disposed to surround the second alignment mark and a second sub-structure disposed to surround the second alignment mark.

[0308] According to an exemplary embodiment of the present disclosure, the first substructure may be disposed inside the first main structure, and the second substructure may be disposed outside the second main structure.

[0309] According to an exemplary embodiment of the present disclosure, the first substructure may be disposed outside the first main structure, and the second substructure may be disposed inside the second main structure.

[0310] According to an exemplary embodiment of the present disclosure, the alignment mark may further include a third alignment mark disposed between the first alignment mark and the second alignment mark, and wherein the second structure is disposed adjacent to the third alignment mark.

[0311] According to an exemplary embodiment of the present disclosure, the second structure may be provided to surround the second alignment mark and the third alignment mark.

[0312] According to an exemplary embodiment of the present disclosure, the display device may further include a pad electrode disposed in the first pad area. A portion of the structure may be disposed between the pad electrode and the alignment mark.

[0313] According to an exemplary embodiment of the present disclosure, the pad electrode may include a plurality of pad electrodes arranged in a plurality of rows. The alignment mark may be arranged to be spaced apart from an outermost pad electrode arranged at an end of at least one of the plurality of rows. A portion of the structure may be arranged between the outermost pad electrode and the alignment mark.

[0314] According to an exemplary embodiment of the present disclosure, the display device may further include a data driving circuit disposed in the first pad region. The data driving circuit may be disposed to overlap at least a portion of the structure, the alignment mark, and the first pad region.

[0315] According to an exemplary embodiment of the present disclosure, the display device may further include a second pad region disposed in the non-display region. The first pad region may be disposed between the display region and the second pad region.

[0316] A display device according to an exemplary embodiment of the present disclosure may include: a substrate including a display area and a non-display area; a plurality of insulating layers disposed on the substrate; a pad electrode disposed on the substrate and including a plurality of metal layers; an alignment mark disposed on the substrate and adjacent to the pad electrode; and a structure disposed on the substrate and including a plurality of metal layers. The structure may be disposed between the pad electrode and the alignment mark.

[0317] According to an exemplary embodiment of the present disclosure, the pad electrode may include a first metal layer, a second metal layer, and a third metal layer.

[0318] According to an exemplary embodiment of the present disclosure, the structure may include a fourth metal layer, a fifth metal layer, a sixth metal layer, and a seventh metal layer.

[0319] According to an exemplary embodiment of the present disclosure, an eighth metal layer and the first layer may be provided in the alignment mark.

[0320] According to an exemplary embodiment of the present disclosure, the first layer may be provided to cover the eighth metal layer.

[0321] According to the length display device of the exemplary embodiment of the present disclosure, the eighth metal layer may be formed of the same material as the first metal layer or the second metal layer.

[0322] According to a display device according to an exemplary embodiment of the present disclosure, the plurality of insulating layers may include a first insulating layer disposed on the substrate, a second insulating layer disposed on the first insulating layer, a third insulating layer disposed on the second insulating layer, a fourth insulating layer disposed on the third insulating layer, and a fifth insulating layer disposed on the fourth insulating layer.

[0323] According to an exemplary embodiment of the present disclosure, the pad electrode may be provided in a region where a portion of the fourth insulating layer and the fifth insulating layer is removed. The structure may be provided in a region where a portion of the first insulating layer to the fifth insulating layer is removed.

[0324] According to an exemplary embodiment of the present disclosure, the display device may further include a link line positioned in a region overlapping the pad electrode and positioned between the first insulating layer and the second insulating layer.

[0325] According to an exemplary embodiment of the present disclosure, the structure may be in an electrically floating state.

[0326] According to an exemplary embodiment of the present disclosure, the thickness of the structure may be greater than the thickness of the alignment mark and not greater than the thickness of the pad electrode.

[0327] According to an exemplary embodiment of the present disclosure, the thickness of the structure may correspond to the thickness of the pad electrode.

[0328] According to an exemplary embodiment of the present disclosure, the display device may further include a data driving circuit disposed on the insulating layer. The data driving circuit may include a first bump electrically connected to the pad electrode.

[0329] According to an exemplary embodiment of the present disclosure, the data driving circuit may further include a second bump disposed to overlap the alignment mark and a third bump disposed to overlap the structure.

[0330] According to an exemplary embodiment of the present disclosure, the display device may further include an adhesive layer disposed between the insulating layer and the data driving circuit. The adhesive layer may include conductive balls and an adhesive.

[0331] According to an exemplary embodiment of the present disclosure, the conductive ball may include a core and a shell surrounding the core, wherein the core is formed of a resin and the shell is formed of a metal material. According to an exemplary embodiment of the present disclosure, the conductive ball may include a core, wherein the core is formed of a metal material.

[0332] According to an exemplary embodiment of the present disclosure, a display panel is provided, which is provided with a display area and a non-display area, and includes: a first pad area, which is provided in the non-display area; an alignment mark, which is provided to be spaced apart from the first pad area; and a structure, which is provided to be adjacent to the alignment mark.

[0333] According to an exemplary embodiment of the present disclosure, a display panel is provided, which includes: a plurality of insulating layers; a pad electrode, which is arranged among the plurality of insulating layers and includes a plurality of metal layers; an alignment mark, which is arranged among the plurality of insulating layers and adjacent to the pad electrode; and a structure, which is arranged among the plurality of insulating layers and includes a plurality of metal layers, wherein the structure is arranged between the pad electrode and the alignment mark.

[0334] According to exemplary embodiments of the present disclosure, a display device with enhanced reliability may be provided.

[0335] According to exemplary embodiments of the present disclosure, it is possible to provide a display device capable of preventing cracks from occurring or propagating in a display panel by providing a structure in an insulating layer of the display panel.

[0336] According to exemplary embodiments of the present disclosure, a display device having enhanced resistance to moisture permeation by preventing cracks from occurring or propagating in a display panel may be provided.

[0337] According to exemplary embodiments of the present disclosure, a display device capable of preventing damage to various wirings by preventing cracks from occurring or propagating in a display panel may be provided.

[0338] According to exemplary embodiments of the present disclosure, it is possible to provide a display device capable of reducing power consumption by improving the service life of the display device by preventing cracks from occurring or propagating in a display panel.

[0339] The display device according to various exemplary embodiments of the present disclosure can be applied to mobile devices, video phones, smart watches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved devices, slidable devices, deformable devices, electronic notebooks, electronic books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, notebook computers, workstations, navigation devices, vehicle navigation, vehicle displays, vehicle devices, theater devices, theater displays, televisions, wallpaper devices, signage devices, game consoles, laptop computers, monitors, cameras, camcorders, and home appliances.

[0340] The above description is provided to enable those skilled in the art to implement and use the technical ideas of the present disclosure, and is provided in the context of specific applications and their requirements. Various modifications, additions, and substitutions to the described exemplary embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other exemplary embodiments and applications without departing from the spirit and scope of the present disclosure. The above description and accompanying drawings provide examples of the technical ideas of the present disclosure for illustrative purposes only. That is, the disclosed exemplary embodiments are intended to illustrate the scope of the technical concepts of the present disclosure.

[0341] CROSS-REFERENCE TO RELATED APPLICATIONS

[0342] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0030226, filed on February 29, 2024, which is hereby incorporated by reference in its entirety for all purposes.

Claims

1. A display device, comprising: A substrate, the substrate comprising a display area and a non-display area; a first pad region, the first pad region being disposed in the non-display region; an alignment mark disposed to be spaced apart from the first pad region; as well as A structure is provided adjacent to the alignment mark.

2. The display device according to claim 1, wherein The structures surround the alignment mark and are continuously arranged.

3. The display device according to claim 1, wherein The structure surrounds the alignment mark and is provided to be disconnected.

4. The display device according to claim 1, wherein The structure includes: a main structure disposed to surround the alignment mark; and A substructure is provided to surround the alignment mark.

5. The display device according to claim 4, wherein The substructure is arranged inside the main structure. The display device according to claim 4 , wherein: The substructure is arranged outside the main structure.

7. The display device according to claim 1, wherein The first pad region includes a first sub-pad region and a second sub-pad region, and The first sub-pad region is disposed between the display region and the second sub-pad region.

8. The display device according to claim 7, wherein: The alignment mark includes a first alignment mark disposed to be spaced apart from the first sub-pad region, and The structure includes a first structure disposed adjacent to the first alignment mark.

9. The display device according to claim 8, wherein The alignment mark includes a second alignment mark disposed to be spaced apart from the second sub-pad region, and The structure includes a second structure disposed adjacent to the second alignment mark.

10. The display device according to claim 9, wherein The first structure includes: a first main structure disposed to surround the first alignment mark; and a first substructure, the first substructure being arranged to surround the first alignment mark, and Wherein, the second structure includes: a second main structure disposed around the second alignment mark; and A second substructure is provided to surround the second alignment mark.

11. The display device according to claim 10, wherein: The first substructure is disposed inside the first main structure, and the second substructure is disposed outside the second main structure.

12. The display device according to claim 10, wherein: The first substructure is disposed outside the first main structure, and the second substructure is disposed inside the second main structure.

13. The display device according to claim 9, wherein: The alignment mark further includes a third alignment mark disposed between the first alignment mark and the second alignment mark, and Wherein, the second structure is arranged adjacent to the third alignment mark.

14. The display device according to claim 13, wherein: The second structure is provided to surround the second alignment mark and the third alignment mark.

15. The display device according to claim 1, further comprising a pad electrode, wherein the pad electrode is provided in the first pad region. in, A portion of the structure is disposed between the pad electrode and the alignment mark.

16. The display device according to claim 15, wherein The pad electrode includes a plurality of pad electrodes arranged in a plurality of rows, wherein the alignment mark is provided to be spaced apart from an outermost pad electrode provided at an end portion of at least one of the plurality of rows, and Wherein, a portion of the structure is disposed between the outermost pad electrode and the alignment mark.

17. The display device according to claim 1, further comprising a data driving circuit disposed in the first pad region. in, The data driving circuit is disposed to overlap the alignment mark, the first pad region, and at least a portion of the structure.

18. The display device according to claim 1, further comprising a second pad region disposed in the non-display region. in, The first pad region is disposed between the display region and the second pad region.

19. A display device, comprising: A substrate, the substrate comprising a display area and a non-display area; a plurality of insulating layers, wherein the plurality of insulating layers are disposed on the substrate; a pad electrode, the pad electrode being disposed on the substrate and comprising a plurality of metal layers; an alignment mark disposed on the substrate and adjacent to the pad electrode; as well as a structure disposed on the substrate and comprising a plurality of metal layers, Wherein, the structure is arranged between the pad electrode and the alignment mark.

20. The display device according to claim 19, wherein The pad electrode includes a first metal layer, a second metal layer, and a third metal layer.

21. The display device according to claim 20, wherein The structure includes a fourth metal layer, a fifth metal layer, a sixth metal layer, and a seventh metal layer.

22. The display device according to claim 21, wherein In the alignment mark, an eighth metal layer and the first layer are provided.

23. The display device according to claim 22, wherein: The first layer is provided to cover the eighth metal layer.

24. The display device according to claim 22, wherein: The eighth metal layer is formed simultaneously with the first metal layer or the second metal layer and is made of the same material as the first metal layer or the second metal layer.

25. The display device according to claim 22, wherein The plurality of insulating layers include: a first insulating layer, the first insulating layer being disposed on the substrate; a second insulating layer, the second insulating layer being disposed on the first insulating layer; a third insulating layer, the third insulating layer being disposed on the second insulating layer; a fourth insulating layer, the fourth insulating layer being disposed on the third insulating layer; and a fifth insulating layer, the fifth insulating layer being disposed on the fourth insulating layer, The pad electrode is provided in a region where a portion of the fourth insulating layer and the fifth insulating layer is removed, and The structure is provided in a region where a portion of the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer is removed. 26 . The display device of claim 25 , further comprising a link line positioned in a region overlapping the pad electrode and positioned between the first insulating layer and the second insulating layer.

27. The display device according to claim 19, wherein The structure is in an electrically floating state.

28. The display device according to claim 19, wherein The thickness of the structure is greater than the thickness of the alignment mark and is not greater than the thickness of the pad electrode.

29. The display device according to claim 28, wherein The thickness of the structure corresponds to the thickness of the pad electrode.

30. The display device according to claim 19, further comprising a data driving circuit disposed on the insulating layer. in, The data driving circuit includes a first bump electrically connected to the pad electrode.

31. The display device according to claim 30, wherein: The data driving circuit further includes: a second bump disposed to overlap the alignment mark; and A third bump is arranged to overlap with the structure.

32. The display device according to claim 30, further comprising an adhesive layer provided between the insulating layer and the data driving circuit. in, The adhesive layer includes conductive balls and an adhesive.

33. The display device according to claim 32, wherein: The conductive ball includes a core and a shell surrounding the core, Herein, the core is formed of resin, and the shell is formed of a metal material.

34. The display device according to claim 32, wherein: The conductive ball includes a core, Wherein, the core is formed of metal material.

35. A display panel, comprising a display area and a non-display area, the display panel comprising: a first pad region, the first pad region being disposed in the non-display region; an alignment mark disposed to be spaced apart from the first pad region; as well as A structure is provided adjacent to the alignment mark.

36. A display panel, comprising: Multiple insulation layers; a pad electrode disposed among the plurality of insulating layers and comprising a plurality of metal layers; an alignment mark disposed in the plurality of insulating layers and adjacent to the pad electrode; as well as A structure is provided among the plurality of insulating layers and includes a plurality of metal layers, wherein the structure is provided between the pad electrode and the alignment mark.

37. A vehicle comprising: At least one display device according to any one of claims 1 to 34.

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