Display device

Abstract

According to one aspect of the present disclosure, a display device includes: at least one sensor; and a display panel divided into a first display area overlapping with the at least one sensor, in which a first pixel unit in which at least one pixel is disposed and a transmission unit in which at least one pixel is disposed, are disposed, and a second display area in which at least one transmission unit in which at least one pixel is disposed is disposed. A first pixel unit is provided, a second pixel unit is provided, at least one pixel is provided in the second pixel unit, and the transmission unit is continuously provided in a first direction and a second direction different from the first direction, thereby improving a modulation transfer function (MTF) characteristic of the sensor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0028661 filed on February 28, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device, wherein a sensor is disposed below a display area. Background Art

[0004] In recent years, with the advent of the information age, the display field that visually expresses electrical information signals has rapidly developed, and in response thereto, various display devices having excellent properties such as thin thickness, light weight, and low power consumption have been developed.

[0005] Unlike liquid crystal display (LCD) devices that include backlight sources, organic light-emitting display (OLED) devices do not require a separate light source. Therefore, organic light-emitting display devices can be manufactured to be thin and lightweight, have process advantages, and have low power consumption due to low voltage driving. First, organic light-emitting display devices include self-luminous elements and layers formed of organic thin films, making them more flexible and elastic than other display devices, and therefore they are advantageously implemented as flexible display devices or transparent display devices.

[0006] Meanwhile, the display device has a display area and a frame area. The display area essentially displays an image, and the frame area is a non-display area that is blocked by a light-shielding member so that the image is substantially not displayed. In the display area, a display element is provided to display an image, and in the frame area, various wiring or drive circuits for driving the display element are provided. The display device includes a camera, a speaker, and various sensors to provide various functions, and these components are also provided in the frame area.

[0007] In recent years, research has been actively underway to reduce the bezel area in order to enhance the design of display devices and to maximize the size of screens within the limited display device size. To address this issue, components such as cameras and sensors, which have traditionally been located in the bezel area, are now located within the display area. However, in order to smoothly display images, a technology has been proposed in which these components are located on the rear surface of the display panel. Summary of the Invention

[0008] One object of the present disclosure is to provide a display device that improves the modulation transfer function (MTF) characteristics of a sensor by utilizing the placement relationship of a transmissive hole of a display panel that overlaps with the sensor.

[0009] Furthermore, another object of the present disclosure is to provide a display device that maximizes an opening area of ​​a display panel by utilizing a placement relationship of signal lines provided in the display panel.

[0010] The objects of the present disclosure are not limited to the above objects, and other objects not mentioned above can be clearly understood by those skilled in the art from the following description.

[0011] To achieve the objectives described above, according to one aspect of the present disclosure, a display device includes: at least one sensor; and a display panel, wherein the display panel is divided into a first display area overlapping with the at least one sensor, and a second display area, wherein a first pixel unit and a transmission unit are provided in the first display area, at least one pixel is provided in the first pixel unit, a second pixel unit is provided in the second display area, at least one pixel is provided in the second pixel unit, and the transmission unit is continuously provided in a first direction and a second direction different from the first direction, thereby improving a modulation transfer function (MTF) characteristic of the sensor.

[0012] To achieve the objectives described above, according to another embodiment of the present disclosure, a display device includes: at least one sensor; and a display panel, wherein a plurality of gate lines extending in a first direction, a plurality of data lines extending in a second direction, and a plurality of pixels are formed in the display panel, and in a transmissive region of the display panel overlapping with the at least one sensor, a plurality of transmissive holes are arranged in the first direction and the second direction, thereby improving the modulation transfer function (MTF) characteristics of the sensor.

[0013] Additional details of exemplary embodiments are included in the detailed description and accompanying drawings.

[0014] In the display device according to an exemplary embodiment of the present disclosure, the ratio of the transmissive holes is maximized to increase the amount of light detectable by the sensor, thereby improving the sensing performance of the sensor.

[0015] In the display device according to an exemplary embodiment of the present disclosure, the transmissive holes are arranged in a matrix to optimize the MTF, thereby optimizing the optical characteristics of the sensor.

[0016] The effects according to the present disclosure are not limited to the above-exemplified contents, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0018] Figure 1is a view showing a front surface and corresponding side surfaces of a display device according to an embodiment of the present disclosure;

[0019] Figure 2 is a circuit diagram of one sub-pixel of a display device according to an exemplary embodiment of the present disclosure;

[0020] Figure 3 is a view schematically illustrating a second display area of ​​a display panel of a display device according to an exemplary embodiment of the present disclosure;

[0021] Figure 4 is a view schematically illustrating a first display area of ​​a display panel of a display device according to an exemplary embodiment of the present disclosure;

[0022] Figure 5 is a view showing a detailed layout of a first display area of ​​a display panel of a display device according to an exemplary embodiment of the present disclosure;

[0023] Figure 6 It is along Figure 5 A cross-sectional view taken along line VI-VI';

[0024] Figure 7 It is along Figure 5 A cross-sectional view taken along line VII-VII′;

[0025] Figure 8 It is along Figure 5 A cross-sectional view taken along line VIII-VIII';

[0026] Figure 9 is a view illustrating a placement relationship of a transmission unit in a display device according to an exemplary embodiment of the present disclosure;

[0027] Figure 10A and Figure 10B is a graph showing a modulation transfer function (MTF) of a transmission unit TA in a display device according to an exemplary embodiment of the present disclosure; and

[0028] Figure 11 is a view illustrating a detailed layout of a first display area of ​​a display panel of a display device according to another exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] The advantages and features of the present disclosure and methods for achieving these advantages and features will be apparent by referring to the exemplary embodiments described in detail below in conjunction with the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure and scope of the present disclosure.

[0030] The shapes, sizes, ratios, angles, quantities, etc. shown in the drawings for describing exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals generally represent the same elements. In addition, in the following description of the present disclosure, detailed explanations of known related arts may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including," "having," and "consisting of" used herein are generally intended to allow the addition of other components unless the term is used together with the term "only." Unless expressly stated otherwise, any reference to the singular may include the plural.

[0031] Even if not explicitly stated, the components are to be construed as including the ordinary error range.

[0032] When terms such as “on,” “above,” “below,” and “next to” are used to describe a positional relationship between two components, one or more components may be located between the two components unless the terms are used with the terms “immediately” or “directly.”

[0033] When an element or layer is referred to as being “on” another element or layer, the layer or element may be directly on the other element or interposed therebetween.

[0034] Although the terms "first," "second," and the like are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component mentioned below may be the second component in the technical concept of the present disclosure.

[0035] Throughout this specification, like reference numerals generally refer to like elements.

[0036] The size and thickness of each component shown in the drawings are illustrated for convenience of description, and the present disclosure is not limited to the size and thickness of the components shown.

[0037] The features of the various embodiments of the present disclosure may be combined or coupled with each other in part or in whole, and may be technically interlocked and operated in various ways, and the embodiments may be performed independently or in association with each other.

[0038] Hereinafter, a display device according to exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0039] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0040] Figure 1 are views illustrating a front surface and corresponding side surfaces of a display device according to an embodiment of the present disclosure.

[0041] Reference Figure 1, a display device 100 according to an exemplary embodiment of the present disclosure may include a display panel 110 and a sensor module SEN.

[0042] The display panel 110 (or pixel unit or display unit) can display an image. The display panel 110 may include various circuits, signal lines, and light-emitting diodes provided on a substrate. The display panel 110 is divided by a plurality of data lines and a plurality of gate lines that intersect each other, and may include a plurality of pixels PXL connected to the plurality of data lines and the plurality of gate lines.

[0043] The display panel 110 may include a display area DA, a plurality of pixels PXL being arranged in the display area DA to display an image, and a non-display area NDA being located outside the display area DA and including various signal lines or pads. The display panel 110 may be implemented as a display panel used in various display devices (e.g., a liquid crystal display device, an organic light-emitting display device, or an electrophoretic display device). Hereinafter, the display panel 110 is described as a panel used in an organic light-emitting display device, but exemplary embodiments of the present disclosure are not limited thereto.

[0044] The display panel 110 may include a plurality of pixels PXL disposed on a display area DA. Each of the plurality of pixels PXL may be electrically connected to a corresponding gate line among gate lines and a corresponding data line among data lines. Therefore, a gate signal and a data signal may be applied to each pixel PXL via the gate line and the data line. Furthermore, each pixel PXL may implement a gray scale by applying the gate signal and the data signal, and ultimately, an image may be displayed in the display area by the gray scale displayed by the pixel PXL.

[0045] Further, the display area DA may include a first display area A1 overlapping the sensor module SEN and a second display area A2 not overlapping the sensor module SEN. That is, the sensor module SEN may be disposed on the rear surface of the first display area A1.

[0046] Further, in the display area DA, an image needs to be displayed in the entire area, so at least one pixel PXL may be provided in each of the first display area A1 and the second display area A2.

[0047] Specifically, the pixels provided in the first display area A1 are referred to as first pixels PXL1 , and the pixels provided in the second display area A2 are referred to as second pixels PXL2 .

[0048] Furthermore, each of the plurality of pixels may include a plurality of sub-pixels. The sub-pixels included in a pixel PXL may emit light of different colors. For example, the sub-pixels include red sub-pixels, green sub-pixels, and blue sub-pixels, but are not limited thereto and may also include white sub-pixels. Multiple sub-pixels may constitute a pixel PXL.

[0049] More specifically, in the first display area A1 overlapping the sensor module SEN, light needs to be transmitted to the sensor module. Therefore, the first display area A1 includes not only a plurality of first pixels PXL1 but also a transmissive region for transmitting external light. In other words, the first display area A1 includes a first pixel unit in which the plurality of first pixels PXL1 are disposed, and a transmissive unit (transmissive region) in which no pixels are disposed.

[0050] In addition, light does not need to be transmitted to the second display area A2 that does not overlap with the sensor module SEN, so that only a plurality of second pixels PXL2 can be provided in the second display area A2. That is, the second display area A2 may include a second pixel unit in which a plurality of second pixels PXL2 are provided, without including a transmission unit.

[0051] The sensor module SEN may be a camera that senses visible rays, but is not limited thereto, and may include various sensors such as an IR sensor that senses infrared rays and a thermal sensor that senses heat.

[0052] The sensor module SEN may be disposed at a position corresponding to the transmissive unit disposed in the first display area A1. That is, the sensor module may be disposed so as to overlap only the transmissive unit disposed in the first display area A1, but is not limited thereto. The sensor module may be disposed so as to overlap not only the transmissive unit disposed in the first display area A1 but also the first pixel unit.

[0053] The transmissive unit has a higher light transmittance than other areas, allowing the sensor module located in the corresponding position to detect more light incident on the front surface than in other areas. Accordingly, in the first display area A1, not only is the light incident on the front surface detected by the sensor module, but an image can also be output by the first pixel unit located in the first display area A1.

[0054] Meanwhile, the non-display area NDA is an area located near the display area DA and may refer to a remaining area except the display area DA. In the non-display area NDA, a data driver, a gate driver, and a timing controller may be disposed.

[0055] The timing controller (or timing control circuit) can receive timing signals such as vertical synchronization signals, horizontal synchronization signals, data enable signals, or dot clocks through a receiving circuit (e.g., an LVDS or TMDS interface) connected to an external device (e.g., a host system). The timing controller can generate and output timing control signals based on the input timing signals to control the data driver and gate driver.

[0056] The data driver (or data driver circuit) can supply data signals to a plurality of pixels. For this purpose, the data driver may include at least one source driver IC (integrated circuit). The source driver IC may be supplied with a source timing control signal and digital video data from a timing controller. The source driver IC converts the digital video data into a gamma voltage in response to the source timing control signal to generate a data signal, and can supply the data signal to the pixel through the data line of the display panel 110. The source driver IC may be connected to the data line of the display panel 110 by a chip on glass (COG) process or a tape automated bonding (TAB) process. In addition, the source driver IC may be formed on the display panel 110, or formed on a separate PCB substrate to be connected to the display panel 110.

[0057] The gate driver (or gate drive circuit, scan driver or scan drive circuit) can supply gate signals to multiple sub-pixels. The gate driver may include a level shifter and a shift register. The level shifter shifts the level of the clock signal input at a transistor-transistor-logic (TTL) level from the timing controller, and then supplies the clock signal to the shift register. The shift register may be formed in the non-display area NDA of the display panel in a GIP manner, but is not limited thereto. The shift register may be composed of a plurality of stages that shift and output gate signals in response to a clock signal and a drive signal. The plurality of stages included in the shift register may output gate signals in sequence through a plurality of output terminals.

[0058] Figure 2 is a circuit diagram of one sub-pixel of a display device according to an exemplary embodiment of the present disclosure.

[0059] exist Figure 2 , a pixel circuit provided in one sub-pixel is shown to be a 6T1C pixel circuit structure composed of six transistors and one capacitor, but this is exemplary, and the number of transistors and the number of capacitors constituting the pixel circuit are not limited thereto.

[0060] Reference Figure 2, a pixel circuit includes a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a driving transistor DT , a storage capacitor Cst and a light emitting diode LED.

[0061] The light emitting diode LED emits light by the driving current supplied from the driving transistor DT. An anode of the light emitting diode LED is connected to the fourth node N4, and a cathode of the light emitting diode LED is connected to the input terminal of the low potential voltage VSS.

[0062] The driving transistor DT controls the driving current applied to the light emitting diode LED according to the voltage (Vsg) between the source electrode and the gate electrode. The source electrode of the driving transistor DT is connected to the input terminal of the high potential voltage VDD, the gate electrode is connected to the second node N2, and the drain electrode is connected to the third node N3.

[0063] The first transistor T1 includes a gate electrode connected to an input terminal of a first scan signal SCAN1, a source electrode connected to a data line DL supplying a data voltage VDATA, and a drain electrode connected to a first node N1. The first transistor T1 can apply the data voltage VDATA supplied from the data line DL to the first node N1 in response to the first scan signal SCAN1.

[0064] The second transistor T2 includes a source electrode connected to the third node N3, a drain electrode connected to the second node N2, and a gate electrode connected to the input terminal of the first scan signal SCAN1. The second transistor T2 can form a diode connection between the gate electrode and the drain electrode of the driving transistor DT in response to the first scan signal SCAN1.

[0065] The third transistor T3 includes a gate electrode connected to an input terminal of an emission signal EM, a source electrode connected to a first node N1, and a drain electrode connected to an input terminal of a reference voltage VREF. The third transistor T3 can apply the reference voltage VREF to the first node N1 in response to the emission signal EM.

[0066] The fourth transistor T4 includes a source electrode connected to the third node N3, a drain electrode connected to the fourth node N4, and a gate electrode connected to the input terminal of the emission signal EM. The fourth transistor T4 forms a current path between the third node N3 and the fourth node N4 in response to the emission signal EM.

[0067] The fifth transistor T5 includes a drain electrode connected to the fourth node N4, a source electrode connected to an input terminal of a reference voltage VREF, and a gate electrode connected to an input terminal of a second scan signal SCAN2. The fifth transistor T5 can apply the reference voltage VREF to the fourth node N4 in response to the second scan signal SCAN2.

[0068] The storage capacitor Cst includes a first electrode connected to the first node N1 and a second electrode connected to the second node N2.

[0069] In the display device 100, a frame period can be divided into an initial period, a sampling period, and an emission period. The initial period is a period during which the gate voltage of the driving transistor DT is initialized. The sampling period is a period during which the voltage of the anode of the light-emitting diode LED is initialized and the threshold voltage of the driving transistor DT is sampled and stored in the second node N2. The emission period is a period during which the sampled threshold voltage is included to program the voltage between the source electrode and the gate electrode of the driving transistor DT, and the light-emitting diode LED emits light using a driving current according to the programmed voltage.

[0070] Here, during the emission period, the emission signal EM is inverted to the gate-on voltage. That is, the emission signal EM drops to the gate-on voltage. Therefore, the fourth transistor T4 is turned on by the emission signal EM, and a drive current for driving the light-emitting diode LED is applied to the light-emitting diode LED via the fourth node N4. Therefore, during the emission period, the light-emitting diode LED can emit light. Although the present disclosure describes the gate-on voltage as a gate-low voltage and the gate-off voltage as a gate-high voltage, depending on the type of transistor, the gate-on voltage may be a gate-high voltage and the gate-off voltage may be a gate-low voltage.

[0071] Figure 3 is a view schematically illustrating a second display area of ​​a display panel of a display device according to an exemplary embodiment of the present disclosure.

[0072] As described above, a plurality of second pixels PXL2 may be provided in the second display area A2. Figure 2 , the plurality of second pixels PXL2 are shown to be arranged in a 2×2 matrix, but the number of the plurality of second pixels PXL2 is not limited thereto but may be varied in various forms.

[0073] In addition, a plurality of signal lines extending in the first direction D1 may be connected to a plurality of second pixels PXL2 disposed in the first direction D1.

[0074] More specifically, the plurality of gate lines GL1 to GL5 extend in the first direction D1 to be connected to the sub-pixels R, G, and B of the plurality of second pixels PXL2 arranged in the first direction D1.

[0075] For example, the plurality of gate lines GL1 to GL5 may include first to fifth gate lines GL1 to GL5. In addition, the second scan signal SCAN2 is applied to the first gate line GL1, the emission signal EM is applied to the second gate line GL2, the second scan signal SCAN2 is applied to the third gate line GL3, the first scan signal SCAN1 is applied to the fourth gate line GL4, and the emission signal EM is applied to the fifth gate line GL5.

[0076] Therefore, in the second display area A2, the second scan signal SCAN2 can be applied to each of the multiple sub-pixels R, G, and B of the second pixel PXL2 via the first gate line GL1. In addition, in the second display area A2, the emission signal EM can be applied to each of the multiple sub-pixels R, G, and B of the second pixel PXL2 via the second gate line GL2. In addition, in the second display area A2, the second scan signal SCAN2 can be applied to each of the multiple sub-pixels R, G, and B of the second pixel PXL2 via the third gate line GL3. In addition, in the second display area A2, the first scan signal SCAN1 can be applied to each of the multiple sub-pixels R, G, and B of the second pixel PXL2 via the fourth gate line GL4. In addition, in the second display area A2, the emission signal EM can be applied to each of the multiple sub-pixels R, G, and B of the second pixel PXL2 via the fifth gate line GL5.

[0077] Figure 4 is a view schematically illustrating a first display area of ​​a display panel of a display device according to an exemplary embodiment of the present disclosure.

[0078] As described above, in the first display area A1 , the first pixel PXL1 and the transmission unit TA may be disposed.

[0079] Furthermore, a plurality of signal lines extending in the first direction D1 may be connected to the first pixel PXL1.

[0080] More specifically, the plurality of gate lines GL1 to GL5 extend in the first direction D1 to be connected to the sub-pixels R, G, and B of the first pixel PXL1.

[0081] For example, the plurality of gate lines GL1 to GL5 may include first to fifth gate lines GL1 to GL5. In addition, the second scan signal SCAN2 is applied to the first gate line GL1, the emission signal EM is applied to the second gate line GL2, the second scan signal SCAN2 is applied to the third gate line GL3, the first scan signal SCAN1 is applied to the fourth gate line GL4, and the emission signal EM is applied to the fifth gate line GL5.

[0082] Therefore, in the first display area A1, the second scan signal SCAN2 can be applied to each of the multiple sub-pixels R, G, and B of the first pixel PXL1 through the first gate line GL1. In addition, in the first display area A1, the emission signal EM can be applied to each of the multiple sub-pixels R, G, and B of the first pixel PXL1 through the second gate line GL2. In addition, in the first display area A1, the second scan signal SCAN2 can be applied to each of the multiple sub-pixels R, G, and B of the first pixel PXL1 through the third gate line GL3. In addition, in the first display area A1, the first scan signal SCAN1 can be applied to each of the multiple sub-pixels R, G, and B of the first pixel PXL1 through the fourth gate line GL4. In addition, in the first display area A1, the emission signal EM can be applied to each of the multiple sub-pixels R, G, and B of the first pixel PXL1 through the fifth gate line GL5.

[0083] Furthermore, a signal connection line extending in the first direction D1 to be electrically connected to a plurality of signal lines may be provided in the transmission unit TA.

[0084] More specifically, the plurality of gate connection lines GCL1, GCL2, and GCL3 extend in the first direction D1 to be connected to the plurality of gate lines GL1 to GL5. In addition, any one of the plurality of gate connection lines GCL1, GCL2, and GCL3 can be connected to the plurality of gate lines GL1 to GL5 transmitting the same signal.

[0085] Therefore, the number of the plurality of gate link lines GCL1 , GCL2 , and GCL3 may be smaller than the number of the plurality of gate lines GL1 to GL5 .

[0086] For example, the plurality of gate connection lines GCL1, GCL2, and GCL3 may include first to third gate connection lines GCL1 to GCL3. Furthermore, the first and third gate lines GL1 and GL3, to which the second scan signal SCAN2 is applied, may be connected to the first gate connection line GCL1. Furthermore, the fourth gate line GL4, to which the first scan signal SCAN1 is applied, may be connected to the second gate connection line GCL2. Furthermore, the second and fifth gate lines GL2 and GL5, to which the emission signal EM is applied, may be connected to the third gate connection line GCL3.

[0087] In other words, in the first display area A1, the first gate line GL1 and the third gate line GL3 may be integrated into the first gate connection line GCL1. Further, in the first display area A1, the second gate line GL2 and the fifth gate line GL5 may be integrated into the third gate connection line GCL3 of the first display area A1.

[0088] Figure 5is a view illustrating a detailed layout of a first display area of ​​a display panel of a display device according to an exemplary embodiment of the present disclosure.

[0089] Figure 6 It is along Figure 5 A cross-sectional view taken along line VI-VI'.

[0090] Figure 7 It is along Figure 5 A cross-sectional view taken along line VII-VII'.

[0091] Figure 8 It is along Figure 5 A cross-sectional view taken along line VIII-VIII'.

[0092] exist Figure 5 , portions of the plurality of gate lines GL1 to GL5 overlapping the plurality of sub-pixels R, G, and B are indicated by dotted lines.

[0093] That is to say, Figure 6 is a cross-sectional view illustrating a stacked structure of a display device according to an exemplary embodiment.

[0094] Reference Figure 6 , Figure 6 is a cross-sectional view of a device including two switching thin film transistors TFT1 and TFT2 and a storage capacitor CST. The two thin film transistors TFT1 and TFT2 include either a switching thin film transistor or a driving transistor made of a polycrystalline semiconductor material, and an oxide thin film transistor TFT2 made of an oxide semiconductor material. In this case, the thin film transistor made of a polycrystalline semiconductor material is referred to as a polycrystalline thin film transistor TFT1, and the thin film transistor made of an oxide semiconductor material is referred to as an oxide thin film transistor TFT2.

[0095] Figure 6 The illustrated polycrystalline thin film transistor TFT1 is an emission switching thin film transistor connected to the light emitting diode OLED, and the oxide thin film transistor TFT2 is a driving transistor or any one switching thin film transistor connected to the storage capacitor CST.

[0096] Each pixel PXL includes a light-emitting diode (OLED) and a pixel driving circuit that applies a driving current to the light-emitting diode (OLED). The pixel driving circuit is disposed on a substrate 111, and the light-emitting diode (OLED) is disposed on the pixel driving circuit. Furthermore, an encapsulation layer 120 is disposed on the light-emitting diode (OLED). The encapsulation layer 120 protects the light-emitting diode (OLED).

[0097] The pixel driving circuit may refer to a pixel array unit, which includes a driving thin film transistor, a switching thin film transistor, and a capacitor. Furthermore, the light-emitting diode (OLED) may refer to an array unit, which includes an anode electrode, a cathode electrode, and an emission layer disposed between the anode electrode and the cathode electrode for emitting light.

[0098] In one exemplary embodiment, the driver thin film transistor and at least one switching thin film transistor use an oxide semiconductor as their active layer. Thin film transistors using oxide semiconductor materials as their active layers have excellent leakage current blocking effects and are relatively inexpensive to manufacture than thin film transistors using polycrystalline semiconductor materials as their active layers. Accordingly, to reduce power consumption and save manufacturing costs, the pixel driving circuit according to the exemplary embodiment includes at least one switching thin film transistor and a driver thin film transistor using oxide semiconductor materials.

[0099] All thin film transistors constituting the pixel driving circuit may be implemented using an oxide semiconductor material, or only some switching thin film transistors may be implemented using an oxide semiconductor material.

[0100] However, in the case of thin film transistors using oxide semiconductor materials, it is difficult to ensure reliability, while thin film transistors using polycrystalline semiconductor materials have fast operation speed and excellent reliability. Therefore, exemplary embodiments include both switching thin film transistors using oxide semiconductor materials and switching thin film transistors using polycrystalline semiconductor materials.

[0101] The substrate 111 may be configured as a multilayer in which organic films and inorganic films are alternately stacked. For example, in the substrate 111, an organic film such as polyimide and an inorganic film such as silicon oxide SiO2 may be alternately stacked.

[0102] A lower buffer layer 112a is formed on the substrate 111. The lower buffer layer 112a is provided to block moisture from penetrating from the outside and may be configured by stacking a plurality of silicon oxide (SiO2) films. An auxiliary buffer layer 112b may be further provided on the lower buffer layer 112a to protect the element from moisture penetration.

[0103] A polycrystalline thin film transistor TFT1 is formed on a substrate 111. The polycrystalline thin film transistor TFT1 may use a polycrystalline semiconductor as an active layer. The polycrystalline thin film transistor TFT1 includes a first active layer ACT1, a first gate electrode GE1, a first source electrode SD1, and a first drain electrode SD2. The first active layer ACT1 includes a channel through which electrons or holes move.

[0104] The first active layer ACT1 includes a first channel region, a first source region disposed on one side of the first channel region, and a first drain region disposed on the other side thereof. The first channel region is disposed between the first source region and the first drain region.

[0105] The first source region and the first drain region are regions where an intrinsic polycrystalline semiconductor material is doped with a predetermined concentration of Group V or Group III impurity ions (e.g., phosphorus (P) or boron (B)) to conduct electricity. In the first channel region, the polycrystalline semiconductor material remains in an intrinsic state and provides a path through which electrons or holes move.

[0106] Meanwhile, the polycrystalline thin film transistor TFT1 includes a first gate electrode GE1 overlapping the first channel region of the first active layer ACT1. A first gate insulating layer 113 is provided between the first gate electrode GE1 and the first active layer ACT1. The first gate insulating layer 113 can be configured by stacking an inorganic layer (such as a silicon oxide (SiO2) film or a silicon nitride (SiNx)) as a single layer or multiple layers.

[0107] In an exemplary embodiment, the polycrystalline thin-film transistor TFT1 has a top-gate structure in which the first gate electrode GE1 is located above the first active layer ACT1. Therefore, the first electrode CST1 included in the storage capacitor CST and the light shielding layer LS included in the oxide thin-film transistor TFT2 are formed of the same material as the first gate electrode GE1. The first gate electrode GE1, the first electrode CST1, and the light shielding layer LS are formed using a single mask process, thereby reducing the number of mask processes.

[0108] The first gate electrode GE1 is made of a metal material. For example, the first gate electrode GE1 may be a single layer or multiple layers formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof, but is not limited thereto.

[0109] A first interlayer insulating layer 114 is disposed on the first gate electrode GE1 and may be formed of silicon oxide (SiO 2 ) or silicon nitride (SiNx).

[0110] The display panel may further include an upper buffer layer 115, a second gate insulating layer 116, and a second interlayer insulating layer 117 sequentially disposed on the first interlayer insulating layer 114. The polycrystalline thin film transistor TFT1 includes a first source electrode SD1 and a first drain electrode SD2, which are formed on the second interlayer insulating layer 117 and connected to the first source region and the first drain region, respectively.

[0111] The first source electrode SD1 and the first drain electrode SD2 may be a single layer or a multilayer formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof, but are not limited thereto.

[0112] The upper buffer layer 115 separates the second active layer ACT2 of the oxide thin film transistor TFT2 , which is implemented with an oxide semiconductor material, from the first active layer ACT1 , which is implemented with a polycrystalline semiconductor material, and provides a basis for forming the second active layer ACT2 .

[0113] The second gate insulating layer 116 covers the second active layer ACT2 of the oxide thin film transistor TFT2. The second gate insulating layer 116 is formed on the second active layer ACT2 implemented by the oxide semiconductor material, so that the second gate insulating layer is implemented by an inorganic film. For example, the second gate insulating layer 116 can be silicon oxide (SiO2) or silicon nitride (SiNx).

[0114] The second gate electrode GE2 is made of a metal material. For example, the second gate electrode GE2 may be a single layer or multiple layers formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof, but is not limited thereto.

[0115] Meanwhile, the oxide thin film transistor TFT2 includes a second active layer ACT2 formed on the upper buffer layer 115 and implemented with an oxide semiconductor material, a second gate electrode GE2 disposed on the second gate insulating layer 116, and a second source electrode SD3 and a second drain electrode SD4. The second source electrode SD3 and the second drain electrode SD4 are disposed on the second interlayer insulating layer 117.

[0116] The second active layer ACT2 includes an intrinsic second channel region implemented by an oxide semiconductor material and not doped with impurities, and a second source region and a second drain region doped with impurities to become conductive.

[0117] The oxide thin-film transistor TFT2 further includes a light-shielding layer LS, which is located below the upper buffer layer 115 and overlaps the second active layer ACT2. The light-shielding layer LS blocks light from entering the second active layer ACT2, thereby ensuring the reliability of the oxide thin-film transistor TFT2. The light-shielding layer LS is formed from the same material as the first gate electrode GE1 and is formed on the upper surface of the first gate insulating layer 113. The light-shielding layer LS is electrically connected to the second gate electrode GE2 to form a dual-gate structure.

[0118] The second source electrode SD3 and the second drain electrode SD4 are formed of the same material as the first source electrode SD1 and the first drain electrode SD2 on the second interlayer insulating layer 117 to reduce the number of mask processes.

[0119] Meanwhile, the second electrode CST2 is disposed on the first interlayer insulating layer 114 to overlap with the first electrode CST1, thereby implementing a storage capacitor CST. For example, the second electrode CST2 may be a single layer or multiple layers formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0120] The storage capacitor CST stores a data voltage applied through the data line DL for a predetermined period of time and then supplies the data voltage to the light emitting diode OLED. The storage capacitor CST includes two corresponding electrodes and a dielectric material disposed therebetween. A first interlayer insulating layer 114 is disposed between the first electrode CST1 and the second electrode CST2.

[0121] The first electrode CST1 or the second electrode CST2 of the storage capacitor CST may be electrically connected to the second source electrode SD3 or the second drain electrode SD4 of the oxide thin film transistor TFT2. However, the present disclosure is not limited thereto, and the connection relationship of the storage capacitor CST may vary depending on the pixel driving circuit.

[0122] At the same time, a first planarization layer 118 and a second planarization layer 119 are sequentially disposed on the pixel driving circuit to planarize the upper end of the pixel driving circuit. The first planarization layer 118 and the second planarization layer 119 can be organic films, such as polyimide or acryl resin.

[0123] Furthermore, a light emitting diode (OLED) is formed on the second planarization layer 119 .

[0124] The light-emitting diode OLED includes an anode electrode ANO, a cathode electrode CAT, and an emission layer EL disposed between the anode electrode ANO and the cathode electrode CAT. If a pixel driving circuit that uses a low potential voltage connected to the cathode electrode CAT is implemented, the anode electrode ANO is provided as a separate electrode in each sub-pixel. If a pixel driving circuit that uses a high potential voltage is implemented, the cathode electrode CAT can be provided as a separate electrode in each sub-pixel.

[0125] The light emitting diode OLED is electrically connected to the driving element through the intermediate electrode CNE provided on the first planarization layer 118. Specifically, the anode electrode ANO of the light emitting diode OLED and the first source electrode SD1 of the polycrystalline thin film transistor TFT1 constituting the pixel driving circuit are connected to each other through the intermediate electrode CNE.

[0126] The anode electrode ANO is connected to the intermediate electrode CNE exposed through a contact hole passing through the second planarization layer 119. In addition, the intermediate electrode CNE is connected to the first source electrode SD1 exposed through a contact hole passing through the first planarization layer 118.

[0127] The intermediate electrode CNE serves as a medium connecting the first source electrode SD1 and the anode electrode ANO. The intermediate electrode CNE may be formed of a conductive material such as copper (Cu), silver (Ag), molybdenum (Mo), or titanium (Ti).

[0128] The anode electrode ANO can be formed to have a multilayer structure including a transparent conductive film and an opaque conductive film with high reflection efficiency. The transparent conductive film is made of a material with a higher work function, such as indium tin oxide (ITO) or indium zinc oxide (IZO). The opaque conductive film is configured to include a single layer or multilayer structure of aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti) or an alloy thereof. For example, the anode electrode ANO is formed into a structure in which a transparent conductive film, an opaque conductive film and a transparent conductive film are stacked in sequence, or it can also be formed into a structure in which a transparent conductive film and an opaque conductive film are stacked in sequence.

[0129] The emission layer EL may be formed by stacking a hole-related layer, an organic emission layer, and an electron-related layer on the anode electrode ANO in this order or in a reverse order.

[0130] The bank layer BNK may be a pixel definition film that exposes the anode electrode ANO of each pixel PXL. The bank layer BNK may be formed of an opaque (e.g., black) material to suppress light interference between adjacent pixels PXL. In this case, the bank layer BNK includes a light-shielding material formed of at least one of a color pigment, an organic black substance, and carbon. A spacer may also be provided on the bank layer BNK.

[0131] The cathode electrode CAT is formed on the top and side surfaces of the emission layer EL to face the anode electrode ANO, wherein the emission layer EL is between the cathode electrode CAT and the anode electrode ANO. The cathode electrode CAT is integrally formed over the entire display area DA. When the cathode electrode CAT is applied to a top-emission organic light-emitting display device, the cathode electrode may be formed of a transparent conductive layer (e.g., indium tin oxide (ITO) or indium zinc oxide (IZO)).

[0132] An encapsulation layer 120 may also be disposed on the cathode electrode CAT to suppress moisture penetration.

[0133] The encapsulation layer 120 can prevent moisture or oxygen from penetrating into the light-emitting diode (OLED), which is susceptible to moisture or oxygen from the outside. To this end, the encapsulation layer 120 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer, but is not limited thereto. In this disclosure, the structure of the encapsulation layer 120, in which the first encapsulation layer 121, the second encapsulation layer 122, and the third encapsulation layer 123 are sequentially stacked, is used as an example for description.

[0134] The first encapsulating layer 121 is formed on the substrate 111 on which the cathode electrode CAT is formed. The third encapsulating layer 123 is formed on the substrate 111 on which the second encapsulating layer 122 is formed. The third encapsulating layer 123, together with the first encapsulating layer 121, surrounds the top surface, bottom surface and side surface of the second encapsulating layer 122. The first encapsulating layer 121 and the third encapsulating layer 123 can minimize or inhibit the penetration of external moisture or oxygen into the light-emitting diode OLED. The first encapsulating layer 121 and the third encapsulating layer 123 can be formed of an inorganic insulating material that allows low-temperature deposition thereon, such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON) or aluminum oxide (Al2O3). The first encapsulating layer 121 and the third encapsulating layer 123 are deposited in a low-temperature atmosphere, so that the light-emitting diode OLED, which is susceptible to high-temperature atmospheres, can be prevented from being damaged during the deposition of the first encapsulating layer 121 and the third encapsulating layer 123.

[0135] The second encapsulating layer 122 serves as a buffer layer that relieves stress between layers caused by bending of the display device 100 and can flatten steps between layers. The second encapsulating layer 122 may be formed on the substrate 111 on which the first encapsulating layer 121 is formed, using, but not limited to, acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyethylene, or a non-photosensitive organic insulating material (e.g., silicon oxycarbide (SiOC)) or a photosensitive organic insulating material (e.g., photoacrylic material).

[0136] Among the plurality of signal lines, signal lines configured to output the same signal may be connected by a signal jumper line.

[0137] At the same time, refer to Figure 5 Among the plurality of gate lines GL1 to GL5 extending in the first direction D1, gate lines configured to output the same gate signal may be connected by a plurality of gate jumper lines GJL1 and GJL2 extending in the second direction.

[0138] Specifically, the first gate line GL1 and the third gate line GL3 extending in the first direction D1 are connected via a first gate jumper line GJL1 extending in the second direction D2. Furthermore, the first gate line GL1 and the third gate line GL3 connected by the first gate jumper line GJL1 are connected to a first gate connection line GCL1 extending in the first direction D1. Therefore, the first gate line GL1 and the third gate line GL3, the first gate jumper line GJL1, and the first gate connection line GCL1 can all transmit the second scan signal SCAN2.

[0139] In addition, the second gate line GL2 and the fifth gate line GL5 extending in the first direction D1 are connected via a second gate jumper line GJL2 extending in the second direction D2. Furthermore, the second gate line GL2 and the fifth gate line GL5 connected by the second gate jumper line GJL2 are connected to a third gate connection line GCL3 extending in the first direction D1. Therefore, the second gate line GL2 and the fifth gate line GL5, the second gate jumper line GJL2, and the third gate connection line GCL3 can all transmit the emission signal EM.

[0140] Reference Figure 7 The gate line GL5 may be disposed on the first gate insulating layer 113. Furthermore, the metal layer on which the first gate electrode GE1 and the gate line GL5 are disposed may be defined as a first layer. Furthermore, on the first layer, a first interlayer insulating layer 114 may be disposed to insulate the gate line GL5 from the first data line SDL1 disposed on the first layer.

[0141] In addition, refer to Figure 8 , the metal layer on which the first data line SDL1 is disposed can be defined as the second layer. Figure 6 The first source electrode SD1 and the first drain electrode SD2 and the second source electrode SD3 and the second drain electrode SD4 , which have been described in , are provided on the same layer.

[0142] In addition, a first planarization layer 118 is provided on the first data line SDL1 provided on the second layer. The first planarization layer 118 planarizes the upper portion of the first data line SDL1 provided on the second layer. In addition, the first planarization layer 118 insulates the first data line SDL1 provided on the second layer from the second data line SDL2 provided on the third layer.

[0143] That is, the metal layer on which the second data line SDL2 is disposed may be defined as a third layer. Figure 6 The intermediate electrode CNE described in is formed on the same layer.

[0144] However, the voltage applied to the first and second data lines SDL1 and SDL2 may be various voltages such as a reference voltage VREF, a high potential voltage VDD, and a low potential voltage VSS, without being limited to the data voltage VDATA.

[0145] In addition, the second planarization layer 119 is disposed on the second data line SDL2 disposed on the third layer. The second planarization layer 119 planarizes an upper portion of the second data line SDL2 disposed on the third layer.

[0146] In addition, a bank layer BNK and a cathode electrode CAT may be formed on the second planarization layer 119 in a region except for the transmission hole TH.

[0147] Further, an encapsulation layer 120 is disposed on the second planarization layer 119 and the cathode electrode CAT in the entire region including the transmission hole TH, in which a first encapsulation layer 121 , a second encapsulation layer 122 , and a third encapsulation layer 123 are sequentially stacked.

[0148] That is, the first data line SDL1 of the second layer may be disposed on the gate line GL5 of the first layer. In addition, the second data line SDL2 of the third layer may be disposed on the first data line SDL1 of the second layer.

[0149] At the same time, refer to Figure 5 , a plurality of gate connection lines GCL1, GCL2 and GCL3 and a plurality of gate jumper lines GJL1 and GJL2 may be provided on the second layer. More specifically, referring to Figure 7 The third gate connection line GCL3 and the second gate jumper line GJL2 may be disposed on the second layer. Further, the second gate jumper line GJL2 contacts the fifth gate line GL5 through the contact hole, and the third gate connection line GCL3 also contacts the fifth gate line GL5 through the contact hole.

[0150] Therefore, the second and fifth gate lines GL2 and GL5 , the second gate jumper line GJL2 , and the third gate link line GCL3 may all transmit the emission signal EM.

[0151] At the same time, refer to Figure 5 , a plurality of transmission holes TH may be provided in the transmission unit TA of the first display area A1.

[0152] In addition, as described above, the number of the plurality of gate link lines GCL1 , GCL2 , and GCL3 disposed in the transmission unit TA of the first display area A1 may be smaller than the number of the plurality of gate lines GL1 to GL5 .

[0153] That is, the area of ​​the first display region A1 is limited, but the number of wirings to be provided is reduced, so that the area of ​​each of the plurality of transmissive holes TH can be relatively increased.

[0154] Unlike the display device according to the exemplary embodiment of the present disclosure, if the number of the plurality of gate connection lines GCL1, GCL2, and GCL3 provided in the transmission unit TA of the first display area A1 is equal to the number of the plurality of gate lines GL1 to GL5, the plurality of gate connection lines GCL1, GCL2, and GCL3 occupy a larger area in the transmission unit TA of the first display area A1. Therefore, the area of ​​the transmission hole TH can be relatively small.

[0155] That is, if the number of the plurality of gate link lines GCL1, GCL2, GCL3 disposed in the transmission unit TA of the first display area A1 is equal to the number of the plurality of gate lines GL1-GL5, the area ratio of the transmission hole TH can be measured to be 23.9%.

[0156] However, as in the display device according to the exemplary embodiment of the present disclosure, if the number of the plurality of gate connection lines GCL1, GCL2, and GCL3 provided in the transmission unit TA of the first display area A1 is smaller than the number of the plurality of gate lines GL1 to GL5, the area occupied by the plurality of gate connection lines GCL1, GCL2, and GCL3 in the transmission unit TA of the first display area A1 is reduced. Therefore, the area of ​​the transmission hole TH can be relatively large.

[0157] That is, if the number of the plurality of gate link lines GCL1, GCL2, GCL3 disposed in the transmission unit TA of the first display area A1 is smaller than the number of the plurality of gate lines GL1-GL5, the area ratio of the transmission hole TH can be measured to be 52.4%.

[0158] That is, according to the exemplary embodiment of the present disclosure, the area ratio of the transmission hole TH is increased by 21.4%, so that the amount of light detectable by the sensor can be increased.

[0159] As a result, according to exemplary embodiments of the present disclosure, the sensing performance of the sensor may be improved.

[0160] Meanwhile, the shapes of the plurality of transmissive holes TH may be determined according to the shape of the second data line SDL2 .

[0161] like Figure 5As shown, the shape of the second data line SDL2 is circular, so that the boundaries of the plurality of transmissive holes TH may also be circular.

[0162] However, the shapes of the plurality of transmissive holes TH may be deformed into various shapes, such as an elliptical shape, without being limited to a circular shape.

[0163] Figure 9 is a view illustrating a placement relationship of a transmission unit in a display device according to an exemplary embodiment of the present disclosure.

[0164] Reference Figure 5 , the plurality of transmissive holes TH may be continuously disposed not only in the first direction D1 but also in the second direction D2. That is, the plurality of transmissive holes TH may be disposed in a matrix form.

[0165] Therefore, refer to Figure 9 , the transmission units may be disposed in a matrix form in the first display area A1 so as to be continuously disposed in the first direction D1 and the second direction D2.

[0166] Figure 10A and Figure 10B is a graph illustrating a modulation transfer function (MTF) of a transmission unit TA in a display device according to an exemplary embodiment of the present disclosure.

[0167] MTF indicates the ability of a lens to display the contrast of a sample as an image using spatial frequency (lp / mm), and the unit is %.

[0168] Meanwhile, at a spatial frequency of 120 lp / mm or less, the target MTF of the display device must be 30% or higher. In a display device, if the MTF of the transmissive unit TA is 30% or lower at 120 lp / mm or less, there is a problem of deteriorating the optical performance of the sensor.

[0169] Specifically, in Figure 10A In the embodiment, the MTF of the transmission unit TA is measured with respect to the X-axis as the first direction, and Figure 10B , the MTF is measured with respect to the Y-axis as the second direction.

[0170] In addition, refer to Figure 10A and Figure 10B , the MTF was measured when the transmittance T of the transmission unit TA was 30%, 35%, and 40%.

[0171] Reference Figure 10A, as in the display device according to the exemplary embodiment of the present disclosure, when the transmissive holes TH are continuously arranged in the first direction D1 and the second direction D2, and the transmittance T is 30%, 35%, and 40%, it is confirmed that: at a spatial frequency of 120 lp / mm or less, the MTF based on the X-axis is 30% or greater.

[0172] Further, refer to Figure 10B , as in the display device according to the exemplary embodiment of the present disclosure, when the transmissive holes TH are continuously arranged in the first direction D1 and the second direction D2, and the transmittance T is 30%, 35% and 40%, it is confirmed that: at a spatial frequency of 120lp / mm or less, the MTF based on the Y-axis is 30% or greater.

[0173] That is, it is confirmed that the display device according to the exemplary embodiment of the present disclosure achieves the MTF target value. Therefore, it is confirmed that the display device according to the exemplary embodiment of the present disclosure includes the transmissive holes TH continuously arranged in the first direction D1 and the second direction D2, thereby improving the optical performance of the sensor.

[0174] A display device according to another exemplary embodiment of the present disclosure is described below.

[0175] A display device according to another exemplary embodiment of the present disclosure differs from the display device according to the exemplary embodiment of the present disclosure in that the shape of the second data line and the shape of the plurality of transmissive holes are different. Therefore, in the display device according to another exemplary embodiment of the present disclosure and the display device according to the exemplary embodiment of the present disclosure, the following description will be made by denoting the same components with the same reference numerals and denoting different components with different reference numerals.

[0176] Figure 11 is a view illustrating a detailed layout of a first display area of ​​a display panel of a display device according to another exemplary embodiment of the present disclosure.

[0177] In the transmission unit TA' of the first display area A1, a plurality of transmission holes TH1 and TH2 may be provided, and shapes of the plurality of transmission holes TH1 and TH2 may be determined according to the shape of the second data line SDL2'.

[0178] like Figure 11 As shown, the shape of the second data line SDL2 ′ is circular or elliptical, so that the boundaries of the plurality of transmissive holes TH1 and TH2 may also be circular or elliptical.

[0179] In other words, in a display device according to another exemplary embodiment of the present disclosure, the plurality of transmissive holes TH1 and TH2 may include a circular first transmissive hole TH1 and an elliptical second transmissive hole TH2. Furthermore, the size of the second transmissive hole TH2 may be larger than that of the first transmissive hole TH1. Furthermore, the elliptical second transmissive hole TH2 may have a major axis in the second direction D2. Furthermore, the first transmissive holes TH1 and the second transmissive holes TH2 may be alternately arranged in the first direction, and the plurality of second transmissive holes TH2 may be continuously arranged in the second direction D2.

[0180] Therefore, in the first display area A1 ′ of the display panel of the display device according to another exemplary embodiment of the present disclosure, the transmission units TA′ may be disposed in a matrix form so as to be continuously disposed in the first direction D1 and the second direction D2 .

[0181] Further, the ratio of the transmission area of ​​the first transmission hole TH1 is 56.2%, and the ratio of the transmission area of ​​the second transmission hole TH2 is 65.0%, so that in the first display area A1' of the display panel of the display device according to another exemplary embodiment of the present disclosure, the ratio of the transmission area of ​​the transmission unit TA' can be 46.5%.

[0182] Therefore, according to another exemplary embodiment of the present disclosure, the areas of the transmission holes TH1 and TH2 are increased by 21.4% of the area of ​​the transmission hole TH of the exemplary embodiment of the present disclosure, so that the amount of light detectable by the sensor may be further increased.

[0183] Therefore, according to another exemplary embodiment of the present disclosure, the sensing performance of the sensor may be further improved.

[0184] Exemplary embodiments of the present disclosure can also be described as follows.

[0185] According to one aspect of the present disclosure, a display device includes: at least one sensor; and a display panel, the display panel being divided into a first display area overlapping the at least one sensor, and a second display area, wherein a first pixel unit and a transmission unit are provided in the first display area, and at least one pixel is provided in the first pixel unit; a second pixel unit is provided in the second display area, and at least one pixel is provided in the second pixel unit, and the transmission unit is continuously provided in a first direction and in a second direction different from the first direction, thereby improving a modulation transfer function (MTF) characteristic of the sensor.

[0186] In the first pixel unit, multiple signal lines electrically connected to at least one pixel in the first pixel unit can be set, and in the transmission unit, multiple signal connection lines electrically connected to the multiple signal lines can be set, and the number of the multiple signal connection lines can be less than the number of the multiple signal lines.

[0187] Among a plurality of signal lines, wirings configured to output the same signal may be connected by one signal connection line.

[0188] The plurality of signal lines and the plurality of signal connection lines may all extend in the first direction.

[0189] Among a plurality of signal lines, wirings configured to output the same signal may be connected by a signal jumper line.

[0190] The signal jumper may extend in the second direction.

[0191] A plurality of signal lines may be provided on a first layer, and a plurality of signal connection lines may be provided on a second layer on the first layer.

[0192] A gate electrode of a transistor included in at least one pixel in the first pixel unit may be provided on a first layer, and a source electrode and a drain electrode of a transistor included in at least one pixel in the first pixel unit may be provided on a second layer.

[0193] A plurality of transmissive holes may be provided in the transmissive unit, and boundaries of the plurality of transmissive holes may be formed by wirings on the third layer formed on the second layer.

[0194] The plurality of transmissive holes may have a circular shape and may be continuously disposed in the first and second directions.

[0195] The plurality of transmissive holes may include first and second transmissive holes having different sizes, and at least one of the first and second transmissive holes has an elliptical shape having a major axis in the second direction.

[0196] The first transmission holes and the second transmission holes may be alternately arranged in the first direction.

[0197] According to another embodiment of the present disclosure, a display device includes: at least one sensor; and a display panel, in which a plurality of gate lines extending in a first direction, a plurality of data lines extending in a second direction, and a plurality of pixels are formed, and in a transmissive region of the display panel overlapping with the at least one sensor, a plurality of transmissive holes are arranged in the first direction and the second direction, thereby improving the modulation transfer function (MTF) characteristics of the sensor.

[0198] Each of the plurality of transmissive holes may have a circular shape or an elliptical shape.

[0199] The plurality of transmissive holes may include first transmissive holes and second transmissive holes having different sizes, and the first transmissive holes and the second transmissive holes may be alternately disposed.

[0200] In the transmissive region, a plurality of gate lines configured to output the same signal may be integrated together through one gate connection line.

[0201] In the transmissive area, a plurality of gate lines configured to output the same signal are connected through one gate jumper line.

[0202] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all aspects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be understood to fall within the scope of the present disclosure.

Claims

1. A display device comprising: at least one sensor; as well as a display panel divided into a first display area overlapping the at least one sensor and a second display area; In which, in the first display area, a first pixel unit and a transmission unit are set, and at least one pixel is set in the first pixel unit. In the second display area, a second pixel unit is set, and at least one pixel is set in the second pixel unit, and the transmission unit is continuously arranged in a first direction and a second direction different from the first direction.

2. The display device according to claim 1, wherein In the first pixel unit, a plurality of signal lines electrically connected to the at least one pixel in the first pixel unit are provided, and in the transmission unit, a plurality of signal connection lines electrically connected to the plurality of signal lines are provided, and the number of the plurality of signal connection lines is less than the number of the plurality of signal lines.

3. The display device according to claim 2, wherein: Among the plurality of signal lines, wirings configured to output the same signal are connected by one signal connection line.

4. The display device according to claim 2, wherein The plurality of signal lines and the plurality of signal connection lines all extend in the first direction.

5. The display device according to claim 4, wherein Among the plurality of signal lines, wirings configured to output the same signal are connected by a signal jumper line. The display device according to claim 5 , wherein: The signal jumper extends in the second direction.

7. The display device according to claim 2, wherein: The plurality of signal lines are provided on a first layer, and the plurality of signal connection lines are provided on a second layer on the first layer.

8. The display device according to claim 7, wherein: A gate electrode of a transistor included in the at least one pixel in the first pixel unit is disposed on the first layer, and a source electrode and a drain electrode of the transistor included in the at least one pixel in the first pixel unit are disposed on the second layer.

9. The display device according to claim 7, wherein: A plurality of transmission holes are provided in the transmission unit, and boundaries of the plurality of transmission holes are formed by wirings formed on a third layer on the second layer.

10. The display device according to claim 9, wherein The plurality of transmissive holes have a circular shape and are continuously arranged in the first direction and the second direction.

11. The display device according to claim 9, wherein The plurality of transmissive holes include a first transmissive hole and a second transmissive hole having different sizes, and at least one of the first transmissive hole and the second transmissive hole has an elliptical shape having a major axis in the second direction.

12. The display device according to claim 11, wherein The first transmission holes and the second transmission holes are alternately arranged in the first direction.

13. A display device comprising: at least one sensor; as well as a display panel in which a plurality of gate lines extending in a first direction, a plurality of data lines extending in a second direction, and a plurality of pixels are formed; Wherein, in a transmission area of ​​the display panel overlapping with the at least one sensor, a plurality of transmission holes are arranged in the first direction and the second direction.

14. The display device according to claim 13, wherein: Each of the plurality of transmissive holes has a circular shape or an elliptical shape.

15. The display device according to claim 13, wherein The plurality of transmissive holes include first transmissive holes and second transmissive holes, the first transmissive holes and the second transmissive holes have different sizes, and the first transmissive holes and the second transmissive holes are alternately arranged.

16. The display device according to claim 13, wherein In the transmissive region, a plurality of gate lines configured to output the same signal are integrated together by one gate connection line.

17. The display device according to claim 13, wherein: In the transmissive region, a plurality of gate lines configured to output the same signal are connected through a gate jumper line.

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