Imaging device and electronic device

Abstract

The present invention can reduce power consumption and improve image quality of a captured image. An imaging device according to the present disclosure is provided with: a pixel circuit having a photoelectric conversion unit and an amplification transistor in which a gate electrode is connected to the photoelectric conversion unit; a first signal line connected to one electrode side of the amplification transistor; a switching unit connected to the first signal line; a second signal line connected to the other electrode side of the amplification transistor; the comparison input end of the comparator is connected to the second signal line; a selector connected to the first signal line and an output terminal of the comparator; and the counter is connected to the output end of the selector. The switching unit is provided with: a first switching element selectively connecting a first signal line to a power supply node; and a second switching element selectively connecting the first signal line to a current source.

Description

Technical Field

[0001] The present technology relates to an imaging device, and more particularly to an imaging device having a function for reducing power consumption, and an electronic device having the imaging device. Background Art

[0002] For example, in imaging devices such as complementary metal oxide semiconductor (CMOS) image sensors, technologies for reducing power consumption are known. As such technologies for reducing power consumption, for example, a technology for reducing power consumption by reading pixel signals using a pulse width modulation (PWM) method has been proposed (for example, see Patent Document 1).

[0003] Reference List

[0004] Patent Literature

[0005] Patent Document 1: International Publication No. 2007 / 000879 Summary of the Invention

[0006] Problems to be solved by the present invention

[0007] As with the conventional technology described above, power consumption can be reduced by reading pixel signals using a pulse width modulation method. However, since the conventional technology described above has a pixel configuration in which the potential VPD of the photodiode is read using a grounded source amplifier, the image quality of the captured image is lower than that of a pixel configuration in which the pixel signal is read using a source follower circuit (grounded drain circuit) having good frequency characteristics.

[0008] The present technology has been made in view of such circumstances, and an object thereof is to achieve reduction in power consumption and improvement in image quality of captured images.

[0009] Solution to the problem

[0010] The present technology has been developed to address the above-mentioned issues, and in its first aspect, an imaging device includes: a pixel circuit including a photoelectric conversion unit and an amplifier transistor, a gate electrode of the amplifier transistor being connected to the photoelectric conversion unit; a first signal line connected to one electrode side of the amplifier transistor; a switching unit connected to the first signal line; a second signal line connected to the other electrode side of the amplifier transistor; a comparator having a comparison input terminal connected to the second signal line; a selector connected to the first signal line and an output terminal of the comparator; and a counter connected to the output terminal of the selector, wherein the switching unit includes a first switching element that selectively connects the first signal line to a power supply node, and a second switching element that selectively connects the first signal line to a current source. This results in the effects of achieving reduced power consumption and improved image quality of captured images.

[0011] Furthermore, in the first aspect, the switching unit can set a first imaging mode in which the image quality of the captured image is relatively high by turning on the first switching element and turning off the second switching element, and can set a second imaging mode in which the power consumption is relatively low by turning off the first switching element and turning on the second switching element. This provides the advantage of being able to set the first imaging mode as a high-image-quality mode and the second imaging mode as a low-power-consumption mode.

[0012] Furthermore, in the first aspect, the pixel circuit may include a charge-voltage conversion unit that converts the charge photoelectrically converted by the photoelectric conversion unit into a voltage, a source follower circuit being formed when the first imaging mode is set, and the voltage of the charge-voltage conversion unit is read to the second signal line via the source follower circuit. This results in an effect that a captured image with relatively high image quality can be obtained when the first imaging mode is set.

[0013] Furthermore, in the first aspect, the pixel circuit may include a charge-voltage conversion unit that converts the charge photoelectrically converted by the photoelectric conversion unit into a voltage, a grounded source amplifier being formed when the second imaging mode is set, and the voltage of the charge-voltage conversion unit being read to the first signal line via the grounded source amplifier. This allows imaging to be performed with relatively low power consumption when the second imaging mode is set.

[0014] Furthermore, in the first aspect, when the second imaging mode is set, the pixel circuit can read the change in the potential of the charge-voltage conversion unit as the pulse width of the digital pulse. This has the effect of reducing power consumption by reading the change in the potential of the charge-voltage conversion unit as the pulse width of the digital pulse.

[0015] Furthermore, in the first aspect, when an event is detected during imaging in the second imaging mode, the switching unit can switch to the first imaging mode and perform imaging. This has the effect of reducing power consumption until the event is detected, and obtaining a captured image with relatively high image quality after the event is detected.

[0016] Furthermore, in the first aspect, when the second imaging mode is set, the current of the current source can be set to a ramp shape that changes linearly with a predetermined gradient over time. This has the effect of improving the dynamic range by allowing the potential of the charge-voltage conversion unit to exceed the threshold level and detect light intensity even under low illumination.

[0017] Furthermore, in the first aspect, a sample-and-hold circuit may be provided to sample and hold the pixel signal output from the pixel circuit when the first imaging mode is set. This allows for reduced power consumption and improved image quality of captured images, even in an imaging device including the sample-and-hold circuit.

[0018] Furthermore, in the first aspect, when the pixel circuit further includes a reset transistor for resetting the charge-voltage conversion unit, the power supply voltage to be applied to the amplifying transistor and the power supply voltage to be applied to the reset transistor can be set to different power supply voltages. This results in the effect of reducing power consumption and improving the image quality of captured images, even in an imaging device in which the power supply voltage applied to the amplifying transistor and the power supply voltage applied to the reset transistor are different.

[0019] In addition, a second aspect of the present technology is an electronic device including an imaging device, the imaging device comprising: a pixel circuit including a photoelectric conversion unit and an amplifier transistor, the gate electrode of the amplifier transistor being connected to the photoelectric conversion unit; a first signal line connected to one electrode side of the amplifier transistor; a switching unit connected to the first signal line; a second signal line connected to the other electrode side of the amplifier transistor; a comparator having a comparison input terminal connected to the second signal line; a selector connected to the first signal line and an output terminal of the comparator; and a counter connected to the output terminal of the selector, wherein the switching unit includes a first switching element that selectively connects the first signal line to a power supply; and a second switching element that selectively connects the first signal line to a current source. This results in the effects of reducing power consumption and improving the image quality of captured images. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a system configuration diagram illustrating a configuration example of an imaging device according to a first embodiment of the present technology.

[0021] Figure 2 It is an explanatory diagram of an imaging mode of the imaging device according to the first embodiment of the present technology.

[0022] Figure 3 : is a circuit diagram showing a circuit example of a pixel circuit, a switching unit for one pixel column, and an analog-to-digital conversion circuit of the imaging device according to the first embodiment of the present technology.

[0023] Figure 4 is a timing chart for describing an operation example in the first imaging mode of the imaging device according to the first embodiment of the present technology.

[0024] Figure 5 is a timing chart for describing an operation example in the second imaging mode of the imaging device according to the first embodiment of the present technology.

[0025] Figure 6 1 is an exploded perspective view schematically showing a stacked chip structure 1 of a semiconductor chip structure of an imaging device according to a first embodiment of the present technology.

[0026] Figure 7 1 is an exploded perspective view schematically showing a stacked chip structure 2 of a semiconductor chip structure of an imaging device according to a first embodiment of the present technology.

[0027] Figure 8 is a circuit diagram showing an arrangement example of a pixel circuit, a switching unit, and an analog-to-digital conversion circuit corresponding to the stacked chip structure 2 .

[0028] Figure 9 is a timing chart for describing an operation example in the second imaging mode of the imaging device according to the second embodiment of the present technology.

[0029] Figure 10 is a system configuration diagram illustrating a configuration example of an imaging device according to a third embodiment of the present technology.

[0030] Figure 11 : is a circuit diagram showing a circuit example of a pixel circuit, a sample-and-hold circuit for one pixel column, a switching unit, and an analog-to-digital conversion circuit of an imaging device according to a third embodiment of the present technology.

[0031] Figure 12 is a timing chart for describing an operation example in the second imaging mode of the imaging device in the third embodiment of the present technology.

[0032] Figure 13 : is a circuit diagram showing a circuit example of a pixel circuit, a sample-and-hold circuit for one pixel column, a switching unit, and an analog-to-digital conversion circuit of an imaging device according to a fourth embodiment of the present technology.

[0033] Figure 14 is a diagram illustrating on / off of the first to fourth switching elements in each imaging mode and a relationship with each connection-destination power supply of the reset transistor and the amplifying transistor.

[0034] Figure 15 is a block diagram illustrating a configuration example of a camera system as an example of an electronic device to which the present technology is applied.

[0035] Figure 16 is a block diagram showing a schematic configuration example of a vehicle control system.

[0036] Figure 17 1 is an explanatory diagram showing an example of the installation position of the imaging section. DETAILED DESCRIPTION

[0037] Hereinafter, modes for carrying out the present technology (hereinafter, referred to as embodiments) will be described. The description will be given in the following order.

[0038] 1. First embodiment (basic configuration example of the present technology)

[0039] 1-1. Configuration Example of Imaging Device

[0040] 1-2. Circuit Examples of Pixel Circuit, Switching Unit, and Analog-to-Digital Conversion Circuit

[0041] 1-3. Operation Example of Imaging Device

[0042] 1-4. Semiconductor Chip Structure

[0043] 2. Second Embodiment (Example of Improving Dynamic Range When Setting the Second Imaging Mode)

[0044] 3. Third Embodiment (Application Example of an Imaging Device Including a Sample-and-Hold Circuit, Which Samples and Holds an Output Pixel Signal When a First Imaging Mode is Set)

[0045] 4. Fourth Embodiment (Modification of the Third Embodiment: Application Example to an Imaging Device in Which the Power Sources of the Reset Transistor and the Amplification Transistor Are Different)

[0046] 5. Modifications

[0047] 6. Examples of Imaging Device Usage

[0048] 7. Possible configurations of this technology

[0049] <First embodiment>

[0050] As an imaging device according to the first embodiment of the present technology, for example, a CMOS image sensor, which is a type of XY address system imaging device, can be exemplified. A CMOS image sensor is an imaging device manufactured by applying or partially using a CMOS process. The fact that the imaging device is, for example, a CMOS image sensor is similar in each of the embodiments described later.

[0051] [Configuration Example of Imaging Device]

[0052] Figure 1 1 is a system configuration diagram illustrating an example configuration of an imaging device according to a first embodiment of the present technology. The imaging device 10 according to the first embodiment of the present technology is a basic configuration example of the present technology, and has a configuration including a pixel array unit 11 and peripheral circuit units of the pixel array unit 11. The peripheral circuit units of the pixel array unit 11 include, for example, a vertical scanning unit 12, an imaging mode setting unit 13, an analog-to-digital conversion unit 14, a memory unit, a data processing unit 16, an output unit 17, a timing control unit 18, and the like.

[0053] The pixel array unit 11 has a configuration in which pixel circuits (pixels) 20 including photoelectric conversion units (photoelectric conversion elements) are arranged two-dimensionally in the row direction and the column direction (i.e., in a matrix form). Here, the row direction indicates the arrangement direction of the pixel circuits 20 in the pixel rows, and the column direction indicates the arrangement direction of the pixel circuits 20 in the pixel columns. The pixel circuits 20 perform photoelectric conversion in the photoelectric conversion units to generate and accumulate photoelectric charges corresponding to the amount of incident light. Figure 1 In the example shown, the pixel array of the pixel array unit 11 is an array of m rows and n columns (m and n are integers). That is, "m" represents the number of rows, and "n" represents the number of columns.

[0054] In the pixel array unit 11, a pixel control line 31 is wired for each pixel row for a pixel array of m rows and n columns. In addition, a first signal line 32 and a second signal line 33 are wired for each pixel column.

[0055] When reading a signal from the pixel circuit 20, the pixel control line 31 transmits a drive signal output from the vertical scanning unit 12 in units of pixel rows. Figure 1 , the pixel control line 31 is shown as one wiring, but the number is not limited to one. One end of the pixel control line 31 is connected to the output terminal corresponding to each row of the vertical scanning unit 12. The first signal line 32 transmits the signal read from the pixel circuit 20 to the imaging mode setting unit 13. The second signal line 33 transmits the signal read from the pixel circuit 20 to the analog-to-digital conversion unit 14.

[0056] Hereinafter, each component in the peripheral circuit unit of the pixel array unit 11, namely, the vertical scanning unit 12, the imaging mode setting unit 13, the analog-to-digital conversion unit 14, the memory unit, the data processing unit 16, the output unit 17 and the timing control unit 18 will be described.

[0057] The vertical scanning unit 12 includes a shift register, an address decoder, and the like, and controls scanning of pixel rows and addresses of pixel rows based on a timing control signal supplied from the timing control unit 18 when selecting each pixel circuit 20 in the pixel array unit 11. Although a specific configuration of the vertical scanning unit 12 is not shown, the vertical scanning unit 12 generally includes two scanning systems: a read scanning system and a clear scanning system.

[0058] The read scanning system sequentially and selectively scans the pixel circuits 20 in the pixel array unit 11 row by row to read pixel signals from the pixel circuits 20. The pixel signals read from the pixel circuits 20 are analog signals. The sweep scanning system performs a sweep scanning on the read rows to be read scanned by the read scanning system, the sweep scanning being performed earlier than the read scanning by a time corresponding to the shutter speed.

[0059] When the sweep scan is performed by the sweep scan system, unnecessary charges are cleared from the photoelectric conversion units of the pixel circuits 20 in the read row. Thus, the photoelectric conversion units are reset. Then, when the sweep scan system clears (resets) the unnecessary charges, a so-called electronic shutter operation is performed. Here, the electronic shutter operation refers to an operation in which the photoelectric conversion units are released and exposure is restarted (accumulation of photoelectric charges is restarted).

[0060] The signal read by the read scanning system during the read operation corresponds to the amount of light received during the immediately preceding read operation or after the electronic shutter operation. The period from the read timing during the immediately preceding read operation or the clearing time during the immediately preceding electronic shutter operation to the read timing during the current read operation is the exposure period for the photocharge in the pixel circuit 20.

[0061] like Figure 2 As shown, the imaging device 10 according to the first embodiment is configured to be able to set a first imaging mode as a high image quality mode and a second imaging mode as a low power consumption mode. For example, in a place where there is no socket or power supply equipment in the installation location of the camera system including the imaging device 10 (such as a high place, a narrow space or outdoors), a battery is used as a driving source. In a case where the imaging device 10 is always in an imaging state (i.e., always on) when driven by the battery, the second imaging mode (i.e., low power consumption mode) is set to reduce power consumption. Then, when an event is detected, the mode is switched to the first imaging mode to obtain a high-definition captured image, and the first imaging mode is a high image quality mode for obtaining a high-resolution captured image in all pixels.

[0062] The imaging mode setting unit 13 appropriately sets the first imaging mode and the second imaging mode. Details of the first imaging mode and the second imaging mode, and details of setting the first imaging mode and the second imaging mode by switching control of the imaging mode setting unit 13 will be described later.

[0063] The analog-to-digital (A / D) conversion unit 14 converts an analog pixel signal read from the pixel circuit 20 to the first signal line 32 and provided via the imaging mode setting unit 13, or an analog pixel signal read from the pixel circuit 20 to the second signal line 33 and provided directly from the second signal line 33, into a digital pixel signal.

[0064] The memory unit stores the analog-to-digital conversion result in the analog-to-digital conversion unit 14 under processing by the data processing unit 16 .

[0065] The data processing unit 16 is a digital signal processing unit that processes the digital pixel signal output from the analog-to-digital conversion unit 14 and performs processing of writing / reading the analog-to-digital conversion result to / from the memory unit and performs various processing on the analog-to-digital conversion result.

[0066] The output unit 17 derives the signal processed by the data processing unit 16 as an imaging output.

[0067] The timing control unit 18 generates various timing signals, clock signals, control signals, etc. based on a synchronization signal supplied from the outside. Then, the timing control unit 18 performs drive control of the vertical scanning unit 12, the imaging mode setting unit 13, the analog-to-digital conversion unit 14, the memory unit, the data processing unit 16, etc. based on the generated signals.

[0068] [Circuit Examples of Pixel Circuit, Switching Unit, and Analog-to-Digital Conversion Circuit]

[0069] The imaging mode setting unit 13 includes a plurality of switching units 130 provided corresponding to the pixel columns of the pixel array unit 11. In addition, the analog-to-digital (A / D) conversion unit 14 has a so-called column-parallel analog-to-digital conversion unit configuration including a plurality of analog-to-digital conversion circuits 140 provided corresponding to the pixel columns of the pixel array unit 11. Figure 3 is a circuit diagram showing a circuit example of the pixel circuit 20 , the switching unit 130 for one pixel column, and the analog-to-digital conversion circuit 140 . Figure 3 One pixel circuit 20 for each of the selected pixel rows and the unselected pixel rows is shown. Note that Figure 3 A state corresponding to an operation example in the second imaging mode is shown (transistor off).

[0070] (Pixel circuit)

[0071] The pixel circuit 20 has a circuit configuration including a photoelectric conversion unit 21 , a transfer transistor 22 , a charge-voltage conversion unit 23 , a reset transistor 24 , an amplification transistor 25 , and a selection transistor 26 .

[0072] Here, for example, N-channel metal oxide semiconductor (MOS) field effect transistors (hereinafter referred to as MOS transistors) can be used as the transfer transistor 22, the reset transistor 24, the amplifying transistor 25, and the selecting transistor 26. However, the combination of the conductivity types of the four MOS transistors 22, 24, 25, and 26 exemplified here is only an example, and the combination is not limited thereto.

[0073] For the pixel circuits 20, a plurality of pixel control lines are wired so as to be common to the pixel circuits 20 in the same pixel row as the above-mentioned pixel control lines 31. The plurality of pixel control lines are connected in units of pixel rows to output terminals corresponding to each pixel row of the vertical scanning unit 12. The vertical scanning unit 12 appropriately outputs a transfer signal TRG, a reset signal RST, and a selection signal SEL to the plurality of pixel control lines.

[0074] The photoelectric conversion unit 21 is a PN junction photodiode (PD). The photodiode has an anode electrode connected to a low-potential side power supply (for example, ground), and generates and accumulates charge according to the amount of incident light.

[0075] The transfer transistor 22 transfers the charge accumulated in the photoelectric conversion unit 21 to the charge-voltage conversion unit 23 in accordance with the transfer signal TRG supplied from the vertical scanning unit 12. Specifically, the transfer signal TRG activated at a high level is supplied from the vertical scanning unit 12 to the gate electrode of the transfer transistor 22. Then, the transfer transistor 22 is turned on and transfers the charge accumulated in the photoelectric conversion unit 21 to the charge-voltage conversion unit 23.

[0076] The charge-voltage conversion unit 23 is a capacitor C of a floating diffusion (FD) region formed between the drain region of the transfer transistor 22 and the source region of the reset transistor 24. FD The charge-voltage conversion unit 23 converts the charge transferred from the photoelectric conversion unit 21 through the transfer transistor 22 into a voltage.

[0077] The reset transistor 24 has a source electrode connected to the charge-voltage conversion unit 23 and a drain electrode connected to the first signal line 32. A reset signal RST activated at a high level is supplied from the vertical scanning unit 12 to the gate electrode of the reset transistor 24. Then, when the reset signal RST becomes a high level, the reset transistor 24 is turned on to electrically connect the charge-voltage conversion unit 23 and the first signal line 32.

[0078] The gate electrode of the amplifying transistor 25 is connected to the charge-voltage conversion unit 23, the drain electrode connected to the first signal line 32, and the source electrode connected to the second signal line 33 via the selection transistor 26. Note that the drain electrode of the amplifying transistor 25 is an example of one electrode described in the claims, and the source electrode is an example of the other electrode described in the claims.

[0079] The selection transistor 26 selects any pixel circuit 20 in the pixel array unit 11 under selective scanning by the vertical scanning unit 12. The selection transistor 26 is connected between the source electrode of the amplifying transistor 25 and the second signal line 33, and a selection signal SEL activated at a high level is supplied from the vertical scanning unit 12 to the gate electrode of the selection transistor 26. Then, when the selection signal SEL becomes a high level, the selection transistor 26 is turned on to select the pixel circuit 20.

[0080] For example, the imaging device 10 according to the first embodiment has a stacked chip structure as a semiconductor chip structure in which at least two semiconductor substrates, a first semiconductor substrate 41 and a second semiconductor substrate 42, are stacked. In this stacked chip structure, the pixel circuit 20 and the first and second signal lines 32 and 33 are formed on the first semiconductor substrate 41 side, and the imaging mode setting unit 13 and the analog-to-digital conversion unit 14 are formed on the second semiconductor substrate 42 side. The details of the semiconductor chip structure will be described later.

[0081] The first signal line 32 on the first-layer semiconductor substrate 41 and the imaging mode setting unit 13 on the second-layer semiconductor substrate 42 are electrically connected via a connection unit 43 such as a Cu-Cu connection, a through-silicon via (TSV), or a micropump. The second signal line 33 on the first-layer semiconductor substrate 41 and the analog-to-digital conversion unit 14 on the second-layer semiconductor substrate 42 are also electrically connected via a similar connection unit 43.

[0082] (Switching unit)

[0083] The switching unit 130 of the imaging mode setting unit 13 includes a first switching element S1, a second switching element S2, and a current source 131. The switching unit is set for each pixel column in the pixel array unit 11 and switches the imaging mode of the imaging device 10. One end of the first switching element S1 is electrically connected to the first signal line 32 via the connecting unit 43, and the other end is connected to the node (power supply node) of the high potential side power supply voltage VH. One end of the second switching element S2 is electrically connected to the first signal line 32 via the connecting unit 43. The current source 131 is connected between the other end of the second switching element S2 and the node of the low potential side power supply voltage VL. The on / off control of the first switching element S1 and the second switching element S2 is based on the Figure 1 The timing control unit 18 shown in FIG. 1 is provided with a control signal (not shown) to execute the timing control unit 18 shown in FIG.

[0084] In the switching unit 130 having the above configuration, the first switching element S1 is turned on (closed) and the high-potential-side power supply voltage VH is applied to the first signal line 32, thereby setting the first imaging mode in which the image quality of the captured image is relatively high as the imaging mode of the imaging device 10. At this time, the second switching element S2 is in a disconnected (open) state.

[0085] In the first imaging mode, the pixel circuit 20 is used as a source follower circuit (grounded drain circuit) by applying the high-potential-side power supply voltage VH to the drain electrodes of the reset transistor 24 and the amplifier transistor 25 of the pixel circuit 20 via the first signal line 32. That is, in the first imaging mode, when the pixel circuit 20 forms a source follower circuit, a pixel signal at a level corresponding to the charge accumulated in the charge-voltage conversion unit 23 is read out by the source follower circuit to the second signal line 33, and is provided to the analog-to-digital conversion circuit 140 through the second signal line 33 and the connection unit 43.

[0086] The second switching element S2 is turned on and supplies the current IR of the current source 131 to the first signal line 32, thereby setting the second imaging mode in which power consumption is low over a relatively long period as the imaging mode of the imaging device 10. At this time, the first switching element S1 is in an off state.

[0087] In the second imaging mode, the drain electrodes of the reset transistor 24 and the amplifier transistor 25 of the pixel circuit 20 are connected to the current source 131 via the first signal line 32, and the load MOS 141 is used as a switch, so that the pixel circuit 20 is used as a grounded source amplifier. That is, in the second imaging mode, when the pixel circuit 20 forms a grounded source amplifier, the change in the potential FD of the charge-voltage conversion unit 23 is provided to the analog-to-digital conversion circuit 140 via the connection unit 43 and the third signal line 34, so that the change is read as the pulse width of a digital pulse. The operation of reading the change in the potential FD of the charge-voltage conversion unit 23 as the pulse width of a digital pulse is a pulse width modulation (PWM) operation. The details of reading the pixel signal through the PWM operation will be described later.

[0088] Regarding the imaging modes of the imaging device 10, the first imaging mode in which the image quality of the captured image is relatively high is a high image quality mode in which the image quality of the captured image is higher than the image quality of the second imaging mode, and the second imaging mode in which the power consumption is relatively low is a low power consumption mode in which the power consumption is lower than the power consumption of the first imaging mode.

[0089] Note that, in the pixel circuit 20 , the source follower circuit in the first imaging mode has better frequency characteristics than the grounded source amplifier in the second imaging mode.

[0090] (Analog-to-digital conversion circuit)

[0091] The analog-to-digital (A / D) conversion circuit 140 of the analog-to-digital conversion unit 14 may be a well-known analog-to-digital conversion circuit. Specifically, examples of the analog-to-digital conversion circuit 140 include a single-slope analog-to-digital conversion circuit, a successive approximation analog-to-digital conversion circuit, or a delta-sigma (ΔΣ) analog-to-digital conversion circuit. In the imaging device 10 according to the first embodiment, a single-slope analog-to-digital conversion circuit is used as the analog-to-digital conversion circuit 140.

[0092] In the imaging device 10 according to the first embodiment, for example, a so-called single-slope AD conversion circuit, which is an example of a reference signal comparison type AD conversion circuit, is used as the AD conversion circuit 140 .

[0093] In the single slope analog-to-digital conversion circuit 140, a reference signal of a ramp waveform (ie, a ramp reference signal V RAMP ) is used as the reference signal for analog-to-digital conversion. RAMP Generated by the reference signal generation unit 19.

[0094] The analog-to-digital conversion circuit 140 includes a load MOS 141 , a comparator 142 , a selector 143 , and a counter 144 , and is provided for each pixel column of the pixel array unit 11 .

[0095] The load MOS 141 is connected between the second signal line 33 and a reference potential node (e.g., ground) via the connection unit 43, and forms a source follower circuit together with the amplifying transistor 25 of the pixel circuit 20 when the first imaging mode as the high image quality mode is set.

[0096] The comparator 142 uses the analog pixel signal V supplied from each pixel circuit 20 in the pixel array unit 11 through the second signal line 33 and input via the capacitance element C1. sig The comparator 142 uses the ramp reference signal V generated by the reference signal generating unit 19 and input via the capacitive element C2 as a comparison input. RAMP As a reference input.

[0097] The comparator 142 compares the input signal and the reference signal V RAMP Exceeds the analog pixel signal V sig When the voltage value is greater than 1, the comparison result V co Therefore, the comparator 142 outputs the analog pixel signal V sig The pulse signal corresponding to the signal level of the analog pixel signal V sig The amplitude of the signal level corresponds to the pulse width of the pulse signal, as the comparison result V co .

[0098] The selector 143 inputs the pixel signal supplied from the first signal line 32 through the third signal line 34 when the second imaging mode as the low power consumption mode is set, and inputs the comparison result V of the comparator 142 when the second imaging mode as the high image quality mode is set. co , any input is selected according to the imaging mode MODE, and the selected input is provided to the counter 144.

[0099] The reference signal V RAMP At the same time, a clock signal (not shown) is supplied from the timing control unit 18 to the counter 144. The counter 144 measures the period of the pulse width of the output pulse of the comparator 142, that is, the period from the start of the comparison operation to the end of the comparison operation, by performing a counting operation in synchronization with the clock signal supplied from the timing control unit 18. The counting result (count value) of the counter 144 is used as the value obtained by digitizing the analog pixel signal V sig The obtained digital value is provided to the data processing unit 16 .

[0100] As the counter 144, for example, an up / down counter can be used. The counter 144 including the up / down counter performs down counting (DOWN) or up counting (UP) in synchronization with the clock signal supplied from the timing control unit 18. Specifically, when the first imaging mode as the high image quality mode is set, for example, with respect to the reset signal output from the pixel circuit 20 and at the reset level when resetting the charge-voltage conversion unit 23, and the data signal at the signal level based on the photoelectric conversion, the reset signal is down counted, and the data signal is up counted.

[0101] The difference between the data signal and the reset signal can be obtained by a down-counting operation / up-counting operation. Therefore, in addition to the analog-to-digital conversion process, the analog-to-digital conversion circuit 140 also performs a correlated double sampling (CDS) process. Here, "CDS processing" is a process for removing pixel-specific fixed pattern noise (such as reset noise of the pixel circuit 20 and threshold variation of the amplifier transistor 25) by obtaining the difference between the data signal, which is a signal level based on photoelectric conversion, and the reset signal, which is a reset level when resetting the charge-voltage conversion unit 23.

[0102] As described above, the analog-to-digital conversion unit 14 including the single-slope analog-to-digital conversion circuit 140 converts the analog pixel signal V output from the pixel circuit 20 into sig The reference signal V of the ramp wave generated by the reference signal generating unit 19 RAMP Then, the analog pixel signal Vsig and the ramp reference signal V can be compared based on the time from the start of the comparison. RAMPThe digital value is obtained by the time information from when the amplitude relationship between them changes (that is, when the output of the comparator 142 is inverted).

[0103] [Operation Example of Imaging Device]

[0104] Next, operation examples of the imaging device 10 in the first embodiment will be described, specifically, operation examples in the first imaging mode as the high image quality mode and operation examples in the second imaging mode as the low power consumption mode will be described.

[0105] (Operation Example in First Imaging Mode)

[0106] Figure 4 is a timing chart for describing an operation example in the first imaging mode of the imaging device 10 according to the first embodiment of the present technology.

[0107] In the first imaging mode, the first switch element S1 is turned on (closed) in the switching unit 130 of the imaging mode setting unit 13. Therefore, the high potential side power supply voltage VH is applied to the drain electrodes of the reset transistor 24 and the amplifier transistor 25 of the pixel circuit 20. In addition, a predetermined bias voltage is applied to the load MOS 141 as the bias voltage V B Therefore, the pixel circuit 20 operates as a source follower circuit (grounded drain circuit) that reads a pixel signal of a level corresponding to the charge accumulated in the charge-voltage conversion unit 23 to the second signal line 33 .

[0108] Hereinafter, an operation example in the first imaging mode will be described in more detail. 11 , the selection signal SEL becomes a high level, and the selection transistor 26 is turned on, so that the pixel circuits 20 of one pixel row enter a selected state.

[0109] At time t 12 After the reset transistor 24 releases the reset of the charge-voltage conversion unit 23, at time t 13 The reference signal V of the ramp wave is output from the reference signal generating unit 19. RAMP Then, in the comparator 142, the 14 At time t 15 The pulse width of the signal is used as the comparison result V co From time t 14 At time t 15 The pulse width signal of φ is a reset signal (so-called P-phase signal) which is a reset level when the charge-voltage conversion unit 23 is reset by the reset transistor 24 .

[0110] Next, at time t 16 At time t17 During the time period of t, the transfer signal TRG becomes high level, and the transfer transistor 22 is turned on, so that the charge based on the photoelectric conversion in the photoelectric conversion unit 21 is transferred to the charge-voltage conversion unit 23. Then, in the comparator 142, the charge having the value from the time t is obtained. 18 At time t 19 The pulse width of the signal is used as the comparison result V co . With time t 18 At time t 19 The signal having a pulse width of φ1 is a data signal (so-called D-phase signal) having a signal level corresponding to the charge photoelectrically converted in the photoelectric conversion unit 21 .

[0111] At time t 20 , the reset signal RST and the transfer signal TRG change from low level to high level, and at time t 21 , the selection signal SEL changes from a high level to a low level, whereby, in the selected pixel row, the source follower circuit in each pixel circuit 20 responds to the pixel signal V including the reset signal and the P-phase signal. sig The read operation is completed.

[0112] (Operation Example in Second Imaging Mode)

[0113] Figure 5 1 is a timing chart for describing an operation example in the second imaging mode of the imaging device 10 according to the first embodiment of the present technology.

[0114] In the second imaging mode, in the switching unit 130 of the imaging mode setting unit 13 , the second switching element S2 is turned on (closed), and a pixel signal is read by a pulse width modulation (PWM) method, whereby power consumption can be reduced.

[0115] Specifically, in the PWM operation in the second imaging mode, when the second switching element S2 is turned on, the drain electrodes of the reset transistor 24 and the amplifying transistor 25 of the pixel circuit 20 are connected to the current source 131 through the first signal line 32. In addition, the bias voltage V B is fixed to a high level (Hi), and the load MOS 141 becomes on. Therefore, the pixel circuit 20 operates as a grounded source amplifier. That is, the pixel signal is read out to the first signal line 32 through the grounded source amplifier. At this time, for the pixel circuits 20 of the unselected pixel rows, by turning off the reset transistor 24 and the select transistor 26 (see Figure 3 ), only a single pixel row as a selected pixel row can be set to an active state.

[0116] Hereinafter, an example of operation in the second imaging mode will be described in more detail. First, when the transfer signal TRG is fixed to a high level and the transfer transistor 22 is in an on-state, the reset signal RST becomes a high level, thereby turning on the reset transistor 24, performing an initialization operation of the charge-voltage conversion unit 23, and setting the potential FD of the charge-voltage conversion unit 23 to an intermediate level.

[0117] After the initialization operation of the charge-voltage conversion unit 23, the selection signal SEL is 31 becomes high, turning on the select transistor 26, and then at time t 32 The reset signal RST becomes low level, turning off the reset transistor 24. At the same time, the current IR of the current source 131 decreases (or is pulled down), and the potential RD of the third signal line 34 is temporarily set to low level. The current IR of the current source 131 is a constant current.

[0118] When the photoelectric conversion unit 21 is irradiated with light after reset by the reset transistor 24 is released, a reverse bias current is generated and the potential FD of the charge-voltage conversion unit 23 gradually decreases. The rate of decrease of the potential FD at this time increases as the illuminance increases. Figure 5 The timing diagram schematically shows the decreasing speed of high illumination, medium illumination and low illumination.

[0119] When the potential FD of the charge-voltage conversion unit 23 drops below the threshold level of the grounded source amplifier, the potential RD of the third signal line 34 rises through the first signal line 32. Figure 5 In the example of the timing diagram, the potential RD changes with the potential FD at high illumination at time t 33 The potential RD rises as the potential FD at the middle illumination falls below the threshold level. 34 The potential RD rises as the potential FD at low illumination falls below the threshold level at time t 35 By measuring the time when the potential RD rises using the counter 144 via the selector 143 , an illuminance signal can be obtained as a measurement result of the counter 144 (the pulse width of the digital pulse).

[0120] When the reset signal RST is at time t 36 When the select signal SEL is turned high, the reset transistor 24 is turned on, and then when the select signal SEL is turned high at time t 37 When the voltage is low, the selection transistor 26 is turned on. The above series of operations is a PWM operation. Through this PWM operation, the level of the illumination signal is converted into the pulse width of a digital pulse.

[0121] As described above, in the PWM operation in the second imaging mode of the imaging device 10 in the first embodiment, since the change in the potential FD of the charge-voltage conversion unit 23 is read (read out) as the pulse width of the digital pulse, the power supply voltage of the pixel circuit 20 can be reduced. Therefore, in the second imaging mode, the power consumption of the imaging device 10 can be reduced by the PWM operation.

[0122] [Semiconductor chip structure]

[0123] Next, the semiconductor chip structure of the imaging device 10 according to the first embodiment will be described. As the semiconductor chip structure of the imaging device 10, a flat chip structure in which the peripheral circuit unit of the pixel array unit 11 is formed on the same semiconductor substrate as the pixel circuit 20 can be adopted. However, in the imaging device 10 according to the first embodiment, a stacked chip structure in which at least two semiconductor substrates of the first-layer semiconductor substrate 41 and the second-layer semiconductor substrate 42 are stacked is adopted.

[0124] In this stacked chip structure, by arranging the pixel circuit 20 on the first-layer semiconductor substrate 41 and the peripheral circuit unit on the second-layer semiconductor substrate 42, the process applicable to manufacturing the pixel circuit 20 can be applied to the first-layer semiconductor substrate 41, and the process applicable to manufacturing the circuit portion can be applied to the second-layer semiconductor substrate 42. Therefore, it is possible to optimize the process when manufacturing the imaging device 10. Specifically, advanced processes can be applied when manufacturing the circuit portion.

[0125] Hereinafter, a stacked chip structure 1 and a stacked chip structure 2 will be described as specific examples of the stacked chip structure. The specific examples of the stacked chip structure are also applicable to each embodiment described later.

[0126] (Stacked chip structure 1)

[0127] Figure 6 is an exploded perspective view schematically showing a stacked chip structure 1 of a semiconductor chip structure of an imaging device according to a first embodiment of the present technology. Figure 3 , and has a structure in which at least two semiconductor substrates of a first-layer semiconductor substrate 41 and a second-layer semiconductor substrate 42 are stacked.

[0128] In the stacked chip structure 1, the first semiconductor substrate 41 is a pixel chip in which pixel circuits 20 including photoelectric conversion units (e.g., photodiodes) are arranged two-dimensionally in a matrix. On the first semiconductor substrate 41, first signal lines 32 and second signal lines 33 are wired for each pixel column.

[0129] The second semiconductor substrate 42 is a logic chip on which the peripheral circuit units of the pixel array unit 11 are formed, namely, the imaging mode setting unit 13 including the switching unit 130 , the analog-to-digital conversion unit 14 including the analog-to-digital conversion circuit 140 , and the like.

[0130] The first signal line 32 and the second signal line 33 electrically connected to the pixel circuit 20 on the first semiconductor substrate 41, and the switching unit 130 and the analog-to-digital conversion circuit 140 on the second semiconductor substrate 42 are electrically connected via a connection unit 43 such as a Cu-Cu connection, a through silicon via (TSV) or a micropump.

[0131] As described above, the stacked chip structure 1 and Figure 3 , and has a configuration in which the switching unit 130 and the analog-to-digital conversion circuit 140 are arranged in a logic chip as the second-layer semiconductor substrate 42 .

[0132] (Stacked chip structure 2)

[0133] Figure 7 is an exploded perspective view schematically showing a stacked chip structure 2 of a semiconductor chip structure of an imaging device according to a first embodiment of the present technology. Figure 8 corresponds to the circuit configuration shown in . Figure 8 1 is a circuit diagram showing an example of the arrangement of the pixel circuit 20, the switching unit 130, and the analog-to-digital conversion circuit 140 corresponding to the stacked chip structure 2. Similar to the stacked chip structure 1, the stacked chip structure 2 also has a structure in which at least two semiconductor substrates of the first-layer semiconductor substrate 41 and the second-layer semiconductor substrate 42 are stacked.

[0134] In the stacked chip structure 2, pixel circuits 20, including photoelectric conversion units (e.g., photodiodes), are arranged two-dimensionally in a matrix on a first-layer semiconductor substrate 41 serving as a pixel chip. First signal lines 32 and second signal lines 33 are wired for each pixel column on the first-layer semiconductor substrate 41. In the stacked chip structure 2, a switching unit 130 is also formed on the first-layer semiconductor substrate 41.

[0135] The second-layer semiconductor substrate 42 as a logic chip is a logic chip that forms, for example, the analog-to-digital conversion circuit 140 and the like between peripheral circuit units of the pixel array unit 11. Then, the first signal line 32 and the second signal line 33 on the first-layer semiconductor substrate 41 and the analog-to-digital conversion circuit 140 on the second-layer semiconductor substrate 42 are electrically connected via a connection unit 43 such as a Cu-Cu connection.

[0136] As described above, the stacked chip structure 2 and Figure 8, and has a configuration in which the switching unit 130 is arranged in the pixel chip as the first layer semiconductor substrate 41 and the analog-to-digital conversion circuit 140 is arranged in the logic chip as the second layer semiconductor substrate 42 .

[0137] <Second embodiment>

[0138] The second embodiment of the present technology is an example of improving the dynamic range when the second imaging mode as the low power consumption mode is set. Note that the overall configuration of the imaging device 10 is similar to that of the first embodiment described above, and therefore, detailed description is omitted.

[0139] In the imaging device 10 in the first embodiment described above, when the second imaging mode, which is the low power consumption mode, is set, the current IR of the current source 131 is set to a constant current. When the current IR of the current source 131 is a constant current, all low illumination signals for which the potential FD of the charge-voltage conversion unit 23 does not exceed the threshold level are regarded as having the same intensity.

[0140] Therefore, in the imaging device 10 according to the second embodiment of the present technology, when the second imaging mode, which is the low power consumption mode, is set, the current IR of the current source 131 has a ramp shape that changes linearly with a predetermined gradient over time. By making the current IR of the current source 131 have a ramp shape, the potential FD of the charge-voltage conversion unit 23 exceeds the threshold level, and light intensity can be detected even under low illumination, thereby improving the dynamic range.

[0141] Figure 9 This is a timing chart for describing an example of operation in the second imaging mode of the imaging device according to the second embodiment of the present technology. Note that the operation in the first imaging mode of the imaging device in the second embodiment is similar to the operation in the first imaging mode of the imaging device in the first embodiment.

[0142] First, when the transfer signal TRG is fixed to a high level and the transfer transistor 22 is in an on state, the reset signal RST becomes a high level, thereby turning on the reset transistor 24, performing the initialization operation of the charge-voltage conversion unit 23, and setting the potential FD of the charge-voltage conversion unit 23 to an intermediate level.

[0143] After the initialization operation of the charge-voltage conversion unit 23, the selection signal SEL is 41 becomes high, turning on the selection transistor 26, and then the reset signal RST is turned on at time t 42 becomes low level, turning off the reset transistor 24. At the same time, the current IR of the current source 131 increases in a ramp shape to the current at the time of initialization.

[0144] When the photoelectric conversion unit 21 is irradiated with light after reset by the reset transistor 24 is released, a reverse bias current is generated and the potential FD of the charge-voltage conversion unit 23 gradually decreases. The rate of decrease of the potential FD at this time increases as the illuminance increases. Figure 9 The timing diagram schematically shows the decreasing speed of high illumination, medium illumination and low illumination.

[0145] When the potential FD of the charge-voltage conversion unit 23 drops below the threshold level of the grounded source amplifier, the potential RD of the third signal line 34 rises. Figure 9 In the example of the timing diagram, the potential RD changes with the potential FD at high illumination at time t 43 The potential RD rises as the potential FD at the middle illumination falls below the threshold level. 44 The potential RD rises as the potential FD at low illumination falls below the threshold level at time t 45 By measuring the time when the potential RD rises using the counter 144 via the selector 143 , an illuminance signal can be obtained as a measurement result of the counter 144 (the pulse width of the digital pulse).

[0146] When the reset signal RST is at time t 46 When the select signal SEL is turned high, the reset transistor 24 is turned on, and then when the select signal SEL is turned high at time t 47 When the voltage is low, the selection transistor 26 is turned on. The above series of operations is a PWM operation. Through this PWM operation, the level of the illumination signal is converted into the pulse width of a digital pulse.

[0147] As described above, in the PWM operation in the second imaging mode of the imaging device 10 in the second embodiment, the change in the potential FD of the charge-voltage conversion unit 23 is read (read out) as the pulse width of a digital pulse, thereby reducing the power supply voltage of the pixel circuit. Therefore, in the second imaging mode, the power consumption of the imaging device 10 can be reduced through PWM operation. Furthermore, by making the current IR of the current source 131 ramp-shaped, the threshold level of the grounded source amplifier changes according to the current IR, allowing the potential FD of the charge-voltage conversion unit 23 to exceed the threshold level even under low illumination, and intensity detection is possible. Consequently, the dynamic range can be improved.

[0148] <Third embodiment>

[0149] A third embodiment of the present technology is an application example of an imaging device including a sample-and-hold circuit that samples and holds an output pixel signal when the first imaging mode is set.

[0150] Figure 10is a system configuration diagram illustrating a configuration example of an imaging device according to a third embodiment of the present technology. Figure 11 : is a circuit diagram showing a circuit example of a pixel circuit, a sample-and-hold circuit for one pixel column, a switching unit, and an analog-to-digital conversion circuit of an imaging device according to a third embodiment. Figure 11 A state corresponding to an operation example in a second imaging mode described later is shown (transistor off).

[0151] The imaging device 10 according to the third embodiment of the present technology includes a sampling and holding unit 50 that samples and holds the pixel signal output from the pixel circuit 20 via a source follower circuit when the first imaging mode is set. The sampling and holding unit 50 is configured to implement a global shutter (an electronic shutter for all pixels collectively) that starts and ends exposure at the same time for all pixels, and has a configuration including, for example, a plurality of sampling and holding circuits 501 provided corresponding to pixel columns of the pixel array unit 11.

[0152] A plurality of sample and hold circuits 501 are formed on the second-layer semiconductor substrate 42 , and are electrically connected to the pixel circuits 20 of corresponding pixel columns on the first-layer semiconductor substrate 41 via the connection units 43 .

[0153] The sample-and-hold circuit 501 includes an input transistor 51, a D-phase capacitor element Cd, a P-phase capacitor element Cr, a P-phase transistor 52, a D-phase transistor 53, a connecting transistor 54, an amplifying transistor 55, and a selecting transistor 56. As the transistors in the sample-and-hold circuit 501, for example, an N-channel MOS transistor can be used. However, the combination of conductivity types of the MOS transistors exemplified here is merely an example, and the combination is not limited thereto.

[0154] In the sample-and-hold circuit 501, when a P-phase signal is output as a reset signal from the pixel circuit 20, the P-phase signal level is sampled and held with respect to the P-phase capacitive element Cr under the control of the control signal SR. Furthermore, when a D-phase signal is output as a data signal from the pixel circuit 20, the D-phase signal is sampled and held with respect to the D-phase capacitive element Cd under the control of the control signal SD.

[0155] These operations are performed simultaneously for all pixels. That is, exposure is performed using a global shutter method, in which the start and end times of exposure for all pixels are perfectly matched.

[0156] Note that, in the case of the imaging device 10 according to the third embodiment of the present technology, the second signal line 33 is wired on the second-layer semiconductor substrate 42 like the plurality of sample-and-hold circuits 501 .

[0157] Figure 12This is a timing chart for describing an example of operation in the second imaging mode of the imaging device according to the third embodiment of the present technology. Note that the operation in the first imaging mode of the imaging device 10 in the third embodiment is substantially similar to the operation in the first imaging mode of the imaging device 10 in the first embodiment.

[0158] In the second imaging mode of the imaging device in the third embodiment, when the second switch element S2 is turned on, the drain electrodes of the reset transistor 24 and the amplifier transistor 25 of the pixel circuit 20 are connected to the current source 131 through the first signal line 32. In addition, when the bias voltage V B When the control signal PC is fixed to a low level (Lo), the load MOS 141 is turned off, and conversely, when the control signal PC is fixed to a high level (Hi), the input transistor 51 of the sample and hold circuit 501 is turned on.

[0159] Therefore, the pixel circuit 20 operates as a grounded source amplifier. That is, the pixel signal is read out to the first signal line 32 via the grounded source amplifier. At this time, for the pixel circuits 20 of the unselected pixel rows, by turning off the reset transistor 24 and the select transistor 26, only the single pixel row, which is the selected pixel row, can be set to an active state.

[0160] Hereinafter, an example of operation in the second imaging mode will be described in more detail. First, when the transfer signal TRG is fixed to a high level and the transfer transistor 22 is in an on-state, the reset signal RST becomes a high level, thereby turning on the reset transistor 24, performing an initialization operation of the charge-voltage conversion unit 23, and setting the potential FD of the charge-voltage conversion unit 23 to an intermediate level.

[0161] After the initialization operation of the charge-voltage conversion unit 23, the selection signal SEL is 51 becomes high, turning on the select transistor 26, and then at time t 52 The reset signal RST becomes low level, turning off the reset transistor 24. At the same time, the current IR of the current source 131 decreases (or is pulled down), and the potential RD of the third signal line 34 is temporarily set to low level.

[0162] When the photoelectric conversion unit 21 is irradiated with light after reset by the reset transistor 24 is released, a reverse bias current is generated and the potential FD of the charge-voltage conversion unit 23 gradually decreases. The rate of decrease of the potential FD at this time increases as the illuminance increases. Figure 12 The timing diagram schematically shows the decreasing speed of high illumination, medium illumination and low illumination.

[0163] When the potential FD of the charge-voltage conversion unit 23 drops below the threshold level of the grounded source amplifier, the potential RD of the third signal line 34 rises through the first signal line 32. Figure 12 In the example of the timing diagram, the potential RD changes with the potential FD at high illumination at time t 53 The potential RD rises as the potential FD at the middle illumination falls below the threshold level. 54 The potential RD rises as the potential FD at low illumination falls below the threshold level at time t 55 By measuring the time when the potential RD rises using the counter 144 via the selector 143 , an illuminance signal can be obtained as a measurement result of the counter 144 (the pulse width of the digital pulse).

[0164] When the reset signal RST is at time t 56 When the select signal SEL is turned high, the reset transistor 24 is turned on, and then when the select signal SEL is turned high at time t 57 When the voltage is low, the selection transistor 26 is turned on. The above series of operations is a PWM operation. Through this PWM operation, the level of the illumination signal is converted into the pulse width of a digital pulse.

[0165] As described above, in the imaging device 10 of the third embodiment also having a configuration including the sampling and holding unit 50, when the first imaging mode is set, the sampling and holding unit samples and holds the output pixel signal. Similar to the imaging device 10 of the first embodiment, in the first imaging mode, a captured image with relatively high image quality can be obtained, and in the second imaging mode, a PWM operation can be performed. In this PWM operation, the change in the potential FD of the charge-voltage conversion unit 23 is read (read out) as the pulse width of a digital pulse, thereby reducing the power supply voltage of the pixel circuit. Therefore, in the second imaging mode of the imaging device 10 of the third embodiment, the power consumption of the imaging device 10 can also be reduced through the PWM operation.

[0166] <Fourth embodiment>

[0167] The fourth embodiment of the present technology is a modification of the third embodiment, and is an application example of an imaging device in which the power supply of the reset transistor and the power supply of the amplification transistor in the pixel circuit are different power supplies.

[0168] Figure 13 : is a circuit diagram showing a circuit example of a pixel circuit, a sample-and-hold circuit for one pixel column, a switching unit, and an analog-to-digital conversion circuit of an imaging device according to a fourth embodiment of the present technology.

[0169] On the first-layer semiconductor substrate 41, in which the pixel circuits 20 are two-dimensionally arranged in a matrix form, fourth signal lines 35 are wired for each pixel column in addition to the first signal lines 32. The fourth signal lines 35 are electrically connected to the switching unit 130 on the second-layer semiconductor substrate 42 via the connection unit 43. In addition to the nodes for the high-potential-side power supply voltage VH and the low-potential-side power supply voltage VL, the switching unit 130 is also provided with a node for a high-potential-side power supply voltage VR different from the high-potential-side power supply voltage VH.

[0170] On the first-layer semiconductor substrate 41 , the drain electrode of the reset transistor 24 of the pixel circuit 20 is electrically connected to the first signal line 32 , and the drain electrode of the amplification transistor 25 of the pixel circuit 20 is electrically connected to the fourth signal line 35 .

[0171] On the second semiconductor substrate 42 , in addition to the first switching element S1 , the second switching element S2 and the current source 131 , the switching unit 130 electrically connected to the fourth signal line 35 via the connection unit 43 further includes a third switching element S3 and a fourth switching element S4 .

[0172] The third switching element S3 is connected between the first switching element S1 electrically connected to the first signal line 32 and the second switching element S2 electrically connected to the fourth signal line 35. The fourth switching element S4 is connected between the second switching element S2 and a node of the high-potential-side power supply voltage VR that is different from the high-potential-side power supply voltage VH.

[0173] By Figure 10 The timing control unit 18 shown in FIG. 1 is configured to control the first to fourth switching elements S1 to S4 by a control signal (not shown) provided thereto. Furthermore, the first to fourth switching elements S1 to S4 are turned on / off to set the first imaging mode and the second imaging mode, and the global shutter mode and the signal reading mode are switched in the first imaging mode.

[0174] Figure 14 1 is a diagram illustrating on / off of the first to fourth switching elements S1 to S4 in each imaging mode and a relationship with each connection target power supply of the reset transistor 24 and the amplifying transistor 25 .

[0175] When the first switch element S1 is turned on, the second switch element S2 is turned off, the third switch element S3 is turned on, and the fourth switch element S4 is turned off, and the connection target of the reset transistor 24 and the amplification transistor 25 is the node of the power supply voltage VH, the global shutter mode of the first imaging mode is set.

[0176] When the first switch element S1 is turned on, the second switch element S2 is turned off, the third switch element S3 is turned off, and the fourth switch element S4 is turned on, the connection target of the amplification transistor 25 is the node of the power supply voltage VR, and the connection target of the reset transistor 24 is the node of the power supply voltage VH, the signal reading mode of the first imaging mode is set.

[0177] When the first switching element S1 is turned off, the second switching element S2 is turned on, the third switching element S3 is turned on, the fourth switching element S4 is turned off, and the connection destination of the reset transistor 24 and the amplifying transistor 25 is the current source 131, the second imaging mode (i.e., low power consumption mode) of the PWM operation is set.

[0178] As described above, in the imaging device 10 of the fourth embodiment, in which the power supply for the reset transistor 24 and the power supply for the amplifier transistor 25 in the pixel circuit 20 are different power supplies, similar to the imaging device 10 of the first embodiment, a captured image with relatively high image quality can be obtained in the first imaging mode, and a PWM operation can be performed in the second imaging mode. In this PWM operation, the change in the potential FD of the charge-voltage conversion unit 23 is read (read out) as the pulse width of the digital pulse, thereby reducing the power supply voltage of the pixel circuit. Therefore, in the second imaging mode of the imaging device 10 of the fourth embodiment, the power consumption of the imaging device 10 can also be reduced through the PWM operation.

[0179] <Modification>

[0180] Note that the above-described embodiments illustrate examples for embodying the present technology, and that the matters in the embodiments correspond to the matters specifying the present invention in the claims. Similarly, the matters specifying the present invention in the claims correspond to the matters with the same names in the embodiments of the present technology. However, the present technology is not limited to the embodiments, and various modifications to the embodiments may be applied without departing from the scope of the present technology.

[0181] <Application Examples of Electronic Devices>

[0182] The imaging device according to the embodiment of the present technology described above can be applied to various electronic devices having an imaging function, such as camera systems of surveillance cameras, vehicle-mounted cameras, and the like.

[0183] [Example of camera system]

[0184] Figure 15 is a block diagram illustrating a configuration example of a camera system as an example of an electronic device to which the present technology is applied.

[0185] The camera system 100 according to this application example is a device for performing imaging of a subject, and includes an imaging optical system 101 including a lens group, etc., an imaging unit 102, a digital signal processor (DSP) circuit 103, a display unit 104, an operation unit 105, a storage unit 106, and a power supply unit 107. These components are connected to each other via a bus 108. For example, a surveillance camera, an in-vehicle camera, or the like is assumed as the camera system 100.

[0186] The imaging unit 102 generates pixel data through photoelectric conversion. The imaging device in the embodiment of the present technology can be used as the imaging unit 102. Light from the subject is condensed by the imaging optical system 101, which is arranged on the incident light side, and guided to the light receiving surface of the imaging unit 102. The imaging unit 102 supplies the pixel data generated by photoelectric conversion to the DSP circuit 103 at the subsequent stage.

[0187] The DSP circuit 103 performs predetermined signal processing on the pixel data from the imaging unit 102. The display unit 104 displays the pixel data. For example, a liquid crystal panel or an organic electroluminescent (EL) panel is assumed as the display unit 104. The operation unit 105 generates an operation signal based on a user operation. The storage unit 106 stores various types of data, such as pixel data. The power supply unit 107 supplies power to the imaging unit 102, the DSP circuit 103, the display unit 104, and the like.

[0188] In the camera system 100 having the above-described configuration, the imaging device 10 according to the embodiment of the present technology (ie, the imaging device 10 capable of achieving reduction in power consumption and improvement in image quality of captured images) may be mounted as the imaging unit 102 .

[0189] In locations where the camera system 100, including the imaging device 10, is installed without an outlet or power supply (such as high places, confined spaces, or outdoors), a battery is used as a driving power source. When the imaging device 10 is constantly in an imaging state while powered by the battery, a second imaging mode (i.e., low power consumption mode) can be set to extend battery life. When an event is detected, the mode is switched to the first imaging mode, a high-quality mode for capturing high-resolution images using all pixels, to obtain high-definition images.

[0190] For example, assuming that a surveillance camera is used as the camera system 100, a second imaging mode is set, imaging is always performed with low power consumption, and when a person is detected, imaging is performed by switching to the second imaging mode, thereby being able to obtain a captured image with high image quality for the person detected in the second imaging mode.

[0191] <Application examples for mobile objects>

[0192] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can also be implemented as a device installed on any type of mobile object (such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, an unmanned aerial vehicle, a ship, and a robot).

[0193] Figure 16 : is a block diagram showing a schematic configuration example of a vehicle control system as an example of a mobile body control system to which the technology according to the present disclosure can be applied.

[0194] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Figure 16 In the illustrated example, a vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. Furthermore, the functional configuration of the integrated control unit 12050 includes a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053.

[0195] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 functions as a control device for a drive force generating device (such as an internal combustion engine, a drive motor, etc.) for generating the vehicle's drive force, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the vehicle's steering angle, a braking device for generating the vehicle's braking force, and the like.

[0196] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 is used as a control device for a keyless entry system, a smart key system, power windows, or various lights such as headlights, taillights, brake lights, turn signals, fog lights, etc. In this case, radio waves transmitted from a mobile device (as a substitute for a key) or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door locks, power windows, lights, etc.

[0197] The vehicle exterior information detection unit 12030 detects information outside the vehicle, including information about the vehicle control system 12000. For example, an imaging unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the vehicle exterior and receive the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can perform object detection or distance detection on objects such as people, vehicles, obstacles, signs, and text on the road surface.

[0198] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 can be visible light or invisible light such as infrared light.

[0199] The in-vehicle information detection unit 12040 detects information about the vehicle interior. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 that detects the driver's condition. For example, the driver state detection unit 12041 includes a camera that captures the driver's image. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or concentration, or determine whether the driver is dozing off.

[0200] The microcomputer 12051 can calculate control target values ​​for the driving force generation device, the steering mechanism, or the braking device based on information about the interior or exterior of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control to implement functions of an advanced driver assistance system (ADAS), including vehicle collision avoidance or impact cushioning, following driving based on following distance, speed maintenance driving, vehicle collision warning, lane departure warning, and the like.

[0201] In addition, the microcomputer 12051 can perform collaborative control for automatic driving by controlling the driving force generation device, steering mechanism, braking device, etc. based on the information about the outside or inside of the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, which enables the vehicle to travel automatically without relying on the driver's operation, etc.

[0202] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the vehicle exterior information acquired by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlights, for example, changing from high beam to low beam, according to the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0203] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device, which can notify the occupants of the vehicle or the outside of the vehicle of information in a visual or auditory manner. Figure 16 In the example of FIG, an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are exemplified as output devices. For example, the display portion 12062 may include at least one of an in-vehicle display and a head-up display.

[0204] Figure 17 is a diagram showing an example of the installation position of the imaging unit 12031.

[0205] exist Figure 17 , the imaging unit 12031 includes imaging units 12101 , 12102 , 12103 , 12104 and 12105 .

[0206] For example, imaging units 12101, 12102, 12103, 12104, and 12105 are provided at locations within the interior of the vehicle 12100, such as the front nose, side-view mirrors, rear bumper, rear door, and upper portion of the windshield. Imaging unit 12101 provided to the front nose of the vehicle and imaging unit 12105 provided to the upper portion of the windshield primarily obtain images of the front of the vehicle 12100. Imaging units 12102 and 12103 provided to the side mirrors primarily obtain images of the sides of the vehicle 12100. Imaging unit 12104 provided to the rear bumper or rear door primarily obtains images of the rear of the vehicle 12100. Imaging unit 12105 provided to the upper portion of the windshield within the vehicle is primarily used to detect vehicles ahead, pedestrians, obstacles, signals, traffic signs, lanes, and the like.

[0207] Notice, Figure 17Examples of the imaging ranges of imaging units 12101 through 12104 are shown. Imaging range 12111 represents the imaging range of imaging unit 12101 positioned at the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103, respectively, positioned at the side mirrors. Imaging range 12114 represents the imaging range of imaging unit 12104 positioned at the rear bumper or rear door. For example, a bird's-eye view image of vehicle 12100 viewed from above can be obtained by superimposing image data captured by imaging units 12101 through 12104.

[0208] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0209] For example, based on the distance information obtained from imaging units 12101 to 12104, microcomputer 12051 can determine the distance to each three-dimensional object within imaging ranges 12111 to 12114, as well as the temporal change in that distance (relative speed to vehicle 12100), and thereby extract the closest three-dimensional object as the leading vehicle, which is located on the travel path of vehicle 12100 and is traveling at a predetermined speed (e.g., equal to or greater than 0 km / h) in substantially the same direction as vehicle 12100. Furthermore, microcomputer 12051 can pre-set a following distance to be maintained with the leading vehicle and execute automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. Thus, cooperative control of autonomous driving can be performed, allowing the vehicle to travel automatically without relying on driver operations or the like.

[0210] For example, based on the distance information obtained from imaging units 12101 to 12104, microcomputer 12051 can classify three-dimensional object data related to three-dimensional objects into three-dimensional object data for two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, microcomputer 12051 identifies obstacles around vehicle 12100 as obstacles that the driver of vehicle 12100 can visually identify and obstacles that are difficult for the driver of vehicle 12100 to visually identify. Microcomputer 12051 then determines a collision risk, indicating the risk of collision with each obstacle. If the collision risk is equal to or greater than a set value and therefore a collision possibility exists, microcomputer 12051 outputs a warning to the driver via audio speaker 12061 or display unit 12062, and executes forced deceleration or evasive steering via drive system control unit 12010. Microcomputer 12051 can thereby assist driving to avoid collisions.

[0211] At least one of imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, microcomputer 12051 may identify pedestrians by determining whether a pedestrian exists in images captured by imaging units 12101 to 12104. This identification of pedestrians is performed, for example, by extracting feature points from images captured by imaging units 12101 to 12104, which are infrared cameras, and then performing pattern matching on a series of feature points representing the outline of an object to determine whether the pedestrian is present. When microcomputer 12051 determines that a pedestrian exists in the images captured by imaging units 12101 to 12104 and identifies the pedestrian, audio / video output unit 12052 controls display unit 12062 to display a square outline superimposed on the identified pedestrian for emphasis. Audio / video output unit 12052 may also control display unit 12062 to display an icon representing the pedestrian at a desired location.

[0212] An example of a vehicle control system to which the technology of the present disclosure can be applied has been described above. For example, in the above-described configuration, the technology of the present disclosure can be applied to imaging unit 12031 and the like. Furthermore, the technology of the present disclosure, namely, a technology capable of setting a first imaging mode as a high-image quality mode and a second imaging mode as a low-power consumption mode, can be applied to imaging unit 12031 and the like. Thus, by continuously performing imaging in the second imaging mode during normal operation, battery life can be extended, and when an obstacle is detected, by switching to the first imaging mode, it is possible to obtain a captured image of the obstacle, etc., having high image quality, that is, detected in the second imaging mode.

[0213] Note that the effects described in this specification are merely illustrative and not restrictive; other effects may also exist.

[0214] <Configurations that this technology can take>

[0215] Note that the present technology is also applicable with the following configurations.

[0216] (1) An imaging device comprising:

[0217] a pixel circuit comprising a photoelectric conversion unit and an amplifying transistor, wherein a gate electrode of the amplifying transistor is connected to the photoelectric conversion unit;

[0218] a first signal line connected to one electrode side of the amplifying transistor;

[0219] a switching unit connected to the first signal line;

[0220] a second signal line connected to the other electrode side of the amplifying transistor;

[0221] a comparator, wherein a comparison input terminal of the comparator is connected to the second signal line;

[0222] a selector connected to the first signal line and the output terminal of the comparator; and

[0223] Counter, connected to the output of the selector, where

[0224] The switching unit includes:

[0225] a first switching element selectively connecting the first signal line to a power supply node, and

[0226] The second switch element selectively connects the first signal line to the current source.

[0227] (2) The imaging device according to (1), wherein

[0228] The switching unit sets a first imaging mode in which image quality of a captured image is relatively high by turning on the first switching element and turning off the second switching element, and sets a second imaging mode in which power consumption is relatively low by turning off the first switching element and turning on the second switching element.

[0229] (3) The imaging device according to (2), wherein

[0230] The pixel circuit includes a charge-voltage conversion unit, which converts the charge photoelectrically converted by the photoelectric conversion unit into a voltage, forms a source follower circuit when the first imaging mode is set, and reads the voltage of the charge-voltage conversion unit to the second signal line through the source follower circuit.

[0231] (4) The imaging device according to (2), wherein

[0232] The pixel circuit includes a charge-voltage conversion unit, which converts the charge photoelectrically converted by the photoelectric conversion unit into a voltage, forms a grounded source amplifier when the second imaging mode is set, and reads the voltage of the charge-voltage conversion unit to the first signal line through the grounded source amplifier.

[0233] (5) The imaging device according to (4), wherein

[0234] When the second imaging mode is set, the pixel circuit reads the change in the potential of the charge-voltage conversion unit as the pulse width of the digital pulse.

[0235] (6) The imaging device according to (2), wherein

[0236] When an event is detected during imaging in the second imaging mode, the switching unit switches to the first imaging mode and performs imaging.

[0237] (7) The imaging device according to (2), wherein

[0238] When the second imaging mode is set, the current of the current source is set to a ramp shape that changes linearly with a predetermined gradient over time.

[0239] (8) The imaging device according to (1), further comprising:

[0240] The sampling and holding circuit samples and holds the pixel signal output from the pixel circuit when the first imaging mode is set.

[0241] (9) The imaging device according to (8), wherein

[0242] The pixel circuit further includes a reset transistor for resetting the charge-voltage conversion unit; and

[0243] A power supply voltage to be applied to the amplifying transistor and a power supply voltage to be applied to the reset transistor are set to different power supply voltages.

[0244] (10) An electronic device including an imaging device, the imaging device comprising:

[0245] a pixel circuit comprising a photoelectric conversion unit and an amplifying transistor, wherein a gate electrode of the amplifying transistor is connected to the photoelectric conversion unit;

[0246] a first signal line connected to one electrode side of the amplifying transistor;

[0247] a switching unit connected to the first signal line;

[0248] a second signal line connected to the other electrode side of the amplifying transistor;

[0249] a comparator, wherein a comparison input terminal of the comparator is connected to the second signal line;

[0250] a selector connected to the first signal line and the output terminal of the comparator; and

[0251] Counter, connected to the output of the selector, where

[0252] The switching unit includes:

[0253] a first switching element selectively connecting the first signal line to a power source, and

[0254] The second switch element selectively connects the first signal line to the current source.

[0255] Explanation of symbols

[0256] 10 Imaging device

[0257] 11 pixel array unit

[0258] 12 vertical scanning units

[0259] 13 Imaging mode setting unit

[0260] 14 analog-to-digital conversion unit

[0261] 15 memory cells

[0262] 16 Data processing unit

[0263] 17 Output Units

[0264] 18 Timing control unit

[0265] 19 Reference signal generation unit

[0266] 20 pixel circuit (pixel)

[0267] 21 photoelectric conversion unit (photodiode)

[0268] 22 transfer transistors

[0269] 23 Charge-voltage conversion unit

[0270] 24 Reset transistor

[0271] 25 Amplifier transistor

[0272] 26 Select transistor

[0273] 31 pixel control lines

[0274] 32 First signal line

[0275] 33 Second signal line

[0276] 34 Third signal line

[0277] 35 Fourth signal line

[0278] 41. First semiconductor substrate

[0279] 42 second semiconductor substrate

[0280] 43 connection unit

[0281] 50 sample and hold units

[0282] 130 Switching Unit

[0283] 131 Current Source

[0284] 140 Analog-to-digital conversion circuit

[0285] 141 load MOS

[0286] 142 Comparator

[0287] 143 Selector

[0288] 144 Counter

[0289] 501 Sample and Hold Circuit

[0290] S1 First switching element

[0291] S2 Second switching element

[0292] S3 third switching element

[0293] S4 is a fourth switching element.

Claims

1. An imaging device comprising: a pixel circuit comprising a photoelectric conversion unit and an amplifying transistor, wherein a gate electrode of the amplifying transistor is connected to the photoelectric conversion unit; a first signal line connected to one electrode side of the amplifying transistor; a switching unit connected to the first signal line; a second signal line connected to the other electrode side of the amplifying transistor; a comparator, wherein a comparison input terminal of the comparator is connected to the second signal line; a selector connected to the first signal line and the output terminal of the comparator; as well as A counter connected to the output of the selector, wherein The switching unit includes: a first switching element selectively connecting the first signal line to a power supply node, and The second switch element selectively connects the first signal line to a current source.

2. The imaging device according to claim 1, wherein The switching unit sets a first imaging mode in which image quality of a captured image is relatively high by turning on the first switching element and turning off the second switching element, and sets a second imaging mode in which power consumption is relatively low by turning off the first switching element and turning on the second switching element.

3. The imaging device according to claim 2, wherein The pixel circuit includes a charge-voltage conversion unit, which converts the charge photoelectrically converted by the photoelectric conversion unit into a voltage, forms a source follower circuit when the first imaging mode is set, and reads the voltage of the charge-voltage conversion unit to the second signal line through the source follower circuit.

4. The imaging device according to claim 2, wherein The pixel circuit includes a charge-voltage conversion unit, which converts the charge photoelectrically converted by the photoelectric conversion unit into a voltage, forms a grounded source amplifier when the second imaging mode is set, and reads the voltage of the charge-voltage conversion unit to the first signal line through the grounded source amplifier.

5. The imaging device according to claim 4, wherein When the second imaging mode is set, the pixel circuit reads a change in the potential of the charge-voltage conversion unit as a pulse width of a digital pulse.

6. The imaging device according to claim 2, wherein When an event is detected during imaging in the second imaging mode, the switching unit switches to the first imaging mode and performs imaging.

7. The imaging device according to claim 2, wherein When the second imaging mode is set, the current of the current source is set to a ramp shape that changes linearly with a predetermined slope over time.

8. The imaging device according to claim 1, further comprising: The sampling and holding circuit samples and holds the pixel signal output from the pixel circuit when the first imaging mode is set.

9. The imaging device according to claim 8, wherein The pixel circuit further includes a reset transistor for resetting the charge-voltage conversion unit; and A power supply voltage to be applied to the amplifying transistor and a power supply voltage to be applied to the reset transistor are set to different power supply voltages.

10. An electronic device comprising an imaging device, the imaging device comprising: a pixel circuit comprising a photoelectric conversion unit and an amplifying transistor, wherein a gate electrode of the amplifying transistor is connected to the photoelectric conversion unit; a first signal line connected to one electrode side of the amplifying transistor; a switching unit connected to the first signal line; a second signal line connected to the other electrode side of the amplifying transistor; a comparator, wherein a comparison input terminal of the comparator is connected to the second signal line; a selector connected to the first signal line and the output terminal of the comparator; as well as A counter connected to the output of the selector, wherein The switching unit includes: a first switching element selectively connecting the first signal line to a power supply node, and The second switch element selectively connects the first signal line to a current source.

Images