An LDPC decoding performance evaluation system under an AWGN channel

Abstract

This invention discloses an LDPC decoding performance evaluation system under an AWGN channel, implemented on an FPGA hardware platform. The system includes: a baseband data framing module for generating pseudo-random numbers of appropriate length according to the encoding / decoding type and adding a frame header to complete framing; an LDPC encoding module for encoding the framed baseband data; a BPSK AWGN channel module for simulating the channel, completing BPSK mapping, and adding Gaussian white noise; a log-likelihood ratio (LLR) information conversion module for converting data with added Gaussian white noise into LLR soft-decision information and transmitting it to a frame synchronization module; a frame synchronization module for performing frame synchronization of the LLR soft-decision information with configurable parameters; an LDPC decoding module for decoding the frame-synchronized LLR soft-decision information; and an LDPC decoding performance evaluation module for displaying decoding status information in real time and calculating the frame error rate.

Description

Technical Field

[0001] This invention relates to the fields of electronics and communication technology, and in particular to a system for evaluating the performance of LDPC decoding under AWGN channels. Background Technology

[0002] LDPC (Low-Density Parity-Check) codes are widely used in modern communication systems due to their excellent performance and ability to approach the Shannon limit. The performance of LDPC codes is affected by code length, code rate, channel characteristics, and the decoding algorithm used. Typically, designers need to evaluate decoding performance after completing the codec design. Currently, most literature uses software simulation to evaluate decoding performance, but the time cost of this method is often prohibitive. The method described in the paper "FPGA Implementation of LDPC Code Hardware Simulation Platform" (Journal of Nanjing University (Natural Science Edition), Vol. 6, No. 3, May 2014) uses a hardware simulation platform; however, the noise generator module implementation is somewhat complex, and it requires the design of dedicated PC control software, increasing development costs. Therefore, it is essential to design a simple, easy-to-operate, and highly portable hardware platform to accelerate the evaluation of decoding performance. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of the existing technology and to propose a performance evaluation system for LDPC decoding under AWGN channels.

[0004] In view of this, the present invention proposes an LDPC decoding performance evaluation system under AWGN channels, implemented on an FPGA hardware platform, characterized by comprising:

[0005] The baseband data framing module is used to generate pseudo-random numbers of appropriate length according to the encoding / decoding type, add frame headers, and complete the framing process.

[0006] The LDPC encoding module is used to encode the baseband data of the frames;

[0007] The BPSK AWGN channel module is used to simulate a channel, complete BPSK mapping, and add Gaussian white noise.

[0008] The Log-Likelihood Ratio (LLR) information conversion module is used to convert data with added Gaussian white noise into LLR soft decision information and transmit it to the frame synchronization module.

[0009] The frame synchronization module is used to perform frame synchronization of LLR soft decision information with various configurable parameters;

[0010] The LDPC decoding module is used to decode the LLR soft-decision information after frame synchronization; and

[0011] The LDPC decoding performance evaluation module is used to display decoding status information in real time and to count the frame error rate.

[0012] Preferably, the processing procedure of the baseband data framing module includes:

[0013] The frame length is determined based on the type of LDPC decoding: if the type is LDPC (8160, 7136) long code, the frame length after adding the frame header is 8192 bits; if the type is LDPC (512, 256) short code, the frame length after adding the frame header is 544 bits.

[0014] Generate a counter of the corresponding length based on the frame length, fill the frame header in the first 32 bits, and add a pseudo-random sequence at the position of frame length - 32 bits.

[0015] Preferably, the pseudo-random sequence is implemented by calling the linear feedback shift register (LFSR) under System Generator, and the number of register chains of the LFSR is set to a maximum of 64 bits.

[0016] Preferably, the encoding of the LDPC encoding module includes: 1 / 2 LDPC encoding and 7 / 8 LDPC encoding.

[0017] Preferably, the BPSK AWGN channel module is implemented by calling the BPSK AWGNChannel component under System Generator, and the input SNR of this component is defined as channel Eb / N0 in dB.

[0018] Preferably, the processing procedure of the log-likelihood ratio (LLR) information conversion module includes:

[0019] Based on Bayes' theorem, the LLR coefficients LLR(y) of BPSK modulation under AWGN channel are generated:

[0020]

[0021] Where, σ 2 The actual noise power is given by y, where y is the amplitude of the received signal; coefficients are also present. It is obtained by addressing the ROM lookup table.

[0022] Preferably, the frame synchronization module can be configured with various parameters including: frame length, frame header, frame header fault tolerance bits, number of check states, and number of synchronization state out-of-sync times.

[0023] Preferably, the LDPC decoding module includes 1 / 2 LDPC decoding and 7 / 8 LDPC decoding.

[0024] Preferably, the LDPC decoding performance evaluation module uses the VIO built into the programming tool Vivado / ISE to set the channel Eb / N0 online.

[0025] Preferably, the FPGA hardware platform is a Xilinx KC705 evaluation board, and the operating clock setting takes into account both the throughput of the encoding and decoding algorithm implementation and the highest operating clock that the FPGA can meet timing constraints.

[0026] Compared with the prior art, the advantages of the present invention are:

[0027] 1. The present invention uses a hardware platform to greatly accelerate the evaluation of LDPC decoding performance and reduce the time cost of software simulation evaluation of decoding.

[0028] 2. The method of the present invention is simple to implement and easy to operate. The generation of baseband signal source, BPSK modulation and AWGN channel modeling can be completed by calling the components in System Generator. System Generator is a solution for algorithm design in FPGA using Simulink. Many modules in Xilinx are integrated into Simulink. Algorithms can be designed directly by drag and drop and fixed-point simulation can be performed directly. HDL code or netlist can be generated directly by System Generator, with a clear structure.

[0029] 3. Adjust the Eb / N0 parameters online in small steps by calling the VIO IP core that comes with the Vivado or ISE programming tools, and count the frame error rate without increasing the additional development cost. Attached Figure Description

[0030] Figure 1 This is a block diagram of the LDPC decoding performance evaluation system under AWGN channel. Detailed Implementation

[0031] This invention discloses a LDPC decoding performance evaluation system under AWGN channels, implemented on an FPGA hardware platform, comprising:

[0032] The baseband data framing module is used to generate pseudo-random numbers of appropriate length according to the encoding / decoding type, add frame headers, and complete the framing process.

[0033] The LDPC encoding module is used to encode the baseband data of the frames;

[0034] The BPSK AWGN channel module is used to simulate a channel, complete BPSK mapping, and add Gaussian white noise.

[0035] The Log-Likelihood Ratio (LLR) information conversion module is used to convert data with added Gaussian white noise into LLR soft decision information and transmit it to the frame synchronization module.

[0036] The frame synchronization module is used to perform frame synchronization of LLR soft decision information with various configurable parameters;

[0037] The LDPC decoding module is used to decode the LLR soft decision information after frame synchronization;

[0038] The LDPC decoding performance evaluation module is used to display decoding status information in real time and to count the frame error rate.

[0039] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0040] Example

[0041] The embodiments of the present invention propose an LDPC decoding performance evaluation system under AWGN channels, which utilizes the advantages of SystemGenerator for digital signal processing and uses a Field Programmable Gate Array (FPGA) hardware platform to complete the board-level performance testing of LDPC decoding.

[0042] Figure 1 A block diagram of the LDPC decoding performance evaluation system under AWGN channel is given, which shows the connection relationship of each functional module.

[0043] The baseband data framing module first needs to determine the frame length (FrameLength) based on the type of LDPC decoding. If it is a long LDPC (8160, 7136) code, the frame length after adding the frame header (32'h1ACFFC1D) is 8192 bits; if it is a short LDPC (512, 256) code, the frame length after adding the frame header (32'h1ACFFC1D) is 544 bits. The baseband data framing module generates a counter of the corresponding length according to the frame length, fills the frame header in the first 32 bits, and adds a pseudo-random sequence at the (FrameLength-32) bit position.

[0044] The pseudo-random sequence is implemented by calling the Linear Feedback Shift Register (LFSR) under System Generator. In order to ensure the randomness of each frame of data during the testing phase, the number of register chains of LFSR is set to a maximum of 64 bits. In addition, LFSR also supports two structures, Galois and Fibonacci, and can be implemented using either an XOR gate or a NOR gate.

[0045] The LDPC encoding module receives pseudo-random sequence frames output by the baseband data framing module and selects either LDPC (8160, 7136) long code or LDPC (512, 256) short code according to the encoding type.

[0046] BPSK AWGN channel modeling involves adding noise to the signal and completing BPSK mapping by calling the BPSK AWGN Channel under System Generator. The advantage of the BPSK AWGN Channel component is that it can not only complete BPSK mapping but also eliminates the need for artificial noise simulation. Eb / N0 can be directly set in dB. The inputs of this component are SNR (equivalent to Eb / N0 in this embodiment) and the baseband data DIN output by the encoding module. SNR is fixed-point represented as (0,8,4), unsigned, with a total data bit width of 8 bits and a fractional bit width of 4 bits. The specific value is set through VIO.

[0047] The log-likelihood ratio (LLR) information conversion module is used to generate the LLR information required by the decoder; according to Bayes' theorem, the formula for generating the LLR coefficients of BPSK is:

[0048]

[0049] Let μ = 1, then: Where, σ 2 The actual noise power is given by y, where y is the amplitude of the received signal, and the coefficient is... This coefficient can be obtained through an addressable ROM lookup table.

[0050] The LLR coefficient expression stored in the ROM lookup table needs to take into account the Binary Point of SNR in fixed-point representation, and convert the dB value to the original value, which is: 4*10^([0:255] / 16 / 10)=4*10^([0:255] / 160).

[0051] The SNR is fixed at (0,8,4), representing a range of 0 to 15.9375 dB, and the corresponding LLR coefficient ranges from 4 to 156.9676. To accurately represent the LLR coefficient, the fixed point is (0,18,10).

[0052] The information after modeling the BPSK AWGN channel is multiplied by the LLR coefficients to obtain the LLR information, which is then sent to the frame synchronization module. The LLR information is fixed at (1,6,2), representing a signed number, with a total data width of 6 bits and a fractional width of 2 bits.

[0053] In the BPSK AWGN Channel, the input 0 / 1 baseband signals are actually mapped, with 0 mapped to +1 and 1 mapped to -1. After adding noise to the baseband data channel model, the frame synchronization module at the receiver only needs to take the most significant bit of the LLR information to complete the BPSK demapping and search the frame header to complete frame synchronization.

[0054] The decoding module performs LDPC (8160,7136) long code decoding or LDPC (512,256) short code decoding according to the decoding type, and counts the current decoding status, the number of correctly decoded frames and the number of incorrectly decoded frames, and sends them to VIO for monitoring.

[0055] VIO is an IP core that can be directly called by the Vivado tool. In this embodiment, it is used to set the channel Eb / N0 and display the decoding status, the number of correctly decoded frames, the number of incorrectly decoded frames, and to count the FER. It is necessary to refer to the FER curves for different decoding types given in the CCSDS literature to select an appropriate range for setting the channel Eb / N0, with each test step being 0.2 dB. Table 1 provides a comparison of VIO settings for LDPC(512,256) decoding to illustrate Eb / N0.

[0056] Table 1. Schematic diagram of VIO settings for LDPC(512,256) decoding Eb / N0

[0057]

[0058] To reduce the time cost of evaluating decoding performance, while considering both the throughput of the encoding / decoding algorithm and the maximum clock rate that the FPGA can withstand (timing requirements for setup and hold times), the maximum operating clock frequency in the design is 100MHz. To ensure test reliability, when Eb / N0 is low, the number of erroneous frames increases rapidly, allowing for shorter test intervals; when the number of decoded erroneous frames reaches a certain threshold, the current test is terminated. When Eb / N0 is high, the number of erroneous frames increases slowly, requiring longer test intervals until the total number of frames required for the test is reached.

[0059] The specific testing process is as follows:

[0060] Step 1) After the device loads the program, set the compilation / decoding method via VIO;

[0061] Step 2) Set the channel Eb / N0 to a value close to the decoding threshold using VIO;

[0062] Step 3) Observe whether the decoding error frame count is greater than 20 frames. If the decoding error frame count is greater than 20 frames, record the current frame error rate FER and increase the channel Eb / N0 by 0.2dB. If the decoding error frame count is not greater than 20 frames, continue to wait until the decoding error frame count reaches 20 frames.

[0063] Step 4) Repeat step 3) and record the frame error rate FER under the current Eb / N0;

[0064] Step 5) As Eb / N0 increases, the probability of decoding error frames occurring becomes smaller and smaller. Therefore, when no decoding error frames occur, but the total number of test frames reaches the required upper limit, such as when the number of test frames is greater than 1e10 frames, record the current Eb / N0 and stop the test.

[0065] Step 6) Plot the FER curves corresponding to different channel Eb / N0 and compare them with the FER curves given in the CCSDS literature to evaluate the decoding performance.

[0066] It is worth noting that in the embodiments of the above system, the modules included are divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be achieved; in addition, the specific names of each functional module are only for easy differentiation and are not used to limit the scope of protection of the present invention.

[0067] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to the embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of the present invention do not depart from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A performance evaluation system for LDPC decoding under AWGN channels, implemented on an FPGA hardware platform, characterized in that, include: The baseband data framing module is used to generate pseudo-random numbers of appropriate length according to the encoding / decoding type, add frame headers, and complete the framing process. The LDPC encoding module is used to encode the baseband data of the frames; the encoding includes 1 / 2 LDPC encoding and 7 / 8 LDPC encoding. The BPSK AWGN channel module is used to simulate a channel, complete BPSK mapping, and add Gaussian white noise. The Log-Likelihood Ratio (LLR) information conversion module is used to convert data with added Gaussian white noise into LLR soft decision information and transmit it to the frame synchronization module. The frame synchronization module is used to perform frame synchronization of LLR soft decision information with various configurable parameters; The configurable parameters include: frame length, frame header, frame header fault tolerance bits, number of check states, and number of synchronization state out-of-sync times; The LDPC decoding module is used to decode the LLR soft-decision information after frame synchronization; the decoding includes 1 / 2 LDPC decoding and 7 / 8 LDPC decoding; and The LDPC decoding performance evaluation module is used to set the channel Eb / N0 online using the programming tool Vivado or the VIO built into ISE, execute the test process, display the decoding status information in real time, and count the frame error rate; the test process includes: Step 1) Set the encoding / decoding mode via VIO and set the channel Eb / N0 to a value close to the decoding threshold; Step 2) Determine if the decoding error frame count is greater than the set frame count. If yes, record the current frame error rate FER under Eb / N0 and increase the channel Eb / N0 by a preset fixed value; otherwise, continue to wait until the decoding error frame count reaches the set frame count. Step 3) Repeat step 2) until the total number of test frames reaches the preset upper limit, then stop the test; Step 4) Plot the FER curves corresponding to different channel Eb / N0 and compare them with the FER curves given in the CCSDS literature to evaluate the decoding performance.

2. The LDPC decoding performance evaluation system under AWGN channel according to claim 1, characterized in that, The processing procedure of the baseband data framing module includes: The frame length is determined based on the type of LDPC decoding: if the type is LDPC (8160, 7136) long code, the frame length after adding the frame header is 8192 bits; if the type is LDPC (512, 256) short code, the frame length after adding the frame header is 544 bits. Generate a counter of the corresponding length based on the frame length, fill the frame header in the first 32 bits, and add a pseudo-random sequence at the position of frame length - 32 bits.

3. The LDPC decoding performance evaluation system under AWGN channel according to claim 2, characterized in that, The pseudo-random sequence is implemented by calling the linear feedback shift register LFSR under System Generator, and the number of register chains of LFSR is set to a maximum of 64 bits.

4. The system for evaluating LDPC decoding performance over AWGN channel according to claim 1, characterized in that, The BPSKAWGN channel module is implemented by calling the BPSKAWGN Channel component under System Generator. The input SNR of this component is defined as channel Eb / N0 in dB.

5. The system for evaluating LDPC decoding performance over AWGN channel according to claim 4, characterized in that, The processing steps of the log-likelihood ratio (LLR) information conversion module include: Based on Bayes' theorem, generate the LLR coefficients of BPSK modulation under AWGN channel. : ； in, For the actual noise power, y The amplitude of the received signal; coefficient It is obtained by addressing the ROM lookup table.

6. The system for evaluating LDPC decoding performance over AWGN channel according to claim 1, characterized in that, The FPGA hardware platform is a Xilinx KC705 evaluation board. The operating clock is set to balance the throughput of the encoding and decoding algorithm implementation with the highest operating clock that the FPGA can meet timing constraints.

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