Digital circuit and method for driving control of multi-way electromagnetic valve

Abstract

The application relates to a driving control digital circuit and a driving control method suitable for multi-path electromagnetic valves. The driving control digital circuit comprises a driving processing circuit, a driving signal generating circuit and a driving signal generating circuit. The driving processing circuit receives driving operation information, generates next period driving control information corresponding to the driving operation information, and loads the generated next period driving control information to the driving signal generating circuit. The driving signal generating circuit generates a channel PWM driving signal corresponding to each path electromagnetic valve based on the received next period driving control information, so as to drive and control the connected electromagnetic valve based on the channel PWM driving signal. The application adopts a digital circuit to realize driving control of the multi-path electromagnetic valve, and through resource scheduling of the driving control, the area and power consumption during the driving control can be reduced, the driving control cost of the multi-path electromagnetic valve is further reduced, and the driving control precision and reliability of the multi-path electromagnetic valve are improved.

Description

Technical Field

[0001] This invention relates to a digital circuit for drive control and a drive control method, and more particularly to a digital circuit for drive control and a drive control method suitable for multi-channel solenoid valves. Background Technology

[0002] As a core component of hydraulic actuators, the accuracy and reliability of solenoid valve drive control directly affect the performance of hydraulic actuators. For example, in automotive electronic stability control (ESC) systems, the accuracy and reliability of solenoid valve drive control directly affect the accuracy and reliability of brake pressure regulation.

[0003] When a hydraulic actuator contains multiple solenoid valves, it is necessary to drive and control these valves to operate in their respective states, thus creating a multi-way solenoid valve drive and control scenario. Currently, driving and controlling multiple solenoid valves requires implementing corresponding logic control, such as frequency processing and analog-to-digital conversion. However, the lack of effective resource scheduling in implementing this logic control results in large circuit / chip areas and high power consumption, leading to high costs and difficulty in guaranteeing the accuracy of multi-way solenoid valve drive and control. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the existing technology and provide a digital circuit and driving control method suitable for multi-way solenoid valves. It uses digital circuits to realize the driving control of multi-way solenoid valves. Through resource scheduling of driving control, the area and power consumption during driving control can be reduced, thereby reducing the driving control cost of multi-way solenoid valves and improving the driving control accuracy and reliability of multi-way solenoid valves.

[0005] According to the technical solution provided by the present invention, a digital circuit for driving and controlling a multi-way solenoid valve is provided for driving and controlling the multi-way solenoid valve. The digital circuit for driving and controlling the multi-way solenoid valve includes:

[0006] The drive processing circuit receives drive operation information, generates drive control information for the next cycle corresponding to the drive operation information, and loads the generated drive control information for the next cycle into the drive signal generation circuit.

[0007] The drive operation information includes at least the target drive frequency and the drive status information of each solenoid valve drive circuit when driving the corresponding solenoid valve.

[0008] The next cycle drive control information includes at least the next cycle drive clock information and the next cycle drive regulation information;

[0009] The next cycle drive clock information includes the number of next cycle channel drive clocks corresponding to each solenoid valve;

[0010] The next cycle drive control information includes the next cycle channel drive start signal corresponding to each solenoid valve;

[0011] The drive signal generation circuit generates a channel PWM drive signal corresponding to each solenoid valve based on the received drive control information for the next cycle. This channel PWM drive signal is then used to configure the solenoid valve drive circuit to drive and control the connected solenoid valves.

[0012] When generating the channel PWM drive signal corresponding to each solenoid valve, the next cycle channel drive clock number and the next cycle channel drive start signal corresponding to the current solenoid valve are obtained. Then, based on the obtained next cycle channel drive clock number and the next cycle channel drive start signal, the corresponding channel PWM drive signal is generated.

[0013] The drive processing circuit includes a frequency processing unit, a phase scheduling unit, and a drive clock number generation unit, wherein...

[0014] The frequency processing unit processes the target driving frequency and generates the next cycle reference clock number and the next cycle reference start signal corresponding to the target driving frequency, and loads the generated next cycle reference clock number into the driving clock number generation unit.

[0015] Based on the next cycle reference start signal and the preset working phase of each solenoid valve, the phase scheduling unit generates the next cycle channel drive start signal and clock number generation request information corresponding to each solenoid valve, and loads all the next cycle channel drive start signals into the drive signal generation circuit.

[0016] Based on the clock count generation request information, the drive status information of each solenoid valve is collected sequentially. Based on the collected drive status information, the PWM ratio information of the channel corresponding to each solenoid valve drive circuit is determined at least. Then, based on the corresponding channel PWM ratio information and the reference clock count for the next cycle, the drive clock count generation unit generates the channel drive clock count for the next cycle corresponding to each solenoid valve.

[0017] The clock count generation request information includes several generation processing sub-requests, each corresponding to a solenoid valve and a solenoid valve drive circuit for driving and controlling the solenoid valve.

[0018] When a solenoid valve in one channel is a digital solenoid valve, the corresponding generation processing sub-request includes the channel number corresponding to the current solenoid valve and the PWM percentage acquisition request corresponding to the current solenoid valve drive circuit. The drive status information corresponding to the current solenoid valve is the channel PWM percentage information.

[0019] When generating the next cycle channel drive clock count, the channel PWM percentage information of the current solenoid valve drive circuit is obtained based on the PWM percentage acquisition request. Then, based on the channel PWM percentage information and the next cycle reference clock count, the corresponding next cycle channel drive clock count is generated.

[0020] When one solenoid valve is a current-type solenoid valve, the corresponding generation processing sub-request includes the channel number corresponding to the current solenoid valve and the PWM percentage calculation request corresponding to the current solenoid valve drive circuit. Furthermore, the drive status information of the current solenoid valve drive circuit must be at least the channel current.

[0021] When generating the next cycle channel drive clock count, the corresponding channel current is obtained based on the PWM ratio calculation request, and the corresponding channel PWM ratio information is calculated based on the obtained channel current. Then, based on the channel PWM ratio information and the next cycle reference clock count, the corresponding next cycle channel drive clock count is generated.

[0022] When calculating the channel PWM percentage information, the following is included:

[0023] The obtained channel current is subjected to AD conversion to generate a channel quantization current value corresponding to the channel current;

[0024] Perform PID calculations on the generated channel quantized current values ​​to generate the corresponding channel PWM percentage information after the PID calculation.

[0025] For multi-channel solenoid valves, when generating the corresponding next-cycle channel drive clock number, based on the channel number of each solenoid valve, the drive clock number generation unit is configured to generate the corresponding next-cycle channel drive clock number in a pipelined manner.

[0026] When calculating the number of channel drive clocks to generate the next cycle, we have:

[0027]

[0028] in, For the channel drive clock number in the next cycle, This provides information on the channel PWM duty cycle. This is the maximum duty cycle value. This serves as the reference clock number for the next cycle.

[0029] The drive signal generation circuit includes several independent PWM drive signal generation units, wherein...

[0030] A channel PWM drive signal generation unit is adapted and connected to a solenoid valve drive circuit, and each channel PWM drive signal generation unit receives the corresponding next cycle channel drive clock number and the next cycle channel drive start signal;

[0031] Based on the received next cycle channel drive clock count and the next cycle channel drive start signal, the channel PWM drive signal generation unit generates the corresponding channel PWM drive signal and loads the generated channel PWM drive signal onto the connected solenoid valve drive circuit.

[0032] Each channel PWM drive signal generation unit generates the channel PWM drive signal, including:

[0033] Upon receiving a valid next cycle channel drive start signal, the channel PWM drive signal is configured to be valid within the counting time of the next cycle channel drive clock.

[0034] When the frequency processing unit processes the target driving frequency, it includes:

[0035] The current cycle reference clock count is counted, and a next cycle reference start signal is generated when the current cycle reference clock count is completed. Furthermore, the next cycle reference clock count is updated when the next cycle reference start signal is generated.

[0036] When updating the reference clock count for the next cycle, the reference clock count for the next cycle is first calculated. In calculating the reference clock count for the next cycle, the reference digital clock frequency in the frequency processing unit is obtained, and the result of dividing the reference digital clock frequency by the target driving frequency is configured as the reference clock count for the next cycle.

[0037] The verification of the drive of a multi-way solenoid valve includes:

[0038] The aforementioned drive processing circuit, drive signal generation circuit, multi-way solenoid valve, and solenoid valve drive circuit adapted to the multi-way solenoid valve are comprehensively modeled using the Verilog hardware description language.

[0039] During drive verification, the drive status information of the multi-channel solenoid valve drive circuit in the comprehensive modeling is loaded into the drive clock number generation unit, so that the drive clock number generation unit can generate the next cycle channel drive clock number corresponding to the solenoid valve drive circuit.

[0040] A drive control method suitable for multi-way solenoid valves is provided, wherein the multi-way solenoid valve to be driven and controlled is driven and controlled by the aforementioned required digital drive control circuit.

[0041] Advantages of the present invention: The drive processing circuit receives drive working information and processes the received drive working information to generate corresponding drive control information for the next cycle. The drive signal generation circuit can generate PWM drive signals corresponding to each solenoid valve to realize drive control of multiple solenoid valves.

[0042] The drive processing circuit, drive signal generation circuit, and solenoid valve drive circuit are implemented using digital circuits. In other words, digital circuits are used to drive and control the multi-channel solenoid valves. Through resource scheduling in drive control, the area and power consumption during drive control can be reduced, thereby reducing the cost of drive control for the multi-channel solenoid valves and improving the accuracy and reliability of drive control for the multi-channel solenoid valves. Attached Figure Description

[0043] Figure 1 This is a structural block diagram of one embodiment of the digital drive control circuit of the present invention.

[0044] Figure 2 This is a simplified equivalent circuit diagram of the solenoid valve drive circuit and an embodiment of the solenoid valve according to the present invention. Detailed Implementation

[0045] The present invention will be further described below with reference to specific accompanying drawings and embodiments.

[0046] To reduce the driving control cost of multi-way solenoid valves and improve their driving control accuracy and reliability, this invention provides a digital driving control circuit suitable for multi-way solenoid valves. Specifically, it is used to drive and control multi-way solenoid valves, and the digital driving control circuit includes:

[0047] The drive processing circuit receives drive operation information, generates drive control information for the next cycle corresponding to the drive operation information, and loads the generated drive control information for the next cycle into the drive signal generation circuit.

[0048] The drive operation information includes at least the target drive frequency and the drive status information of each solenoid valve drive circuit when driving the corresponding solenoid valve.

[0049] The next cycle drive control information includes at least the next cycle drive clock information and the next cycle drive regulation information;

[0050] The next cycle drive clock information includes the number of next cycle channel drive clocks corresponding to each solenoid valve;

[0051] The next cycle drive control information includes the next cycle channel drive start signal corresponding to each solenoid valve;

[0052] The drive signal generation circuit generates a channel PWM drive signal corresponding to each solenoid valve based on the received drive control information for the next cycle. This channel PWM drive signal is then used to configure the solenoid valve drive circuit to drive and control the connected solenoid valves.

[0053] When generating the channel PWM drive signal corresponding to each solenoid valve, the next cycle channel drive clock number and the next cycle channel drive start signal corresponding to the current solenoid valve are obtained. Then, based on the obtained next cycle channel drive clock number and the next cycle channel drive start signal, the corresponding channel PWM drive signal is generated.

[0054] It should be noted that the drive control digital circuit of this invention, when controlling a multi-way solenoid valve, adopts a digital circuit form. Here, "multi-way solenoid valve" specifically refers to multiple solenoid valves. Multi-way solenoid valves can be used in applications such as the automotive electronic stability control system mentioned above. Generally, each solenoid valve needs to be connected to a solenoid valve drive circuit; that is, each solenoid valve has a corresponding connected solenoid valve drive circuit. Therefore, when controlling a multi-way solenoid valve, "corresponding to a solenoid valve" means corresponding to the solenoid valve drive circuit connected to the current solenoid valve. Specifically, the solenoid valve drive circuit can be used to drive and control the solenoid valves. The method by which the solenoid valve drive circuit drives and controls the solenoid valves can be consistent with existing technologies, and will not be elaborated here.

[0055] Understandably, the number of solenoid valves can be selected according to actual needs, based on meeting the specific application requirements. Figure 1 The external solenoid valves (multiple) in the context refer to multiple solenoid valves, that is... Figure 1 The phrase “plural ones” in the text all mean multiple, such as Figure 1 The term "solenoid valve drive circuit (multiple)" refers to multiple solenoid valve drive circuits, with a one-to-one correspondence between the solenoid valves and their drive circuits. Generally, the multiple solenoid valves operate independently, but depending on the operational requirements, a fixed phase difference is typically set between the operating phases of different solenoid valves. This phase difference allows for better EMC characteristics when driving the solenoid valves, which is beneficial for scheduling the ADC sampling conversion and PID calculations described below. When there is no phase difference between the operating phases of different solenoid valves, it can be considered a special case where the phase difference is set to 0, thus allowing the same drive control method to be used.

[0056] The solenoid valve drive circuit can use existing commonly used circuits, such as analog circuits. The circuit form used in the solenoid valve drive circuit can be selected according to needs, based on whether it can meet the drive control requirements of the solenoid valve. When using the solenoid valve drive circuit to drive and control the solenoid valve, a PMW (Pulse Width Modulation) signal should be loaded onto the solenoid valve drive circuit. If there are multiple solenoid valves and corresponding solenoid valve drive circuits, a corresponding channel PMW drive signal should be loaded onto each solenoid valve drive circuit. This allows the drive state of the connected solenoid valve to be controlled by the channel PWM drive signal. Figure 1 The PWM drive signal in the code is the channel PWM drive signal applied to each solenoid valve drive circuit.

[0057] In order to load the corresponding channel PWM drive signal to the solenoid valve drive circuit, the drive control digital circuit of the present invention should include at least a drive processing circuit and a drive signal generation circuit. The drive processing circuit receives drive operation information and generates drive control information for the next cycle corresponding to the drive operation information. Specifically, the drive operation information includes at least the drive target frequency and the drive status information of each solenoid valve drive when driving the corresponding solenoid valve. The drive target frequency can be determined according to the control requirements in the working scenario. The driving of each solenoid valve drive to the corresponding solenoid valve specifically refers to the driving of the solenoid valve drive circuit to the connected solenoid valve. The drive status information is generally related to the type of solenoid valve. The drive status will be explained in detail below.

[0058] In specific implementation, the next cycle drive control information should include at least the next cycle drive clock information and the next cycle drive adjustment information. The next cycle drive clock information includes the number of next cycle channel drive clocks corresponding to each solenoid valve. Generally, the number of next cycle channel drive clocks should be consistent with the number of solenoid valves in the multi-channel solenoid valve, that is, consistent with the number of solenoid valve drive circuits. Therefore, the number of next cycle channel drive clocks corresponds one-to-one with the solenoid valve drive circuits, and the number of next cycle channel drive clocks corresponding to each solenoid valve drive circuit can be different.

[0059] Specifically, the next cycle drive control information includes several next cycle channel drive start signals. The correspondence between these next cycle channel drive start signals and the solenoid valve drive circuit can be found in the explanation of the next cycle channel drive clock number and its correspondence with the solenoid valve drive circuit here, and will not be repeated here. Generally, the next cycle channel drive start signal serves as the drive enable signal; therefore, the phase of different next cycle channel drive start signals will vary, depending on whether it meets the drive control requirements of different solenoid valves.

[0060] The drive processing circuit loads the generated next cycle drive control information into the drive signal generation circuit, so that the drive signal generation circuit generates a channel PWM drive signal corresponding to each solenoid valve. That is, for multiple solenoid valves, the drive signal generation circuit will generate multiple channel PWM drive signals. The channel PWM drive signals are also in a one-to-one correspondence with the solenoid valve and the solenoid valve drive circuit. As can be seen from the above description, each PWM drive signal should be loaded into the corresponding solenoid valve drive circuit so that the solenoid valve drive circuit can perform the required drive control on the connected solenoid valve.

[0061] Since the PWM drive signal corresponds to the solenoid valve drive circuit and the solenoid valve, when generating the PWM drive signal, the corresponding next cycle channel drive clock number and the next cycle channel drive start signal should be obtained. After that, the corresponding channel PWM drive signal can be generated. The process of generating the channel PWM drive signal will be explained in detail below.

[0062] In one embodiment of the present invention, the driving processing circuit includes a frequency processing unit, a phase scheduling unit, and a driving clock number generation unit, wherein,

[0063] The frequency processing unit processes the target driving frequency and generates the next cycle reference clock number and the next cycle reference start signal corresponding to the target driving frequency, and loads the generated next cycle reference clock number into the driving clock number generation unit.

[0064] Based on the next cycle reference start signal and the preset working phase of each solenoid valve, the phase scheduling unit generates the next cycle channel drive start signal and clock number generation request information corresponding to each solenoid valve, and loads all the next cycle channel drive start signals into the drive signal generation circuit.

[0065] Based on the clock count generation request information, the drive status information of each solenoid valve is collected sequentially. Based on the collected drive status information, the PWM ratio information of the channel corresponding to each solenoid valve drive circuit is determined at least. Then, based on the corresponding channel PWM ratio information and the reference clock count for the next cycle, the drive clock count generation unit generates the channel drive clock count for the next cycle corresponding to each solenoid valve.

[0066] Figure 1 The figure illustrates one embodiment of the drive processing circuit. As shown in the figure, the drive processing circuit may include a frequency processing unit, a phase scheduling unit, and a drive clock number generation unit. Figure 1 The part within the red dashed line is the drive clock number generation unit. After receiving the target drive frequency, the frequency processing unit can process the target drive frequency to generate the reference clock number for the next cycle and the reference start signal for the next cycle.

[0067] In one embodiment of the present invention, the frequency processing unit, when processing the target driving frequency, includes:

[0068] The current cycle reference clock count is counted, and a next cycle reference start signal is generated when the current cycle reference clock count is completed. Furthermore, the next cycle reference clock count is updated when the next cycle reference start signal is generated.

[0069] When updating the reference clock count for the next cycle, the reference clock count for the next cycle is first calculated. In calculating the reference clock count for the next cycle, the reference digital clock frequency in the frequency processing unit is obtained, and the result of dividing the reference digital clock frequency by the target driving frequency is configured as the reference clock count for the next cycle.

[0070] Specifically, the frequency processing unit should include at least a frequency processing counter and a clock count calculator. The current reference clock count is the number of reference clocks that already exist in the frequency processing unit before receiving the target drive frequency. It can be understood that the current reference clock count and the next cycle reference clock count have the same meaning. The difference is that the current reference clock count and the next cycle reference clock count refer to different drive control cycles.

[0071] It is understandable that the current cycle reference clock count is a clock count value. After determining the current cycle reference clock count, a frequency processing counter can be used for counting. The specific technical method is related to the reference digital clock frequency used by the frequency processing counter, and the specific calculation method and process can be consistent with existing technology. When the current cycle reference clock count is completed, a next cycle reference start signal is immediately generated. The next cycle reference start signal is generally an identifier signal. The generated next cycle reference start information can indicate that the drive control will enter the next cycle. Therefore, the moment when the current cycle reference clock count is completed should be regarded as the start of the next cycle. At the same time, the current cycle reference clock count is updated to obtain the next cycle reference clock count after the update.

[0072] It should be understood that after counting the updated next-cycle reference clock count, the currently updated next-cycle reference clock count becomes the current cycle reference clock count. When updating the next-cycle reference clock count, it should first be calculated based on the target drive frequency. Specifically, if the target drive frequency is 21.5kHz and the reference digital clock frequency is 16MHz, the next-cycle reference clock count can be calculated as: 16M / 21.5k=744, meaning the calculated next-cycle reference clock count is 744. Other calculation methods can be found here and will not be elaborated further. Specifically, a clock counter can be used for this calculation. The frequency processing counter and clock counter can adopt existing commonly used forms, prioritizing the ability to count and calculate.

[0073] As can be seen from the above description, after updating the reference clock count for the next cycle, the counting of the reference clock for the current cycle will be repeated. That is, after receiving the target driving frequency, the frequency processing unit will repeat the above process of counting the reference clock count for the current cycle, generating the reference start signal for the next cycle, and updating the reference clock count for the next cycle, so as to realize the required driving control of the solenoid valve.

[0074] After the frequency processing unit generates the next cycle reference start signal, it should load the next cycle reference start signal into the phase scheduling unit. The phase scheduling unit typically stores the preset operating phase for each solenoid valve. Therefore, upon receiving the next cycle reference start signal, it can generate the next cycle channel drive start signal and clock count generation request information based on the preset operating phase. It's understood that the number of generated next cycle channel drive start signals should correspond to the number of solenoid valves. For example, in an application scenario with 6 solenoid valves, 6 next cycle channel drive start signals should be generated, and these 6 signals should satisfy the preset operating phase. For instance, the preset operating phase could be a 40-clock interval between the drive control phases of each solenoid valve. In this case, after receiving the next cycle reference start signal, the next cycle channel drive start signals corresponding to the 6 solenoid valves will be generated sequentially after 0, 40, 80, 120, 160, and 200 clock cycles, respectively. For other preset operating phases, please refer to the corresponding explanation here.

[0075] It should be noted that the number of clock cycles for the phase interval mentioned above can be obtained from the reference digital clock frequency. Therefore, the number of intervals during phase scheduling can be determined based on the reference digital clock frequency and the state of phase scheduling.

[0076] Furthermore, when the phase scheduling unit generates the corresponding next-cycle channel drive start signal, it should also output clock number generation request information and load the generated clock number generation request information into the drive clock number generation unit. As explained above, the generated next-cycle channel drive start signal should be loaded into the drive signal generation circuit. Therefore, during drive control, there will be a phase delay in the drive control of different solenoid valves. This allows for better EMC characteristics and facilitates the drive clock number generation unit in generating the next-cycle channel drive clock number corresponding to different solenoid valves, thereby achieving resource scheduling and reducing the area and power consumption during drive control.

[0077] The clock number generation request information generated by the phase scheduling unit is generally related to the type of solenoid valve, which will be explained in detail below.

[0078] In one embodiment of the present invention, the clock count generation request information includes several generation processing sub-requests, each generation processing sub-request corresponding to a solenoid valve and a solenoid valve drive circuit for driving and controlling the solenoid valve, wherein,

[0079] When a solenoid valve in one channel is a digital solenoid valve, the corresponding generation processing sub-request includes the channel number corresponding to the current solenoid valve and the PWM percentage acquisition request corresponding to the current solenoid valve drive circuit. The drive status information corresponding to the current solenoid valve is the channel PWM percentage information.

[0080] When generating the next cycle channel drive clock count, the channel PWM percentage information of the current solenoid valve drive circuit is obtained based on the PWM percentage acquisition request. Then, based on the channel PWM percentage information and the next cycle reference clock count, the corresponding next cycle channel drive clock count is generated.

[0081] When one solenoid valve is a current-type solenoid valve, the corresponding generation processing sub-request includes the channel number corresponding to the current solenoid valve and the PWM percentage calculation request corresponding to the current solenoid valve drive circuit. Furthermore, the drive status information of the current solenoid valve drive circuit must be at least the channel current.

[0082] When generating the next cycle channel drive clock count, the corresponding channel current is obtained based on the PWM ratio calculation request, and the corresponding channel PWM ratio information is calculated based on the obtained channel current. Then, based on the channel PWM ratio information and the next cycle reference clock count, the corresponding next cycle channel drive clock count is generated.

[0083] In practical implementation, the clock count generation request information should include multiple generation processing sub-requests. Each generation processing sub-request corresponds to a solenoid valve and its corresponding solenoid valve drive circuit, meaning there is a one-to-one correspondence between the generation processing sub-request and the solenoid valve. Generally, the solenoid valve can be a digital solenoid valve or a current-type solenoid valve. The use of digital or current-type solenoid valves can be consistent with existing technologies. It should be noted that in a multi-way solenoid valve system, the types of solenoid valves in different channels can be the same or different. That is, in a multi-way solenoid valve system, the solenoid valves can be of the same type, such as all solenoid valves being digital or current-type solenoid valves. Alternatively, the multi-way solenoid valves can belong to different types, such as some solenoid valves being digital solenoid valves and some being current-type solenoid valves. Of course, the types of different solenoid valves in a multi-way solenoid valve system can be selected according to actual needs, based on meeting the actual application requirements.

[0084] Specifically, in order to achieve accurate correspondence with multiple solenoid valves, each solenoid valve should be transformed. That is, when each solenoid valve and its corresponding solenoid valve drive circuit are treated as a channel, they will be assigned a unique channel number. Therefore, each channel number can correspond to a solenoid valve and a solenoid valve drive circuit used to drive the solenoid valve. The form of the channel number can be selected as needed, with the aim of uniquely identifying the corresponding solenoid valve and solenoid valve drive circuit.

[0085] In one embodiment of the present invention, when a digital solenoid valve is used in one solenoid valve channel, the corresponding generation processing sub-request includes the channel number corresponding to the current solenoid valve and the PWM percentage acquisition request corresponding to the current solenoid valve drive circuit. In this case, the channel number and the PWM percentage acquisition request are associated, and the drive status information corresponding to the current solenoid valve is the channel PWM percentage information. Specifically, the channel PWM percentage information refers to the PWM percentage used by the solenoid valve drive circuit when driving the digital solenoid valve. Generally, the channel PWM percentage information used by the solenoid valve drive circuit when driving the digital solenoid valve can be directly obtained, such as... Figure 1 As shown.

[0086] In specific implementation, for a PWM percentage acquisition request, the drive clock generation unit can obtain the corresponding channel PWM percentage information based on the channel number associated with the PWM percentage acquisition request. Then, based on the channel PWM percentage information and the next cycle reference clock number, the corresponding next cycle channel drive clock number is generated. One feasible method for generating the next cycle channel drive clock number is as follows:

[0087] When calculating the number of channel drive clocks to generate the next cycle, we have:

[0088]

[0089] in, For the channel drive clock number in the next cycle, This provides information on the channel PWM duty cycle. This is the maximum duty cycle value. This serves as the reference clock number for the next cycle.

[0090] Specifically, the maximum duty cycle The duty cycle can be predetermined according to the requirements for driving and controlling the solenoid valve. In specific design, the maximum duty cycle can generally be determined by the range of the target current value of the channel and the range of the PID operation coefficients used in the PID calculation. In specific implementation, based on the range of the target current value of the channel and the PID operation coefficients used in the PID calculation, the range of the output in equilibrium state is obtained through PID calculation, thereby determining the corresponding maximum duty cycle. In one embodiment of the present invention, the maximum duty cycle can be set to 1023.

[0091] It should be noted that for digital solenoid valves, the maximum duty cycle reflects the control precision of the digital solenoid valve. For example, if 1023 is the maximum duty cycle, then the smallest control granularity is 1 / 1023 = 0.098%. Therefore, in specific implementations, when the solenoid valve is a digital solenoid valve, the maximum duty cycle can be the maximum duty cycle determined by the current-following electronic valve.

[0092] In addition, other calculation methods can be used to calculate the channel drive clock count for the next cycle. As explained here, the drive clock count generation unit mainly converts the channel PWM duty cycle into the corresponding drive clock count. Therefore, the drive clock count generation unit should at least include... Figure 1 The channel PWM duty cycle to clock count unit in the middle can perform the above calculation to generate and output the channel drive clock count for the next cycle.

[0093] It should be understood that for any solenoid valve that uses a digital solenoid valve, the corresponding next cycle channel drive clock number can be generated by the drive clock number generation unit in the above manner.

[0094] When one solenoid valve is a current-type solenoid valve, the generated processing sub-request should include the corresponding channel number and the corresponding PWM percentage calculation request. Unlike digital solenoid valves, the channel PWM percentage information for current-type solenoid valves must be calculated; it cannot be directly obtained. Generally, both the calculated and obtained channel PWM percentage information are numerical values ​​representing the PWM percentage. When calculating the channel PWM percentage information, the drive status information of the current solenoid valve drive circuit must be at least the channel current. Generally, solenoid valve drive circuits often use analog circuits, and the channel current in the drive status information is typically an analog current value.

[0095] As explained above, the PWM percentage calculation request is also associated with the channel number. Therefore, for any PWM percentage calculation request, based on the channel number corresponding to the PWM percentage calculation request, the drive clock generation unit can obtain the corresponding channel current. Subsequently, the drive clock generation unit should calculate the corresponding channel PWM percentage information based on the channel current. Then, the channel drive clock count for the next cycle can be calculated using the same method. Figure 1 The channel PWM duty cycle to clock count unit generates the corresponding channel drive clock count for the next cycle. The following section combines... Figure 1 The calculation of the PWM ratio information of the generated channels is explained in detail.

[0096] In one embodiment of the present invention, the calculation of the channel PWM proportion information includes:

[0097] The obtained channel current is subjected to AD conversion to generate a channel quantization current value corresponding to the channel current;

[0098] Perform PID calculations on the generated channel quantized current values ​​to generate the corresponding channel PWM percentage information after the PID calculation.

[0099] Figure 1 The figure illustrates one embodiment for calculating channel PWM percentage information. As shown, when calculating the channel PWM percentage information, the drive clock number generation unit should include an ADC module and a PID calculation module. For any PWM percentage acquisition request, the ADC module can obtain the channel current corresponding to the channel number associated with the PWM percentage request, such as... Figure 1 As shown, the acquired channel current can then be converted to an AD converter via the ADC module, and the corresponding channel quantized current value can be obtained after the AD conversion. The method of converting the channel current to an AD converter and obtaining the channel quantized current value is consistent with the existing technology, and will not be elaborated here.

[0100] After obtaining the channel quantized current value, a PID calculation module can be used to perform PID calculations. After the PID calculation, the channel PWM proportion information can be calculated. When performing PID calculations, a target current value corresponding to the current channel code should be set. That is, the target current value should be related to the drive control state of the solenoid valve. Therefore, after determining the drive control state of the current-type solenoid valve, the corresponding target current value can be determined. Then, the target current value is used as a reference value, and the channel quantized current is used as the input value. Based on the channel quantized current value and the target current value, the corresponding channel PWM proportion information can be calculated using the commonly used PID calculation method.

[0101] It should be understood that when performing PID calculations, the proportional coefficient, integral coefficient, and / or derivative coefficients used in the PID calculations should be determined. In practice, the corresponding proportional coefficient, integral coefficient, and / or derivative coefficients can be determined by means of pre-experimentation, trial and error, etc. The method of determining the corresponding proportional coefficient, integral coefficient, and / or derivative coefficients can be consistent with the existing technology, and will not be elaborated here.

[0102] As explained above, when a current-type solenoid valve is used, the drive clock generation unit should also include an ADC module and a PID calculation module. It is understood that the ADC module may include one or more ADC sub-modules, and the PID calculation module may include one or more PID calculation sub-modules. When multiple ADC sub-modules and multiple PID calculation sub-modules exist, one ADC sub-module and one PID calculation sub-module can be used to perform the aforementioned ADC conversion and PID calculation for one solenoid valve.

[0103] To further optimize resource scheduling, reduce the area and power consumption during drive control, and thus lower the drive control cost for multi-channel solenoid valves, in one embodiment of the present invention, when generating the corresponding next-cycle channel drive clock number for multi-channel solenoid valves, the drive clock number generation unit is configured to generate the corresponding next-cycle channel drive clock number in a pipeline manner based on the channel number of each solenoid valve. Figure 1 The diagram illustrates an embodiment employing a pipelined approach, in which the ADC module within the drive clock generation unit contains only one ADC submodule, and the PID calculation module contains only one PID calculation submodule.

[0104] When using a pipelined approach, the drive clock generation unit should acquire or calculate the channel PWM percentage information based on the channel number. In other words, it can select and execute the corresponding process based on the channel number to achieve the reuse of the ADC module, PID calculation module, and channel PWM duty cycle to clock unit.

[0105] In practical implementation, the target current value of different solenoid valve channels and the PID calculation coefficient information can be associated and stored with the channel number. After obtaining the corresponding channel number, the target current value of the corresponding channel and the PID calculation coefficient information can be read and configured in the PID calculation module to realize the corresponding PID calculation. Specifically, the PID calculation coefficient information is the aforementioned proportional coefficient, integral coefficient and / or derivative coefficient.

[0106] In order to accurately control the solenoid valve, Figure 1 The figure shows an embodiment of the present invention that follows and transmits the channel number. That is, when performing the above data processing, it is necessary to bind with the corresponding channel number so that the PWM drive information can be accurately loaded into the solenoid valve drive circuit of the corresponding channel number.

[0107] In one embodiment of the present invention, the drive signal generation circuit includes a plurality of mutually independent channel PWM drive signal generation units, wherein,

[0108] A channel PWM drive signal generation unit is adapted and connected to a solenoid valve drive circuit, and each channel PWM drive signal generation unit receives the corresponding next cycle channel drive clock number and the next cycle channel drive start signal;

[0109] Based on the received next cycle channel drive clock count and the next cycle channel drive start signal, the channel PWM drive signal generation unit generates the corresponding channel PWM drive signal and loads the generated channel PWM drive signal onto the connected solenoid valve drive circuit.

[0110] In order to generate multiple PWM drive signals and apply them to the corresponding solenoid valve drive circuits, in one embodiment of the present invention, the drive signal generation circuit may include multiple independent channel PWM drive signal generation units, as can be seen from the above description. Figure 1 The term "multiple channel PWM drive signal generation units" refers to the situation where there are multiple channel PWM drive signal generation units. Specifically, the number of channel PWM drive signal generation units in the drive signal generation circuit is no less than the number of solenoid valve drive circuits, so that the solenoid valve drive circuits and channel PWM drive signal generation units are configured in a one-to-one correspondence connection state.

[0111] As can be seen from the above description, the solenoid valve drive circuit corresponds to the channel number mentioned above. Therefore, for any channel PWM drive signal generation unit, the generated next cycle channel drive clock number and the next cycle channel drive start signal can be loaded into the current solenoid valve drive circuit. After that, the current channel PWM drive signal generation unit can generate the channel PWM drive signal and load the generated channel PWM drive signal into the corresponding solenoid valve drive circuit. The corresponding solenoid valve drive circuit is the solenoid valve drive circuit connected to the channel PWM drive signal generation unit.

[0112] In one embodiment of the present invention, when each channel PWM drive signal generation unit generates a channel PWM drive signal, it includes:

[0113] Upon receiving a valid next cycle channel drive start signal, the channel PWM drive signal is configured to be valid within the counting time of the next cycle channel drive clock.

[0114] As explained above, each channel PWM drive signal generation unit receives both the next cycle channel drive clock count and the next cycle channel drive start signal simultaneously. Specifically, once the next cycle channel drive start signal is active, the channel PWM drive signal is configured to be active during the counting time of the next cycle channel drive clock count. When the channel PWM drive signal is active, it generally means that the channel PWM drive signal is in a high-level state. It can be understood that outside the counting time of the next cycle channel drive clock count, the channel PWM drive signal should be in a low-level inactive state, thereby achieving the corresponding duty cycle control state.

[0115] Specifically, when the channel PWM drive signal is in an active state, the solenoid valve can be driven and controlled by the solenoid valve drive circuit. However, when the channel PWM drive signal is in an inactive state, the solenoid valve drive circuit generally cannot drive and control the solenoid valve.

[0116] In one embodiment of the present invention, the verification of the drive of the multi-way solenoid valve includes:

[0117] The aforementioned drive processing circuit, drive signal generation circuit, multi-way solenoid valve, and solenoid valve drive circuit adapted to the multi-way solenoid valve are comprehensively modeled using the Verilog hardware description language.

[0118] During drive verification, the drive status information of the multi-channel solenoid valve drive circuit in the comprehensive modeling is loaded into the drive clock number generation unit, so that the drive clock number generation unit can generate the next cycle channel drive clock number corresponding to the solenoid valve drive circuit.

[0119] It should be understood that in order to verify the driving effect of multi-way solenoid valves, driving verification should generally be performed. In traditional verification, functional verification is usually achieved based on Matlab modeling and simulation or mixed-signal simulation. Specifically, Matlab modeling and simulation have the problem of inconsistency with the actual RTL logic design, which can easily lead to missed design problems and tape-out failure. Mixed-signal simulation has the problems of slow simulation speed and inability to port FPGA to accelerate verification, making it difficult to fully cover the functional verification in a short period of time, thus delaying production and delivery time.

[0120] To effectively verify the drive of the multi-channel solenoid valve, this invention employs Verilog hardware description language for comprehensive modeling. Specifically, Verilog hardware description language is used to model the aforementioned drive processing circuit, drive signal generation circuit, multi-channel solenoid valve, and multi-channel solenoid valve drive circuit. Due to the characteristics of Verilog hardware description language, it can effectively avoid the problems of inconsistent MATLAB designs, slow mixed-signal simulation speed, and inability to port to FPGA, thereby achieving a reliable and efficient verification process.

[0121] In practice, the drive processing circuit, drive signal generation circuit, and multi-channel solenoid valve drive circuit can be located within the same digital chip. Figure 1 The diagram illustrates one embodiment of drive verification. Specifically, the solenoid valve's synthetic simulation model refers to modeling the solenoid valve. Figure 2 An equivalent simplified solenoid valve drive circuit and an embodiment of the solenoid valve are shown.

[0122] Figure 2 In the diagram, Vsup and Vpre are the voltage sources provided to the solenoid valve by the solenoid valve drive circuit, Vss is grounded with a voltage value of 0V, and the PWM drive signal (high side hs, low side ls) is used to control the switching of the voltage source provided to the solenoid valve. The solenoid valve drive circuit has an internal equivalent resistance Rint from the voltage source to the chip port; the solenoid valve can be equivalently represented as a resistor R and an inductor L connected in series.

[0123] It should be noted that both the high side and the low side truth values ​​follow the state of the PWM drive signal. The difference is that the low side is strictly equal to the duration of the PWM drive signal, while the high side needs to be equal to 1 a certain period of time before the low side is equal to 1, and then equal to 0 a certain period of time after the low side is equal to 0. That is, from the time axis perspective, the high side = 1 needs to cover the low side = 1, which is equivalent to dead zone protection.

[0124] In practice, the driving state of the solenoid valve is determined by the PWM drive signal, including:

[0125] 1) When the upper side = 1 and the lower side = 1, Va = Vss = 0V;

[0126] 2) When the high side = 0 and the low side = 0, Va = Vsup. This is generally a high positive voltage, i.e., charging.

[0127] 3) When the high side = 1 and the low side = 0, Va = Vpre, which is generally a negative voltage, i.e., discharge.

[0128] Specifically, in the design implementation, there is no case where the higher side = 0 and the lower side = 1. Based on the circuit conditions, an RL differential equation can be established, which is: ,in, That is Figure 2 voltage in .

[0129] Since the PWM drive signal changes periodically with a digital clock, the frequency of the digital clock can be used as the smallest unit of change during discretization, resulting in the corresponding Verilog hardware description language, as follows:

[0130] Va = (hs==1)?0:((ls==1) ?Vpre:Vsink);

[0131] Vb = Va - I*(R+Rint);

[0132] Inext = I + Vb / L;

[0133] Initially, I=0. After each clock cycle, I=Inext, and then the above operation is repeated.

[0134] Taking a clock frequency of 16MHz, Vsup=12V, Vpre=-1V, Rint=0.1Ω, R=3.5Ω, and L=5uH as an example:

[0135] Va = (hs==1) ? 0 : ((ls==1)?-1_000_000 : 12_000_000); / / Unit: uV

[0136] Vb = Va - I*3600; / / Unit: μV

[0137] Inext = I + Vb / 5000; / / Unit (mA / 16000000)

[0138] Register I is initialized to 0 and connected to a 16MHz clock. The D terminal is connected to Inext. By operating in this way, the current value I is implemented in the form of a register. By modifying the smallest unit of parameters such as current, voltage, resistance, and inductance and making them fixed-point, synthesizable logic can be implemented for FPGA simulation.

[0139] In summary, a drive control method suitable for multi-way solenoid valves can be obtained. In one embodiment of the present invention, the multi-way solenoid valve to be driven and controlled is driven and controlled by the aforementioned drive control digital circuit.

[0140] Specifically, the drive control method for multi-way solenoid valves can be referred to the above description. The specific method should be based on the ability to perform the required drive control on the multi-way solenoid valves, and will not be elaborated here.

Claims

1. A digital circuit for driving and controlling multi-way solenoid valves, characterized in that, The digital circuit for driving and controlling a multi-way solenoid valve includes: The drive processing circuit receives drive operation information, generates drive control information for the next cycle corresponding to the drive operation information, and loads the generated drive control information for the next cycle into the drive signal generation circuit. The drive operation information includes at least the target drive frequency and the drive status information of each solenoid valve drive circuit when driving the corresponding solenoid valve. The next cycle drive control information includes at least the next cycle drive clock information and the next cycle drive regulation information; The next cycle drive clock information includes the number of next cycle channel drive clocks corresponding to each solenoid valve; The next cycle drive control information includes the next cycle channel drive start signal corresponding to each solenoid valve; The drive signal generation circuit generates a channel PWM drive signal corresponding to each solenoid valve based on the received drive control information for the next cycle. This channel PWM drive signal is then used to configure the solenoid valve drive circuit to drive and control the connected solenoid valves. When generating the channel PWM drive signal corresponding to each solenoid valve, the next cycle channel drive clock number and the next cycle channel drive start signal corresponding to the current solenoid valve are obtained. Then, based on the obtained next cycle channel drive clock number and the next cycle channel drive start signal, the corresponding channel PWM drive signal is generated.

2. The digital circuit for driving and controlling multi-channel solenoid valves according to claim 1, characterized in that: The drive processing circuit includes a frequency processing unit, a phase scheduling unit, and a drive clock number generation unit, wherein... The frequency processing unit processes the target driving frequency and generates the next cycle reference clock number and the next cycle reference start signal corresponding to the target driving frequency, and loads the generated next cycle reference clock number into the driving clock number generation unit. Based on the next cycle reference start signal and the preset working phase of each solenoid valve, the phase scheduling unit generates the next cycle channel drive start signal and clock number generation request information corresponding to each solenoid valve, and loads all the next cycle channel drive start signals into the drive signal generation circuit. Based on the clock count generation request information, the drive status information of each solenoid valve is collected sequentially. Based on the collected drive status information, the PWM ratio information of the channel corresponding to each solenoid valve drive circuit is determined at least. Then, based on the corresponding channel PWM ratio information and the reference clock count for the next cycle, the drive clock count generation unit generates the channel drive clock count for the next cycle corresponding to each solenoid valve.

3. The digital circuit for driving and controlling multi-channel solenoid valves according to claim 2, characterized in that: The clock count generation request information includes several generation processing sub-requests, each corresponding to a solenoid valve and a solenoid valve drive circuit for driving and controlling the solenoid valve. When a solenoid valve in one channel is a digital solenoid valve, the corresponding generation processing sub-request includes the channel number corresponding to the current solenoid valve and the PWM percentage acquisition request corresponding to the current solenoid valve drive circuit. The drive status information corresponding to the current solenoid valve is the channel PWM percentage information. When generating the next cycle channel drive clock count, the channel PWM percentage information of the current solenoid valve drive circuit is obtained based on the PWM percentage acquisition request. Then, based on the channel PWM percentage information and the next cycle reference clock count, the corresponding next cycle channel drive clock count is generated. When one solenoid valve is a current-type solenoid valve, the corresponding generation processing sub-request includes the channel number corresponding to the current solenoid valve and the PWM percentage calculation request corresponding to the current solenoid valve drive circuit. Furthermore, the drive status information of the current solenoid valve drive circuit must be at least the channel current. When generating the next cycle channel drive clock count, the corresponding channel current is obtained based on the PWM ratio calculation request, and the corresponding channel PWM ratio information is calculated based on the obtained channel current. Then, based on the channel PWM ratio information and the next cycle reference clock count, the corresponding next cycle channel drive clock count is generated.

4. The digital circuit for driving and controlling multi-channel solenoid valves according to claim 3, characterized in that, When calculating the channel PWM percentage information, the following is included: The obtained channel current is subjected to AD conversion to generate a channel quantization current value corresponding to the channel current; Perform PID calculations on the generated channel quantized current values ​​to generate the corresponding channel PWM percentage information after the PID calculation.

5. The digital circuit for driving and controlling multi-channel solenoid valves according to claim 2, characterized in that: For multi-channel solenoid valves, when generating the corresponding next-cycle channel drive clock number, based on the channel number of each solenoid valve, the drive clock number generation unit is configured to generate the corresponding next-cycle channel drive clock number in a pipelined manner. When calculating the number of channel drive clocks to generate the next cycle, we have: in, For the channel drive clock number in the next cycle, This provides information on the channel PWM duty cycle. This is the maximum duty cycle value. This serves as the reference clock number for the next cycle.

6. The digital circuit for driving and controlling a multi-way solenoid valve according to any one of claims 1 to 5, characterized in that, The drive signal generation circuit includes several independent PWM drive signal generation units, wherein... A channel PWM drive signal generation unit is adapted and connected to a solenoid valve drive circuit, and each channel PWM drive signal generation unit receives the corresponding next cycle channel drive clock number and the next cycle channel drive start signal; Based on the received next cycle channel drive clock count and the next cycle channel drive start signal, the channel PWM drive signal generation unit generates the corresponding channel PWM drive signal and loads the generated channel PWM drive signal onto the connected solenoid valve drive circuit.

7. The digital circuit for driving and controlling multi-channel solenoid valves according to claim 6, characterized in that, Each channel PWM drive signal generation unit generates the channel PWM drive signal, including: Upon receiving a valid next cycle channel drive start signal, the channel PWM drive signal is configured to be valid within the counting time of the next cycle channel drive clock.

8. The digital circuit for driving and controlling a multi-way solenoid valve according to any one of claims 2 to 5, characterized in that, When the frequency processing unit processes the target driving frequency, it includes: The current cycle reference clock count is counted, and a next cycle reference start signal is generated when the current cycle reference clock count is completed. Furthermore, the next cycle reference clock count is updated when the next cycle reference start signal is generated. When updating the reference clock count for the next cycle, the reference clock count for the next cycle is first calculated. In calculating the reference clock count for the next cycle, the reference digital clock frequency in the frequency processing unit is obtained, and the result of dividing the reference digital clock frequency by the target driving frequency is configured as the reference clock count for the next cycle.

9. The digital circuit for driving and controlling a multi-way solenoid valve according to any one of claims 2 to 5, characterized in that, The verification of the drive of a multi-way solenoid valve includes: The aforementioned drive processing circuit, drive signal generation circuit, multi-way solenoid valve, and solenoid valve drive circuit adapted to the multi-way solenoid valve are comprehensively modeled using the Verilog hardware description language. During drive verification, the drive status information of the multi-channel solenoid valve drive circuit in the comprehensive modeling is loaded into the drive clock number generation unit, so that the drive clock number generation unit can generate the next cycle channel drive clock number corresponding to the solenoid valve drive circuit.

10. A drive control method suitable for multi-way solenoid valves, characterized in that, For the multi-way solenoid valve to be driven and controlled, the drive control digital circuit of any one of claims 1 to 9 is used for drive control.

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