Memory compiler ip timing convergence and power co-optimization method and system

Abstract

The application provides a memory compiler IP timing convergence and power consumption collaborative optimization method and system, relates to the technical field of compilers, and comprises the following steps: obtaining circuit netlist information, extracting a timing path, performing wiring topology analysis, dividing a power consumption control domain by adopting a fine-grained power consumption control strategy, constructing a deep neural network model to predict a delay, training a decision tree model to obtain an optimization strategy, calculating a path priority to perform function partitioning, and finally generating a layout and wiring scheme that meets timing convergence requirements and is optimized in terms of power consumption. The application realizes the collaborative optimization of timing convergence and power consumption of the memory compiler IP, and improves the performance of integrated circuits.

Description

TECHNICAL FIELD

[0001] The present application relates to compiler technology, and in particular to a memory compiler IP timing convergence and power consumption collaborative optimization method and system. BACKGROUND

[0002] With the continuous improvement of the complexity of integrated circuit design, the optimization of performance, power consumption and area of memory compiler IP as a key component in chip design becomes particularly important. Memory compiler IP can automatically generate memory units of different specifications according to user requirements and is widely used in various chip designs. At the nanometer process node, the timing convergence and power consumption optimization of memory compiler IP becomes a key challenge in design. The traditional memory compiler IP design method mainly focuses on function implementation and area optimization, and lacks consideration of timing convergence and power consumption collaborative optimization, resulting in low design efficiency and performance bottleneck.

[0003] In the prior art, the timing convergence and power consumption optimization of memory compiler IP usually adopts coarse-grained global voltage adjustment or simple power consumption gating technology, and lacks fine-grained power consumption control strategies for timing paths. This method cannot make fine voltage distribution according to the characteristics of different timing paths, resulting in unnecessary power waste while meeting timing requirements, and it is difficult to achieve optimal balance between timing and power consumption.

[0004] Existing memory compiler IP optimization methods mostly rely on the experience of designers and repeated manual adjustment, and lack intelligent prediction models and automatic optimization strategies. This method not only consumes time and effort, but also is difficult to deal with multi-variable optimization problems in complex designs, resulting in limited optimization effect and difficulty in adapting to changes in different process nodes and design specifications.

[0005] In addition, the layout and routing optimization of memory compiler IP in the prior art usually adopts a general layout and routing algorithm, without fully considering the unique structural characteristics and timing path priorities of memory, resulting in deficiencies in timing convergence and power consumption control of the generated layout and routing scheme, and difficulty in meeting the design requirements of high performance and low power consumption. SUMMARY

[0006] The embodiments of the present application provide a memory compiler IP timing convergence and power consumption collaborative optimization method and system, which can solve the problems in the prior art.

[0007] The first aspect of the embodiments of the present application is,

[0008] A memory compiler IP timing convergence and power consumption collaborative optimization method is provided, comprising:

[0009] Obtaining circuit netlist information of a memory compiler IP, extracting a timing path based on the circuit netlist information, performing a wiring topology analysis on the timing path, and determining the length of a connection between timing units and the interconnection delay in the timing path;

[0010] Based on the length of the connection and the interconnection delay, the timing path is divided into multiple power consumption control domains using a fine-grained power consumption control strategy, and different operating voltages are set for each power consumption control domain, so that the operating voltage of the power consumption control domain close to the timing end point is higher than that of the power consumption control domain close to the timing start point.

[0011] Based on the voltage and delay data of the power consumption control domain, a deep neural network model is constructed, and a delay prediction value is obtained based on the deep neural network model. According to the prediction error between the delay prediction value and the actual delay value, the parameters of the deep neural network model are dynamically adjusted and the reliability index is calculated. When the reliability index meets the preset reliability threshold, the delay prediction value is used for timing optimization.

[0012] Obtaining feature parameters of the timing path, constructing a feature vector matrix based on the feature parameters, training a decision tree model based on the feature vector matrix to obtain an optimization strategy, and iteratively updating the parameters of the decision tree model through loss function gradient and sample weight until the optimization target improvement meets the preset condition threshold.

[0013] Based on the timing path, the path priority is calculated, the memory compiler IP is functionally partitioned based on the path priority, and a partition cost function is constructed. According to the partition cost function, the unit position optimization and hierarchical wiring optimization are performed, and the memory compiler IP layout and wiring scheme that meets the timing convergence requirement and power consumption optimization is generated.

[0014] Based on the length of the connection and the interconnection delay, the timing path is divided into multiple power consumption control domains using a fine-grained power consumption control strategy, and different operating voltages are set for each power consumption control domain, so that the operating voltage of the power consumption control domain close to the timing end point is higher than that of the power consumption control domain close to the timing start point.

[0015] Obtaining physical parameters of the connection segment in the timing path, the physical parameters including the length of the connection segment, the width of the connection segment, the interlayer medium thickness of the connection segment, and the metal specific resistance of the connection segment;

[0016] Based on the physical parameters of the connection segment, the unit length resistance and the unit length capacitance of the connection segment are calculated using a distributed RC model, and the total resistance and the total capacitance of the connection segment are calculated according to the unit length resistance and the unit length capacitance.

[0017] Calculate the interconnection delay of the wire segment based on the total resistance and the total capacitance of the wire segment, and obtain the interconnection delay distribution characteristics of the timing path; according to the delay sensitivity of the timing units in the timing path, adopt a hierarchical clustering algorithm to divide adjacent timing units with similar delay sensitivity into multiple power consumption control domains, wherein the delay sensitivity represents the influence degree of the operating voltage of the timing unit on the total delay of the timing path;

[0018] For the multiple power consumption control domains obtained by division, under the condition of meeting the timing constraint, the operating voltage of each power consumption control domain is determined by minimizing the dynamic power consumption of each power consumption control domain, wherein the operating voltage of the power consumption control domain close to the timing end point is higher than the operating voltage of the power consumption control domain close to the timing start point.

[0019] Based on the physical parameters of the wire segment, the unit length resistance and the unit length capacitance of the wire segment are calculated by using a distributed RC model, and the total resistance and the total capacitance of the wire segment are calculated according to the unit length resistance and the unit length capacitance, which comprises:

[0020] The unit length resistance of the wire segment is calculated by using a distributed RC model, and the calculation process of the unit length resistance is as follows: the metal specific resistance is divided by the product of the wire segment width and the interlayer dielectric thickness;

[0021] Based on the physical parameters of the wire segment, the unit length capacitance of the wire segment is calculated, and the calculation process of the unit length capacitance comprises: calculating the parallel plate capacitance, multiplying the vacuum relative dielectric constant system by the wire segment width and dividing by the interlayer dielectric thickness; calculating the edge capacitance, multiplying the vacuum relative dielectric constant system by the logarithmic function of the ratio of the interlayer dielectric thickness to the wire segment width; calculating the coupling capacitance, multiplying the vacuum relative dielectric constant system by the interlayer dielectric thickness and dividing by the metal specific resistance; adding the parallel plate capacitance, the edge capacitance and the coupling capacitance to obtain the unit length capacitance;

[0022] Obtain the signal frequency parameter of the wire segment, the signal frequency parameter includes the signal frequency band and the characteristic frequency parameter, multiply the signal frequency parameter by the unit length resistance to obtain the frequency corrected unit length resistance;

[0023] Divide the wire segment into multiple equal-length sub-segments, multiply the frequency corrected unit length resistance of each sub-segment by the sub-segment length and accumulate to obtain the total resistance of the wire segment, and multiply the unit length capacitance of each sub-segment by the sub-segment length and accumulate to obtain the total capacitance of the wire segment.

[0024] dynamically adjusting parameters of the deep neural network model according to a prediction error between the delay prediction value and an actual delay value and calculating a reliability index, and using the delay prediction value for timing optimization when the reliability index meets a preset reliability threshold, comprising:

[0025] constructing a comprehensive loss function, training the deep neural network model using a gradient descent method, calculating a weight gradient according to the comprehensive loss function, and updating weight parameters of the neural network based on the weight gradient;

[0026] obtaining a new working voltage combination, inputting the working voltage combination into the deep neural network model to obtain a corresponding delay prediction value;

[0027] collecting an actual delay measurement value under the working voltage combination, and calculating a prediction error between the delay prediction value and the actual delay measurement value;

[0028] dynamically adjusting model parameters according to the prediction error, calculating a weight update amount, and calculating a bias update amount, wherein the weight update amount is directly proportional to the product of the prediction error and the weight gradient, and the bias update amount is directly proportional to the sign value of the prediction error;

[0029] calculating a confidence degree of a prediction result based on the prediction error, wherein the confidence degree decreases with the increase of a prediction variance, and using a difference value between the confidence degree and the prediction error as a reliability index;

[0030] when the reliability index is greater than a preset reliability threshold, using the current delay prediction value to guide timing optimization; and when the reliability index is less than the preset reliability threshold, triggering an online learning process of the model, adding new training data to a historical data set, and retraining the deep neural network model.

[0031] constructing a feature vector matrix based on the feature parameters, and training a decision tree model to obtain an optimization strategy based on the feature vector matrix, wherein parameters of the decision tree model are iteratively updated by a loss function gradient and a sample weight until an optimization target improvement amount meets a preset condition threshold, comprising:

[0032] constructing a feature vector matrix based on the feature parameters, wherein the feature vector matrix includes a timing feature vector, a power consumption feature vector, and an area feature vector;

[0033] calculating sensitivities of the timing feature vector, the power consumption feature vector, and the area feature vector to voltage, constructing a sensitivity feature vector, and the sensitivity feature vector includes a timing sensitivity to voltage, a power consumption sensitivity to voltage, and an area sensitivity to voltage;

[0034] combine the timing feature vector, the power consumption feature vector, the area feature vector and the sensitivity feature vector to form an input feature matrix;

[0035] construct a decision tree model based on the input feature matrix, output a voltage adjustment amount, a size adjustment amount and a topology adjustment scheme through the decision tree model, wherein the voltage adjustment amount is obtained through a sigmoid function, the size adjustment amount is obtained through a tanh function, and the topology adjustment scheme is obtained through a softmax function;

[0036] construct an optimization loss function, calculate a loss function gradient based on the optimization loss function, calculate an optimization target improvement amount, and determine a sample weight according to the optimization target improvement amount, wherein the sample weight increases with the increase of the optimization target improvement amount;

[0037] update parameters of the decision tree model according to the sample weight and the loss function gradient, and optimize and adjust the timing path based on the updated decision tree model until the weighted ratio of the optimization target improvement amount and the optimization overhead meets a preset condition threshold.

[0038] perform cell position optimization and hierarchical routing optimization according to the partition cost function to generate a memory compiler IP layout and routing scheme that meets timing convergence requirements and power consumption optimization, including:

[0039] perform functional partitioning of the memory compiler IP based on the partition cost function, construct a cell position optimization cost function based on the results of the functional partitioning, and determine the optimization direction of the cell through the gradient direction of the cell position optimization cost function;

[0040] multiply the optimization direction of the cell by an exponential decay function of power consumption change to obtain a power consumption-aware cell movement amount, wherein the power consumption change is determined by the power consumption difference before and after movement, and adjust the cell position based on the power consumption-aware cell movement amount;

[0041] construct an interlayer routing cost function for the adjusted cell position, perform routing layer allocation based on the interlayer routing cost function, calculate the routing congestion degree after the routing layer allocation, wherein the routing congestion degree is the ratio of routing demand to routing capacity, and perform power consumption-aware adjustment of the network line width according to the routing congestion degree;

[0042] construct a layout quality evaluation function, wherein the layout quality evaluation function is the weighted sum of the ratio of each evaluation index to the target value, and the evaluation index includes a timing margin index, a power consumption index and a routing quality index, and calculate the gradient of the layout quality evaluation function;

[0043] Multiplying the gradient of the layout quality assessment function by the constraint matrix to obtain an optimization direction, and performing iterative optimization using an adaptive step size, wherein the adaptive step size decays exponentially with an increase in the number of iterations;

[0044] According to the optimization direction, the unit position and routing scheme are updated until the improvement of the layout quality evaluation function is less than a preset improvement threshold and the worst negative margin is greater than zero and the total negative margin is greater than zero, thereby generating a memory compiler IP layout and routing scheme that meets the timing closure requirements and optimizes power consumption. The second aspect of the embodiment of the present invention is,

[0045] Provides memory compiler IP timing closure and power consumption co-optimization system, including:

[0046] The first unit is configured to obtain circuit netlist information of a memory compiler IP, extract a timing path based on the circuit netlist information, perform wiring topology analysis on the timing path, and determine the connection length and interconnection delay between timing cells in the timing path;

[0047] a second unit, configured to divide the timing path into a plurality of power control domains based on the connection length and the interconnection delay by adopting a fine-grained power control strategy, and set a different operating voltage for each of the power control domains, so that the operating voltage of the power control domain close to the timing end point is higher than the operating voltage of the power control domain close to the timing start point;

[0048] A third unit is configured to construct a deep neural network model based on the voltage and delay data of the power consumption control domain, obtain a delay prediction value based on the deep neural network model; dynamically adjust parameters of the deep neural network model according to a prediction error between the delay prediction value and the actual delay value and calculate a reliability index; and use the delay prediction value for timing optimization when the reliability index meets a preset reliability threshold;

[0049] A fourth unit is configured to obtain characteristic parameters of the time series path and construct a characteristic vector matrix based on the characteristic parameters; train a decision tree model based on the characteristic vector matrix to obtain an optimization strategy, and iteratively update the parameters of the decision tree model through the loss function gradient and sample weights until the optimization target improvement meets a preset condition threshold;

[0050] The fifth unit is used to calculate the path priority based on the timing path, functionally partition the memory compiler IP based on the path priority and construct a partition cost function; perform cell location optimization and hierarchical routing optimization according to the partition cost function, and generate a memory compiler IP layout and routing solution that meets timing convergence requirements and optimizes power consumption.

[0051] According to a third aspect of the embodiments of the present invention,

[0052] An electronic device is provided, comprising:

[0053] a processor;

[0054] a memory for storing processor-executable instructions;

[0055] wherein the processor is configured to invoke the instructions stored by the memory to perform the aforementioned method.

[0056] A fourth aspect of the embodiments of the present application,

[0057] A computer-readable storage medium is provided, which stores computer program instructions, and the computer program instructions are executed by a processor to implement the aforementioned method.

[0058] The beneficial effects of the present application are as follows:

[0059] The present application divides the timing path into multiple power consumption control domains through a fine-grained power consumption control strategy, and sets different working voltages for each power consumption control domain, thereby realizing the collaborative optimization of timing convergence and power consumption of the memory compiler IP, effectively balancing the contradiction between timing performance and power consumption, and improving the overall performance of the memory compiler IP.

[0060] The present application predicts the delay based on a deep neural network model, improves the prediction accuracy by dynamically adjusting the model parameters, and generates an optimization strategy by using a decision tree model, thereby realizing accurate analysis and intelligent optimization of the timing path, greatly improving the timing convergence efficiency, reducing the design iteration times, and shortening the design cycle of the memory compiler IP.

[0061] The present application realizes global optimization of the memory compiler IP by the path priority calculation and functional partitioning method, combined with the unit position optimization and hierarchical routing optimization guided by the cost function, significantly improves the timing margin of the critical path, reduces the overall power consumption, and improves the stability and reliability of the memory compiler IP under different working conditions. BRIEF DESCRIPTION OF DRAWINGS

[0062] Figure 1 The flowchart of the memory compiler IP timing convergence and power consumption collaborative optimization method of the embodiments of the present application is shown in the figure.

[0063] Figure 2 The comparative diagram of the loss convergence curve of the deep neural network model training of the embodiments of the present application is shown in the figure.

[0064] Figure 3 The comparative thermodynamic diagram of the Monte Carlo simulation routing quality of the embodiments of the present application is shown in the figure. DETAILED DESCRIPTION

[0065] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0066] The technical solutions of the present application will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and some embodiments may not be described again for the same or similar concepts or processes.

[0067] Figure 1 The flowchart of the memory compiler IP timing convergence and power consumption collaborative optimization method of the embodiments of the present application is shown as Figure 1 indicated, the method comprises:

[0068] Obtaining circuit netlist information of a memory compiler IP, extracting a timing path based on the circuit netlist information, performing wiring topology analysis on the timing path, and determining the length of the connection between the timing units in the timing path and the interconnection delay;

[0069] Based on the length of the connection and the interconnection delay, the timing path is divided into multiple power consumption control domains by using a fine-grained power consumption control strategy, different working voltages are set for each power consumption control domain, and the working voltage of the power consumption control domain close to the timing end point is higher than that of the power consumption control domain close to the timing start point;

[0070] Based on the voltage and delay data of the power consumption control domain, a deep neural network model is constructed, and a delay prediction value is obtained based on the deep neural network model; according to the prediction error between the delay prediction value and the actual delay value, the parameters of the deep neural network model are dynamically adjusted and the reliability index is calculated, and when the reliability index meets the preset reliability threshold, the delay prediction value is used for timing optimization;

[0071] Obtaining feature parameters of the timing path, constructing a feature vector matrix based on the feature parameters; training a decision tree model based on the feature vector matrix to obtain an optimization strategy, and iteratively updating the parameters of the decision tree model through loss function gradient and sample weight until the optimization target improvement meets the preset condition threshold;

[0072] Based on the timing path, a path priority is calculated, a functional partition of the memory compiler IP is performed based on the path priority, and a partition cost function is constructed; according to the partition cost function, unit position optimization and hierarchical wiring optimization are performed, and a memory compiler IP layout and wiring scheme meeting the timing convergence requirement and power consumption optimization is generated.

[0073] In an alternative embodiment, based on the wire length and the interconnect delay, the timing path is divided into multiple power control domains using a fine-grained power control strategy, and different operating voltages are set for each of the power control domains, such that the operating voltage of the power control domain close to the timing end point is higher than the operating voltage of the power control domain close to the timing start point, comprising:

[0074] Obtaining the physical parameters of the wire segment in the timing path, the physical parameters including the length of the wire segment, the width of the wire segment, the interlayer dielectric thickness of the wire segment, and the metal specific resistance of the wire segment;

[0075] Based on the physical parameters of the wire segment, the unit length resistance and the unit length capacitance of the wire segment are calculated using a distributed RC model, and the total resistance and the total capacitance of the wire segment are calculated according to the unit length resistance and the unit length capacitance;

[0076] Based on the total resistance and the total capacitance of the wire segment, the interconnect delay of the wire segment is calculated, and the interconnect delay distribution characteristics of the timing path are obtained; according to the delay sensitivity of the timing unit in the timing path, a hierarchical clustering algorithm is used to divide the adjacent timing units with similar delay sensitivity into multiple power control domains, wherein the delay sensitivity represents the degree of influence of the operating voltage of the timing unit on the total delay of the timing path;

[0077] For the multiple power control domains obtained by division, under the condition of meeting the timing constraint, the operating voltage of each power control domain is determined by minimizing the dynamic power consumption of each power control domain, wherein the operating voltage of the power control domain close to the timing end point is higher than the operating voltage of the power control domain close to the timing start point.

[0078] Obtaining the physical parameters of the wire segment in the timing path. In a specific embodiment, the key timing path in the chip design is analyzed, and the physical parameters of each wire segment are extracted, including the length, width, interlayer dielectric thickness, and metal specific resistance of the wire segment. For example, for a timing path containing 10 wire segments, the first wire segment has a length of 100 microns, a width of 0.5 microns, an interlayer dielectric thickness of 0.3 microns, and a metal specific resistance of 0.05 ohms / square; the second wire segment has a length of 150 microns, a width of 0.6 microns, an interlayer dielectric thickness of 0.35 microns, and a metal specific resistance of 0.06 ohms / square; and the physical parameters of all wire segments are obtained in this way.

[0079] Based on the physical parameters of the wire segment, the unit length resistance and the unit length capacitance of the wire segment are calculated using a distributed RC model. In actual implementation, the unit length resistance can be calculated by dividing the specific resistance of the metal by the width of the wire. For example, the unit length resistance of the first wire segment is 0.05 ohm / square divided by 0.5 micrometers, which equals 0.1 ohm / micrometer. The unit length capacitance is calculated according to the parallel plate capacitor model, taking into account the width of the wire, the thickness of the interlayer dielectric, and the dielectric constant. Assuming the dielectric constant is 3.9, the unit length capacitance of the first wire segment can be calculated as 0.057 femtofarad / micrometer.

[0080] The total resistance and the total capacitance of the wire segment are calculated based on the unit length resistance and the unit length capacitance. The total resistance is equal to the unit length resistance multiplied by the length of the wire, and the total capacitance is equal to the unit length capacitance multiplied by the length of the wire. Taking the first wire segment as an example, the total resistance is 0.1 ohm / micrometer multiplied by 100 micrometers, which equals 10 ohms; the total capacitance is 0.057 femtofarad / micrometer multiplied by 100 micrometers, which equals 5.7 femtofarads.

[0081] Based on the total resistance and the total capacitance of the wire segment, the interconnection delay of the wire segment is calculated to obtain the interconnection delay distribution characteristics of the timing path. In one embodiment, the Elmore delay model is used to calculate the interconnection delay, which takes into account the effects of resistance and capacitance in the RC network on signal transmission. For example, the interconnection delay of the first wire segment can be calculated as half of 10 ohms multiplied by 5.7 femtofarads, which is approximately 28.5 picoseconds. Similar calculations are performed for all wire segments to obtain the complete interconnection delay distribution characteristics.

[0082] According to the delay sensitivity of the timing units in the timing path, a hierarchical clustering algorithm is used to divide adjacent timing units with similar delay sensitivity into multiple power consumption control domains. Delay sensitivity represents the degree of influence of the operating voltage of a timing unit on the total delay of the timing path. In specific implementation, the delay change rate of each timing unit under different operating voltages can be obtained through a static timing analysis tool. For example, for a path containing 20 timing units, when the operating voltage decreases from 1.0 volt to 0.9 volt, the delay of the first timing unit increases by 15%, the delay of the second timing unit increases by 14%, the delay of the third timing unit increases by 16%, the delay of the eighteenth timing unit increases by 25%, the delay of the nineteenth timing unit increases by 27%, and the delay of the twentieth timing unit increases by 26%.

[0083] The specific implementation steps of the hierarchical clustering algorithm are as follows: first, each timing unit is regarded as an independent power consumption control domain; then, the delay sensitivity difference between adjacent power consumption control domains is calculated; then, the adjacent power consumption control domains with the smallest delay sensitivity difference are merged; the merging process is repeated until the preset number of power consumption control domains is reached or the delay sensitivity difference exceeds the threshold. In the above example, the threshold is set to 5%, and 20 timing units are divided into 3 power consumption control domains: the first to the tenth timing units are the first power consumption control domain (the delay sensitivity is about 15%), the eleventh to the fifteenth timing units are the second power consumption control domain (the delay sensitivity is about 20%), and the sixteenth to the twentieth timing units are the third power consumption control domain (the delay sensitivity is about 26%).

[0084] For the multiple power consumption control domains obtained by division, the operating voltage of each power consumption control domain is determined by minimizing the dynamic power consumption of each power consumption control domain under the condition of meeting the timing constraint. The dynamic power consumption is proportional to the square of the operating voltage, so reducing the operating voltage is an effective method to reduce dynamic power consumption. In one embodiment, an iterative optimization method is used to determine the operating voltage of each power consumption control domain: first, set the initial operating voltage of all power consumption control domains to the standard voltage (such as 1.0 volt); then, gradually reduce the operating voltage of each power consumption control domain from the timing starting point, while ensuring that the timing constraint is still met through static timing analysis; finally, when the operating voltage of any power consumption control domain cannot be further reduced without violating the timing constraint, the optimization process ends.

[0085] In the above example, after optimization, the operating voltage of the first power consumption control domain (close to the timing starting point) is set to 0.8 volts, the operating voltage of the second power consumption control domain is set to 0.9 volts, and the operating voltage of the third power consumption control domain (close to the timing end point) is set to 1.0 volts. This setting ensures that the operating voltage of the power consumption control domain close to the timing end point is higher than that of the power consumption control domain close to the timing starting point, thereby achieving power optimization while meeting the timing constraint.

[0086] Through actual testing, in a design containing 1000 timing paths, compared with the traditional single voltage domain method, the method can achieve about 20% reduction in dynamic power consumption while maintaining a timing margin of no less than 50 picoseconds. In addition, compared with the traditional multi-voltage domain method, the method can additionally reduce about 8% of the dynamic power consumption through the fine-grained power consumption control strategy.

[0087] The method is suitable for various integrated circuit designs, especially for mobile device chips, artificial intelligence accelerators and low-power Internet of Things devices that have strict requirements for power consumption and performance. Through the fine-grained power consumption control strategy, the chip power consumption can be significantly reduced under the premise of ensuring performance, prolonging battery life and improving user experience.

[0088] In an alternative embodiment, based on the physical parameters of the wire segment, the unit length resistance and the unit length capacitance of the wire segment are calculated using a distributed RC model, and the total resistance and the total capacitance of the wire segment are calculated according to the unit length resistance and the unit length capacitance, which comprises:

[0089] The unit length resistance of the wire segment is calculated using a distributed RC model, and the calculation process of the unit length resistance is that the metal specific resistance is divided by the product of the wire segment width and the interlayer dielectric thickness.

[0090] Based on the physical parameters of the wire segment, the unit length capacitance of the wire segment is calculated, and the calculation process of the unit length capacitance comprises: calculating a parallel plate capacitance, multiplying the vacuum relative dielectric constant system by the wire segment width and dividing the product by the interlayer dielectric thickness; calculating an edge capacitance, multiplying the vacuum relative dielectric constant system by the logarithmic function of the ratio of the interlayer dielectric thickness to the wire segment width; calculating a coupling capacitance, multiplying the vacuum relative dielectric constant system by the interlayer dielectric thickness and dividing the product by the metal specific resistance; and adding the parallel plate capacitance, the edge capacitance and the coupling capacitance to obtain the unit length capacitance.

[0091] The signal frequency parameter of the wire segment is obtained, the signal frequency parameter comprises a signal frequency band and a characteristic frequency parameter, and the signal frequency parameter is multiplied by the unit length resistance to obtain a frequency-corrected unit length resistance.

[0092] The wire segment is divided into a plurality of equal-length sub-segments, the product of the frequency-corrected unit length resistance of each sub-segment and the sub-segment length is accumulated to obtain the total resistance of the wire segment, and the product of the unit length capacitance of each sub-segment and the sub-segment length is accumulated to obtain the total capacitance of the wire segment.

[0093] The physical parameters of the wire segment are obtained, including the width, length, metal specific resistance, interlayer dielectric thickness and vacuum relative dielectric constant system of the wire segment. For example, for a 90-nanometer process metal wire segment, the width is 0.12 micrometers, the length is 100 micrometers, the metal specific resistance is 2.2 x 10^-8 ohm-meters, the interlayer dielectric thickness is 0.18 micrometers, and the vacuum relative dielectric constant system is 8.85 x 10^-12 farad / meter.

[0094] The unit length resistance of the wire segment is calculated using the distributed RC model. The calculation process is as follows: divide the metal specific resistance by the product of the wire segment width and the interlayer dielectric thickness. Using the above parameters as an example, the unit length resistance is calculated as follows: divide the metal specific resistance 2.2 x 10"8ohm-m by the product of the wire segment width 0.12 microns and the interlayer dielectric thickness 0.18 microns, to obtain a unit length resistance of 1.02 x 103ohm / m.

[0095] Based on the physical parameters of the wire segment, the unit length capacitance of the wire segment is calculated. The calculation of the unit length capacitance includes three parts: parallel plate capacitance, edge capacitance, and coupling capacitance.

[0096] The calculation process of the parallel plate capacitance is as follows: multiply the vacuum relative dielectric constant system by the wire segment width, and then divide by the interlayer dielectric thickness. Using the above parameters as an example, the parallel plate capacitance is calculated as follows: multiply the vacuum relative dielectric constant system 8.85 x 10"12farad / m by the wire segment width 0.12 microns, and then divide by the interlayer dielectric thickness 0.18 microns, to obtain a parallel plate capacitance of 5.9 x 10"11farad / m.

[0097] The calculation process of the edge capacitance is as follows: multiply the vacuum relative dielectric constant system by the logarithmic function of the ratio of the interlayer dielectric thickness to the wire segment width. Using the above parameters as an example, the edge capacitance is calculated as follows: multiply the vacuum relative dielectric constant system 8.85 x 10"12farad / m by the logarithmic function of the ratio of the interlayer dielectric thickness 0.18 microns to the wire segment width 0.12 microns (take the natural logarithm ln(0.18 / 0.12)≈0.405), to obtain an edge capacitance of 3.58 x 10"12farad / m.

[0098] The calculation process of the coupling capacitance is as follows: multiply the vacuum relative dielectric constant system by the interlayer dielectric thickness, and then divide by the metal specific resistance. Using the above parameters as an example, the coupling capacitance is calculated as follows: multiply the vacuum relative dielectric constant system 8.85 x 10"12farad / m by the interlayer dielectric thickness 0.18 microns, and then divide by the metal specific resistance 2.2 x 10"8ohm-m, to obtain a coupling capacitance of 7.23 x 10"5farad / m.

[0099] The parallel plate capacitance, edge capacitance, and coupling capacitance are added together to obtain a unit length capacitance of 7.23 x 10"5farad / m.

[0100] The signal frequency parameters of the connection segment include the signal frequency band and the characteristic frequency parameter. For example, for a connection segment working at a frequency of 1 GHz, the characteristic frequency parameter can be set to 1x10^9 Hz. Multiply the signal frequency parameter by the unit length resistance to obtain the frequency-modified unit length resistance. Taking the above parameters as an example, the frequency-modified unit length resistance is 1.02x10^3 ohms / m multiplied by 1x10^9 Hz, i.e. 1.02x10^12 ohms·Hz / m.

[0101] The connection segment is divided into multiple equal-length sub-segments, and the resistance and capacitance of each sub-segment are calculated. Assume that the 100-micron-long connection segment is divided into 10 equal-length sub-segments, each with a length of 10 microns. For each sub-segment, the product of its frequency-modified unit length resistance and sub-segment length is calculated to obtain the sub-segment resistance. Taking the above parameters as an example, the resistance of each sub-segment is 1.02x10^12 ohms·Hz / m multiplied by 10 microns, i.e. 1.02x10^7 ohms·Hz. The resistances of all sub-segments are added to obtain the total resistance of the connection segment, which is 1.02x10^8 ohms·Hz.

[0102] For each sub-segment, the product of its unit length capacitance and sub-segment length is calculated to obtain the sub-segment capacitance. Taking the above parameters as an example, the capacitance of each sub-segment is 7.23x10^-5 farad / m multiplied by 10 microns, i.e. 7.23x10^-10 farad. The capacitances of all sub-segments are added to obtain the total capacitance of the connection segment, which is 7.23x10^-9 farad.

[0103] The number of sub-segments can be adjusted according to the specific circumstances of the connection segment to improve the calculation accuracy. For example, for a connection segment with large length variation or uneven width, the number of sub-segments can be increased, or unequal-length sub-segment division can be performed according to the actual shape of the connection segment.

[0104] During the calculation process, environmental factors such as temperature and humidity can also be considered to affect the resistance and capacitance of the connection segment. For example, an increase in temperature will cause the specific resistance of the metal to increase, thereby affecting the resistance value of the connection segment. A temperature coefficient can be introduced to modify the calculation results.

[0105] The total resistance and total capacitance of the connection segment can be accurately calculated, providing important reference for integrated circuit design. This method is suitable for integrated circuit design of various process nodes, especially for circuit design of high-frequency signal transmission, which can effectively predict the delay and distortion of signal transmission, and improve the accuracy and reliability of the design.

[0106] In an optional embodiment, dynamically adjusting the parameters of the deep neural network model and calculating a reliability index based on a prediction error between the delay prediction value and the actual delay value, and using the delay prediction value for timing optimization when the reliability index meets a preset reliability threshold includes:

[0107] Constructing a comprehensive loss function, training the deep neural network model using a gradient descent method, calculating weight gradients according to the comprehensive loss function, and updating weight parameters of the neural network based on the weight gradients;

[0108] Obtaining a new operating voltage combination, inputting the operating voltage combination into the deep neural network model, and obtaining a corresponding delay prediction value;

[0109] Collecting an actual delay measurement value under the operating voltage combination, and calculating a prediction error between the delay prediction value and the actual delay measurement value;

[0110] Dynamically adjusting model parameters according to the prediction error, calculating a weight update amount, wherein the weight update amount is proportional to the product of the prediction error and the weight gradient; and calculating a bias update amount, wherein the bias update amount is proportional to the sign value of the prediction error;

[0111] Calculating a confidence level of a prediction result based on the prediction error, wherein the confidence level decreases as the prediction variance increases, and using the difference between the confidence level and the prediction error as a reliability indicator;

[0112] When the reliability index is greater than the preset reliability threshold, the current delay prediction value is used to guide timing optimization; when the reliability index is less than the preset reliability threshold, the model online learning process is triggered, new training data is added to the historical data set, and the deep neural network model is retrained.

[0113] A comprehensive loss function is constructed, and the deep neural network model is trained using the gradient descent method. The deep neural network model includes an input layer, multiple hidden layers, and an output layer. The input layer receives the operating voltage combination data, and the output layer outputs the corresponding delay prediction value. The comprehensive loss function consists of a mean square error term and a regularization term. The mean square error term is used to measure the gap between the predicted value and the actual value, and the regularization term is used to prevent the model from overfitting. Specifically, the mean square error term is the sum of the squares of the differences between the predicted delay value and the actual delay value, and the regularization term is the sum of the squares of the model weight parameters multiplied by the regularization coefficient. The regularization coefficient can be set to 0.001 to control the regularization strength.

[0114] The batch gradient descent method is adopted, and 64 samples are selected for each batch. The learning rate is initially set to 0.01, and the learning rate decay strategy is adopted, that is, the learning rate is multiplied by 0.95 every 100 training batches. The weight gradient is calculated according to the comprehensive loss function, that is, the partial derivative of the loss function with respect to each layer weight. For example, for the weight matrix of the i-th layer, the gradient calculation involves the product of the input of this layer and the error term of the next layer. After the gradient is calculated, the weight parameters of the neural network are updated based on the gradient, and the update formula is the current weight minus the learning rate multiplied by the gradient.

[0115] A new working voltage combination is obtained. The working voltage combination includes core voltage, memory voltage and input / output voltage, for example (0.9V, 1.1V, 1.8V). The working voltage combination is input into the trained deep neural network model, and the corresponding delay prediction value is obtained through forward propagation calculation. For example, for the above voltage combination, the model predicts the delay value to be 2.5 nanoseconds.

[0116] The actual delay measurement value under the working voltage combination is collected. The collection method can be to run a standard test program on the actual hardware and record the execution time. Assume that the actual measured delay value is 2.7 nanoseconds. Calculate the prediction error between the delay prediction value and the actual delay measurement value, that is, 2.5 nanoseconds minus 2.7 nanoseconds, to get -0.2 nanoseconds.

[0117] The model parameters are dynamically adjusted according to the prediction error. First, calculate the weight update amount, which is proportional to the product of the prediction error and the weight gradient. Specifically, the weight update amount is equal to the learning rate multiplied by the prediction error multiplied by the weight gradient. For example, if the gradient of a certain weight is 0.05, the prediction error is -0.2 nanoseconds, and the learning rate is 0.01, then the update amount of the weight is 0.01 x (-0.2) x 0.05 = -0.0001. At the same time, calculate the bias update amount, which is proportional to the absolute value of the prediction error. For example, the prediction error is -0.2 nanoseconds, and its absolute value is -1. If the bias update coefficient is 0.005, then the bias update amount is 0.005 x (-1) = -0.005.

[0118] The confidence of the prediction result is calculated based on the prediction error. The confidence decreases as the prediction variance increases. The prediction variance can be estimated by the sum of the squares of the historical prediction errors divided by the number of samples minus one. For example, if the sum of the squares of the errors of the last 10 predictions is 0.5, then the prediction variance is estimated to be 0.5 / (10-1)≈0.056. The confidence can be represented as 1 minus the ratio of the prediction variance to the preset variance threshold, which can be set to 0.1. In this example, the confidence is 1-(0.056 / 0.1)=0.44. The difference between the confidence and the absolute value of the prediction error is taken as the reliability indicator. The absolute value of the prediction error is 0.2, so the reliability indicator is 0.44-0.2=0.24.

[0119] When the reliability index is greater than the preset reliability threshold, the current delay prediction value is used to guide timing optimization. The preset reliability threshold can be set to 0.2. In this example, the reliability index is 0.24, which is greater than the preset reliability threshold 0.2, so the current delay prediction value 2.5 nanoseconds can be used to guide timing optimization. Timing optimization includes adjusting clock frequency, reallocating critical path resources, and other operations.

[0120] When the reliability index is less than the preset reliability threshold, the model online learning process is triggered. For example, if the calculated reliability index is 0.15, which is less than the preset reliability threshold 0.2, the model online learning needs to be triggered. In the online learning process, new training data is added to the historical data set. The new training data includes the working voltage combination and its corresponding actual delay measurement value, such as ((0.9V, 1.1V, 1.8V), 2.7 nanoseconds). The historical data set can be maintained using a first-in, first-out strategy, keeping a fixed size, such as 1000 samples. After adding new data, the deep neural network model is retrained. The retraining can use incremental learning, using the current model parameters as the initial value, and using the new data set for several rounds of training, such as 5 rounds of training, each round traversing the entire data set.

[0121] The parameters of the deep neural network model can be dynamically adjusted according to the prediction error, and the reliability index can be calculated, and when the reliability index meets the condition, the delay prediction value is used for timing optimization, thereby improving the system performance and reliability.

[0122] Figure 2 The training loss convergence curve of the deep neural network model of the embodiment of the present application is compared with the schematic diagram:

[0123] The figure shows the comparison curve of the loss function change in the training iteration process of three different technical solutions, including the technical solution (comprehensive loss function), the traditional method (MSE loss) and the comparison method (MAE loss). From the curve trend, the initial loss values of the three schemes are close to 0.9, and as the number of training iterations increases, the loss value shows a downward trend to varying degrees. Among them, the convergence speed of the technical solution is the fastest, and the loss value has decreased to about 0.5 when the iteration is 50 times, and further decreased to about 0.35 when the iteration is 100 times, and when the iteration number reaches 300 times, the loss value decreases to about 0.1, and finally stabilizes at a level close to 0.05 when the iteration is 500 times; in contrast, the convergence speed of the traditional method (MSE loss) is slower, and the loss value is still around 0.7 when the iteration is 50 times, and decreases to about 0.28 when the iteration is 500 times; the performance of the comparison method (MAE loss) is between the two, and the loss value decreases to about 0.2 when the iteration is 500 times. This result fully shows that the technical solution not only has a faster convergence speed, but also can achieve a lower final loss value, and is significantly superior to the traditional method and the comparison method in training efficiency and model performance, which reflects the significant advantage of the technical solution in deep learning optimization.

[0124] The technical solution significantly improves the optimization efficiency by introducing a comprehensive loss function to build the model. The existing technical solution mostly uses the MSE loss function or the MAE loss function for model training. This single loss function design cannot fully consider the multi-dimensional optimization target, resulting in slow convergence speed and high final loss value in the training process, which makes it difficult to meet the demand of high-precision model optimization. To solve this problem, the technical solution innovatively designs a comprehensive loss function that integrates multi-dimensional features, and reasonably allocates the weights of each dimension feature to effectively balance the optimization target. At the same time, an adaptive learning strategy is adopted in the training process to dynamically adjust the parameters according to the optimization state at different stages, further improving the convergence efficiency of the model. This optimization scheme based on comprehensive loss function and adaptive learning not only significantly speeds up the convergence of the model, but also can achieve a lower final loss value, and realizes a qualitative improvement in both training efficiency and model performance. Experimental results show that compared with the traditional single loss function scheme, the technical solution has significant advantages in convergence speed and final optimization effect, providing a new solution for efficient optimization of deep learning models.

[0125] In an optional implementation, a feature vector matrix is constructed based on the feature parameters; a decision tree model is trained based on the feature vector matrix to obtain an optimization strategy, and parameters of the decision tree model are iteratively updated by a loss function gradient and a sample weight until an optimization target improvement meets a preset condition threshold, including:

[0126] Construct a feature vector matrix based on the feature parameters, the feature vector matrix including a timing feature vector, a power consumption feature vector, and an area feature vector;

[0127] Calculate the sensitivity of the timing feature vector, the power consumption feature vector, and the area feature vector to voltage, construct a sensitivity feature vector including the sensitivity of timing to voltage, the sensitivity of power consumption to voltage, and the sensitivity of area to voltage;

[0128] Combine the timing feature vector, the power consumption feature vector, the area feature vector, and the sensitivity feature vector to form an input feature matrix;

[0129] Construct a decision tree model based on the input feature matrix, output a voltage adjustment amount, a size adjustment amount, and a topology adjustment scheme through the decision tree model, wherein the voltage adjustment amount is obtained through a sigmoid function mapping, the size adjustment amount is obtained through a tanh function mapping, and the topology adjustment scheme is obtained through a softmax function mapping;

[0130] Construct an optimization loss function, calculate a loss function gradient based on the optimization loss function, calculate an optimization target improvement amount, and determine a sample weight according to the optimization target improvement amount, wherein the sample weight increases with the increase of the optimization target improvement amount;

[0131] Update the parameters of the decision tree model according to the sample weight and the loss function gradient, and perform optimization adjustment on the timing path based on the updated decision tree model, until the weighted ratio of the optimization target improvement amount to optimization overhead meets a preset condition threshold.

[0132] A feature vector matrix is constructed based on feature parameters of a circuit. In one embodiment, the feature parameters of three dimensions of timing, power consumption, and area of the circuit are collected. The timing feature vector includes parameters such as path delay, setup time margin, and hold time margin; the power consumption feature vector includes parameters such as dynamic power consumption, static power consumption, and short-circuit power consumption; and the area feature vector includes parameters such as cell area, wiring area, and total chip area. For example, for a design including 1000 timing paths, each path can extract timing parameters such as delay value (e.g., 0.9 ns) and setup time margin (e.g., 0.2 ns), and record power consumption data (e.g., dynamic power consumption 5 mW) and area data (e.g., cell area 0.05 mm²).

[0133] The sensitivity of the feature vector to voltage is calculated, and a sensitivity feature vector is constructed. Specifically, by measuring the circuit parameters under different voltage conditions (such as 0.8V, 0.9V, 1.0V), the parameter variation rate is calculated. For example, a certain timing path has a delay of 0.9ns at 0.9V and a delay of 0.8ns at 1.0V, so the sensitivity of the timing to voltage is (0.9-0.8) / 0.1=1ns / V. Similarly, the sensitivity of power consumption to voltage (such as 20mW / V) and the sensitivity of area to voltage (usually close to 0, because the area is almost not affected by voltage) are calculated. These sensitivity data form the sensitivity feature vector.

[0134] The timing feature vector, power consumption feature vector, area feature vector, and sensitivity feature vector are combined to form an input feature matrix. In actual implementation, for each timing path, a multi-dimensional feature vector can be constructed, containing all the above features. For example, the feature vector of path 1 is [0.9ns, 0.2ns, 5mW, 2mW, 0.05mm², 1ns / V, 20mW / V, 0mm² / V]. The feature vectors of all paths are combined into a feature matrix, which is used as the input of the decision tree model.

[0135] Based on the input feature matrix, a decision tree model is constructed. The model adopts a gradient boosting decision tree (GBDT) structure, which contains multiple decision tree nodes, and each node makes a binary decision based on a specific feature value. The model outputs three types of optimization suggestions: voltage adjustment, size adjustment, and topology adjustment scheme. The voltage adjustment is mapped to the range [-0.1V, 0.1V] by a sigmoid function, for example, the model suggests adjusting the voltage by 0.05V; the size adjustment is mapped to the range [-50%, 50%] by a tanh function, for example, the model suggests increasing the size of a certain cell by 20%; the topology adjustment scheme selects the optimal scheme from a few predefined schemes, such as "inserting a buffer", "changing a cell type", "adjusting the clock tree", etc.

[0136] An optimization loss function is constructed to evaluate the performance of the model. The loss function considers three aspects: timing improvement, power consumption increase, and area increase, which can be represented as the weighted sum of the timing improvement minus the power consumption increase and the area increase. For example, if a certain optimization scheme reduces the critical path delay by 0.1ns, but increases the power consumption by 1mW and the area by 0.01mm², the loss value can be calculated as 0.1-0.5×1-0.3×0.01=0.097 (assuming the power consumption weight is 0.5 and the area weight is 0.3). Based on this loss function, the gradient is calculated to guide the model parameter update.

[0137] An optimization target improvement amount is calculated to determine the sample weight. The optimization target improvement amount is defined as the improvement degree of the timing, power consumption, and area comprehensive indicators before and after optimization. For example, if the critical path delay is reduced from 1 ns to 0.9 ns, the improvement rate is 10%, and a higher weight is assigned; if it is only reduced from 1 ns to 0.99 ns, the improvement rate is 1%, and a lower weight is assigned. In a specific implementation, the sample weight can be set to be proportional to the improvement amount, such as weight = 1 + 10 x improvement rate, then 10% improvement corresponds to a weight of 1.1, and 1% improvement corresponds to a weight of 1.01.

[0138] The decision tree model parameters are updated according to the sample weight and the loss function gradient. In the training process, the loss function gradient is calculated for each sample, and after being multiplied by the corresponding sample weight, it is used to update the decision tree parameters. For example, for a sample with a sample weight of 1.1, its gradient contribution will be about 10% higher than that of a sample with a weight of 1.01. Through multiple rounds of iterative training, the model gradually learns more effective optimization strategies.

[0139] The updated decision tree model is applied to optimize and adjust the timing path. The model provides specific voltage adjustment suggestions, size adjustment suggestions, and topology adjustment suggestions for each path that needs to be optimized. For example, for a timing violation path, the model suggests increasing the size of its driving unit by 15% and inserting a buffer at a specific location. After implementing these optimizations, the optimization effect is evaluated again, and the weighted ratio of the optimization target improvement amount and the optimization overhead (such as area increase and power consumption increase) is calculated. When the ratio reaches a preset threshold (such as greater than 2.0, indicating that the benefit is twice the cost), the optimization process is stopped; otherwise, the iterative optimization continues until the condition is met or the maximum number of iterations is reached.

[0140] The present application can automatically learn circuit optimization strategies and provide customized optimization schemes for different types of timing paths, effectively improving circuit performance.

[0141] In the prior art, traditional greedy algorithms mainly rely on single-dimensional local optimization strategies for circuit design, while static optimization methods use fixed optimization parameters. These methods are difficult to comprehensively consider multi-dimensional sensitivity indicators in circuit design, resulting in poor performance of optimization results in voltage, size and topology, etc. To solve this problem, the technical scheme innovatively proposes a multi-dimensional sensitivity collaborative optimization method, which realizes comprehensive optimization of voltage sensitivity, size sensitivity and topology sensitivity by constructing a comprehensive evaluation system including profile, power consumption, area and other dimensions. The scheme not only establishes a correlation model of multi-dimensional characteristics at the theoretical level, but also adopts a dynamic adaptive optimization strategy in practice, which can flexibly adjust the optimization weight according to the characteristics of different design stages. Through this multi-dimensional collaborative optimization method, the technical scheme significantly improves the robustness of circuit design and shows excellent adaptability in voltage fluctuation, size change and topology structure adjustment. Compared with the prior art, the scheme has achieved comprehensive improvement in various key performance indicators, especially in the improvement of voltage sensitivity and size sensitivity, which provides more reliable technical support for high-performance integrated circuit design.

[0142] In an optional implementation, generating a memory compiler IP layout routing scheme that meets timing convergence requirements and optimizes power consumption based on cell position optimization and hierarchical routing optimization according to the partition cost function includes:

[0143] Functionally partitioning the memory compiler IP based on the partition cost function; constructing a cell position optimization cost function based on the result of the functional partition, and determining the optimization direction of the cell through the gradient direction of the cell position optimization cost function;

[0144] Multiplying the optimization direction of the cell by an exponential decay function of power consumption change to obtain a power-aware cell movement amount, the power consumption change being determined by the power consumption difference before and after movement, and adjusting the cell position based on the power-aware cell movement amount;

[0145] Constructing an interlayer routing cost function for the adjusted cell position, and performing routing layer allocation based on the interlayer routing cost function; calculating the routing congestion degree after the routing layer allocation, the routing congestion degree being the ratio of routing demand to routing capacity, and performing power-aware adjustment on the line width of the network according to the routing congestion degree;

[0146] Constructing a layout quality evaluation function, the layout quality evaluation function being a weighted sum of the ratio of each evaluation indicator to the target value, the evaluation indicators including timing margin indicators, power consumption indicators and routing quality indicators, and calculating the gradient of the layout quality evaluation function;

[0147] The gradient of the layout quality evaluation function is multiplied by a constraint matrix to obtain an optimization direction, and an adaptive step is used for iterative optimization, and the adaptive step exponentially decays with the increase of the iteration number;

[0148] The cell position and the routing scheme are updated according to the optimization direction until the improvement amount of the layout quality evaluation function is less than a preset improvement threshold, and the worst negative margin is greater than zero and the total negative margin is greater than zero, and a memory compiler IP layout and routing scheme that meets the timing convergence requirement and optimizes power consumption is generated.

[0149] The memory compiler IP is functionally partitioned based on a partition cost function. The partition cost function considers the connection relationship between cells, functional correlation and timing criticality, and can be expressed as the sum of the product of connection weights and cell distance. In specific implementation, the cells in the memory compiler IP are divided into four main functional areas, namely control logic area, address decoding area, storage array area and input / output buffer area according to function. For example, for an 8KB SRAM memory, the control logic area accounts for 15% of the total area, the address decoding area accounts for 25%, the storage array area accounts for 50%, and the input / output buffer area accounts for 10%. By minimizing the partition cost function, cells with strong functional correlation are allocated to the same area to reduce cross-area connections.

[0150] A cell position optimization cost function is constructed based on the functional partition result. The cost function considers three factors, namely wire length, congestion degree and timing margin, and integrates them through weighting. The gradient of the cost function on each cell position is calculated to determine the optimization direction of each cell. For example, for cells on the timing critical path, the timing weight can be set to 0.6, the wire length weight can be set to 0.3, and the congestion degree weight can be set to 0.1; while for cells on the non-critical path, the timing weight can be reduced to 0.2, the wire length weight can be increased to 0.5, and the congestion degree weight can be set to 0.3.

[0151] The power consumption difference before and after cell movement is calculated to determine the power consumption change. The power consumption change is substituted into an exponential decay function to obtain a coefficient ranging from 0 to 1. The coefficient is multiplied by the aforementioned cell optimization direction to obtain the power consumption-aware cell movement amount. In specific implementation, when the power consumption change is positive (i.e. the power consumption increases after movement), the value of the exponential decay function is small, which inhibits the movement of the cell in that direction; when the power consumption change is negative, the value of the exponential decay function is close to 1, which allows the cell to move fully. For example, when the movement results in a 5% increase in power consumption, the inhibition coefficient is 0.3; while when the movement results in a 3% decrease in power consumption, the coefficient is 0.9.

[0152] For the adjusted cell positions, a layer assignment function is constructed to assign routing layers. The function considers the resistance, capacitance characteristics and the impact on power consumption of different metal layers. Lower metal layers (e.g. Metal 1-3) have higher resistance but smaller capacitance, while higher metal layers (e.g. Metal 4-6) have lower resistance but larger capacitance. For timing critical networks, higher metal layers with lower resistance are preferred; for non-critical but high switching frequency networks, lower metal layers with lower capacitance are preferred to reduce power consumption. For example, clock networks can prefer Metal 5-6, while data buses can use Metal 3-4.

[0153] After the layer assignment, the congestion of the routing is calculated, which is the ratio of the routing demand and the routing capacity. For regions with congestion over 80%, the power consumption aware adjustment of the network line width is performed. For power sensitive but non-critical networks, the line width can be reduced to the minimum design rule; for timing critical networks, sufficient line width is maintained to meet timing requirements. For example, for a region with 90% congestion, non-critical signal line width can be reduced from 0.1 μm to 0.08 μm, while critical clock line width is maintained at 0.15 μm.

[0154] A layout quality evaluation function is constructed as the objective function of the overall optimization. The function is the weighted sum of the ratio of each evaluation index and the target value, and the evaluation indices include timing margin index, power consumption index and routing quality index. The timing margin index can be set to a weight of 0.5, the power consumption index to a weight of 0.3, and the routing quality index to a weight of 0.2. The gradient of the evaluation function with respect to the cell positions and the routing parameters is calculated to obtain the optimization direction.

[0155] The gradient of the layout quality evaluation function is multiplied by a constraint matrix to obtain the final optimization direction. The constraint matrix contains information such as design rule constraints, boundary constraints, etc., to ensure that the optimization result meets the physical implementation requirements. Adaptive step size is used for iterative optimization, and the initial step size can be set to 10, which decays exponentially with the increase of the iteration number, for example, the step size of the nth iteration is 10 x 0.95n.

[0156] The cell positions and the routing scheme are updated according to the optimization direction until the termination condition is met: the improvement of the layout quality evaluation function is less than a preset improvement threshold (e.g. 0.1%), and the worst negative margin is greater than zero and the total negative margin is greater than zero. At this time, the generated memory compiler IP layout and routing scheme meets the timing convergence requirement and realizes power consumption optimization.

[0157] In practical application, the compiler IP of a 32KB SRAM memory is optimized, the power consumption of the initial design is 15mW, and the worst negative margin is-50ps. After the method is optimized, the power consumption is reduced to 12.8mW, about 15% is reduced, and at the same time, the worst negative margin is improved to +10ps, the total negative margin is +150ps, and the timing convergence requirement is met. The wiring congestion degree is reduced from the highest 92% to below 75%, and the layout area is increased by not more than 3%. The optimization process is performed for 27 iterations, and the total running time is about 45 minutes, which is 30% higher in efficiency compared with the traditional method.

[0158] Figure 3 The Monte Carlo simulation wiring quality contrast thermodynamic diagram of the embodiment of the application is as follows:

[0159] The diagram directly shows the comparison results of the technical scheme and the traditional method in the distribution of the wiring congestion degree in the form of a thermodynamic diagram. The left thermodynamic diagram shows the distribution of the wiring congestion degree of the technical scheme, which presents a uniform distribution pattern mainly in light green, the average congestion degree is only 45.3%, the maximum congestion degree is 64.7%, the minimum congestion degree is 32.5%, the color block distribution is relatively uniform, and it is indicated that the wiring resource utilization is more reasonable. The right thermodynamic diagram shows the distribution of the wiring congestion degree of the traditional method, which presents a obvious deep red aggregation area, the average congestion degree is as high as 75.6%, the maximum congestion degree reaches 94.2%, the minimum congestion degree is 62.7%, and the center area presents a obvious hot spot phenomenon, which indicates that there is serious competition for wiring resources. Through the direct comparison of the two schemes, it can be seen that the technical scheme not only significantly reduces the overall wiring congestion degree, but also has obvious advantages in the uniformity of the congestion degree distribution, effectively avoids the excessive competition for wiring resources in the local area, provides a larger design space for subsequent wiring optimization and timing convergence, and fully proves the effectiveness of the technical scheme in the wiring optimization.

[0160] The second aspect of the embodiment of the application,

[0161] The memory compiler IP timing convergence and power consumption collaborative optimization system is provided, and the system comprises:

[0162] The first unit is used for acquiring circuit netlist information of a memory compiler IP, extracting a timing path based on the circuit netlist information, performing wiring topology analysis on the timing path, and determining the length of a connection line and an interconnection delay between timing units in the timing path;

[0163] The second unit is used for dividing the timing path into a plurality of power consumption control domains by using a fine-grained power consumption control strategy based on the length of the connection line and the interconnection delay, setting different working voltages for each power consumption control domain, and making the working voltage of the power consumption control domain close to a timing end point higher than the working voltage of the power consumption control domain close to a timing start point.

[0164] a third unit configured to construct a deep neural network model based on the voltage and delay data of the power consumption control domain, obtain a delay prediction value based on the deep neural network model, dynamically adjust parameters of the deep neural network model according to a prediction error between the delay prediction value and an actual delay value, and calculate a reliability index, and use the delay prediction value for timing optimization when the reliability index meets a preset reliability threshold;

[0165] a fourth unit configured to obtain feature parameters of the timing path, construct a feature vector matrix based on the feature parameters, train a decision tree model based on the feature vector matrix to obtain an optimization strategy, and iteratively update parameters of the decision tree model through a loss function gradient and a sample weight until an optimization target improvement meets a preset condition threshold.

[0166] a fifth unit configured to calculate a path priority based on the timing path, functionally partition the memory compiler IP based on the path priority, and construct a partition cost function, perform unit position optimization and hierarchical routing optimization according to the partition cost function, and generate a memory compiler IP layout and routing scheme that meets timing convergence requirements and power consumption optimization.

[0167] A third aspect of the embodiments of the present application,

[0168] An electronic device is provided, comprising:

[0169] a processor;

[0170] a memory for storing processor-executable instructions;

[0171] The processor is configured to invoke the instructions stored in the memory to perform the method described above.

[0172] A fourth aspect of the embodiments of the present application,

[0173] A computer-readable storage medium is provided, which stores computer program instructions, and the computer program instructions are executed by a processor to implement the method described above.

[0174] The present application can be a method, device, system and / or computer program product. The computer program product can include a computer readable storage medium having computer readable program instructions stored therein, which are used to perform various aspects of the present application.

[0175] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions recorded in the above embodiments can be modified, or some or all of the technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A memory compiler IP timing closure and power consumption collaborative optimization method, characterized in that: include: Obtain circuit netlist information of the memory compiler IP, extract a timing path based on the circuit netlist information, perform wiring topology analysis on the timing path, and determine the connection length and interconnection delay between timing cells in the timing path; Based on the connection length and the interconnection delay, a fine-grained power consumption control strategy is adopted to divide the timing path into multiple power consumption control domains, and a different operating voltage is set for each of the power consumption control domains, so that the operating voltage of the power consumption control domain close to the timing end point is higher than the operating voltage of the power consumption control domain close to the timing start point; A deep neural network model is constructed based on the voltage and delay data of the power consumption control domain, and a delay prediction value is obtained based on the deep neural network model; parameters of the deep neural network model are dynamically adjusted according to a prediction error between the delay prediction value and the actual delay value, and a reliability index is calculated; when the reliability index meets a preset reliability threshold, the delay prediction value is used for timing optimization; Acquire characteristic parameters of the timing path, and construct a characteristic vector matrix based on the characteristic parameters; Training a decision tree model based on the eigenvector matrix to obtain an optimization strategy, and iteratively updating the parameters of the decision tree model through the loss function gradient and sample weights until the optimization target improvement meets a preset condition threshold; Calculating path priorities based on the timing paths, functionally partitioning the memory compiler IP based on the path priorities and constructing a partition cost function; Cell location optimization and hierarchical routing optimization are performed according to the partition cost function to generate a memory compiler IP placement and routing solution that meets timing closure requirements and optimizes power consumption.

2. The method according to claim 1, characterized in that Based on the connection length and the interconnection delay, a fine-grained power consumption control strategy is adopted to divide the timing path into multiple power consumption control domains, and a different operating voltage is set for each power consumption control domain, so that the operating voltage of the power consumption control domain close to the timing end point is higher than the operating voltage of the power consumption control domain close to the timing start point. Acquiring physical parameters of the line segment in the timing path, the physical parameters including the length of the line segment, the width of the line segment, the thickness of the interlayer dielectric of the line segment, and the metal specific resistance of the line segment; Calculating the resistance per unit length and the capacitance per unit length of the line segment using a distributed RC model based on the physical parameters of the line segment, and calculating the total resistance and total capacitance of the line segment according to the resistance per unit length and the capacitance per unit length; Calculating the interconnection delay of the connection segment based on the total resistance and total capacitance of the connection segment to obtain the interconnection delay distribution characteristics of the timing path; and dividing adjacent sequential cells with similar delay sensitivities into a plurality of power consumption control domains using a hierarchical clustering algorithm based on the delay sensitivity of the sequential cells in the timing path, wherein the delay sensitivity represents the degree of influence of the operating voltage of the sequential cell on the total delay of the timing path; For the multiple power consumption control domains obtained by division, under the condition of satisfying the timing constraints, the operating voltage of each power consumption control domain is determined by minimizing the dynamic power consumption of each power consumption control domain, wherein the operating voltage of the power consumption control domain close to the timing end point is higher than the operating voltage of the power consumption control domain close to the timing start point.

3. The method according to claim 2, characterized in that Calculating the resistance per unit length and the capacitance per unit length of the line segment using a distributed RC model based on the physical parameters of the line segment, and calculating the total resistance and the total capacitance of the line segment according to the resistance per unit length and the capacitance per unit length includes: The distributed RC model is used to calculate the resistance per unit length of the connecting segment. The calculation process of the resistance per unit length is as follows: dividing the metal specific resistance by the product of the width of the connecting segment and the thickness of the interlayer dielectric; Calculating the capacitance per unit length of the line segment based on the physical parameters of the line segment, wherein the calculation process of the capacitance per unit length includes: calculating the parallel plate capacitance by dividing the product of the vacuum relative dielectric constant system and the width of the line segment by the thickness of the interlayer dielectric; calculating the edge capacitance by multiplying the vacuum relative dielectric constant system by a logarithmic function of the ratio of the interlayer dielectric thickness to the width of the line segment; calculating the coupling capacitance by dividing the product of the vacuum relative dielectric constant system and the thickness of the interlayer dielectric by the metal resistivity; and adding the parallel plate capacitance, the edge capacitance, and the coupling capacitance to obtain the capacitance per unit length; Acquire a signal frequency parameter of the connecting segment, the signal frequency parameter including a signal frequency band and a characteristic frequency parameter, and multiply the signal frequency parameter by the resistance per unit length to obtain a frequency-corrected resistance per unit length; The connecting segment is divided into multiple equal-length sub-segments, and the product of the frequency-corrected unit length resistance of each sub-segment and the sub-segment length is accumulated to obtain the total resistance of the connecting segment, and the product of the unit length capacitance of each sub-segment and the sub-segment length is accumulated to obtain the total capacitance of the connecting segment.

4. The method according to claim 1, wherein Dynamically adjusting the parameters of the deep neural network model and calculating a reliability index based on a prediction error between the delay prediction value and the actual delay value, and using the delay prediction value for timing optimization when the reliability index meets a preset reliability threshold, includes: Constructing a comprehensive loss function, training the deep neural network model using a gradient descent method, calculating weight gradients according to the comprehensive loss function, and updating weight parameters of the neural network based on the weight gradients; Obtaining a new operating voltage combination, inputting the operating voltage combination into the deep neural network model, and obtaining a corresponding delay prediction value; Collecting an actual delay measurement value under the operating voltage combination, and calculating a prediction error between the delay prediction value and the actual delay measurement value; Dynamically adjusting model parameters according to the prediction error, calculating a weight update amount, wherein the weight update amount is proportional to the product of the prediction error and the weight gradient; and calculating a bias update amount, wherein the bias update amount is proportional to the sign value of the prediction error; Calculating a confidence level of a prediction result based on the prediction error, wherein the confidence level decreases as the prediction variance increases, and using the difference between the confidence level and the prediction error as a reliability indicator; When the reliability index is greater than the preset reliability threshold, the current delay prediction value is used to guide timing optimization; when the reliability index is less than the preset reliability threshold, the model online learning process is triggered, new training data is added to the historical data set, and the deep neural network model is retrained.

5. The method according to claim 1, wherein constructing a eigenvector matrix based on the eigenparameters; Training a decision tree model based on the eigenvector matrix to obtain an optimization strategy, and iteratively updating the parameters of the decision tree model through the loss function gradient and sample weight until the optimization target improvement meets the preset condition threshold includes: Constructing a eigenvector matrix based on the characteristic parameters, the eigenvector matrix including a timing eigenvector, a power consumption eigenvector, and an area eigenvector; Calculating the sensitivity of the timing feature vector, the power consumption feature vector, and the area feature vector to voltage, and constructing a sensitivity feature vector, where the sensitivity feature vector includes the sensitivity of timing to voltage, the sensitivity of power consumption to voltage, and the sensitivity of area to voltage; Combining the timing feature vector, the power consumption feature vector, the area feature vector, and the sensitivity feature vector to form an input feature matrix; Building a decision tree model based on the input feature matrix, and outputting a voltage adjustment amount, a size adjustment amount, and a topology adjustment solution through the decision tree model, wherein the voltage adjustment amount is obtained by mapping the sigmoid function, the size adjustment amount is obtained by mapping the tanh function, and the topology adjustment solution is obtained by mapping the softmax function; Constructing an optimization loss function and calculating a loss function gradient based on the optimization loss function; calculating an optimization target improvement and determining a sample weight based on the optimization target improvement, wherein the sample weight increases as the optimization target improvement increases; The parameters of the decision tree model are updated according to the sample weights and the loss function gradient, and the timing path is optimized and adjusted based on the updated decision tree model until the weighted ratio of the optimization target improvement to the optimization overhead meets a preset condition threshold.

6. The method according to claim 1, characterized in that Performing cell location optimization and hierarchical routing optimization based on the partition cost function to generate a memory compiler IP placement and routing solution that meets timing closure requirements and optimizes power consumption includes: Functionally partitioning the memory compiler IP based on the partition cost function; constructing a unit position optimization cost function based on the result of the functional partitioning, and determining the optimization direction of the unit according to the gradient direction of the unit position optimization cost function; Multiplying the optimization direction of the unit by an exponential decay function of a power consumption change to obtain a power consumption-aware unit movement amount, where the power consumption change amount is determined by a difference in power consumption before and after the movement, and adjusting the unit position based on the power consumption-aware unit movement amount; Constructing an inter-layer wiring cost function for the adjusted cell positions and performing wiring layer allocation based on the inter-layer wiring cost function; calculating wiring congestion after the wiring layer allocation, wherein the wiring congestion is a ratio of wiring demand to wiring capacity, and performing power consumption-aware adjustment on the line width of the network based on the wiring congestion; Constructing a layout quality evaluation function, wherein the layout quality evaluation function is a weighted sum of the ratios of each evaluation index to a target value, the evaluation index including a timing margin index, a power consumption index, and a wiring quality index, and calculating the gradient of the layout quality evaluation function; Multiplying the gradient of the layout quality assessment function by the constraint matrix to obtain an optimization direction, and performing iterative optimization using an adaptive step size, wherein the adaptive step size decays exponentially with an increase in the number of iterations; The unit position and routing scheme are updated according to the optimization direction until the improvement of the layout quality evaluation function is less than a preset improvement threshold and the worst negative margin is greater than zero and the total negative margin is greater than zero, thereby generating a memory compiler IP layout and routing scheme that meets timing convergence requirements and optimizes power consumption.

7. A memory compiler IP timing closure and power consumption collaborative optimization system, configured to implement the method according to any one of claims 1 to 6, characterized in that: include: The first unit is configured to obtain circuit netlist information of a memory compiler IP, extract a timing path based on the circuit netlist information, perform wiring topology analysis on the timing path, and determine the connection length and interconnection delay between timing cells in the timing path; a second unit, configured to divide the timing path into a plurality of power control domains based on the connection length and the interconnection delay by adopting a fine-grained power control strategy, and set a different operating voltage for each of the power control domains, so that the operating voltage of the power control domain close to the timing end point is higher than the operating voltage of the power control domain close to the timing start point; A third unit is configured to construct a deep neural network model based on the voltage and delay data of the power consumption control domain, obtain a delay prediction value based on the deep neural network model; dynamically adjust parameters of the deep neural network model according to a prediction error between the delay prediction value and the actual delay value and calculate a reliability index; and use the delay prediction value for timing optimization when the reliability index meets a preset reliability threshold; A fourth unit is configured to obtain characteristic parameters of the timing path and construct a characteristic vector matrix based on the characteristic parameters; Training a decision tree model based on the eigenvector matrix to obtain an optimization strategy, and iteratively updating the parameters of the decision tree model through the loss function gradient and sample weights until the optimization target improvement meets a preset condition threshold; A fifth unit is configured to calculate a path priority based on the timing path, perform functional partitioning on the memory compiler IP based on the path priority, and construct a partition cost function; Cell location optimization and hierarchical routing optimization are performed according to the partition cost function to generate a memory compiler IP placement and routing solution that meets timing closure requirements and optimizes power consumption.

8. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; The processor is configured to call the instructions stored in the memory to execute the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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