DBA additional bandwidth allocation method, device and storage medium for fttr or olt scenario

Abstract

A DBA additional bandwidth allocation method, device and storage medium for FTTR or OLT scene, the method is applied to PON MAC chip in OLT or FTTR ONU, wherein the PON MAC chip is connected with CPU in OLT or FTTR ONU, wherein the method comprises: obtaining a configuration table, wherein the configuration table is obtained based on a rate ratio allocation model and an extended priority weight allocation model, and the configuration table records up to 9 priority AllocIDs in descending order, wherein the weight value of each AllocID in the same priority is sorted in descending order, wherein each weight value is an N-bit integer value, wherein N is an integer greater than or equal to 2; according to the configuration table, the AllocIDs in each priority are allocated additional bandwidth in descending order of priority, so as to reduce hardware cost and improve bandwidth allocation efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to network communication technology, in particular to a DBA additional bandwidth allocation method, device and storage medium for FTTR or OLT scenarios. BACKGROUND

[0002] Passive optical network (PON) is a point-to-multipoint (P2MP) fiber access technology, including gigabit-capable passive optical network (GPON), 10-gigabit-capable symmetric passive optical network (XG(S)PON), etc. The entire PON system is composed of an optical line terminal (OLT), an optical network unit (ONU), and an optical distribution network (ODN). The PON system adopts a broadcast mode for downlink data transmission, and a time division multiplexing mode for uplink to realize conflict-free shared access of multiple ONUs. The ONU contains one or more service transmission containers (TCONTs, identified by Alloc-ID), and the OLT (or FTTR master ONU) allocates uplink time slot bandwidth for multiple AllocIDs of different ONUs through dynamic bandwidth allocation (DBA) technology. How to dynamically allocate appropriate uplink time slot bandwidth for multiple ONUs in the OLT (or FTTR master ONU) is one of the key technologies of the PON access system. In particular, in the core technology of the new generation of home networking (FTTR), low cost, high bandwidth, and low latency are the core demands, and the implementation scheme of the uplink time slot dynamic bandwidth allocation technology based on time division multiplexing is one of the key technical factors to meet the user's demand for low cost, high bandwidth, and low latency, especially the additional bandwidth allocation method for NA and BE type AllocID, which is the key to the success of the DBA scheme. Therefore, how to allocate additional bandwidth for NA and BE type AllocID is a problem to be solved. SUMMARY

[0003] The application provides a DBA additional bandwidth allocation method, device and storage medium for FTTR or OLT scenarios.

[0004] A DBA additional bandwidth allocation method for FTTR or OLT scenario, applied to a PON MAC chip in an OLT or FTTR ONU, wherein the PON MAC chip is connected with a CPU in the OLT or FTTR ONU, and wherein the method comprises:

[0005] obtaining a configuration table, wherein the configuration table is obtained based on a rate proportion allocation model and an extended priority weight allocation model, the configuration table records up to 9 priorities, and the 9 priorities from high to low are NA type, BE_C0, BE_C1, BE_C2, BE_C3, BE_C4, BE_C5, BE_C6 and BE_C7 respectively, wherein the weight values of each AllocID in the same priority are sorted in descending order, and each weight value is an N-bit integer value, wherein N is an integer greater than or equal to 2;

[0006] performing additional bandwidth allocation operation on the AllocIDs in each priority according to the order of the priorities in the configuration table from high to low.

[0007] A storage medium, wherein the storage medium stores a computer program, and wherein the computer program is configured to execute the above method when running.

[0008] A DBA additional bandwidth allocation device for FTTR or OLT scenario, applied to a PON MAC chip in an OLT or FTTR ONU, wherein the PON MAC chip is connected with a CPU in the OLT or FTTR ONU, and wherein the device comprises a storage unit and a processing unit, the storage unit stores a computer program, and the processing unit is configured to execute the computer program to perform the above method.

[0009] The embodiment of the present application converts the execution subject of the additional bandwidth allocation from the CPU to the PON MAC chip, significantly reduces the requirement for the CPU performance, can select a CPU with lower cost, and does not need to use the PON MAC chip with an integrated high-performance CPU core, thereby effectively reducing the hardware cost. Meanwhile, the parameters of the rate proportion allocation model and the extended priority weight allocation model are integrated into one configuration table, reducing the occupation of the storage resources and improving the efficiency of data access and processing. In addition, by normalizing the weight value into an integer value with a fixed bit width, the hardware operation is more efficient, the calculation time and resource consumption are reduced, the real-time performance and accuracy of the bandwidth allocation are improved, and the efficiency and effect of the DBA process are optimized as a whole. Finally, the weight values of the same priority in the configuration table are sorted in descending order, which can ensure that the high-priority service obtains the bandwidth resource preferentially, improves the bandwidth allocation efficiency, simplifies the complexity of the hardware implementation, and facilitates the centralized management and optimization of network resources.

[0010] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art from the description, or can be learned by practice of the present application. Other advantages of the present application can be realized and obtained by means of the instrumentalities and procedures described in the specification and claims. BRIEF DESCRIPTION OF DRAWINGS

[0011] The accompanying drawings are included to provide an understanding of the present application technical scheme, and constitute a part of the specification, and are used together with the embodiments of the present application to explain the present application technical scheme, and do not constitute a limitation on the present application technical scheme.

[0012] Figure 1 A flowchart of the DBA additional bandwidth allocation method for the FTTR or OLT scene provided by the embodiment of the present application is shown in the figure.

[0013] Figure 2 The structure schematic diagram of the OLT or FTTR ONU provided by the embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0014] The present application describes a plurality of embodiments, but the description is exemplary rather than limiting, and it is obvious to those skilled in the art that there can be more embodiments and implementation schemes within the scope of the embodiments described in the present application. Although many possible combinations of features are shown in the drawings and discussed in the specific embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment can be used with any other feature or element of any other embodiment, or can replace any other feature or element of any other embodiment.

[0015] This application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed herein can also be combined with any conventional feature or element to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented alone or in any suitable combination. Embodiments are not otherwise limited— except in accordance with the limits provided by the appended claims and their equivalents. Further, various modifications and changes can be made within the scope of the attached claims.

[0016] Furthermore, in describing representative embodiments, the specification can have presented the method and / or process as a particular sequence of steps. However, to the extent that the method or process depends on the performance of certain steps, the method or process is not limited to the performance of the steps in the specific order described. One of ordinary skill in the art would realize that other step orders are possible. Therefore, the specific order of steps recited in the specification should not be construed as limitations on the claims. Further, the claims should not be limited to the performance of steps in the order written, as one of ordinary skill in the art would readily understand that the order of steps can be varied and still remain within the spirit and scope of the embodiments of the application.

[0017] In the related art, the DBA module and its additional bandwidth allocation sub-module of the NA and BE type AllocID usually take a high-performance CPU as the main carrier for implementation. First, the additional bandwidth allocation module of the DBA is based on the rate proportion allocation model of the DBA algorithm in the G.984.3 or G.987.3 standard, and according to the size proportion of the bandwidth rate parameter and the bandwidth demand estimation of each AllocID, the AllocID with small bandwidth demand and large bandwidth rate proportion is prioritized for allocation, and then each NA type AllocID is processed in turn and the required additional bandwidth is allocated. Second, based on the rate proportion allocation model or the extended priority weight allocation model of the DBA algorithm in the G.984.3 or G.987.3 standard, according to the size proportion of the bandwidth rate parameter and the bandwidth demand estimation of each AllocID, the AllocID with small bandwidth demand and large bandwidth rate proportion is prioritized for allocation, or the AllocID with high priority and large weight is prioritized for allocation. Obviously, in the related art, an AllocID bandwidth parameter table based on the bandwidth demand estimation and the bandwidth rate proportion size sorting is needed to complete the additional bandwidth allocation of the NA and BE type AllocID based on the rate proportion allocation model; in addition, an AllocID bandwidth parameter table based on the bandwidth demand estimation and the priority weight proportion size sorting is needed to complete the additional bandwidth allocation of the BE type AllocID based on the extended priority weight allocation model.

[0018] From the above, in the related art, the DBA module is mainly implemented on the CPU, which has the following problems:

[0019] A high-performance CPU is needed to complete the following tasks: first, the floating-point division calculation of the bandwidth demand and the rate proportion, and the AllocID sorting processing based on the division result; second, the floating-point division calculation of the bandwidth demand and the priority weight proportion, and the AllocID sorting processing based on the division result; third, the corresponding additional bandwidth allocation processing of the NA or BE type AllocID. When the CPU completes these division calculations, sorting operations and additional bandwidth allocation processing, the required calculation time is longer, which increases the DBA period and ultimately leads to an increase in the PON service delay.

[0020] In addition, whether a high-performance CPU chip is selected independently or a PON MAC chip integrated with a high-performance CPU core is selected, the implementation scheme of the two chips has a high cost, and the selection range of the chip is also limited.

[0021] To solve the above technical defects, the embodiments of the present application provide the following solutions, including:

[0022] Figure 1 A flowchart of a DBA additional bandwidth allocation method for FTTR or OLT scenarios provided by the embodiments of the present application is shown in FIG. 1. As shown in FIG. 1, the method is applied to a PON MAC chip in an OLT or FTTR ONU, wherein the PON MAC chip is connected to a CPU in the OLT or FTTR ONU, and the method comprises the following steps. Figure 1

[0023] In step 101, a configuration table is obtained, wherein the configuration table is obtained based on a rate proportion allocation model and an extended priority weight allocation model, the configuration table records up to 9 priorities of AllocIDs, the order of the 9 priorities from high to low is NA type, BE_C0, BE_C1, BE_C2, BE_C3, BE_C4, BE_C5, BE_C6 and BE_C7, respectively, the weight values of each AllocID in the same priority are sorted in descending order, and each weight value is an N-bit wide integer value.

[0024] In the PON system, the AllocID is a number used to identify and distinguish different service transmission containers, so as to facilitate bandwidth allocation and management of different services.

[0025] The rate proportion allocation model and the extended priority weight allocation model are two different allocation models, and the configuration table is generated by fusing the two different allocation models, thereby providing a core basis for subsequent bandwidth allocation. The configuration table integrates the advantages of the two models, can reflect the influence of the rate on the bandwidth allocation, and can meet the needs of different priority services. At the same time, the weight value is limited to an N-bit wide integer value, which reduces the demand for storage resources and facilitates fast processing and operation on the chip.

[0026] ​Optionally, the number (NA_AllocID_num) and the sum of weights (NA_AllocID_weight_sum) of the NA type AllocIDs in the configuration table are also obtained, as well as the number (BE_C0_AllocID_num, BE_C1_AllocID_num, …, BE_C7_AllocID_num) and the sum of weights (BE_C0_AllocID_weight_sum, BE_C1_AllocID_weight_sum, …, BE_C7_AllocID_weight_sum) of the BE type AllocIDs at each level of BE_C0 to BE_C7.

[0027] The above-obtained information, in cooperation with the configuration table, can provide a basis for bandwidth allocation for the PON MAC chip, ensuring the efficiency and accuracy of bandwidth allocation.

[0028] Step 102: According to the order of priority from high to low in the configuration table, additional bandwidth allocation operations are performed on the AllocIDs within each priority level.

[0029] After meeting the basic bandwidth requirements of the AllocIDs, additional bandwidth is allocated according to the remaining bandwidth and service demand, etc., to improve the efficiency and quality of service transmission and better adapt to the burst demand of services.

[0030] Allocating additional bandwidth according to priority order can ensure that high-priority services have priority in obtaining additional bandwidth resources, thereby better meeting their high bandwidth requirements and ensuring the transmission quality and service level of important services. This allocation method improves the rationality and flexibility of bandwidth allocation, enabling more efficient use of limited bandwidth resources.

[0031] By comparing with the implementation manner of the related art, the above process has the following improvements:

[0032] Firstly, the change of the execution subject reduces the hardware configuration requirements.

[0033] In the related art, the DBA module and its additional bandwidth allocation submodule are usually centered on a high-performance CPU. Such a high-performance CPU not only has a higher cost, but also the PON MAC chip integrated with the high-performance CPU core has a relatively limited selection range, which to some extent restricts the flexibility and cost-effectiveness of the system.

[0034] The scheme innovatively changes the subject of performing the additional bandwidth allocation operation from the CPU to the PON MAC chip, so that the system does not need to rely on a high-performance CPU or a PON MAC chip integrated with a high-performance CPU core. The PON MAC chip has high parallel processing capability and architecture optimized for communication tasks, and exhibits excellent performance in bandwidth allocation and data transmission control.

[0035] This change breaks the dependence on a specific high-performance CPU, significantly broadens the chip selection range, and provides greater flexibility for system design. At the same time, due to the efficiency of the PON MAC chip in handling communication tasks, the demand for CPU computing resources is reduced, effectively reducing the hardware cost and overall power consumption of the system, improving the cost-effectiveness and energy efficiency ratio of the system, and being particularly suitable for large-scale deployment of PON systems.

[0036] Further, the merging of the model parameter table optimizes storage and processing efficiency.

[0037] In related technologies, in order to implement additional bandwidth allocation based on the rate proportion allocation model and the extended priority weight allocation model, two independent parameter tables are usually required. This separate storage method not only increases the occupation of storage resources, but also causes additional synchronization and coordination overhead during data processing, affecting the overall performance and efficiency of the system.

[0038] The scheme ingeniously integrates the parameter tables of the original two models, and by redesigning the data structure and storage logic, it realizes the recording of all necessary parameter information in one unified table. This table covers the key parameters of both models, providing one-stop data support for the bandwidth allocation algorithm.

[0039] The merging of the model parameter table significantly reduces the occupation of storage resources and reduces the complexity of storage management. During data processing, since all parameters are stored centrally, the overhead of data switching and integration between different tables is avoided, significantly improving data access speed and processing efficiency. This optimization is of great significance to improving the response speed and stability of the system under high load conditions, and also simplifies the maintenance and upgrade work of the system.

[0040] Furthermore, since the weight is a fixed bit-width integer value, the calculation operation is optimized.

[0041] In computer science, an integer is a data type that represents a number without a decimal part, i.e., an integer. For example, numbers like -5, 0, 3 are all integers. In this scheme, the weight value is stored in the form of an integer, and this integer occupies N bits of binary space in the computer.

[0042] Normalization is a mathematical transformation process that scales data to a specific range. In this application, the rate ratio parameter is normalized so that it can be converted into an integer value format suitable for processing in the PON MAC chip. For example, assuming that the original rate ratio parameter is a floating-point number, it is converted into an integer after normalization, and this integer can be represented by N-bit binary.

[0043] In the PON MAC chip, there are many advantages to using integer weights. Compared to floating-point operations, integer operations are more efficient, require less hardware resources, and are faster. For the DBA scenario that requires a large amount of real-time calculation, using integer weights can reduce the complexity of the chip, improve the performance of the system, reduce the latency, and also help reduce power consumption.

[0044] Finally, the weight values of the same priority in the configuration table are sorted in descending order, which has the following technical advantages:

[0045] Guarantee high-priority service requirements: High weight values are usually associated with high-priority services. Sorting the weight values in descending order ensures that high-priority services (such as critical service data, real-time communication, etc.) can obtain sufficient bandwidth resources during bandwidth allocation, thereby guaranteeing the transmission quality and service level of these services and avoiding service delays or interruptions due to insufficient bandwidth.

[0046] Improve bandwidth allocation efficiency: Sorting by weight in descending order helps optimize the execution efficiency of the bandwidth allocation algorithm. When allocating bandwidth, the PON MAC chip can prioritize high-weight AllocIDs and quickly allocate the required bandwidth for important services, and then process low-weight AllocIDs. This sequential processing reduces unnecessary calculations and judgments during allocation, improving overall allocation efficiency and enabling bandwidth allocation to respond more quickly to changes in service demand.

[0047] Simplify hardware implementation complexity: For the PON MAC chip, sorting by weight in descending order can simplify circuit design and logic control. Hardware logic can process AllocIDs in a fixed order (from high weight to low weight) without the need for complex dynamic scheduling and sorting mechanisms, reducing hardware design complexity, reducing chip area and power consumption, and improving hardware reliability and manufacturability.

[0048] Based on the above analysis, the method provided by the embodiment of the application can significantly reduce the requirement for CPU performance by converting the subject of additional bandwidth allocation from CPU to PON MAC chip, can select a CPU with lower cost, and does not need to use a PON MAC chip with an integrated high-performance CPU core, thereby effectively reducing the hardware cost. Meanwhile, the parameters of the rate proportion allocation model and the extended priority weight allocation model are integrated into one configuration table, reducing the occupation of storage resources and improving the efficiency of data access and processing. In addition, by normalizing the weight value to an integer value with a fixed bit width, the hardware operation is more efficient, the calculation time and resource consumption are reduced, the real-time performance and accuracy of bandwidth allocation are improved, and the efficiency and effect of the DBA process are optimized as a whole. Finally, the weight values of the same priority in the configuration table are sorted in descending order, which can ensure that high-priority services obtain bandwidth resources first, improve the efficiency of bandwidth allocation, and simplify the complexity of hardware implementation, facilitating centralized management and optimization of network resources.

[0049] The method provided by the embodiment of the application will be described below.

[0050] In an exemplary embodiment, the storage mode of the configuration table is optimized.

[0051] Specifically, the high-priority AllocIDs are stored in a continuous low address area, and the low-priority AllocIDs are stored in a continuous high address area in the configuration table, wherein the AllocIDs in the same priority are stored in descending order of weight, and all the AllocID address spaces are continuous without interval.

[0052] Specifically, the NA type AllocIDs under the rate proportion allocation model have the highest priority, so they are normalized and mapped to the highest priority area starting from the 0 address in the configuration table. All the BE type AllocIDs under the rate proportion allocation model are directly normalized and mapped to the next highest priority area after the NA type AllocIDs in the configuration table, that is, they all correspond to the BE_C0 priority. All the BE type AllocIDs under the extended priority weight allocation model are respectively mapped to the BE_C0 to BE_C7 priority areas corresponding to the maximum 8 continuous address intervals in the configuration table according to their different priorities.

[0053] Among them, the actual configuration priority of the BE type AllocID is not a fixed one-to-one mapping relationship between BE_C0 to BE_C7, and the reasons are as follows:

[0054] In the priority configuration table, if the number of NA type AllocIDs is 0, the BE type AllocIDs of BE_C0 level are mapped from address 0. If the number of BE type AllocIDs of BE_C0 level is 0, the number of BE type AllocIDs of BE_C1 to BE_C7 levels must all be 0. If the number of BE type AllocIDs of BE_C0 and BE_C1 levels is not 0, and the number of BE type AllocIDs of BE_C2 level is 0, the number of BE type AllocIDs of BE_C3 to BE_C7 levels must all be 0. Therefore, the real priority of the BE type AllocIDs is not fixedly mapped between the BE_C0 to BE_C7 levels here, but is mapped to the high-priority area in BE_C0 to BE_C7 as much as possible. That is, all type and level AllocIDs are stored continuously in the uninterrupted continuous address interval of the configuration table starting from address 0, without unused empty addresses in between.

[0055] This storage layout facilitates the PON MAC chip to quickly locate and process AllocIDs of different priorities. By storing high-priority AllocIDs in the low-address area, the chip can access and process these important AllocIDs more quickly, and can prioritize processing these AllocIDs when performing bandwidth allocation, without the need for complex sorting or lookup operations, simplifying the bandwidth allocation process and improving the efficiency of bandwidth allocation. At the same time, the continuous storage mode reduces address jumping and addressing time, further optimizing data access speed.

[0056] In the DBA algorithm of G.984.3 or G.987.3, the priority of the AllocID is usually determined according to the weight and bandwidth demand, and the principle is that the AllocID with high weight and small bandwidth demand is allocated first. The configuration table of the present scheme places high-priority AllocIDs in the low-address area, and arranges them in descending order of weight within the same priority, so that the AllocIDs in the low-address area usually have high priority and large weight. When processing in the order of the configuration table, it can be simplified as "AllocIDs with low address and small bandwidth demand are allocated first". This simplification is reasonable, which not only conforms to the priority setting, but also efficiently utilizes the remaining bandwidth and avoids waste. Therefore, the present scheme allocates AllocIDs with low address and small bandwidth demand in the configuration table first.

[0057] Specifically, an iteration threshold round_max is set. When the number of NA type AllocIDs in the configuration table is not 0, after 1 to round_max rounds of additional bandwidth allocation processing, the additional bandwidth allocation of all NA type AllocIDs can be completed.

[0058] Then, the PONMAC chip checks the number of BE type AllocIDs of the maximum 8 priorities BE_C0_num, BE_C1_num, …, BE_C7_num in the configuration table in order of priority from high to low (from BE_C0 to BE_C7). If the number of AllocIDs of a higher priority is 0, the number of AllocIDs of a lower priority is also 0. If the number of AllocIDs of the highest priority BE_C0 is not 0, the chip reads the weight and maximum bandwidth parameters of the corresponding AllocID from the configuration table, and completes the extra bandwidth allocation of the AllocID of the BE_C0 priority through 1 to round_max rounds of iteration in a manner similar to the NA type AllocID. In this way, the extra bandwidth allocation of the BE type AllocID of the BE_C1 to BE_C7 priorities is completed. If the number of AllocIDs of a certain priority is 0, the number of AllocIDs of the current and lower priorities is 0, indicating that the extra bandwidth allocation of the BE type AllocID of all enabled priorities has been completed, and the extra bandwidth allocation process of the BE type AllocID can be stopped immediately.

[0059] In one exemplary embodiment, the specific operation process of the extra bandwidth allocation of the AllocID in any priority is further refined, and an iteration process is introduced. The specific content is as follows:

[0060] When the extra bandwidth allocation of the AllocID in the current priority is performed, the following operations are performed on each AllocID in the current priority that has not been successfully allocated bandwidth in any iteration process, including:

[0061] For the current AllocID, the ratio between the weight value of the current AllocID and the weight sum of the AllocIDs in the current priority that have not been successfully allocated bandwidth in the last iteration is calculated, and the ideal allocable bandwidth of the current AllocID is determined according to the calculated ratio and the current remaining total available bandwidth; if the ideal allocable bandwidth of the current AllocID is greater than or equal to the bandwidth requirement of the current AllocID, the FEC overhead bandwidth of the current AllocID is determined according to the bandwidth requirement of the current AllocID, and if the sum of the bandwidth requirement and the FEC overhead bandwidth of the current AllocID is less than or equal to the current remaining total available bandwidth, the extra bandwidth allocation of the current AllocID is performed according to the bandwidth requirement of the current AllocID, wherein the bandwidth requirement of the current AllocID is not greater than the maximum bandwidth of the current AllocID;

[0062] Wherein, after each iteration is completed, the current remaining total available bandwidth and the weight sum of the AllocID which is unsuccessfully allocated bandwidth in the current priority are updated, and so on until all AllocIDs in the current priority are allocated bandwidth or the iteration number is greater than the iteration threshold.

[0063] Taking the AllocID of the current priority as the NA type as an example:

[0064] In each round of iteration allocation, the theoretical allocatable bandwidth BW_I_i of the current AllocID is calculated according to the weight proportion of the current AllocID, and the calculation expression is BW_I_i=Weight_i of the current AllocID i / NA_AllocID_weight_sum of the current / total remaining available bandwidth size BW_A, wherein i is a positive integer.

[0065] If the calculated value BW_I_i is greater than the current bandwidth demand BW_E_i of the current AllocID i, the bandwidth is pre-allocated according to the current bandwidth demand BW_E_i of the AllocID i, and the possible FEC overhead bandwidth BE_FEC_i is calculated.

[0066] If the total remaining available bandwidth size BW_A is greater than or equal to the sum of BE_E_i+BE_FEC_i, it is determined that the pre-allocated additional bandwidth BW_E_i of the current AllocID is successfully allocated.

[0067] Wherein, the sum of the successfully allocated additional bandwidth BW_E_i and the other types of bandwidths already allocated to the AllocID i cannot exceed the maximum bandwidth of the AllocID i. The minimum value of the maximum bandwidth and the bandwidth demand of the AllocID i can be taken as the current bandwidth demand of the AllocID, so as to ensure that the additional bandwidth allocation result will not exceed the maximum bandwidth limit.

[0068] If the theoretical allocatable bandwidth BW_I_i of the AllocID i calculated in the current round is less than the current bandwidth demand BW_E_i of the AllocID, the additional bandwidth will not be allocated to the AllocID in the current round, but will be tried to allocate in the next round.

[0069] In the new round of extra bandwidth allocation, the AllocIDs which have been successfully allocated in the last round do not need to participate in the allocation again. First, the sum of the weights of all the unallocated AllocIDs in the current priority needs to be updated: NA_AllocID_weight_sum = NA_AllocID_weight_sum - Weight_i of the successfully allocated NA type AllocID i. At the same time, the total available bandwidth size BW_A in the current priority also needs to be updated: BW_A = BW_A - BW_E_i of the successfully allocated NA type AllocID i - FEC overhead bandwidth of the successfully allocated NA type AllocID i. Then, the scanning of the unallocated AllocIDs in the current priority is restarted from the beginning, and the theoretically allocatable bandwidth BW_I_j and the current bandwidth demand BW_E_j of the current AllocID j are recalculated according to the above-mentioned method, and the extra bandwidth allocation is attempted again according to the above-mentioned method, where j is a positive integer.

[0070] By introducing the iteration process, the bandwidth allocation can be more accurate. Each iteration recalculates the ideal allocatable bandwidth according to the current remaining bandwidth and the sum of the weights of the unallocated AllocIDs, ensuring the dynamic and adaptive nature of the bandwidth allocation. At the same time, the FEC overhead bandwidth is considered to ensure the reliability of data transmission. This iterative allocation method avoids the problems of bandwidth waste or uneven allocation that may be caused by one-time allocation, and improves the bandwidth utilization.

[0071] In an exemplary embodiment, the last iteration process for extra bandwidth allocation is specially handled. The specific description is as follows:

[0072] When allocating bandwidth to the AllocIDs in the current priority, in the last iteration process, each unallocated AllocID in the current priority performs the following operations, including:

[0073] For the current AllocID, the ratio between the weight value of the current AllocID and the weight sum of the AllocIDs in the current priority which have not been successfully allocated bandwidth in the last iteration is calculated to determine the ideal allocable bandwidth of the current AllocID in the current total remaining available bandwidth; the expected maximum allocable bandwidth of the current AllocID and the FEC overhead bandwidth of the current AllocID are estimated according to the ideal allocable bandwidth of the current AllocID, and the sum of the two should be equal to or less than the ideal allocable bandwidth of the current AllocID; if the sum of the expected maximum allocable bandwidth of the current AllocID and the FEC overhead bandwidth of the current AllocID is less than or equal to the current total remaining available bandwidth, the current AllocID is allocated additional bandwidth according to the expected maximum allocable bandwidth of the current AllocID.

[0074] Taking the AllocID of the current priority as an example, the process of the additional bandwidth allocation of the AllocID of the NA type is described as follows:

[0075] If the theoretical calculation bandwidth BE_I_j of an AllocID j is always less than its current bandwidth demand BW_E_j, the AllocID j cannot be successfully allocated in each round. In the final round_max round (for example, the 8th round), the following operations are performed on the AllocID j, including:

[0076] If the theoretical calculation bandwidth BE_I_j of the AllocID j is still less than its current bandwidth demand BW_E_j, the AllocID j cannot be successfully allocated, and the theoretical allocable bandwidth value BW_I_j of the AllocID j calculated according to the weight proportion is directly taken as the theoretical allocable additional bandwidth, and the expected maximum allocable bandwidth BW_M_j of the AllocID j and the possible FEC overhead bandwidth BW_FEC_j of the AllocID j are estimated, and the sum of the two should be equal to or less than the ideal allocable bandwidth BW_I_j of the current AllocID j. If FEC is not enabled, BW_FEC_j=0, and BW_M_j=BW_I_j.

[0077] If the updated current total remaining available bandwidth size BW_A is greater than or equal to the sum of BW_M_j + BW_FEC_j, it is determined that the expected maximum allocable bandwidth BW_M_j of the current AllocID j is successfully allocated; otherwise, it is indicated that the AllocID cannot be allocated additional bandwidth in the current additional allocation process

[0078] After the additional bandwidth allocation process of the round_max rounds is completed, the additional bandwidth allocation of all AllocIDs of the NA type is completed.

[0079] At the end of bandwidth allocation, there may be some AllocIDs that have not been allocated bandwidth due to various reasons. At this time, continuing to allocate bandwidth based on the conventional bandwidth demand-based allocation method may not be able to effectively utilize the remaining bandwidth. Therefore, in the last iteration, the allocation is directly based on the weight ratio and the remaining bandwidth, ensuring that all the remaining bandwidth can be fully utilized, further improving the bandwidth utilization, enhancing the flexibility and adaptability of the system. This provides a last chance for those AllocIDs that have not been allocated enough bandwidth in the previous iterations, while also ensuring the fairness of bandwidth allocation.

[0080] In an exemplary embodiment, an optimization scheme for additional bandwidth allocation is proposed, which is as follows:

[0081] After completing the bandwidth allocation of all priority levels of AllocIDs, if the total remaining available bandwidth is not zero, each priority level in the configuration table is considered the same, and the weight is considered 1. The additional bandwidth allocation is supplemented for the AllocIDs in each priority level, and the total bandwidth of the AllocIDs after the supplemented additional bandwidth allocation is not greater than the respective maximum bandwidth.

[0082] Specifically, in the process of the supplemented additional bandwidth allocation, the current bandwidth demand size of the AllocIDs is not referred to, but the maximum bandwidth parameter of the current AllocIDs is used as a substitute restriction condition, and the additional bandwidth allocation processing of the NA and BE type AllocIDs is performed again for a maximum of 2 rounds.

[0083] Through this supplemented allocation mechanism, the remaining bandwidth resources in the system can be fully utilized. By resetting the priority and weight to be the same, it is ensured that all AllocIDs can compete for the remaining bandwidth fairly in the supplemented allocation process, avoiding the waste of bandwidth and further improving the bandwidth utilization. This mechanism is particularly suitable for scenarios with large fluctuations in network traffic, and can flexibly utilize the remaining resources while ensuring the demand of high-priority services, thereby improving the overall network efficiency. In addition, in the process of the supplemented additional bandwidth allocation, it is ensured that the total bandwidth of each AllocID does not exceed its maximum bandwidth limit, not only ensuring the rationality of bandwidth allocation and avoiding resource waste, but also preventing some AllocIDs from occupying too much bandwidth and affecting the normal use of other AllocIDs, thereby maintaining the stability and fairness of the entire system.

[0084] In an exemplary embodiment, the processing mechanism of the PON MAC chip in the iteration process is described as follows:

[0085] The iteration process can be an iteration process for additional bandwidth allocation, or an iteration process for supplemented additional bandwidth allocation.

[0086] In the actual application of DBA additional bandwidth allocation operation, there are two parallel processing procedures running simultaneously, which respectively occupy a set of independent chip logic resources, but share the configuration table. Among them, the reason for using the term "processing procedure" to describe this parallel processing is that the PON MAC chip is usually implemented by FPGA or ASIC, not "process" in CPU processing.

[0087] It should be noted that this parallel processing is not achieved by dividing the task into multiple sub-tasks for parallel processing. For each DBA additional bandwidth allocation processing procedure in the two parallel processing procedures, based on the characteristics of the PON MAC chip (such as FPGA), a pipelined parallel processing task is adopted. For example, in each bandwidth allocation iteration, the information of one AllocID is read in each clock cycle and is given to the parallel pipeline of DBA additional bandwidth allocation logic for calculation and processing. Each logical processing unit on the parallel pipeline processes the information of AllocIDi in the current clock cycle (for example: compares with the current remaining total available bandwidth to determine whether the to-be-allocated bandwidth of AllocIDi can be allocated successfully, and if the allocation is successful, the remaining total available bandwidth is updated at the same time), and processes the information of AllocIDj in the next clock cycle to perform similar judgment and update operation. Among them, in each iteration allocation, both of the two parallel processing procedures must be completed to complete one complete iteration.

[0088] If the additional bandwidth allocation task is divided into multiple sub-tasks and processed by multiple processing units in parallel, it may cause improper use of the current remaining total available bandwidth. For example, if the remaining total available bandwidth is only enough to allocate to one AllocID, multiple tasks at the same time may cause false bandwidth allocation success. However, the embodiment of the present application adopts the allocation mode from low address to high address for each AllocID in the above-mentioned parallel pipeline, and one AllocID is allocated and the remaining total available bandwidth is updated in time in each clock cycle, which can effectively avoid this problem.

[0089] Specifically, the two parallel allocation processes are as follows: in each iteration of the additional bandwidth allocation, each AllocID information read from the configuration table in each clock cycle is shared by the two processes. One of the processes allocates bandwidth preferentially to control information such as physical layer OAM (Operations Administration Maintenance) and then allocates bandwidth to service data, which can be referred to as F1 allocation result. The other process does not allocate bandwidth to control information such as physical layer OAM, but mainly allocates bandwidth to service data, which can be referred to as F2 allocation result. Finally, the authorized data of the additional bandwidth allocation in a DBA period mainly consists of the repeatedly used F2 allocation result and the only used F1 allocation result, wherein a DBA period includes one or more 125us frame periods. In this way, the proportion of overhead bandwidth such as physical layer OAM is generally small.

[0090] The resources available to the DBA of the PON MAC chip are also limited, and the DBA is a sub-module that occupies the most resources in the entire PON MAC chip. Therefore, resource optimization is performed for the DBA in order to use a resource-limited and low-cost FPGA. Since the use of multiple task parallelism will occupy too many resources, the number of control parallel processes is two. In addition, since the DBA of multiple ports requires a long period of serial calculation, the allocation result F2 obtained by one calculation is repeatedly used multiple times, thereby effectively reducing the use of computing resources. Nevertheless, the DBA calculation time in the FPGA is still shorter than that in the CPU, and the time jitter is much smaller. Therefore, compared with the CPU, the FPGA chip has obvious advantages in latency and jitter in implementing the DBA.

[0091] The above parallel processing mechanism can fully utilize the hardware resources of the PON MAC chip, improve the utilization rate of resources, avoid resource idling and waste, and improve the overall performance of the chip.

[0092] Embodiments of the present application also provide a DBA additional bandwidth allocation device for an FTTR or OLT scenario, which is applied to a PON MAC chip in an OLT or FTTR ONU, wherein the PON MAC chip is connected to a CPU in the OLT or FTTR ONU, and wherein the device comprises a storage unit and a processing unit, the storage unit stores a computer program, and the processing unit is configured to run the computer program to execute the method described above.

[0093] In the FTTR or OLT scenario, if a master ONU and at least one slave ONU are deployed, the device is deployed in the master ONU.

[0094] In practical applications, the PON MAC chip can be implemented by FPGA or ASIC.

[0095] Optionally, the apparatus is further configured to obtain the configuration table from the CPU.

[0096] The CPU normalizes the rate proportion coefficient of each AllocID determined by the rate proportion allocation model into a weight value of N-bit width, and sets the weight value of each AllocID determined by the extended priority weight allocation model as the weight value of N-bit width; and generates the configuration table according to the obtained weight values.

[0097] In addition, the apparatus is further configured to obtain the configuration table from the CPU, and obtain the number of AllocIDs and the sum of weight values of each priority in the configuration table from the CPU.

[0098] The apparatus provided by the embodiments of the present application significantly reduces the requirement for CPU performance by converting the execution subject of additional bandwidth allocation from the CPU to the PON MAC chip, can select a CPU with lower cost, and does not need to use a PON MAC chip with an integrated high-performance CPU core, thereby effectively reducing the hardware cost. At the same time, the parameters of the rate proportion allocation model and the extended priority weight allocation model are integrated into one configuration table, reducing the occupation of storage resources and improving the efficiency of data access and processing. In addition, by normalizing the weight values into integer values of fixed bit width, the hardware operation is more efficient, the calculation time and resource consumption are reduced, the real-time performance and accuracy of bandwidth allocation are improved, and the efficiency and effect of the DBA process are optimized as a whole. Finally, the weight values of the same priority in the configuration table are sorted in descending order, which can ensure that high-priority services obtain bandwidth resources in priority, improve the bandwidth allocation efficiency, and at the same time simplify the complexity of hardware implementation, facilitating centralized management and optimization of network resources.

[0099] Figure 2 The embodiments of the present application provide a structure diagram of an OLT or FTTR ONU. As shown in the figure, Figure 2 The OLT or FTTR ONU includes a CPU and a PON MAC chip, wherein the PON MAC chip is deployed with the DBA additional bandwidth allocation apparatus described above, and the apparatus performs DBA additional bandwidth allocation operation by using the method described above.

[0100] In the FTTR or OLT scenario, if a master ONU and at least one slave ONU are deployed, the apparatus is deployed in the master ONU.

[0101] The CPU is configured to normalize the rate proportion coefficient of each AllocID determined by the rate proportion allocation model into an N-bit wide weight value, and set the weight value of each AllocID determined by the extended priority weight allocation model as an N-bit wide weight value; and generate the configuration table according to the obtained weight values.

[0102] Optionally, the CPU is further configured to send the number of AllocIDs in each priority and the sum of the weight values of the AllocIDs in the configuration table at the same time as the configuration table is sent.

[0103] The execution operation of the CPU is described below.

[0104] 1. Priority division mode:

[0105] NA type AllocID: having the highest priority, which is higher than the priority of all BE type AllocIDs. After normalization, the priority of the NA type AllocID still remains the highest.

[0106] BE type AllocID: supporting 8 different priorities, from BE_C0 to BE_C7, wherein BE_C0 corresponds to the highest priority and BE_C7 corresponds to the lowest priority. For the BE type AllocID enabled with the rate proportion allocation model, the priority after normalization can be set as the priority of the BE_C0 level.

[0107] In the above priority division mode, the CPU sorts and normalizes the rate proportion parameters of the NA and BE type AllocIDs according to the rate proportion allocation model and the extended priority weight allocation model, respectively, to determine the priority order, so as to ensure that the PON system reasonably allocates bandwidth according to the importance of the service and guarantees that the high-priority service obtains bandwidth in priority.

[0108] 2. Determination mode of the weight value:

[0109] When the DBA algorithm enables the rate proportion allocation model in the standards such as G.984.3 or G.987.3, the maximum value of the rate proportion parameters of all AllocIDs in each type is taken as the standard for normalization. Specifically, the weight calculation expression of the NA type AllocID is W_NA=(R F +R A ) / (R F +R A ) MAX * (2 N -1); and the weight calculation expression of the BE type AllocID is W_BE=(R M -(R F +RA )) / (R M -(R F +R A )) MAX * (2 N -1), where R F is a fixed bandwidth rate, R A To ensure the bandwidth rate, (R F +R A ) MAX AllocID for all NA types in R F +R A (RM−(RF+RA))MAX is the maximum value of RM - (RF + RA) in all BE type AllocIDs.

[0110] For BE type AllocID, when the DBA algorithm enables the extended priority weight distribution model, the weight value of BE type AllocID directly uses the original weight value without normalization.

[0111] In the above weight determination method, the CPU converts floating-point operations into integers suitable for PON MAC chip operations to improve hardware operation efficiency and reduce computing time and resource consumption.

[0112] 3. Generation of configuration table:

[0113] The CPU combines the parameters of the rate-proportional allocation model and the extended priority-weighted allocation model into a configuration table. This configuration table supports up to nine different priority levels, with NA-type AllocIDs having the highest priority, followed by BE-type AllocIDs at levels BE_C0 to BE_C7.

[0114] In the aforementioned configuration table generation method, the CPU merges the parameters of the two allocation models into a single configuration table. In this configuration table, high-priority AllocIDs are stored in low-address areas, while low-priority AllocIDs are stored in high-address areas. AllocIDs of the same priority are stored in descending order of weight, and all AllocID addresses are contiguous. This merged configuration table simplifies data management, optimizes storage layout, and facilitates fast hardware access and processing.

[0115] 4. Configuration table distribution process:

[0116] The CPU sends the generated configuration table to the PON MAC chip through the low-speed register configuration interface. At the same time, the CPU also sends the following information:

[0117] The number (NA_AllocID_num) and the sum of weights (NA_AllocID_weight_sum) of the NA type AllocIDs, and the number (BE_C0_AllocID_num, BE_C1_AllocID_num, …, BE_C7_AllocID_num) and the sum of weights (BE_C0_AllocID_weight_sum, BE_C1_AllocID_weight_sum, …, BE_C7_AllocID_weight_sum) of the BE type AllocIDs at each level of BE_C0 to BE_C7.

[0118] The configuration table and the information delivered thereby can provide a basis for bandwidth allocation for the PON MAC chip, and ensure the efficiency and accuracy of bandwidth allocation.

[0119] The OLT or FTTR ONU provided by the embodiments of the present application significantly reduces the requirement for CPU performance by converting the subject of execution of additional bandwidth allocation from CPU to PON MAC chip, can select a CPU with lower cost, and does not need to use a PON MAC chip with an integrated high-performance CPU core, thereby effectively reducing the hardware cost. At the same time, the parameters of the rate proportion allocation model and the extended priority weight allocation model are integrated into one configuration table, reducing the occupation of storage resources and improving the efficiency of data access and processing. In addition, by normalizing the weight value to an integer value with a fixed bit width, the hardware operation is more efficient, the calculation time and resource consumption are reduced, the real-time performance and accuracy of bandwidth allocation are improved, and the efficiency and effect of the DBA process are optimized as a whole. Finally, the weight values of the same priority in the configuration table are sorted in descending order, which can ensure that high-priority services obtain bandwidth resources in priority, improve the efficiency of bandwidth allocation, and at the same time simplify the complexity of hardware implementation, facilitating centralized management and optimization of network resources.

[0120] The embodiments of the present application also provide a storage medium, and the storage medium stores a computer program, wherein the computer program is configured to execute the method described above when running.

[0121] Those of ordinary skill in the art will realize and understand that all or some of the steps in the methods disclosed above and the functional modules / units in the systems and devices can be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be performed by several physical components in cooperation. Some or all of the components can be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on computer-readable media, which can include computer storage media (or non-transitory media) and communication media (or transitory media). As is well known to those of ordinary skill in the art, the term "computer storage media" includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and that can be accessed by a computer. Furthermore, it is common and well understood by those of ordinary skill in the art that communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and can include any information delivery media.

Claims

1. A DBA additional bandwidth allocation method for FTTR or OLT scenario, characterized in that, The application is applied to a PON MAC chip in an OLT or FTTR ONU, wherein the PON MAC chip is connected with a CPU in the OLT or FTTR ONU, and the method comprises: obtaining a configuration table, wherein the configuration table is obtained based on a rate proportion allocation model and an extended priority weight allocation model, the configuration table records up to 9 priorities, the order of the 9 priorities from high to low is NA type, BE_C0, BE_C1, BE_C2, BE_C3, BE_C4, BE_C5, BE_C6 and BE_C7, respectively, the weight values of each AllocID in the same priority are sorted in descending order, each weight value is an N-bit integer value, and N is an integer greater than or equal to 2; performing an additional bandwidth allocation operation on the AllocIDs in each priority in the order of the priorities from high to low in the configuration table; wherein the bandwidth allocation operation on the AllocIDs in each priority in the order of the priorities from high to low in the configuration table comprises: when performing the additional bandwidth allocation on the AllocIDs in the current priority, in each iteration, each AllocID in the current priority that has not been successfully allocated bandwidth performs the following operations, including: for the current AllocID, calculating the ratio between the weight value of the current AllocID and the weight sum of the AllocIDs in the current priority that have not been successfully allocated bandwidth in the last iteration, and then determining the ideal allocable bandwidth of the current AllocID according to the calculated ratio and the current remaining total available bandwidth; if the ideal allocable bandwidth of the current AllocID is greater than or equal to the bandwidth demand of the current AllocID, determining the FEC overhead bandwidth of the current AllocID according to the bandwidth demand of the current AllocID, and if the sum of the bandwidth demand of the current AllocID and the FEC overhead bandwidth is less than or equal to the current remaining total available bandwidth, performing the additional bandwidth allocation on the current AllocID according to the bandwidth demand of the current AllocID, wherein the bandwidth demand of the current AllocID is not greater than the maximum bandwidth of the current AllocID; wherein after each iteration is completed, the current remaining total available bandwidth and the weight sum of the AllocIDs in the current priority that have not been successfully allocated bandwidth are updated, and the process is repeated until all AllocIDs in the current priority have been allocated bandwidth or the number of iterations exceeds an iteration threshold.

2. The method of claim 1, wherein, The high-priority AllocIDs in the configuration table are stored in a continuous low-address region, and the low-priority AllocIDs are stored in a continuous high-address region, wherein the AllocIDs in the same priority are stored continuously in descending order of weight, and the address spaces of all AllocIDs are continuous without gaps.

3. The method of claim 1, wherein, The method further comprises: when performing the bandwidth allocation on the AllocIDs in the current priority, in the last iteration, each AllocID in the current priority that has not been successfully allocated bandwidth performs the following operations, including: For the current AllocID, a ratio between a weight value of the current AllocID and a weight sum of the current AllocID and the AllocIDs of which bandwidths are not successfully allocated in the current priority in the last iteration is calculated to determine an ideal allocable bandwidth of the current AllocID in the current total available bandwidth; an expected maximum allocable bandwidth of the current AllocID and an FEC overhead bandwidth of the current AllocID are estimated according to the ideal allocable bandwidth of the current AllocID, and a sum of the expected maximum allocable bandwidth and the FEC overhead bandwidth should be equal to or less than the ideal allocable bandwidth of the current AllocID; if the sum of the expected maximum allocable bandwidth and the FEC overhead bandwidth of the current AllocID is less than or equal to the current total available bandwidth, the current AllocID is allocated with additional bandwidth according to the expected maximum allocable bandwidth of the current AllocID.

4. The method of claim 1, wherein, The method further comprises: After the bandwidth allocation of the AllocIDs in all priorities is completed, if the total available bandwidth is not zero, each AllocID priority in the configuration table is regarded as the same, and the weight is regarded as 1, and the AllocIDs in each priority are allocated with additional bandwidth for supplement, wherein the total bandwidth of the AllocIDs after the additional bandwidth allocation for supplement is not greater than the respective maximum bandwidth.

5. The method of any one of claims 1 to 4, wherein: The PON MAC chip has two processing flows running in parallel and independently, wherein the two processing flows share the configuration table, and a complete iteration is completed only when the two processing flows are both ended in each iteration; wherein: One processing flow allocates bandwidth for control information including physical layer OAM first, and then allocates bandwidth for service data to obtain F1 allocation result; The other processing flow does not allocate bandwidth for control information including physical layer OAM, but allocates at least most of the bandwidth for service data to obtain F2 allocation result; The grant data of the additional bandwidth allocation in one DBA period includes the F2 allocation result repeatedly used multiple times and the F1 allocation result used only once.

6. A storage medium, characterized by The storage medium stores a computer program, wherein the computer program is configured to execute the method described in any one of claims 1 to 5 when running.

7. A DBA extra bandwidth allocation apparatus for FTTR or OLT scenario, applied to a PON MAC chip in an OLT or FTTR ONU, wherein the PON MAC chip is connected with a CPU in the OLT or FTTR ONU, wherein the apparatus comprises a storage unit and a processing unit, characterized in that, The storage unit stores a computer program, and the processing unit is configured to execute the computer program to execute the method described in any one of claims 1 to 5.

8. The apparatus of claim 7, wherein: The apparatus is further configured to obtain the configuration table from the CPU; The CPU normalizes the rate proportion coefficient of each AllocID determined by the rate proportion allocation model to a weight value of N-bit width, and sets the weight value of each AllocID determined by the extended priority weight allocation model to a weight value of N-bit width; and generates the configuration table according to the obtained weight values.

9. The apparatus of claim 8, wherein: The device is further configured to obtain the configuration table from the CPU and obtain the number of AllocIDs and the sum of weight values of each priority in the configuration table from the CPU at the same time.

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