Foundation optical telescope large target surface imaging circuit and imaging system

Abstract

The present application relates to the technical field of splicing detector imaging circuit, and specifically provides a ground-based optical telescope large target surface imaging circuit and imaging system, mainly used for solving the imaging design of a large target surface obtained by splicing multiple sCMOS imaging chips, wherein the imaging circuit selects FPGA as a core processor, and utilizes the FPGA to perform function module design, data flow design, high dynamic synthesis and synchronous operation design; the FPGA comprises a control center and an sCMOS driving unit; the control center is used for controlling the enablement and timing of the function modules of the FPGA according to host computer configuration and state monitoring information; and the sCMOS driving unit is used for generating and providing clock signals and control signals required by sCMOS chips to work, and receiving image signals output by the sCMOS chips. The present application further provides an imaging system, which realizes synchronous control of multiple imaging circuits through a synchronous control terminal to complete image acquisition of a spliced target surface. The imaging circuit and system of the present application meet the large field of view detection requirements of a ground-based large optical telescope.

Description

Technical Field

[0001] This invention belongs to the field of imaging circuit design technology for splicing detectors, and particularly relates to a large target surface imaging circuit and imaging system for a ground-based optical telescope. Background Technology

[0002] Ground-based large optical telescopes play an indispensable role in space situational awareness and space target detection. Their large-aperture design significantly improves optical resolution and sensitivity, while their wide field of view enables efficient monitoring and observation of a larger area of ​​the sky.

[0003] Internationally, numerous countries and research institutions have invested heavily in the construction and operation of advanced large-aperture, wide-field telescopes. The Vera C. Rubin Observatory, located atop Mount Pajang in Chile, formerly known as the Large Synoptic Survey Telescope (LSST), employs a three-reflector optical system and an 8.4-meter primary mirror, enabling imaging with an ultra-large field of view of approximately 9.6 square degrees. Its core objective is to leverage its high sensitivity and large field of view to conduct high-frequency, multi-wavelength observations of the entire southern sky. Within the telescope system, a 320-megapixel high-resolution CCD camera is a key imaging device. This camera relies on a mosaic detector to achieve ultra-large-area imaging. The camera's focal plane is composed of 21 tightly stitched "Raft" modules, each containing nine scientific CCDs, totaling 189 4k×4k resolution CCDs providing a detection scale of 3.2 billion pixels. Eight guiding sensors and four wavefront sensors are also deployed on the periphery. Such a massive CCD array requires complex driving, high-bandwidth data acquisition and transmission designs to ensure that observations can be completed in a short time and that massive amounts of high-quality data can be output quickly.

[0004] Significant progress has been made in the construction and research of large-aperture, wide-field-of-view telescopes in China. The 2.5-meter Wide Field Survey Telescope (WFST) of the University of Science and Technology of China-Purple Mountain Observatory, also named the "Mozi" Survey Telescope, employs internationally advanced master-focus optics design, providing a large field of view, high precision, and wide-band survey capability, boasting advanced performance. The large-scale master-focus camera is a key instrument for WFST's large-field-of-view, high-precision, and high-frequency time-domain observations. The WFST camera has a total of 765 million pixels, with a pixel fill rate of 0.89 within a 3-degree field of view. The focal plane layout is composed of three types of CCDs stitched together. The scientific imaging area uses nine back-illuminated full-frame scientific-grade 9k×9k resolution CCDs, stitched together in a 3×3 configuration with a 0.5mm seam, achieving a peak-to-valley flatness of 20μm. Four back-illuminated full-frame 4k×4k resolution CCDs are installed around the scientific imaging area to guide active optical adjustment. It also integrates four 1k×1k resolution back-illuminated frame-transfer CCD guide sensors.

[0005] In the field of detector chips, scientific-grade complementary metal-oxide-semiconductor (sCMOS) has begun to be applied in the field of space target detection. sCMOS is a high-performance image sensor that significantly reduces readout noise while maintaining high speed, and possesses a wider dynamic range and superior quantum efficiency. In recent years, domestic sCMOS technology has been continuously developing, with Changguang Chenxin's GSENSE series back-illuminated chips reaching international advanced levels. When an sCMOS chip simultaneously outputs high-gain and low-gain images, high-dynamic-range (HDR) synthesis technology can be used to fuse these images, achieving dynamic range expansion. This allows the same image to present details in extremely bright areas without losing weak signals in dark areas, a technology with significant advantages in the field of space target observation. Summary of the Invention

[0006] In view of this, the present invention aims to provide a large target surface imaging circuit and imaging system for a ground-based optical telescope, which effectively solves the problems that traditional imaging circuits cannot effectively drive large-scale mosaic detectors, achieve high dynamic range synthesis, synchronous operation, and record exposure time information. Furthermore, it is at the industry-leading level in tests of camera readout noise suppression, dark current suppression, and image dynamic range.

[0007] To achieve the above objectives, the technical solution created by this invention is implemented as follows: The present invention provides a large target surface imaging circuit for a ground-based optical telescope, comprising: an sCMOS imaging chip, which is used to acquire light signals and convert the light signals into image signals; In addition, the FPGA connected to the sCMOS imaging chip includes a control center and an sCMOS driving unit. The control center is used to control the enabling and timing of functional modules in the FPGA according to the host computer configuration and status monitoring information. The sCMOS driving unit is used to generate and provide the clock signals and control signals required for the operation of the sCMOS chip, as well as receive the image signals output by the sCMOS chip. The control center controls the different power supplies in the sCMOS imaging chip to be powered on in batches. After at least one batch of power supplies is powered on and stabilized, the sCMOS imaging chip is configured via SPI. After all different power supplies are powered on and stabilized, the sCMOS imaging chip is driven to perform image acquisition and transmission according to the input signal from the host computer.

[0008] Preferably, the sCMOS imaging chip is a stitchable back-illuminated sCMOS chip.

[0009] Preferably, during the process of driving the sCMOS imaging chip, the 19 power supplies in the sCMOS imaging chip are powered on in three batches.

[0010] Preferably, it also includes: a data management unit, which includes: four parallel DDR chips connected to the FPGA, and a FLASH chip, wherein the DDR chips are used to buffer image signals, so that the FPGA can store and read image signals; the FLASH chip is used to store the configuration parameters of the sCMOS imaging chip and the program code of the FPGA.

[0011] Preferably, it also includes a temperature monitoring module and a voltage monitoring module. When the 19 power supplies in the sCMOS imaging chip are powered on in batches, the temperature and voltage of the sCMOS imaging chip are monitored by the temperature monitoring module and the voltage monitoring module before and after each batch of power-on, and the data is fed back to the FPGA. When the temperature and / or voltage exceed the set range, the control center controls the different power supplies in the sCMOS imaging chip to be powered off in batches.

[0012] Preferably, the sCMOS driving unit includes: The clock module is used to provide clock signals for sCMOS imaging chips and FPGAs; The SPI control module allows the FPGA to configure the operating mode and parameters of the sCMOS imaging chip. The DECODER control module is used to control the readout order of image signals from each pixel of the sCMOS imaging chip. The TIMING control module is used to generate the timing sequence for the sCMOS imaging chip to acquire optical signals.

[0013] Preferably, the operating modes of the sCMOS imaging chip include: high-gain STD mode, low-gain STD mode, and HDR imaging mode. In HDR imaging mode, the sCMOS imaging chip simultaneously outputs low-gain image signals and high-gain image signals. The FPGA performs high dynamic range synthesis based on the low-gain image signals and high-gain image signals through parallel processing, generates a high dynamic range image, and sends the high dynamic range image to the host computer.

[0014] Preferably, the sCMOS imaging chip acquires the image signals corresponding to each pixel using an ADC at different amplification factors. The photon response curve of the low-gain image signal is as follows: ; in, This represents the pixel output value of a low-gain image signal. This represents the slope of the linear region of the low-gain channel response curve. This represents the black level offset of a low-gain image signal. This indicates the number of photons incident on a pixel of an sCMOS imaging chip; The photon response curve of the high-gain image signal is as follows: ; in, This represents the pixel output value of a high-gain image signal. This represents the slope of the linear region of the high-gain channel response curve. This indicates the black level offset of a high-gain image signal; The photon response curve of a high dynamic range image is as follows: ; in, This represents the pixel output value of a high dynamic range image. This indicates the gain ratio of a high dynamic range image. This represents the compensation value for high dynamic range images. The threshold representing the conversion between high-gain and low-gain image signals. This indicates the maximum value of the output data format.

[0015] Another aspect of this invention provides a ground-based optical telescope large target surface imaging system, comprising: multiple ground-based optical telescope large target surface imaging circuits, a synchronous control terminal, and a host computer; wherein, multiple sCMOS imaging chips are spliced ​​together to form an imaging target surface, and the synchronous control terminal is connected to the FPGA in each ground-based optical telescope large target surface imaging circuit and the synchronous control server of the host computer. The synchronization control terminal is used to receive control signals from the synchronization control server of the host computer, distribute and transmit the control signals to the FPGA in the large target imaging circuit of each ground-based optical telescope, and generate synchronization trigger pulses to transmit to the FPGA in the large target imaging circuit of each ground-based optical telescope, so that all FPGAs synchronously drive their corresponding sCMOS imaging chips, and generate high dynamic range images from the image signals acquired by the sCMOS imaging chips and send them to the host computer.

[0016] Preferably, the imaging target surface is exposed line by line using a rolling shutter exposure method, and the exposure time of the middle line of the target surface plus the start time of the middle line exposure is recorded as the exposure time of each frame of image signal.

[0017] Compared with the prior art, the present invention can achieve the following beneficial effects: This invention provides an imaging circuit and system applicable to large-target mosaic detectors for ground-based large-scale survey telescopes. The imaging circuit uses an FPGA chip as its core processor and integrates functional modules such as sCMOS driver, control center, data center, status monitoring module, and external communication interface. This achieves efficient utilization of hardware resources and high functional integration, improving system reliability and stability. Furthermore, to adapt to large-target mosaic detectors, this invention designs a synchronous control terminal and synchronous operation logic, realizing synchronous control and output of multiple imaging circuits within the mosaic detector. This ensures that all detectors perform exposure and data acquisition within the same time window, effectively avoiding data inconsistencies caused by timing deviations and improving the validity and accuracy of observation data.

[0018] This invention, based on traditional imaging circuits, utilizes the ability of sCMOS imaging chips to output both low-gain and high-gain image signals. It designs an on-board high dynamic range (HVR) image synthesis function, controlling the synchronous output of low-gain and high-gain images from the sCMOS imaging chip and fusing them through HVR synthesis technology. This increases the maximum dynamic range from 71.5dB to 92.4dB, effectively solving the problems of overexposure in bright areas and loss of detail in dark areas in high-contrast scenes using traditional cameras. It achieves the ability to present details in extremely bright areas without losing weak signals in dark areas within the same image, improving image quality and broadening the camera's application range. This is particularly beneficial for astronomical observation scenarios with high dynamic range requirements, such as those requiring large ground-based survey telescopes. Furthermore, the HVR synthesis process fully leverages the parallel processing advantages of FPGAs. Using an FPGA to perform on-board HVR image synthesis significantly improves the efficiency of HVR image synthesis compared to the traditional method of sending high-gain and low-gain images to a host computer for subsequent synthesis processing. The image computation latency is only 16ns, far faster than methods that send images to a host computer for computation.

[0019] This invention designs an optical communication data interface to replace the traditional camera link interface, simplifying the long-distance image transmission link; and designs a function to record the exposure time information of the image inside the camera, with a time resolution of 1μs, which solves the drawback of the traditional optical telescope imaging system requiring the addition of an event latch, improves the time accuracy and simplifies the complexity of the telescope system.

[0020] The imaging circuit of this invention, when applied to a large-target camera in a ground-based large optical telescope, has been tested and calculated to have a camera readout noise of [value missing]. Dark current The dynamic range is 92.4dB, both of which are at the leading level in the industry. Attached Figure Description

[0021] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments and descriptions of the invention are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a circuit diagram of a ground-based optical telescope with a large target surface for imaging, provided according to an embodiment of the present invention. Figure 2 This is a functional module structure design diagram of an FPGA provided according to an embodiment of the present invention; Figure 3 This is an operational logic diagram of the control center provided according to an embodiment of the present invention; Figure 4 This is a schematic diagram of data caching and reading provided according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the synchronous control of an imaging system provided according to an embodiment of the present invention; Figure 6 This is a timing diagram of control and status information of an imaging system provided according to an embodiment of the present invention; Figure 7 This is a timing diagram of exposure time information provided according to an embodiment of the present invention; Figure 8 These are the low-gain and high-gain images displayed on the host computer's image acquisition interface during testing; Figure 9 It is a low-gain image acquired during testing; Figure 10 It is a high-gain image acquired during testing. Figure 11 These are high dynamic range images acquired during testing; Figure 12 It is a local comparison image of the low-gain image and the high-dynamic image acquired during the test; Figure 13 It is a local comparison image of the acquired high-gain image and high-dynamic-range image. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only for explaining the invention and do not constitute a limitation thereof. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of the invention. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, some operations related to the invention are not shown or described in the specification. This is to avoid obscuring the core parts of the invention with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0023] It should be noted that, unless otherwise specified, the embodiments and features described in this invention can be combined to form various implementations. Furthermore, the order of the steps or actions in the method description can be changed or adjusted in a manner readily apparent to those skilled in the art. Therefore, the various orders in the specification and drawings are merely for the clear description of a particular embodiment and do not imply a mandatory order, unless otherwise stated that a particular order must be followed.

[0024] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0025] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0026] The invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0027] In one embodiment of the present invention, a large target surface imaging circuit for a ground-based optical telescope is provided, which is applied to large-field-of-view detection scenarios of ground-based large optical telescopes. To achieve large-field-of-view detection, the imaging circuit of the present invention employs a stitchable back-illuminated sCMOS imaging chip. The sCMOS imaging chip adopts a stitched packaging design, minimizing the size of the package bezel as much as possible, making the sCMOS imaging chip suitable for large target surface stitched detectors. By stitching together multiple sCMOS imaging chips, the target surface of the ground-based optical telescope can be obtained to meet the requirements of large-field-of-view detection. For the imaging design of a single sCMOS imaging chip in a stitched detector, please refer to [link to relevant documentation]. Figure 1 This invention provides a large-target imaging circuit for a ground-based optical telescope, comprising an imaging chip section and a processing circuit section. The imaging chip section uses an sCMOS imaging chip to acquire light signals and convert them into electrical signals, completing the photoelectric conversion process to achieve digital imaging of the target or scene. This electrical signal is the image signal processed by subsequent circuits. Because this imaging circuit needs to be applied to a ground-based optical telescope, the sCMOS imaging chip has high requirements; therefore, a custom design is adopted. The sCMOS imaging chip has a resolution of 16.8 million pixels, a peak quantum efficiency of 92%, and a minimum readout noise of [missing information]. The sCMOS imaging chip uses 10 pairs of LVDS (Low Voltage Differential Signaling Links) to transmit data. Each pair of LVDS operates at a speed of 420 Mbps and supports 12-bit dual-gain imaging mode and 14-bit single-gain imaging mode. It can perform imaging at a maximum speed of 4 fps at full resolution.

[0028] The processing circuitry utilizes an FPGA, which connects to the sCMOS imaging chip via a high-speed connection channel for information transmission. Furthermore, due to the limited data storage capacity of the FPGA, and the fact that the single-frame data volume of the sCMOS imaging chip is approximately 386Mb, far exceeding the FPGA's internal storage resources, the imaging circuit in this embodiment also includes a data management unit. This unit comprises DDR chips and FLASH chips connected in parallel with the FPGA. Four DDR chips are used, specifically DDR3 memory chips with a specification of 256M×16, a data read / write rate of 102.4Gbps, and a storage space of 16Gb. The DDR chips are used to buffer the image signals transmitted from the sCMOS imaging chip to the FPGA, facilitating the FPGA's storage and retrieval of image signals. The DDR chips effectively improve the bandwidth for data storage and transmission to handle the processing of large amounts of image data. Four FLASH chips are also used, specifically QSPI FLASH memory chips, with a total storage space of 2Gb. The main function of the FLASH chips is to store the configuration parameters of the sCMOS imaging chip and the FPGA's program code and other circuit control data, enabling the refreshing of the control data.

[0029] Since the image signal transmitted from the sCMOS imaging chip to the FPGA for processing needs to be further transmitted to the host computer for subsequent processing, the imaging circuit of this invention also includes an external interface unit. Unlike the traditional CameraLink interface, the external interface unit of the imaging circuit in this embodiment includes an optical module and a serial bus transceiver. The optical module is mainly used to transmit the image signal from the sCMOS imaging chip to the FPGA, and the image signal processed by the FPGA is then transmitted to the host computer via optical communication, facilitating subsequent processing of the image data. Furthermore, during image acquisition controlled by the host computer, control commands can also be transmitted to the FPGA via the optical module. The serial bus transceiver uses an RS422 serial data bus and is mainly used to receive and send configuration and status information of the sCMOS imaging chip.

[0030] As a preferred embodiment, since the sCMOS imaging chip requires 19 power supplies for operation, and power-on and power-off operations must be performed sequentially and at time intervals to ensure safe chip operation, and the temperature and voltage data of the sCMOS imaging chip need to be monitored in real time to prevent the sCMOS imaging chip from burning out due to overheating or overvoltage, the imaging circuit of this embodiment also includes a temperature monitoring module and a voltage monitoring module. The temperature monitoring module is connected to the sCMOS imaging chip and monitors the temperature data of the sCMOS imaging chip in real time, feeding the temperature data back to the FPGA for comparison with a set over-temperature threshold. Similarly, the voltage monitoring module monitors the voltage data of the sCMOS imaging chip in real time and feeds the voltage data back to the FPGA for comparison with a set over-voltage threshold. When the FPGA receives temperature and / or voltage data from the sCMOS imaging chip that exceeds the normal range, it promptly controls the sCMOS imaging chip to power down gradually in batches. Correspondingly, since the FPGA may also experience overheating, a temperature monitoring module is also included to monitor the FPGA in real time to prevent the FPGA from burning out due to overheating.

[0031] Please see Figure 2As the core module of the imaging circuit, the FPGA in this embodiment of the invention is also modularly designed, with reasonable encapsulation and separation of its internal components, and the FPGA is modularly designed according to functional modules. Specifically, the FPGA includes a control center, an sCMOS driver unit, and a data center. The control center is the top-level control module in the imaging circuit, which needs to control the enabling and timing of other functional modules based on the host computer configuration and status monitoring information. Enabling refers to the control center sending drive signals to each functional module in the FPGA, and the functional modules execute corresponding actions according to the enable signals sent by the control center. In this embodiment of the invention, the main enable signals sent by the control center include: control signals for the sCMOS driver unit, control signals for the data management unit, control signals for the temperature monitoring module and voltage monitoring module, and control signals for the external interface unit. The external interface unit is designed to enable information transmission with the optical module and serial bus transceiver. This unit primarily consists of a camera status transmission module and a control command receiving module within the FPGA. The camera status transmission module transmits the configuration and hyperparameter information of the sCMOS imaging chip acquired by the FPGA to the host computer for confirmation. The control command receiving module receives control information from the host computer and inputs it into the FPGA to control the sCMOS imaging chip. The camera status transmission module includes an optical camera status transmission module outputting to the optical module and a serial camera status transmission module outputting to the serial bus transceiver. The control command receiving module includes an optical control command receiving module input from the optical module to the FPGA and a serial control command receiving module input from the serial bus transceiver to the FPGA.

[0032] The sCMOS driver unit includes a clock module, an SPI control module, a DECODER control module, and a TIMING control module. The clock module provides clock signals to the sCMOS imaging chip and the FPGA. It provides a 420MHz SDR clock CLK-IN to the sCMOS imaging chip using a low-voltage differential signal. This signal serves as the reference clock for the internal data stream of the sCMOS imaging chip, ensuring that the sCMOS imaging chip and the FPGA have the same reference clock. Furthermore, when the sCMOS imaging chip sends image signals to the FPGA, it also synchronously sends a DDR clock CLK-OUT in addition to the image signals.

[0033] The SPI control module can transmit various control commands issued by the control center and configure the operating mode and parameters of the sCMOS imaging chip via the SPI protocol. The operating modes of the sCMOS imaging chip include, but are not limited to, high-gain STD mode, low-gain STD mode, and HDR imaging mode. Operating parameters include integration time, window size, and frame rate.

[0034] The DECODER and TIMING control modules are used to send signal commands from the control center to the sCMOS imaging chip in corresponding forms, controlling the internal operating timing of the sCMOS imaging chip. Specifically, the DECODER control module controls the readout order of image signals from each pixel of the sCMOS imaging chip; the TIMING control module generates the timing sequence for the sCMOS imaging chip to acquire light signals.

[0035] The data center is primarily used for data transmission and exchange. Its main functions include receiving image signals from the sCMOS imaging chip, transmitting these signals to the host computer, and caching the image signals, configuration parameters, and FPGA program code from the sCMOS imaging chip in DDR and FLASH memory, or retrieving data from DDR and FLASH. Since the sCMOS imaging chip transmits image signals via an LVDS link, an LVDS receiving module is installed at the front end of the data center to receive image data. This module adapts to the LVDS data transmission link of the sCMOS imaging chip. The sCMOS imaging chip transmits the acquired image signals to the FPGA via the LVDS link, where the LVDS receiving module performs serial-to-parallel conversion and multi-channel data alignment before transmitting the signals back to the data center. Because the data center needs to transmit image signals to an optical module, which then transmits them to the host computer, an optical communication arbitration module is installed at the back end of the data center to send the image signals to the optical module.

[0036] Please see Figure 3This invention employs a special design for the power-on and power-off control of the sCMOS imaging chip. Specifically, the power supply circuit for the sCMOS imaging chip includes 19 power supplies. During power-on, these 19 power supplies are provided to the sCMOS imaging chip in three batches. After the telescope system is powered on, it first acquires temperature and voltage data collected by the temperature and voltage monitoring modules. The FPGA compares the temperature and voltage data with set thresholds to confirm that the voltage and temperature of the sCMOS imaging chip are normal, then controls the first batch of power supply supply 1 to power on. After the first batch of power supply supply 1 is powered on and stabilized, it acquires temperature and voltage data again from the temperature and voltage monitoring modules. The FPGA compares the temperature and voltage data with set thresholds to confirm that the voltage and temperature of the sCMOS imaging chip are normal. Then, the SPI control module configures the sCMOS imaging chip according to the configuration operation issued by the control center, i.e., sets the operating mode and parameters of the sCMOS imaging chip. After the sCMOS imaging chip is configured, the FPGA reads back the configuration information of the sCMOS imaging chip. After confirming that the configuration is correct, it performs voltage and temperature detection again. After confirming that the voltage and temperature are normal, power on the second batch of power supplies (supply2). Once the second batch of power supplies (supply2) is stable, repeat the voltage and temperature confirmation. After confirming that everything is correct, power on the third batch of power supplies (supply3). Once the third batch of power supplies (supply3) is stable, repeat the voltage and temperature confirmation. After confirming that everything is correct, enable the TRAIN function to sequentially perform bit alignment, word alignment, and channel alignment. After completion, enter the idle state to prepare for imaging, i.e., initialize and calibrate the sCMOS imaging chip. In the idle state, the sCMOS imaging chip can be driven and image acquisition and transmission can be performed according to the working mode, exposure time, frame rate, and other parameters configured by the host computer.

[0037] During the power-on process described above, if any voltage or temperature abnormality is detected during any voltage and temperature verification, the sCMOS imaging chips will be powered down in batches. If image acquisition is terminated via the host computer, i.e., a camera shutdown command is received, the power-down operation will also be performed in three batches sequentially on the third batch power supply (supply3), the second batch power supply (supply2), and the first batch power supply (supply1).

[0038] After the sCMOS imaging chip is powered on, image acquisition is performed, and the image signal and the feedback clock signal are sent to the FPGA via the LVDS link (this signal is referred to as the LVDS signal). After receiving the LVDS signal, the FPGA needs to convert the LVDS signal into a low-data-rate, high-bit-width signal, which is generally implemented through the ISERDES module. Simultaneously, based on the received clock data, a closed-loop control delay setting is implemented to achieve multi-channel data alignment. This delay setting is typically achieved by designing an IDELAY module at the front end of the data center. In actual testing, the LVDS signals input from the sCMOS imaging chip are shown in Table 1 below. The signal jitter at the receiving end is less than 509 ps, effectively ensuring the stability of the received data.

[0039] Table 1 LVDS signal reception test results

[0040] Since the data volume of a single frame of an sCMOS imaging chip is approximately 386Mb, far exceeding the internal storage resources of an FPGA, the image signal input to the sCMOS imaging chip needs to be written to a DDR chip. The DDR chip has a data read / write rate of 102.4Gbps and uses the AXI-Full bus protocol for data writing and reading. The AXI-Full bus protocol is a high-performance, high-bandwidth, low-latency on-chip bus protocol suitable for high-performance memory mapping requirements. The data caching process is as follows... Figure 4 As shown, the data center uses an AXI bus interaction center, connecting sequentially to the MIG core and DDR chip via the master interface M00_AXI on the data center. Image signals and sCMOS imaging chip configuration data are stored in the DDR through slave interfaces S00_AXI and S01_AXI using a dual FIFO ping-pong buffering method. Then, image signals and sCMOS imaging chip configuration data are read from the slave interfaces S02_AXI and S03_AXI, buffered through the dual FIFO ping-pong buffer, processed, and finally sent to the image processing server, i.e., the host computer.

[0041] In a preferred embodiment, the operating modes of the sCMOS imaging chip are specially designed to include a high-gain STD mode, a low-gain STD mode, and an HDR imaging mode. The HDR imaging mode utilizes the parallel processing capabilities of an FPGA to control the sCMOS imaging chip to simultaneously output low-gain and high-gain images; that is, it acquires the pixel electrical signals using two ADCs with different amplification factors. The FPGA then combines the low-gain and high-gain signals to generate a high dynamic range image, thus achieving the HDR imaging mode. Specifically, the photon response curve of the low-gain image signal is as follows: ; in, This represents the pixel output value of a low-gain image signal. This represents the slope of the linear region of the low-gain channel response curve. This represents the black level offset of a low-gain image signal. This indicates the number of photons incident on the pixels of the sCMOS imaging chip.

[0042] The photon response curve of a high-gain image signal is as follows: ; in, This represents the pixel output value of a high-gain image signal. This represents the slope of the linear region of the high-gain channel response curve. This indicates the black level offset of a high-gain image signal.

[0043] Parallel fusion of low-gain and high-gain image signals yields the photon response curve of the high dynamic range image as follows: ; in, This represents the pixel output value of a high dynamic range image. This indicates the gain ratio of a high dynamic range image. This represents the compensation value for high dynamic range images. The threshold representing the conversion between high-gain and low-gain image signals. This indicates the maximum value of the output data format. From the derivation, we can obtain: ; .

[0044] Because this invention utilizes high-speed parallel processing via FPGA to integrate high dynamic range compositing functionality into the image data stream, it achieves on-chip compositing using FPGA, overcoming the traditional problem of requiring image compositing on a host computer. On-chip compositing effectively improves the efficiency of high dynamic range image compositing and reduces image computation latency. Tests show that the computation latency of on-chip compositing is only 16ns, far lower than the latency of traditional compositing performed on a host computer.

[0045] Based on the aforementioned imaging circuit, this invention also proposes a ground-based optical telescope large target surface imaging system. Specifically, this system serves as an imaging camera for the ground-based optical telescope. Due to the high requirements for field-of-view detection, the imaging system includes multiple of the aforementioned ground-based optical telescope large target surface imaging circuits. Multiple sCMOS imaging chips from these circuits are stitched together to form an imaging target surface. In this embodiment, 16 imaging circuits are included, and the imaging target surface is formed by stitching together 16 sCMOS imaging chips. To achieve synchronous operation of multiple imaging circuits, a synchronous control terminal and a host computer for inputting control commands and outputting images are also designed into the system.

[0046] like Figure 5 As shown, the connection method between the synchronization control terminal and the synchronization control server of the host computer is the same as the connection method between the imaging circuit and the host computer, both using a single fiber optic communication cable, simplifying the camera's external interface. The synchronization control terminal communicates with each imaging circuit via a serial communication bus. For the synchronization control process of the synchronization control terminal over the imaging circuits, please refer to [link to documentation]. Figure 6 Upon receiving control commands, clock signals, and other pulse signals for the imaging target, the synchronization control terminal distributes these signals to the imaging circuits and simultaneously generates synchronization trigger pulses to control the synchronous operation of all imaging circuits. Furthermore, during the information feedback process, the synchronization control terminal also synchronously receives feedback signals from each imaging circuit and combines these signals before sending them to the host computer.

[0047] During the imaging process, the image slices need to be precisely matched with information such as the exposure time and pose. Therefore, it is necessary to accurately record the time information of each exposure to ensure the temporal accuracy of the observation data. Simultaneously, recording the camera exposure time information can confirm the synchronization of multiple devices, effectively avoiding data inconsistencies caused by timing deviations. Therefore, this invention also incorporates the following... Figure 7 The exposure time information recording method shown internally sets the clock signal subdivision resolution to 1µs. Furthermore, the imaging target surface uses a rolling shutter exposure method for line-by-line exposure and line-by-line light signal reading. Half of the exposure time of the middle line of the target surface, plus the start time of the middle line exposure, is recorded as the exposure time of each frame of the image signal. The exposure data and image data are then merged and sent to a host computer image processing server to achieve synchronous exposure imaging of a large target surface.

[0048] To verify the effectiveness of the imaging circuit and system of this invention, the imaging system was powered on and connected to a host computer via optical fiber. The host computer acquired data such as... Figure 8 The images shown are low-gain and high-gain images. After parameter control testing, an imaging rate of 4fps was achieved in 16.8-megapixel full-frame resolution, 16-bit image depth, and high / low gain simultaneous output mode.

[0049] Further imaging tests were conducted on an experimental platform consisting of an integrating sphere light source and a darkroom. The integrating sphere used a custom-designed 15cm aperture high-brightness uniform light source system, USS-2000C, with an illumination uniformity ≥98%. Based on the experimental platform tests, the camera readout noise was calculated to be... Dark current By adjusting the light source and exposure time, the grayscale of the high-gain and low-gain images was adjusted to approximately half of the maximum grayscale value, resulting in a better imaging effect.

[0050] To further verify the high dynamic range synthesis function, results were obtained in different working modes, such as... Figure 9 The low-gain image shown is as follows: Figure 10 The high-gain image shown, and as Figure 11 The high dynamic range image shown. (As shown in the image.) Figure 12 As shown, a comparison of local areas of the low-gain and high-dynamic-range (HDL) images reveals that the HDL composite image, compared to the low-gain image, exhibits increased image detail at low light levels. Calculations show that the HDL composite image improves the out-of-dynamic-range by 20.9 dB compared to the low-gain image. Figure 13 As shown, a local comparison of the high-gain image and the high-dynamic-range image reveals that the high-dynamic-range composite image, compared to the high-gain image, exhibits increased image detail under high light intensity. Calculations show that the high-dynamic-range composite image improves the outgoing dynamic range by 25.1 dB compared to the high-gain image.

[0051] In summary, the imaging circuit and system of this invention achieve 16.8-megapixel resolution full-frame imaging at 4fps, with camera readout noise of [value missing]. Dark current With a dynamic range of 92.4dB, it not only meets the requirements of large target imaging detection for ground-based optical telescopes, but also has all indicators at the industry-leading level.

[0052] In summary, the above description is merely a preferred embodiment of this specification and is not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of protection of this specification.

[0053] The systems, apparatuses, modules, or units described in one or more of the above embodiments may be implemented by a computer chip or entity, or by a product having a certain function. A typical implementation device is a computer. Specifically, a computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smartphone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or any combination of these devices.

[0054] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0055] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

Claims

1. A ground-based optical telescope large target imaging system, characterized in that, It includes large-target imaging circuits for multiple ground-based optical telescopes, synchronous control terminals, and host computers; The ground-based optical telescope's large-target imaging circuit includes: an sCMOS imaging chip for acquiring light signals and converting them into image signals; and an FPGA connected to the sCMOS imaging chip. The FPGA includes a control center and an sCMOS driving unit. The control center controls the enabling and timing of functional modules in the FPGA based on host computer configuration and status monitoring information. The sCMOS driving unit generates and provides clock signals and control signals required for the sCMOS imaging chip to operate, and receives image signals output by the sCMOS imaging chip. The control center controls different power supplies in the sCMOS imaging chip to power on in batches. After at least one batch of power supplies is powered on and stabilized, the sCMOS imaging chip is configured using SPI. After all different power supplies are powered on and stabilized, the sCMOS imaging chip is driven to acquire and transmit images based on the host computer input signal. During the OS imaging chip process, the 19 power supplies of the sCMOS imaging chip are controlled to be powered on in three batches. The system also includes a temperature monitoring module and a voltage monitoring module. When the 19 power supplies of the sCMOS imaging chip are powered on in batches, the temperature and voltage of the sCMOS imaging chip are monitored before and after each batch of power-on, and the data is fed back to the FPGA. When the temperature and / or voltage exceed the set range, the control center controls the different power supplies of the sCMOS imaging chip to be powered off in batches. The sCMOS imaging chip has the following operating modes: high-gain STD mode, low-gain STD mode, and HDR imaging mode. In HDR imaging mode, the sCMOS imaging chip simultaneously outputs low-gain image signals and high-gain image signals. The FPGA performs high dynamic range synthesis based on the low-gain image signals and high-gain image signals through parallel processing, generating a high dynamic range image, and then sends the high dynamic range image to the host computer. Multiple sCMOS imaging chips are stitched together to form an imaging target surface. The synchronization control terminal is connected to the FPGA in the large target surface imaging circuit of each of the ground-based optical telescopes, as well as the synchronization control server of the host computer. The synchronization control terminal is used to receive the control signal from the synchronization control server of the host computer, distribute and transmit the control signal to the FPGA in each of the large target imaging circuits of the ground-based optical telescope, and generate a synchronization trigger pulse to transmit to the FPGA in each of the large target imaging circuits of the ground-based optical telescope, so that all FPGAs synchronously drive their corresponding sCMOS imaging chips, and generate high dynamic range images from the image signals acquired by the sCMOS imaging chips and send them to the host computer.

2. The ground-based optical telescope large target imaging system according to claim 1, characterized in that, The imaging target surface is exposed line by line using a rolling shutter exposure method, and the exposure time of each frame of the image signal is recorded as half of the exposure time of the middle line of the target surface plus the start time of the middle line exposure.

3. The ground-based optical telescope large target imaging system according to claim 1, characterized in that, The sCMOS imaging chip is a stitchable back-illuminated sCMOS chip.

4. The ground-based optical telescope large target imaging system according to claim 1, characterized in that, Also includes: The data management unit includes: four parallel DDR chips connected to the FPGA, and a FLASH chip. The DDR chips are used to buffer image signals, facilitating the FPGA to store and retrieve image signals. The FLASH chip is used to store the configuration parameters of the sCMOS imaging chip and the program code of the FPGA.

5. The ground-based optical telescope large target imaging system according to claim 1, characterized in that, The sCMOS driving unit includes: A clock module is used to provide clock signals for the sCMOS imaging chip and the FPGA; The SPI control module allows the FPGA to configure the operating mode and parameters of the sCMOS imaging chip. The DECODER control module is used to control the readout order of image signals from each pixel of the sCMOS imaging chip. The TIMING control module is used to generate the timing sequence for the sCMOS imaging chip to acquire optical signals.

6. The ground-based optical telescope large target imaging system according to claim 1, characterized in that, The sCMOS imaging chip acquires image signals corresponding to pixels using an ADC at different amplification levels. The photon response curve for the low-gain image signal is as follows: ； in, This represents the pixel output value of a low-gain image signal. This represents the slope of the linear region of the low-gain channel response curve. This represents the black level offset of a low-gain image signal. This indicates the number of photons incident on the pixels of the sCMOS imaging chip; The photon response curve of the high-gain image signal is as follows: ； in, This represents the pixel output value of a high-gain image signal. This represents the slope of the linear region of the high-gain channel response curve. This indicates the black level offset of a high-gain image signal; The photon response curve of a high dynamic range image is as follows: ； in, This represents the pixel output value of a high dynamic range image. This indicates the gain ratio of a high dynamic range image. This represents the compensation value for high dynamic range images. The threshold representing the conversion between high-gain and low-gain image signals. This indicates the maximum value of the output data format.

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