Through-silicon-via #-shaped artificial surface plasmon band-pass filter

Abstract

The invention relates to the technical field of band-pass filters, and discloses a through-silicon-via #-shaped artificial surface plasmon band-pass filter comprising a dielectric substrate which comprises a signal wiring layer, a substrate layer and an RDL layer; the three-dimensional TSV array comprises an odd number of through columns vertically connected with the signal wiring layer and a plurality of #-shaped units; the through columns are divided into independent through columns and through column groups, each through column group comprises two adjacent through columns with the same length, and the independent through columns and the through column groups are alternately arranged along the direction of the signal wiring layer; wherein each through column comprises equal-length TSV parts and RDL parts arranged at the two ends of the TSV parts, the TSV parts are arranged in the substrate layer, the #-shaped units are arranged on the RDL parts at the two ends of the through column group respectively, and the symmetric center of the three-dimensional TSV array is the independent through column.

Description

Technical Field

[0001] The present application relates to the technical field of bandpass filters, and in particular to a through-silicon via (TSV) tic-tac-toe artificial surface plasmon bandpass filter. Background Art

[0002] In the field of three-dimensional integrated circuits, through-silicon via (TSV) technology enables heterogeneous integration by vertically stacking chips, overcoming the physical limitations of traditional planar interconnects. Compared to traditional processes such as bonding and flip-chip bonding, TSV technology utilizes vertical conductive vias within the silicon substrate to effectively shorten signal paths and significantly reduce resistance-capacitance parameters, thereby improving system integration density and energy efficiency. The core advantage of TSV technology lies in its ability to directly interconnect chips with different functions, such as logic layers, memory cells, and RF modules. This allows for three-dimensional wiring reconfiguration through interposers or direct stacking, providing flexible configuration solutions for high-performance computing and wireless communications. In 3D integrated circuit systems, on-chip bandpass filters, as key components in the RF front-end, ensure efficient transmission of signals within the passband and effectively attenuate out-of-band interference signals. This directly determines the signal-to-noise ratio and transmission stability of wireless communication systems. With breakthroughs in TSV technology, vertical interconnect structures have opened up new avenues for heterogeneous integration of RF modules. TSV-based three-dimensional wiring not only shortens signal transmission distances but also improves the filter's frequency response by optimizing the three-dimensional magnetic field distribution.

[0003] Artificial surface plasmon polaritons (SSPPs) are artificially designed periodic structures that mimic the properties of optical surface plasmon polaritons (SPPs) by incorporating surface etchings (e.g., grooves, holes, and interdigitated shapes). This enables surface electromagnetic wave propagation in the microwave, millimeter-wave, and terahertz frequency bands. Surface waves in this structure propagate along the metal-dielectric interface, with the electric field exponentially decaying in the transverse direction, demonstrating strong field confinement. The SSPP's dispersion curve lies to the right of the speed of light line, exhibiting slow-wave characteristics. Its cutoff frequency and mode can be flexibly controlled by adjusting structural parameters (such as groove depth, period, and shape), enabling low-pass, bandpass, or multi-band response.

[0004] Existing on-chip SSPP filters for integrated circuits are mainly based on planar microstrip structures. Their two-dimensional structure limits the further improvement of device integration. In addition, existing SSPP filters are limited by the planar layout space, the number and range of adjustable parameters are limited, and the stopband suppression capability is also subject to certain constraints. At the same time, the application scenarios of traditional on-chip integrated SSPP structures cannot be extended to the stacked inter-layer filtering transmission of three-dimensional integrated circuits, which limits their application in three-dimensional integrated circuits. Summary of the Invention

[0005] In order to solve the above technical problems, the present application provides a through-silicon via (TSV) tic-tac-toe artificial surface plasmon bandpass filter, which adopts the following technical solutions: Through-silicon-via tic-tac-toe artificial surface plasmon bandpass filter, including: A dielectric substrate, including a signal wiring layer, a substrate layer, and an RDL layer; A three-dimensional TSV array, comprising an odd number of through-pillars vertically connected to the signal wiring layer and a plurality of well-shaped units; The through-pillars are divided into independent through-pillars and through-pillar groups, the through-pillar group includes two adjacent through-pillars of equal length, and the independent through-pillars and the through-pillar group are alternately arranged along the direction of the signal wiring layer; Each through-pillar includes a TSV portion of equal length and an RDL portion arranged at both ends of the TSV portion. The TSV portion is arranged in the substrate layer, and the crisscross-shaped units are respectively arranged on the RDL portions at both ends of the through-pillar group. The symmetry center of the three-dimensional TSV array is the independent through-pillar.

[0006] Optionally, the RDL layer includes a plurality of RDL interconnect layers and RDL dielectric layers that are alternately arranged, wherein the RDL dielectric layer is connected to the substrate layer.

[0007] Optionally, the substrate layer includes a stacked substrate and a base substrate symmetrically arranged on both sides of the signal wiring layer.

[0008] Optionally, the TSV portion includes an inner metal conductor and an outer insulating liner layer.

[0009] Optionally, the signal wiring layer includes an integrally formed input port, an RDL signal channel, and an output port.

[0010] Optionally, the number of the through-pillars is 13, and the number of the tic-tac-toe-shaped units is 8.

[0011] Optionally, the RDL interconnect layer and the RDL dielectric layer are both provided with 6 layers.

[0012] Optionally, a height difference between the independent through-pillar and the through-pillar group is the sum of the thicknesses of the RDL interconnect layer and the RDL dielectric layer.

[0013] In summary, this application includes at least the following beneficial technical effects: Given the strong field localization characteristics of SSPP, we propose a three-dimensional SSPP bandpass filter based on an advanced through-silicon via (TSV) and redistribution layer (RDL) packaging process. This TSV-shaped artificial surface plasmon bandpass filter, disclosed in this application, differs from traditional planar integrated structures in that it consists of a vertically symmetrical structure that tightly confines electromagnetic energy at the metal-dielectric interface. This not only reduces crosstalk between adjacent circuits but also enables device miniaturization. By optimizing geometric parameters and designing structural deformations, the high-frequency cutoff and stopband extension characteristics of the dispersion curve can be flexibly controlled to meet multi-band compatibility requirements.

[0014] In addition, in this application, a portion of the planar wiring length is converted into the vertical TSV height, which effectively reduces the wiring area occupied compared to the traditional planar structure. The saved wiring layer space can be used for interconnection or wiring of other on-chip devices, which makes the present invention have a higher integration density. This application introduces eight tic-tac-toe cells to replace the traditional method of uniformly deepening the grooves. This improvement effectively reduces the cutoff frequency and achieves a more compact design. SSPP is typically constructed using a planar process, which limits design flexibility. However, TSV and redistribution layer (RDL) interconnect technologies enable flexible routing within, on top, and on the bottom of the substrate, effectively expanding the design flexibility and performance ceiling of SSPP.

[0015] This application fully utilizes the three-dimensional wiring space inside the substrate (where the TSV is located) and on the front and back sides of the substrate (where the RDL is located), which is conducive to significantly improving the integration density of on-chip filters and has more flexible and adjustable three-dimensional parameters to enhance out-of-band suppression capabilities. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Schematic diagram of the cross-sectional layer structure of the through silicon via tic-tac-toe artificial surface plasmon bandpass filter in this application; Figure 2 This is a schematic diagram of the three-dimensional connection structure of the three-dimensional TSV array and the signal wiring layer of the through silicon via tic-tac-toe artificial surface plasmon bandpass filter in this application; Figure 3 This is the equivalent circuit diagram of the through-silicon via tic-tac-toe artificial surface plasmon bandpass filter in this application; Figure 4 Schematic diagram of the layer structure size parameters of the through silicon via tic-tac-toe artificial surface plasmon bandpass filter in this application; Figure 5 This is a schematic diagram of the top-view dimension parameters of the TSV-shaped artificial surface plasmon bandpass filter in this application.

[0017] Figure numerals: 1, signal wiring layer; 2, substrate layer; 3, RDL layer; 4, independent through-pillar; 5, through-pillar group; 6, tic-tac-toe unit; 11, input port; 12, output port; 13, RDL signal channel; 21, stacked substrate; 22, base substrate; 31, RDL interconnect layer; 32, RDL dielectric layer; 41, TSV part; 42, RDL part; 411, metal conductor; 412, insulating liner layer. DETAILED DESCRIPTION

[0018] Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings.

[0019] Throughout this specification, reference to the terms "certain embodiments," "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0020] The embodiment of the present application discloses a through silicon via tic-tac-toe artificial surface plasmon bandpass filter, such as Figure 1 and Figure 2 As shown, it includes a dielectric substrate and a three-dimensional TSV array; The dielectric substrate includes a signal wiring layer 1, a substrate layer 2 and an RDL layer 3; The three-dimensional TSV array includes 13 through-pillars vertically connected to the signal wiring layer 1 and a plurality of well-shaped cells 6 .

[0021] Among them, the dielectric substrate and the three-dimensional TSV array are both symmetrical bodies. The dielectric substrate takes the signal wiring layer 1 as the symmetry center. The signal wiring layer 1 is located between the stacked substrate 21 and the base substrate 22 with the same structure. The outermost layer is provided with an RDL layer 3 connected to the corresponding substrate; the RDL layer 3 includes 6 layers of RDL interconnect layers 31 and 6 layers of RDL dielectric layers 32 connected alternately, and the RDL dielectric layer 32 is connected to the substrate layer 2.

[0022] The signal wiring layer 1 serves as the main signal transmission path, including an input port 11, an RDL signal channel 13 and an output port 12 that are integrally connected in sequence, and the three-dimensional TSV array serves as a signal transmission path in the vertical direction.

[0023] Taking the direction of the main signal transmission path as an example, the through-pillars in the three-dimensional TSV array are divided into independent through-pillars 4 and through-pillar groups 5. The through-pillar group 5 includes two adjacent through-pillars of equal length. The independent through-pillars 4 and the through-pillar group 5 are alternately arranged along the direction of the signal wiring layer 1, and the heights of the adjacent independent through-pillars 4 and through-pillar groups 5 are different, so that the vertical cross-section of the structure of the entire three-dimensional TSV array is similar to a rugby ball. The independent through-pillar 4 at the center of symmetry is the highest, and then the height of the through-pillars decreases to both sides. At the ends of the via groups 5 on either side of the independent via 4, crisscross units 6 are arranged. Each via includes a TSV portion 41 of equal length and RDL portions 42 disposed at either end of the TSV portion 41. The TSV portion 41 is disposed within the substrate layer 2. The two horizontal structures of the crisscross unit 6 overlap with two adjacent RDL dielectric layers 32. The height difference between adjacent independent vias 4 and via groups 5 is the sum of the thicknesses of the RDL interconnect layer 31 and the RDL dielectric layer 32. A total of eight crisscross units 6 are present. The substrate layer 2 and the TSV portions 41 constitute the non-periodic unit of the SSPP. These are connected by vias, forming the three-dimensional RDL portion 42 that guides the SSPP mode.

[0024] See also Figure 3 The equivalent circuit schematic diagram shows that the tic-tac-toe unit in SSPP can be simplified to be equivalent to a simple signal transmission loop. The inductance value of this loop is Ls, and the capacitance value is Cs. The size of the inductance and capacitance is affected by parameters such as the length and width of the through-column, the opening width, and the spacing between adjacent rings. All through-columns are coupled with the magnetic field of the transmission path through mutual inductance M, and the mutual inductance mainly depends on the distance between the through-column and the transmission path. Lm represents the self-inductance of the signal transmission path, which is mainly determined by the diameter of the TSV and the through-hole, and the width H of the redistribution layer RDL in the present invention. Cp represents the parasitic capacitance introduced by the substrate, which is mainly affected by the conductivity and height of the substrate. The circuit principle can be briefly summarized as follows: when the transmitted signal passes through the through-column, the through-column generates a magnetic response with the signal magnetic field. The design of periodic unequal heights of the through-columns can gradually adjust the equivalent refractive index, so that the overall structure exhibits the characteristics of a bandpass filter. As shown Figure 4 As shown, the height h3 of the TSV portion 41 is 400um, the height h1 of the through hole in the RDL portion 42 (although the appearance is a cylindrical structure, the processes of the through holes in the TSV portion 41 and the RDL portion 42 are completely different and need to be strictly distinguished) is 80um, the height h2 of the wiring layer in the RDL portion 42 is 40um, and the thickness of the signal wiring layer 1 is also h2.

[0025] Distribution reference of through-hole array (TSV, wiring and through-hole) Figure 5There is a corresponding relationship between the position of the through-pillar and the interconnection line of the tic-tac-toe unit 6. The tic-tac-toe unit 6 is set at both ends of two through-pillars of equal height. The main signal input and output port located in the central wiring layer is a square plate W1 with a side length of 240um; the TSV part 41 includes an internal metal conductor 411 and an external insulating pad layer 412; during the manufacturing process, a hole is first etched out, and then an insulating layer is deposited by a vapor deposition process (the insulating layer is silicon dioxide with a thickness of 0.5um), and then the insulating layer is filled with metal (the metal is copper with a diameter of 63um). The length L1 of the tic-tac-toe unit 6 in the RDL layer 32 is 144um, the center distance D between the two through-holes in the RDL part 42 is 120um, the through-hole diameter R1 is 48um, the diameter R3 of the TSV part 41 is 64um, and the diameter R2 of the disc-shaped RDL structure of the RDL part 42 located in the RDL layer 32 is 80um.

[0026] In summary, the beneficial effects of this application are as follows: First, the present invention provides a through-silicon via (TSV) tic-tac-toe artificial surface plasmon bandpass filter for three-dimensional integrated circuits, which is constructed as a three-dimensional structure based on TSV technology. Traditional planar structures can only filter within a plane, and three-dimensional integrated circuit designs have significant advantages in terms of integration. Two-dimensional planar structures are limited by space, and the limited area makes it difficult to accommodate more components. This limitation becomes more pronounced as the functions of the integrated circuit increase. Three-dimensional integrated circuits break through the planar limitations and vertically connect different layers of circuits through TSV technology, allowing components to be distributed in three dimensions, greatly increasing the number of integrated components per unit area, effectively improving integration, shortening signal transmission paths, reducing delays and interference, and improving performance.

[0027] Second, the artificial surface plasmon bandpass filter of the present invention adopts a three-dimensional layout to surround the signal path. Compared with the traditional planar structure that can only be arranged on both sides of the conductor, the present invention can further compress the gain of the signal within the passband, thereby having a stronger bandpass characteristic.

[0028] Third, this paper proposes a novel aperiodic SSPP structure, which incorporates eight tic-tac-toe cells within a conventional H-shaped (or comb-shaped) structure. 6 This new structure significantly reduces the cutoff frequency, which can be achieved by flexibly adjusting the parameters of the tic-tac-toe cells. More importantly, this structure not only offers a wide tunable frequency range but also achieves improved impedance matching. The proposed structure is compact, requires no additional components, and exhibits excellent filtering characteristics.

[0029] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A through silicon via tic-tac-toe artificial surface plasmon bandpass filter, characterized in that: include: A dielectric substrate comprising a signal wiring layer (1), a substrate layer (2), and an RDL layer (3); A three-dimensional TSV array comprising an odd number of through-pillars vertically connected to the signal wiring (1) layer and a plurality of well-shaped units (6); The through-pillars are divided into independent through-pillars (4) and through-pillar groups (5), the through-pillar group (5) includes two adjacent through-pillars of equal length, and the independent through-pillars (4) and the through-pillar group (5) are alternately arranged along the direction of the signal wiring layer (1); Each through-pillar comprises a TSV portion (41) of equal length and an RDL portion (42) arranged at both ends of the TSV portion (41); the TSV portion (41) is arranged in the substrate layer (2); the tic-tac-toe-shaped unit (6) is respectively arranged on the RDL portion (42) at both ends of the through-pillar group (5); and the symmetry center of the three-dimensional TSV array is the independent through-pillar (4).

2. The through silicon via tic-tac-toe artificial surface plasmon bandpass filter according to claim 1, characterized in that: The RDL layer (3) comprises a plurality of alternately arranged RDL interconnection layers (31) and RDL dielectric layers (32), wherein the RDL dielectric layer (32) is connected to the substrate layer (2).

3. The through silicon via tic-tac-toe artificial surface plasmon bandpass filter according to claim 1, characterized in that: The substrate layer (2) comprises a stacked substrate (21) and a base substrate (22) symmetrically arranged on both sides of the signal wiring layer (1).

4. The through silicon via tic-tac-toe artificial surface plasmon bandpass filter according to claim 1, characterized in that: The TSV portion (41) includes an internal metal conductor (411) and an external insulating liner layer (412).

5. The through silicon via tic-tac-toe artificial surface plasmon bandpass filter according to claim 1, characterized in that: The signal wiring layer (1) comprises an integrally formed input port (11), an RDL signal channel (13), and an output port (12).

6. The through silicon via tic-tac-toe artificial surface plasmon bandpass filter according to claim 1, characterized in that: The number of the through-pillars is 13, and the number of the tic-tac-toe-shaped units (6) is 8.

7. The through silicon via tic-tac-toe artificial surface plasmon bandpass filter according to claim 2, characterized in that: The RDL interconnection layer (31) and the RDL dielectric layer (32) are both provided with 6 layers.

8. The through silicon via tic-tac-toe artificial surface plasmon bandpass filter according to claim 2, characterized in that: The height difference between the independent through-pillar (4) and the through-pillar group (5) is the sum of the thicknesses of the RDL interconnection layer (31) and the RDL dielectric layer (32).

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