Low-noise high-frame-frequency short-wave infrared imaging system

Abstract

The invention belongs to the technical field of infrared detection, and particularly relates to a low-noise high-frame-frequency short-wave infrared imaging system. The system comprises an optical element, a detector, an analog acquisition circuit, a digital driving circuit and an upper computer, the digital driving circuit sends time sequence signals to the detector and the analog acquisition circuit respectively to enable the detector and the analog acquisition circuit to keep time sequence synchronization, and the optical element collects infrared light of a detected target and sends the infrared light to the upper computer. The infrared light of a detected target is refracted to a focal plane of the detector, the detector converts the infrared light into an analog electric signal based on a time sequence signal, and the analog acquisition circuit processes the analog electric signal based on the time sequence signal and outputs an obtained digital signal to the digital driving circuit. And the digital driving circuit performs format conversion on the digital signal and sends the signal obtained by format conversion to an upper computer for image display. According to the invention, a high-frame-frequency imaging function under the condition of low readout noise is realized.

Description

Technical Field

[0001] The present invention belongs to the field of infrared detection technology, and in particular relates to a low-noise, high-frame-rate short-wave infrared imaging system. Background Art

[0002] InGaAs shortwave infrared detectors, characterized by high detection efficiency and excellent uniformity, are widely used in aerospace, medical, and military applications. Research on detectors and drive methods has become a hot topic in this field. In recent years, extensive research has been conducted both domestically and internationally on InGaAs focal plane detectors. The performance evaluation of an imaging system requires more than just detector performance; it also requires a low-noise drive circuit and efficient control strategies.

[0003] The world's first InGaAs focal plane detector was produced by Sensors Unlimited in the United States. Thanks to strong military support, the field has rapidly developed. Companies in countries such as France, Japan, and Belgium have developed mass-produced versions of these cameras. Shortwave infrared camera development is limited by the production capacity of focal plane detectors. Although China's shortwave infrared camera industry started relatively late, it has developed rapidly in recent years. The 44th Research Institute of the China Electronics Technology Group Corporation has successfully developed a 640×512 InGaAs focal plane detector. Furthermore, the Northern Night Vision Technology Research Institute has developed a 640×512 uncooled shortwave infrared camera module that weighs less than 200g and consumes less than 3W. Regarding core components, the Shanghai Institute of Technical Physics of the Chinese Academy of Sciences has achieved breakthroughs in key technologies for InGaAs epitaxial growth and readout circuit design, resulting in a 640×512 detector with a quantum efficiency exceeding 70% and a response non-uniformity of less than 5%. A research team at Nanjing University has developed a new shortwave infrared sensor based on quantum dots, which is expected to further reduce manufacturing costs and improve performance. In terms of whole machine development, the LD-SW6401715UC model developed by Xi'an Liding Optoelectronics has a 15μm pixel 640×512 area array short-wave infrared product with a low gain of 390e. - , high gain 32e - The SH640 camera developed by Tianying Optoelectronics has achieved a readout noise of 30e at high gain. - The relevant parameters are significantly inferior to those of foreign products.

[0004] Existing InGaAs short-wave infrared imaging systems still have shortcomings in readout noise, quantum efficiency, cooling efficiency, system integration, manufacturing cost, reliability and technical maturity. Summary of the Invention

[0005] In view of this, the present invention aims to provide a low-noise, high-frame-rate short-wave infrared imaging system to address the shortcomings of existing technologies in terms of readout noise, quantum efficiency, cooling efficiency, system integration, manufacturing cost, reliability and technical maturity. In order to improve application flexibility and reduce project production costs, the present invention designs an FPGA-based InGaAs short-wave infrared imaging system, adopts FPA0640P15F-17-T1 series detectors, designs low-noise analog circuits and high-read and write speed digital drive circuits, and adopts TEC cooling technology to achieve high-frame-rate imaging function under low readout noise conditions, which can be applied to scientific-grade imaging.

[0006] To achieve the above object, the technical solution created by the present invention is implemented as follows: A low-noise, high-frame-rate short-wave infrared imaging system includes an optical element, a detector, an analog acquisition circuit, a digital drive circuit, and a host computer. The digital drive circuit sends timing signals to the detector and the analog acquisition circuit, respectively, so that the detector and the analog acquisition circuit maintain timing synchronization. The optical element collects infrared light from the detected target and refracts the infrared light of the detected target onto the focal plane of the detector. The detector converts the infrared light into an analog electrical signal based on the timing signal. The analog acquisition circuit processes the analog electrical signal based on the timing signal and outputs the obtained digital signal to the digital drive circuit. The digital drive circuit converts the format of the digital signal and sends the signal obtained by the format conversion to the host computer for image display.

[0007] Furthermore, the detector uses a 640×512 array InGaAs detector. The timing signal received by the detector is a 6 MHz clock signal, and the 6 MHz clock signal is used to drive the four-channel mode of the detector to output an analog electrical signal.

[0008] Furthermore, the low-noise, high-frame-rate short-wave infrared imaging system further includes a detector drive power supply and a detector bias drive circuit, wherein the detector drive power supply is used to power the detector, and the detector bias drive circuit is used to provide a drive voltage for the detector's photosensitive device and logic gate; The detector drive power supply includes an analog circuit, a first-stage analog power supply, a second-stage analog power supply, a digital circuit, and a first-stage digital power supply. The analog ground of the analog circuit is connected to the digital ground of the digital circuit via a ferrite bead. The first-stage analog power supply is used to provide a base voltage for the analog circuit. The second-stage analog power supply uses a linear regulator to filter out residual ripple and noise in the base voltage and provide a μV-level noise operating voltage for the analog circuit. The analog circuit is used to process timing signals. The first-stage digital power supply is used to provide an operating voltage for the digital circuit, which is used to process digital signals. The detector bias drive circuit includes a reference voltage source module, a precision resistor voltage divider network, a low-noise operational amplifier, and a rail-to-rail operational amplifier isolation buffer module connected in sequence. The reference voltage source module inputs a reference voltage to the precision resistor voltage divider network. The precision resistor voltage divider network adjusts the voltage value of the reference voltage to a target voltage value adapted to the detector to obtain a divided voltage. The divided voltage is input to the low-noise operational amplifier for signal conditioning and amplification, so that the voltage value of the divided voltage is adapted to the target voltage value of the detector's photosensitive element to obtain a conditioned voltage. The conditioned voltage is input to the rail-to-rail operational amplifier isolation buffer module for isolation and power amplification, and the voltage after isolation and power amplification is used to drive the detector's photosensitive element and logic gate.

[0009] Furthermore, the analog acquisition circuit includes a first-stage follower, a differential amplifier, a low-pass filter circuit and an ADC module connected in sequence. The first-stage follower isolates and buffers the analog electrical signal so that the analog electrical signal is transmitted to the differential amplifier without distortion. The differential amplifier converts the analog electrical signal to obtain a differential signal that meets the input range of the ADC module. The low-pass filter circuit filters out the high-frequency noise of the differential signal to obtain a smooth differential signal, and the smoothed differential signal is input to the differential input end of the ADC module for processing to obtain a digital signal.

[0010] Furthermore, the digital drive circuit includes an FPGA, which includes a System_control module, an FPA_command module, an FPA_control module, an AD_control module, a dual FIFO ping-pong buffer module, a Convertor module, a Gen_image module and a state machine. Among them, the System_control module divides the 200MHz external crystal oscillator into four clocks through a PLL. The four clocks include a 6MHz system clock, a 24MHz control clock, a 12MHz ADC clock and an 80MHz image clock. The 6MHz system clock is used to manage the state machine, the 24MHz control clock is used to drive the timing signal of the detector, the 12MHz ADC clock is used to match the sampling frequency of the ADC module, and the 80MHz image clock is used to realize the data transmission and Cameralink output of the detector. The FPA_command module is used to receive control commands and convert the control commands into register configuration data recognized by the detector. The FPA_control module receives the register configuration data and dynamically switches the working mode of the detector so that the detector outputs four-channel analog electrical signals. The module inputs the digital signal output by the analog acquisition circuit into the dual-FIFO ping-pong buffer module for parallel read and write processing. The Convertor module converts the 64-bit data output by the dual-FIFO ping-pong buffer module into a 16-bit pixel stream and inputs the 16-bit pixel stream into the Gen_image module in the conversion order. The Gen_image module integrates all received 16-bit pixel streams into a complete image signal, which is then packaged and sent to the host computer via the CameraLink interface.

[0011] Furthermore, the detector's working modes include an integrate-while-reading mode and an integrate-first-then-reading mode. The integrate-while-reading mode is suitable for scenarios with an integration time of less than or equal to milliseconds, and the integrate-first-then-reading mode is suitable for scenarios with an integration time of greater than or equal to seconds.

[0012] Furthermore, the dual FIFO ping-pong buffer module includes a control logic module, FIFO_odd and FIFO_even. The specific process of using the dual FIFO ping-pong buffer module to implement read and write parallel processing is as follows: A1: Use the rising edge of the field drive signal as the enable signal to force reset the control logic module, FIFO_odd and FIFO_even; A2: In the initial state, set the control signal odd=1 and the control signal even=0, so that the writing priority of FIFO_odd is higher than the writing priority of FIFO_even; A3: When the rising edge of the row drive signal arrives, the image data to be written is written into FIFO_odd, and the write counter starts counting; A4: When the count value of the write counter is the same as the row value of the image to be written, the control signal even=1 and the control signal odd=0 are set to write the image data to be written into FIFO_even, and the data of FIFO_odd is read out to the Gen_image module through the Convertor module; A5: Repeat steps A3-A4, using FIFO_odd and FIFO_even to alternately read and write the current frame image rows until the entire current frame image is read out to the Gen_image module.

[0013] Furthermore, the low-noise, high-frame-rate short-wave infrared imaging system also includes a cooling system, which includes a DSP, a built-in TEC, an external TEC, a first temperature controller, a second temperature controller and a 16-bit ADC, wherein the DSP is connected to the FPGA, the first temperature controller and the built-in TEC are arranged inside the detector, and the second temperature controller and the external TEC are arranged outside the detector.

[0014] Furthermore, the specific method for the refrigeration system to control the temperature of the low-noise, high-frame-rate short-wave infrared imaging system is as follows: B1: The host computer selects the working mode as manual mode or automatic mode. If manual mode is selected, read the target temperature of the detector set by the host computer and execute step B4; otherwise, execute step B2; B2: The 16-bit ADC simultaneously collects the temperature and voltage signals output by the first temperature controller, the temperature and voltage signals output by the second temperature controller, the driving current of the built-in TEC, and the driving current of the external TEC; B3: Based on the acquisition results of step B2, the low-noise, high-frame-rate short-wave infrared imaging system uses a temperature value 40°C lower than the external temperature as the target temperature of the detector; B4: Determine whether the detector target temperature is greater than the ambient temperature. If so, execute step B5; otherwise, disable the built-in TEC and the external TEC and execute step B1. B5: Based on the collected result of step B2, the DSP generates a first PWM drive control signal for the internal TEC and a second PWM drive control signal for controlling the external TEC through the first PID; B6: Convert the first PWM drive control signal and the second PWM drive control signal into a first DC signal and a second DC signal respectively through an H-bridge, and control the temperature of the internal TEC and the external TEC respectively, so that the target temperature of the detector is lower than the ambient temperature; B7: Determine whether the temperature voltage signals outputted by the first temperature controller and the second temperature controller are stable. If so, execute step B8. Otherwise, generate a third PWM drive control signal for the internal TEC and a fourth PWM drive control signal for controlling the external TEC using the second PID controller, and use the third PWM drive control signal and the fourth PWM drive control signal to control the real-time operating current of the internal TEC and the real-time operating current of the external TEC, respectively, and execute step B8. B8: Determine whether the low-noise high-frame-rate short-wave infrared imaging system continues to work. If so, execute step B1; otherwise, power off the low-noise high-frame-rate short-wave infrared imaging system.

[0015] Compared with the prior art, the present invention can achieve the following beneficial effects: (1) The present invention creates the low-noise, high-frame-rate short-wave infrared imaging system. First, the basic architecture of the imaging system is designed. On this basis, a low-noise hardware circuit is designed. In combination with TEC (Thermoelectric Cooling, TEC) refrigeration technology, a sensor drive, efficient image readout and transmission program based on FPGA (Field Programmable Gate Arrays) is designed while ensuring extremely low readout noise and dark current, forming a system prototype. Experimental results show that the imaging system of the present invention can achieve a full-frame image output of up to 116Hz per second, and achieves 364.87e in low-gain, medium-gain, and high-gain modes, respectively. - 、40.66e - 、15.73e - The noise level is low, the linearity is good, it can work stably and produce clear images both indoors and outdoors, meeting the index requirements of scientific-grade detectors.

[0016] (2) The present invention creates the low-noise, high-frame-rate short-wave infrared imaging system and designs a self-developed prototype of a refrigerated short-wave infrared detector. Through the design of low-noise analog and digital circuits, as well as the design of high-performance FPGA drive and closed-loop temperature control algorithm, it ensures that the imaging system can maintain high performance indicators in the test environment, while reducing costs and ensuring excellent performance, meeting project requirements, and has good development prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which constitute part of the present invention, are intended to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are intended to explain the present invention and do not constitute an undue limitation of the present invention. In the accompanying drawings: Figure 1 A schematic diagram of the structure of a low-noise, high-frame-rate short-wave infrared imaging system according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the overall data flow of the low-noise, high-frame-rate short-wave infrared imaging system according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the FPA driving timing according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the output process of using a dual FIFO ping-pong buffer module to alternately receive a row of data according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the dual-loop PID temperature control described in an embodiment of the present invention; Figure 6 The thermal noise distribution diagram under dark field described in the embodiment of the present invention is created; Figure 7 A distribution diagram of the uniformity of light response as described in an embodiment of the present invention; Figure 8 A response curve diagram of the low-noise, high-frame-rate short-wave infrared imaging system according to an embodiment of the present invention; Figure 9 This is the incandescent filament imaging effect diagram described in the embodiment of the present invention; Figure 10 This is an outdoor imaging effect diagram described in the embodiment of the present invention.

[0018] Description of reference numerals: Optical components, detectors, analog acquisition circuits, digital drive circuits and host computers 1. Optical element; 2. Detector; 3. Refrigeration system; 4. Detector drive power supply; 5. Analog acquisition circuit; 6. Digital drive circuit; 7. Host computer; 8. Power supply; 9. DSP; 6-1. FPGA; 6-2. Signal conditioning circuit. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and do not constitute a limitation of the present invention.

[0020] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other.

[0021] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first", "second" and the like are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, features defined as "first", "second" and the like may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0022] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to internal connections between two components. Those skilled in the art can understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0023] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0024] Ground-based large-aperture telescopes require multiple imaging terminals to ensure operational performance. Shortwave cameras are central to their operation, and their imaging directly reflects their performance. Based on the requirements of ground-based large-aperture telescopes for lightweight, low-noise, high-frame-rate output, and highly consistent shortwave imaging systems, this paper describes the overall system architecture. It also introduces the hardware circuit design, starting with low-noise chip selection, and discusses the system's operating mechanism from the driver's perspective. Finally, through system testing, parameter indicators are obtained.

[0025] like Figure 1As shown, the present invention provides a low-noise, high-frame-rate short-wave infrared imaging system, comprising an optical element 1, a detector 2, an analog acquisition circuit 5, a digital drive circuit 6 and a host computer 7, wherein the digital drive circuit 6 sends timing signals to the detector 2 and the analog acquisition circuit 5 respectively, so that the detector 2 and the analog acquisition circuit 5 maintain timing synchronization, the optical element 1 collects infrared light of the detected target and refracts the infrared light of the detected target onto the focal plane of the detector 2, the detector 2 converts the infrared light into an analog electrical signal based on the timing signal, the analog acquisition circuit 5 processes the analog electrical signal based on the timing signal, and outputs the obtained digital signal to the digital drive circuit 6, the digital drive circuit 6 converts the digital signal into a format, and sends the signal obtained by the format conversion to the host computer 7 for image display.

[0026] It should be noted that the specific workflow of the shortwave infrared imaging system is as follows: Optical element 1 primarily refracts infrared light from the target onto the focal plane of detector 2. Detector 2 receives a stable and precise drive voltage from the power supply circuit. Digital drive circuit 6 provides a timing (drive) signal. This signal undergoes internal photoelectric conversion to generate an analog output. This signal is then modulated by the analog circuit and converted to a digital signal. FPGA 6-1 reads this signal and performs format conversion, ultimately displaying the received image through host computer 7.

[0027] In some embodiments, the detector 2 uses a 640×512 array InGaAs detector 2 , the timing signal received by the detector 2 is a 6 MHz clock signal, and the 6 MHz clock signal is used to drive the four-channel mode of the detector 2 to output an analog electrical signal.

[0028] Furthermore, the detector 2 uses a 640×512 array InGaAs detector 2, and uses a 6MHz clock to drive the detector 2's four-channel mode to output analog electrical signals. The detector 2 drive circuit generates the power required by the detector 2. The electronic design mainly consists of two parts: analog circuit and digital circuit. The analog circuit is divided into power supply circuit and signal conditioning circuit 6-2. The overall data flow diagram of the low-noise, high-frame-rate short-wave infrared imaging system is shown below. Figure 2As shown, the power supply circuit primarily provides low-temperature drift and low-noise power to the entire short-wave infrared imaging system, supplying various digital and analog DC voltages to drive the Focal Plane Array (FPA) (detector 2). The analog circuit processes the continuous voltage signal output by detector 2 through filtering, biasing, and differential amplification, converting it into an analog signal suitable for conversion by the Analog-to-Digital Converter Chip (ADC). The digital circuit acquires the digital signals output by the ADC module and, using FPGA6-1 for sequential logic control and parallel processing, converts the four digital image signals into standard CameraLink base mode signals in real time for output. The first temperature sensor integrated within detector 2 outputs on-chip temperature information in the form of a voltage. FPGA6-1 collects the ADC-converted temperature information and the TEC drive current (both internal and external) as closed-loop temperature control input signals. Using a PID algorithm, it generates a PWM waveform that drives the full-bridge circuit to supply control voltages to the FPA's internal TEC and the external TEC, achieving cooling for detector 2 and further reducing its dark current noise.

[0029] In some embodiments, the low-noise, high-frame-rate short-wave infrared imaging system further includes a detector driving power supply 4 and a detector 2 bias driving circuit, wherein the detector driving power supply 4 is used to power the detector 2, and the detector 2 bias driving circuit is used to provide a driving voltage for the photosensitive device and logic gate of the detector 2; The detector drive power supply 4 includes an analog circuit, a first-stage analog power supply, a second-stage analog power supply, a digital circuit, and a first-stage digital power supply. The analog ground of the analog circuit is connected to the digital ground of the digital circuit via a magnetic bead. The first-stage analog power supply is used to provide a base voltage for the analog circuit. The second-stage analog power supply uses a linear regulator to filter out residual ripple and noise in the base voltage and provide a μV-level noise operating voltage for the analog circuit. The analog circuit is used to process timing signals. The first-stage digital power supply is used to provide an operating voltage for the digital circuit, and the digital circuit is used to process digital signals. The bias drive circuit of detector 2 includes a reference voltage source module, a precision resistor voltage divider network, a low-noise operational amplifier and a rail-to-rail operational amplifier isolation buffer module connected in sequence, wherein the reference voltage source module inputs a reference voltage to the precision resistor voltage divider network, the precision resistor voltage divider network adjusts the voltage value of the reference voltage to a target voltage value adapted to detector 2, obtains a divided voltage, inputs the divided voltage to the low-noise operational amplifier for signal conditioning and amplification, adapts the voltage value of the divided voltage to the target voltage value of the photosensitive element of detector 2, obtains a conditioned voltage, inputs the conditioned voltage to the rail-to-rail operational amplifier isolation buffer module for isolation and power amplification, and uses the voltage after isolation and power amplification to drive the photosensitive element and logic gate of detector 2.

[0030] Design of low-noise detector driver power supply 4: The design of detector driver power supply 4 is mainly divided into the system main power supply circuit and the low-noise bias voltage circuit. First, the overall power supply adopts the method of separating "analog ground" and "digital ground". The components of the analog circuit part are placed at one end of the circuit board, and the parts containing the "digital ground" are concentrated at the other end for unified grounding. Finally, the two are connected with a magnetic bead at a node in the circuit, and the detector driver power supply 4 is grounded. The first-level digital circuit is powered by LT1765, which has sufficient output current to drive the core and IO voltage conversion chip of chips such as FPGA6-1. SPX3819M5-3.3 and SPX3819M5-1.8 are used to provide 3.3V and 1.8V voltages for the digital circuit respectively. They have strong load capacity, high efficiency and small space occupation.

[0031] The power supply system for the first-stage analog circuit utilizes the monolithic LT8608 step-down switching regulator. Its quiescent current consumption is only 1.7μA, and its efficiency exceeds 90% with a 12V input and 5V output. It can continuously supply 1.5A of current while keeping output ripple below 10mV. The output voltage can be adjusted by adjusting the resistor value. The LT8608 serves as the system's first-stage analog power supply in this design.

[0032] The second-stage analog power supply uses a linear regulated LT3045 power supply, primarily powering the op amp, reference power supply, and AD converter chip in signal conditioning circuit 6-2. The LT3045 is an ultra-low-noise linear regulated power supply suitable for noise-sensitive circuits. It features a programmable voltage output range and current limit capability, allowing it to be used in parallel to increase load capacity when output current requirements are high. Since both the first-stage and second-stage analog power supplies are adjustable, the first-stage analog power supply is a DC-DC power supply, and its conversion efficiency is less affected by voltage drop. However, the linear regulated circuit of the second-stage analog power supply is significantly affected by the input-output voltage difference. Therefore, the output of the first-stage analog power supply is designed to meet the input voltage of the second-stage analog power supply. The LT8608 is calculated to output 5.6V. The second-stage analog power supply consists of two LT3045s connected in parallel to provide 5V, supplying all amplifiers and the reference power supply.

[0033] Design of a low-noise analog drive circuit: The infrared detector 2 integrates a large number of photosensors and logic gates. Due to package size limitations, the user must design an external voltage drive circuit. When designing the power supply, it's crucial to consider the input accuracy and noise level of the photosensors, as the quality of these voltages directly impacts the final image quality. The analog drive circuit combines a linear regulator, a voltage reference, and an amplifier. The reference uses a low-noise ADR44X series reference power supply to generate the voltage, which is then adjusted to the desired voltage using a precision resistor divider and the low-noise ADA4805 operational amplifier.

[0034] Because infrared detector 2 requires multiple voltage levels, its actual performance is affected by these voltages and may require user adjustment. Each voltage channel uses a rail-to-rail, low-noise AD8616 op amp to provide emitter voltage following isolation and improve load capacity.

[0035] In some embodiments, the analog acquisition circuit 5 includes a first-stage follower, a differential amplifier, a low-pass filter circuit and an ADC module connected in sequence. The first-stage follower isolates and buffers the analog electrical signal so that the analog electrical signal is transmitted to the differential amplifier without distortion. The differential amplifier converts the analog electrical signal to obtain a differential signal that meets the input range of the ADC module. The low-pass filter circuit filters out the high-frequency noise of the differential signal to obtain a smooth differential signal, and inputs the smooth differential signal to the differential input end of the ADC module for processing to obtain a digital signal.

[0036] It should be noted that since the infrared detector 2 adopts the analog readout mode, the four-channel analog signals output by the sensor are finally output to the ADC module. In order to improve the common-mode rejection ratio of the input signal, a differential input method is adopted. At this time, the amplitude and offset of the detector 2 output signal need to be modulated according to the input requirements of the selected ADC module.

[0037] The ADC module uses the LTC2298, featuring 14-bit resolution, a dual-channel sampling rate of 65Msps, and a low-voltage 3V power supply. The analog signal output by detector 2 is a unilateral signal in the megahertz range. To ensure distortion-free signal sampling, the ADA4805 (first-stage follower) rail-to-rail op amp with low input offset voltage, low noise, and a high slew rate is used to provide the first-stage follower. The AD8139 differential amplifier adjusts the signal to fit within the ADC's input range, and a final low-pass filter is applied. For example, assuming that the FPA (detector 2) outputs a 1V-3.3V analog signal, the ADC requires a differential input signal with a Vcm of 1.5V and a Vpp of 1V. Therefore, the signal must first undergo a first-stage follower before being input to the differential amplifier to adjust the signal's offset and gain. Before the differential amplifier input, IN+ represents the original FPA output signal, and IN- represents the original signal's offset of 2.15V, equivalent to a unilateral input signal amplitude of 1.15V. If the Vocm of the differential amplifier is set to the 1.5V offset allowed by the AD, the gain of the differential amplifier needs to be adjusted to 1V / 1.15V=0.87 to make the differential single-ended signal Vpp=1V, which meets the ADC input signal requirement.

[0038] In some embodiments, the digital drive circuit 6 includes an FPGA 6-1, which includes a System_control module, an FPA_command module, an FPA_control module, an AD_control module, a dual FIFO ping-pong buffer module, a Convertor module, a Gen_image module, and a state machine. The System_control module divides a 200 MHz external crystal oscillator into four clocks through a PLL. The four clocks include a 6 MHz system clock, a 24 MHz control clock, a 12 MHz ADC clock, and an 80 MHz image clock. The 6 MHz system clock is used to manage the state machine. The 24 MHz control clock is used to drive the timing signal of the detector 2. The 12 MHz ADC clock is used to match the sampling frequency of the ADC module. The 80 MHz image clock is used to realize data transmission and Cameralink output of the detector 2. The FPA_command module is used to receive control commands and convert the control commands into register configuration data recognized by the detector 2. The FPA_control module receives the register configuration data, dynamically switches the working mode of the detector 2, and enables the detector 2 to output four-channel analog electrical signals. The module inputs the digital signal output by the analog acquisition circuit 5 into the dual FIFO ping-pong buffer module for parallel reading and writing. The Convertor module converts the 64-bit data output by the dual FIFO ping-pong buffer module into a 16-bit pixel stream and inputs the 16-bit pixel stream into the Gen_image module in the conversion order. The Gen_image module integrates all received 16-bit pixel streams into a complete image signal, which is packaged and sent to the host computer 7 via the Cameralink interface. It should be noted that the state machine is used to divide the working stages of detector 2, and cooperate with the counter to realize the timing control of detector 2. Detector 2 is used to configure the working stages of FPA into idle state, configuration and integration start state, mode switching and integration time calculation state, row cycle state and frame end and reset state, thereby realizing the timing control of detector 2, which belongs to the existing technology.

[0039] The system is clocked by a 200MHz external crystal oscillator, which is multiplied by a phase-locked loop to 6MHz, 12MHz, 24MHz, and 80MHz, which are used for the system clock, ADC clock, control clock, and image clock, respectively.

[0040] The System_control module generates a clock signal, and the FPA_command module sends control words to the FPA_control module. Detector 2 outputs an analog electrical signal. The AD_control module delays data sampling by two clock cycles, as required by the ADC. Because the FPA outputs data on both rising and falling edges, the four-channel output method alternates pixel output row by row, with four columns representing half a clock cycle.

[0041] The driving mode of detector 2 is divided into two modes: Integrate Then Read (ITR) and Integrate While Read (IWR). In order to make FPA output image information faster, it is necessary to select the readout timing of IWR, such as Figure 3 shown.

[0042] The "OUT" signals are divided into four groups: 'A', 'B', 'C', and 'D', representing four signal outputs. Each signal is output within a single clock cycle, and two dual-channel ADCs simultaneously output four 14-bit converted values. Note that since the ADC sampling frequency is twice the FPA operating frequency, and to ensure data matching, the 14-bit image data is padded to 16 bits and read out as 64 bits in the module. After passing through the FIFO, the data is converted to 16 bits by the Convertor module, which then outputs the final image signal to the Gen_image module, which then sends it to the DS90CR287 chip. This image data is then converted into a standard CameraLink signal for output to the computer.

[0043] In some embodiments, the working modes of the detector 2 include an integrate-while-reading mode and an integrate-first-then-reading mode, wherein the integrate-while-reading mode is suitable for scenarios with an integration time less than or equal to milliseconds, and the integrate-first-then-reading mode is suitable for scenarios with an integration time greater than or equal to seconds.

[0044] In some embodiments, the timing signals sent by the digital driving circuit to the detector 2 include a field driving signal, a row driving signal, an FPA driving clock signal, and a serial register configuration signal.

[0045] In some embodiments, the dual FIFO ping-pong buffer module includes a control logic module, FIFO_odd, and FIFO_even. The specific process of using the dual FIFO ping-pong buffer module to implement read and write parallel processing is as follows: A1: Use the rising edge of the field drive signal as the enable signal to force reset the control logic module, FIFO_odd and FIFO_even; A2: In the initial state, set the control signal odd=1 and the control signal even=0, so that the writing priority of FIFO_odd is higher than the writing priority of FIFO_even; A3: When the rising edge of the row drive signal arrives, the image data to be written is written into FIFO_odd, and the write counter starts counting; A4: When the count value of the write counter is the same as the row value of the image to be written, the control signal even=1 and the control signal odd=0 are set to write the image data to be written into FIFO_even, and the data of FIFO_odd is read out to the Gen_image module through the Convertor module; A5: Repeat steps A3-A4, using FIFO_odd and FIFO_even to alternately read and write the current frame image rows until the entire current frame image is read out to the Gen_image module.

[0046] It should be noted that detector 2 needs to construct a driving timing with a selection function according to the timing characteristics of detector 2. C is the number of window columns, which is 640; R is the number of window rows, which is 512; and N is the number of simultaneous output channels, which is 4.

[0047] Because there is a precise clock delay before and after each frame of image output, in order to improve program efficiency and achieve precise control of the transmission time of each frame of image, a state machine plus combinational logic is used to output the field drive signal FSYNC and the line drive signal LSYNC that drive detector 2. A frame of image is divided into five states. A counter is used to count the clock cycles between states to determine the state transition conditions. The system adjusts the readout mode to IWR(1) or ITR(0) by switching the read mode (Read_Mode) in state2 (configuration and integration start state). In IWR mode, when Intergrate_Time (integration time) < (2+18+C / N)×(R+2), the count is (54+(2+18+C / N)×(R+2)+144)-Intergrate_Time; otherwise, the count is 54+144. In ITR mode, the count is fixed to 54+141+(2+18+C / N)×(R+2). A sub-loop of 512 rows of data is designed between state3 (row loop state) and state4 (frame end and reset state) to read a complete frame of signal and realize automatic timing jump within the state machine.

[0048] Furthermore, during the high-speed image data acquisition process, storage and reading take a long time. If a full frame of image is stored before being read out, it will occupy a large amount of system resources and reduce system efficiency. To improve acquisition efficiency, a dual-FIFO-based Ping-Pong Buffer system was designed. Its function is to divide the image into odd-even sequences, one for writing and the other for reading, alternating and working in parallel to achieve conflict-free data reading and writing.

[0049] Assume that the FIFO write and read bit widths are both 16 bits, the depth is 1024 bits, and both read and write counts are available. Since the maximum count is 640 rows, the bit width is set to 10, and the read and write driver clocks are both 80MHz. The system is divided into two modules: the control logic module and the dual FIFO module.

[0050] The control logic module alternately activates the odd and even control signals, using a 640-bit threshold, based on the number of pixels per row. The rising edge of the field drive signal, FSYNC_pos, serves as the frame enable signal, giving it the highest priority. This ensures that each frame begins in a forced reset state. The read and write enable signals for the dual FIFOs are the odd and even control signals, and rely on the external frame valid signal, fval, and row valid signal, lval. The operating sequence is that when odd = 1, writing to FIFO_odd begins. As data is written, the write counter wr_count_odd for FIFO_odd increments. When it reaches 640, indicating that a row of data has been read, the even counter switches to 1, and writing to FIFO_even begins. While writing to FIFO_even, data in FIFO_odd is read synchronously. When FIFO_even is full, odd returns to 1, creating a ping-pong effect.

[0051] The signals received by the ping-pong alternation form a whole line signal and are transmitted to the Gen_image module. When the counters of the two 16-bit FIFOs are full of 640, the digital signal output is controlled by the line drive signal lval of Cameralink, and then the output of a frame signal is controlled by the field drive signal fval and the data valid signal dval. Taking the output of a frame of image as an example, the FSYNC signal is set to 1, and the output process of a line of data is as follows: Figure 4 shown.

[0052] In some embodiments, a built-in TEC, an external TEC, a first temperature controller, a second temperature controller and a 16-bit ADC are provided, wherein DSP9 is connected to FPGA6-1, the first temperature controller and the built-in TEC are provided inside the detector 2, and the second temperature controller and the external TEC are provided outside the detector 2.

[0053] The specific method for the refrigeration system 3 to control the temperature of the low-noise, high-frame-rate short-wave infrared imaging system is as follows: B1: The host computer 7 selects the working mode as manual mode or automatic mode. If manual mode is selected, the target temperature of the detector 2 set by the host computer 7 is read and step B4 is executed. Otherwise, step B2 is executed. B2: The 16-bit ADC simultaneously collects the temperature and voltage signals output by the first temperature controller, the temperature and voltage signals output by the second temperature controller, the driving current of the built-in TEC, and the driving current of the external TEC; B3: Based on the acquisition results of step B2, the low-noise, high-frame-rate short-wave infrared imaging system uses a temperature value 40°C lower than the external temperature as the target temperature of detector 2; B4: Determine whether the target temperature of detector 2 is greater than the ambient temperature. If so, execute step B5; otherwise, disable the built-in TEC and the external TEC and execute step B1; B5: Based on the collected result of step B2, DSP9 generates a first PWM drive control signal for the internal TEC and a second PWM drive control signal for controlling the external TEC through the first PID; B6: Convert the first PWM drive control signal and the second PWM drive control signal into a first DC signal and a second DC signal respectively through an H-bridge, and control the temperature of the internal TEC and the external TEC respectively, so that the target temperature of the detector 2 is lower than the ambient temperature; B7: Determine whether the temperature voltage signals outputted by the first temperature controller and the second temperature controller are stable. If so, execute step B8. Otherwise, generate a third PWM drive control signal for the internal TEC and a fourth PWM drive control signal for controlling the external TEC using the second PID controller, and use the third PWM drive control signal and the fourth PWM drive control signal to control the real-time operating current of the internal TEC and the real-time operating current of the external TEC, respectively, and execute step B8. B8: Determine whether the low-noise high-frame-rate short-wave infrared imaging system continues to work. If so, execute step B1; otherwise, power off the low-noise high-frame-rate short-wave infrared imaging system.

[0054] It should be noted that the main factors affecting the imaging effect of the InGaAs detector 2 are the dark current and system readout noise. The most effective way to control the dark current is to cool the FPA detector 2. Introducing TEC technology is the simplest and most efficient solution, suitable for working conditions with limited space, high integration, and low cooling temperature difference requirements.

[0055] FPAs typically integrate a first-stage TEC (internal TEC), but internal cooling alone cannot achieve sufficiently low temperatures to minimize dark current noise. Therefore, this design incorporates a second-stage TEC (external TEC) external to the FPA. This, along with a heat sink and high-flow DC fan, efficiently dissipates heat, achieving a maximum temperature difference of 40°C at room temperature.

[0056] The refrigeration control part uses DSP9 as the MCU to form an independent control system. The temperature voltage signal output by FPA and the current signal when TEC is working are collected through 16-bit ADC. The DSP9 chip generates PWM drive control signal through PID operation, and converts the AC signal into DC TEC voltage drive signal through H bridge to form fully automatic closed-loop control. It communicates with FPGA6-1 through the serial port, and can select automatic mode, manual mode, cooling temperature, etc. through the host computer 7.

[0057] Since a large amount of heat accumulates on the hot surface of the TEC during the cooling process, if the large temperature difference is still maintained and the heat accumulation exceeds the preset heat dissipation capacity of the system, the hot surface of the TEC will drive the cold surface to heat up, thus forming a positive feedback, affecting the normal operation of the system. Therefore, the system adopts a dual-loop PID algorithm. The specific strategy is to set a temperature sensor outside the FPA system and inside the system, and at the same time design a TEC current monitoring circuit. The temperature loop and current loop are used as the control core, and feedforward, limiting and protection mechanisms are added to ensure that the system can automatically and stably work for a long time. In order to facilitate the decomposition of the control steps, the system is divided into a mode layer, a judgment layer, a control layer and an adjustment layer. The detailed workflow diagram is as follows: Figure 5 As shown. In manual mode, the system closes to the preset target temperature after user settings. In automatic mode, the system measures the internal temperature T_target and the external ambient temperature T_env using temperature sensors inside and outside detector 2. The system automatically starts the closed-loop operation with a target temperature 40°C below the external ambient temperature as the starting point, using the temperature loop as the inner loop and the measured TEC operating current as the outer loop. If the current loop continues to operate at full load during automatic or manual mode and the temperature loop fails to close for a long time, the target temperature is adjusted and the temperature difference is appropriately reduced until the current loop closes to the maximum output when stable and the temperature loop closes to the target temperature. If the TEC does not reach its maximum operating current, the target temperature is appropriately lowered until the current loop closes to the rated maximum power and stabilizes, and the temperature loop closes to the target temperature. If the system-set target temperature is higher than the ambient temperature, cooling system 3 will not operate. Next, we tested the readout noise of the prototype in a dark field environment in different modes: low gain (LG), medium gain (MG), and high gain (HG). The specific method was to set the integration time to 0.05ms, the output frame rate to 100Hz, and continuously acquire 100 frames of images. The temporal standard deviation of each pixel in each frame was calculated, and the standard deviations of all pixels were averaged to obtain the final readout noise grayscale value (DN). Finally, the value was converted to the form of electrons: ; Where K is the resolution divided by the full well capacity. Substituting the gain coefficient into the calculation, the final noise test results are shown in Table 1.

[0058] Table 1

[0059] Adjust the integration time to 3μs, low gain mode, measure the output results of the entire target surface under dark field, and analyze the thermal noise distribution of the system under dark field environment, such as Figure 6 The average grayscale response is 669.14. Adjust the integration time to 100μs, turn on the light source, and put the system in a state of light input. Measure the uniformity of the light response of the system in a flat field environment, as shown in the figure below. Figure 7 The average grayscale response is 3097.1. The burrs are bad pixels in the FPA itself. The flat field and dark field distributions show that the overall response uniformity of the prototype is good.

[0060] To measure the linear response of the system, the sensor target surface needs to be directly aligned with the integrating sphere light source hole, the integration time is kept constant at 20μs, and the input light intensity of the integrating sphere is adjusted from dark field to detector 2 saturation for a total of 40 points. 100 images are collected and stored at each sampling point. The data input to the spectrometer in the range of 900-1700nm is used using the trapezoidal integration method to obtain the cumulative radiant brightness of the corresponding band under each light intensity. The DN values ​​of 100 groups of data at each sampling point output by the prototype are averaged to obtain the system response curve as shown below. Figure 8 The curve in the figure has good linearity in the range close to saturation.

[0061] The system was subjected to actual imaging tests, measuring scenes such as indoor incandescent lamp filaments and outdoor scenes with sufficient sunlight. Figure 9-10 As shown in the figure, when the system works at a low exposure time, the background is pure and the imaging target can be effectively distinguished. At a long integration time, the system can clearly distinguish leaves with strong reflectivity to sunlight and buildings with uniform reflectivity in the distance, with excellent results.

[0062] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in the present disclosure can be achieved. This is not limited herein.

[0063] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A low-noise, high-frame-rate short-wave infrared imaging system, characterized by: The device comprises an optical element, a detector, an analog acquisition circuit, a digital drive circuit and a host computer, wherein the digital drive circuit sends timing signals to the detector and the analog acquisition circuit respectively, so that the detector and the analog acquisition circuit maintain timing synchronization; the optical element collects infrared light of the detected target and refracts the infrared light of the detected target onto the focal plane of the detector; the detector converts the infrared light into an analog electrical signal based on the timing signal; the analog acquisition circuit processes the analog electrical signal based on the timing signal and outputs the obtained digital signal to the digital drive circuit; the digital drive circuit converts the format of the digital signal and sends the signal obtained by the format conversion to the host computer for image display.

2. The low-noise, high-frame-rate short-wave infrared imaging system according to claim 1, characterized in that: The detector adopts a 640×512 array InGaAs detector. The timing signal received by the detector is a 6MHz clock signal, and the 6MHz clock signal is used to drive the four-channel mode of the detector to output an analog electrical signal.

3. The low-noise, high-frame-rate short-wave infrared imaging system according to claim 1, characterized in that: The low-noise, high-frame-rate short-wave infrared imaging system further includes a detector drive power supply and a detector bias drive circuit, wherein the detector drive power supply is used to power the detector, and the detector bias drive circuit is used to provide a drive voltage for the detector's photosensitive device and logic gate; The detector drive power supply includes an analog circuit, a first-stage analog power supply, a second-stage analog power supply, a digital circuit, and a first-stage digital power supply. The analog ground of the analog circuit is connected to the digital ground of the digital circuit via a ferrite bead. The first-stage analog power supply is used to provide a base voltage for the analog circuit. The second-stage analog power supply uses a linear regulator to filter out residual ripple and noise in the base voltage and provide a μV-level noise operating voltage for the analog circuit. The analog circuit is used to process timing signals. The first-stage digital power supply is used to provide an operating voltage for the digital circuit, which is used to process digital signals. The detector bias drive circuit includes a reference voltage source module, a precision resistor divider network, a low-noise operational amplifier, and a rail-to-rail operational amplifier isolation buffer module connected in sequence. The reference voltage source module inputs a reference voltage to the precision resistor divider network. The precision resistor divider network adjusts the voltage value of the reference voltage to a target voltage value adapted to the detector to obtain a divided voltage. The divided voltage is input to the low-noise operational amplifier for signal conditioning and amplification, so that the voltage value of the divided voltage is adapted to the target voltage value of the detector's photosensitive element to obtain a conditioned voltage. The conditioned voltage is input to the rail-to-rail operational amplifier isolation buffer module for isolation and power amplification, and the voltage after isolation and power amplification is used to drive the detector's photosensitive element and logic gate.

4. The low-noise, high-frame-rate short-wave infrared imaging system according to claim 1, characterized in that: The analog acquisition circuit includes a first-stage follower, a differential amplifier, a low-pass filter circuit and an ADC module connected in sequence. The first-stage follower isolates and buffers the analog electrical signal so that the analog electrical signal is transmitted to the differential amplifier without distortion. The differential amplifier converts the analog electrical signal to obtain a differential signal that meets the input range of the ADC module. The low-pass filter circuit filters out the high-frequency noise of the differential signal to obtain a smooth differential signal, and inputs the smoothed differential signal into the differential input end of the ADC module for processing to obtain a digital signal.

5. The low-noise, high-frame-rate short-wave infrared imaging system according to claim 4, characterized in that: The digital drive circuit includes an FPGA, which includes a System_control module, an FPA_command module, an FPA_control module, an AD_control module, a dual FIFO ping-pong buffer module, a Convertor module, a Gen_image module, and a state machine. The System_control module divides the 200MHz external crystal oscillator into four clocks through a PLL. The four clocks include a 6MHz system clock, a 24MHz control clock, a 12MHz ADC clock, and an 80MHz image clock. The 6MHz system clock is used to manage the state machine, the 24MHz control clock is used to drive the detector's timing signal, the 12MHz ADC clock is used to match the sampling frequency of the ADC module, and the 80MHz image clock is used to implement the detector's data transmission and Cameralink output. The FPA_command module is used to receive control commands and convert them into register configuration data recognized by the detector. The FPA_control module receives register configuration data and dynamically switches the detector's operating mode, allowing the detector to output four-channel analog electrical signals. The module inputs the digital signal output by the analog acquisition circuit into the dual-FIFO ping-pong buffer module for parallel read and write processing. The Convertor module converts the 64-bit data output by the dual-FIFO ping-pong buffer module into a 16-bit pixel stream and inputs the 16-bit pixel stream into the Gen_image module in the conversion order. The Gen_image module integrates all received 16-bit pixel streams into a complete image signal, which is packaged and sent to the host computer via the CameraLink interface.

6. The low-noise, high-frame-rate short-wave infrared imaging system according to claim 5, characterized in that: The detector's working modes include integrate-while-reading mode and integrate-first-then-reading mode. The integrate-while-reading mode is suitable for scenarios with integration times less than or equal to milliseconds, while the integrate-first-then-reading mode is suitable for scenarios with integration times greater than or equal to seconds.

7. The low-noise, high-frame-rate short-wave infrared imaging system according to claim 5, characterized in that: The dual FIFO ping-pong buffer module includes a control logic module, FIFO_odd, and FIFO_even. The specific process of using the dual FIFO ping-pong buffer module to implement parallel reading and writing is as follows: A1: Use the rising edge of the field drive signal as the enable signal to force reset the control logic module, FIFO_odd and FIFO_even; A2: In the initial state, set the control signal odd=1 and the control signal even=0, so that the writing priority of FIFO_odd is higher than the writing priority of FIFO_even; A3: When the rising edge of the row drive signal arrives, the image data to be written is written into FIFO_odd, and the write counter starts counting; A4: When the count value of the write counter is the same as the row value of the image to be written, the control signal even=1 and the control signal odd=0 are set to write the image data to be written into FIFO_even, and the data of FIFO_odd is read out to the Gen_image module through the Convertor module; A5: Repeat steps A3-A4, using FIFO_odd and FIFO_even to alternately read and write the current frame image rows until the entire current frame image is read out to the Gen_image module.

8. The low-noise, high-frame-rate short-wave infrared imaging system according to claim 1, characterized in that: The low-noise, high-frame-rate short-wave infrared imaging system also includes a cooling system, which includes a DSP, an internal TEC, an external TEC, a first temperature controller, a second temperature controller, and a 16-bit ADC. The DSP is connected to the FPGA, the first temperature controller and the internal TEC are arranged inside the detector, and the second temperature controller and the external TEC are arranged outside the detector.

9. The low-noise, high-frame-rate short-wave infrared imaging system according to claim 8, characterized in that: The specific method for the refrigeration system to control the temperature of the low-noise, high-frame-rate short-wave infrared imaging system is as follows: B1: The host computer selects the working mode as manual mode or automatic mode. If manual mode is selected, read the target temperature of the detector set by the host computer and execute step B4; otherwise, execute step B2; B2: The 16-bit ADC simultaneously collects the temperature and voltage signals output by the first temperature controller, the temperature and voltage signals output by the second temperature controller, the driving current of the built-in TEC, and the driving current of the external TEC; B3: Based on the acquisition results of step B2, the low-noise, high-frame-rate short-wave infrared imaging system uses a temperature value 40°C lower than the external temperature as the target temperature of the detector; B4: Determine whether the detector target temperature is greater than the ambient temperature. If so, execute step B5; otherwise, disable the built-in TEC and the external TEC and execute step B1. B5: Based on the collected result of step B2, the DSP generates a first PWM drive control signal for the internal TEC and a second PWM drive control signal for controlling the external TEC through the first PID; B6: Convert the first PWM drive control signal and the second PWM drive control signal into a first DC signal and a second DC signal respectively through an H-bridge, and control the temperature of the internal TEC and the external TEC respectively, so that the target temperature of the detector is lower than the ambient temperature; B7: Determine whether the temperature voltage signals outputted by the first temperature controller and the second temperature controller are stable. If so, execute step B8. Otherwise, generate a third PWM drive control signal for the internal TEC and a fourth PWM drive control signal for controlling the external TEC using the second PID controller, and use the third PWM drive control signal and the fourth PWM drive control signal to control the real-time operating current of the internal TEC and the real-time operating current of the external TEC, respectively, and execute step B8. B8: Determine whether the low-noise high-frame-rate short-wave infrared imaging system continues to work. If so, execute step B1; otherwise, power off the low-noise high-frame-rate short-wave infrared imaging system.

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