Time gated pixels with HDR capability

Abstract

The invention relates to a time gated pixel with HDR capability. The present technology relates to time-gated imaging enhanced in a manner that provides high dynamic range (HDR) functionality to time-gated pixels. An overflow path is provided for an accumulation node of a time gated pixel such that when the accumulation node is saturated, excess charge flows to a low gain capacitor, thereby generating a readout signal from the accumulation node and the low gain capacitor in order to obtain an HDR signal. A method includes modulating a reset signal and a transfer signal for an image sensor to selectively accumulate a time-gated charge in a photosensitive region of the image sensor, wherein the time-gated charge corresponds to a selected range of distances. The charge is then transferred to a charge storage region, and a saturated portion of the accumulated charge is stored in a capacitor of the image sensor element. An HDR image is constructed from readout of the charge storage region and the capacitor.

Description

Technical Field

[0001] The present disclosure relates to time-gated pixels with HDR capability. Background Art

[0002] Time-gated imaging synchronizes a global shutter image sensor with light pulses sent from a light source, such as an infrared (IR) light source. By synchronizing the image sensor with the light source, time gating can capture light reflected at a range of distances from the imaging device. This can reduce the sensor's sensitivity to reflections from very close objects, such as raindrops or snowflakes.

[0003] This method enables the capture of excellent images in adverse weather conditions such as rain, snow, or fog. It also enables imaging devices to capture images with uniform illumination over distance at night or in other low-light conditions by increasing the intensity of the light pulses as the distance of the captured scene slice increases. Typically, a time-gated image sensor accumulates light from many consecutive light pulses sent from a source to achieve a sufficient signal.

[0004] The intensity or number of light pulses can be adjusted over distance so that reflections on white surfaces do not saturate the sensor. However, in the presence of highly reflective surfaces or emitting sources, such as mirrors, headlights, or IR sources (e.g., lidar sensors or lighting sources) of vehicles along the road, a sensor with a typical dynamic range may become saturated. Furthermore, while the desired intensity or number of light pulses can be increased to see very dark objects, this may result in saturation of light-colored objects. Such issues may produce inappropriate images, which may have adverse effects on devices or systems that rely on images to function, such as vehicles operating in autonomous driving or flight modes. Summary of the Invention

[0005] This technology relates to enhanced time-gated imaging, and more specifically, to a method for providing high dynamic range (HDR) capabilities to time-gated pixels. An overflow path is provided for the accumulation node of a time-gated pixel, so that when the accumulation node is saturated, excess charge flows to a low-gain capacitor. This method provides two readout signals: one from the accumulation node and one from the low-gain capacitor. These signals can be summed or otherwise processed to obtain an HDR signal.

[0006] According to one aspect of the present technology, an image sensor element includes: a photosensitive region configured to generate charge in response to incident light on the image sensor element; a charge storage region configured to store at least a portion of the charge generated by the photosensitive region; a first actuating element electrically coupling the photosensitive region to the charge storage region, the first actuating element configured to effect charge transfer from the photosensitive region to the charge storage region based on a transfer control signal; a floating diffusion region coupled to the first actuating element; and a gain control signal responsive to a gain control signal. A second actuator element having a first node connected to the floating diffusion region; a third actuator element responsive to a reset control signal, the third actuator element having a first node coupled to the second node of the second actuator element and a second node coupled to a voltage supply; a capacitor having a first node connected to the second node of the second actuator element, the capacitor operatively coupled to the first node of the third actuator element; and a readout control circuit configured to read out charge stored in the charge storage region and charge stored by the capacitor. During operation, responsive to the gain control signal, the second actuator element is configured to electrically couple the capacitor to the floating diffusion region to receive a saturated portion of the charge generated by the photosensitive region. Accumulation for imaging is time-gated to correspond to a pulsed light source, thereby achieving a selected distance range detectable by the image sensor element. Based on the time-gated accumulation, a high dynamic range image can be constructed from the readout of the charge stored in the charge storage region and the charge stored by the capacitor.

[0007] In one example, in response to the reset control signal, the third actuation element is configured to: in a first mode, reset the capacitor but not reset the floating diffusion region; and in a second mode, reset at least both the floating diffusion region and the capacitor. Alternatively or additionally, the second actuation element is configured to set a selectable overflow threshold for the amount of the saturated portion of the charge to be received by the capacitor.

[0008] Alternatively or in addition to any of the above, the charge stored by the capacitor may represent a low-gain image signal. In this case, when the readout control circuit performs readout, the reset voltage level is subtracted from the low-gain image signal to serve as a double-sampled readout of the low-gain image signal with uncorrelated noise. Alternatively or in addition to any of the above, in one scenario, the readout control circuit is configured to first read out the charge stored in the charge storage region and then read out the charge stored by the capacitor. In another scenario, the readout control circuit is configured to first read out the charge stored by the capacitor and then read out the charge stored in the charge storage region.

[0009] Alternatively or additionally to any of the above, the image sensor element further includes a fourth actuation element disposed between the floating diffusion region and the charge storage region. In this example, the transfer control signal for the first actuation element is a first transfer control signal, the fourth actuation element is responsive to a second transfer control signal, and a level of the second transfer control signal sets an overflow threshold for an amount of the saturated portion of the charge to be received by the capacitor.

[0010] In this configuration, the capacitor can be a first capacitor and the gain control signal can be a first gain control signal. In this case, the image sensor element further includes: a fifth actuator element responsive to a second gain control signal, the fifth actuator element having a first node connected to the second node of the second actuator element; and a second capacitor having a first node connected to the second node of the fifth actuator element. Furthermore, in this case, the first node of the third actuator element is coupled to the second node of the fifth actuator element and to the first node of the second capacitor, the first gain control signal is used to read out charge from the first capacitor, and the second gain control signal is used to read out charge from the second capacitor. In one example, overflowing charge from the charge storage region can flow into the second capacitor when the first capacitor overflows. In another example, the capacitance of the second capacitor is greater than the capacitance of the first capacitor. In a third example, the high dynamic range image can be constructed from the readout of the charge stored in the charge storage region, the charge stored by the first capacitor, and the charge stored by the second capacitor. Each of these examples can be complementary to one another. Furthermore, the fifth actuation element can be coupled to the gate arrangement and configured to modulate the overflow current in the time domain. In this case, the modulation of the overflow current is performed synchronously with the accumulation gating.

[0011] As an alternative or in addition to any of the above, the image sensor element may be configured to perform a global shutter operation.

[0012] According to another aspect of the present technology, a method includes causing an illumination module of an imaging system to emit one or more light pulses; modulating a reset signal and a transfer signal for an image sensor element to selectively cause accumulation of a time-gated charge in a photosensitive region of the image sensor element in response to incident light on the image sensor element, the time-gated charge corresponding to a selected distance range for the imaging system; transferring the time-gated charge to a charge storage region of the image sensor element; storing a saturated portion of the time-gated charge accumulated by the photosensitive region in a capacitor of the image sensor element; and constructing a high dynamic range image from a readout of any time-gated charge stored in the charge storage region and the saturated portion of the time-gated charge stored by the capacitor, according to the selected distance range.

[0013] In one example, the method further includes selectively setting an overflow threshold for the amount of the saturated portion of the time-gated charge to be received by the capacitor. Alternatively or additionally, the charge stored by the capacitor may represent a low-gain image signal. In this case, when readout by the readout control circuit of the image sensor element, the method may further include subtracting a reset voltage level from the low-gain image signal to serve as a double-sampled readout with uncorrelated noise of the low-gain image signal. Alternatively or additionally, the method may further include executing, by the readout control circuit of the image sensor element, a readout of the charge stored in the charge storage region and then executing a readout of the charge stored by the capacitor.

[0014] According to yet another aspect of the present technique, an imaging system is provided that includes an illumination module configured to emit one or more light pulses and an image sensor element. The image sensor element includes: a photosensitive region configured to generate charge in response to incident light on the image sensor element; a charge storage region configured to store at least a portion of the charge generated by the photosensitive region; a first actuator element electrically coupling the photosensitive region to the charge storage region, the first actuator element configured to effect charge transfer from the photosensitive region to the charge storage region based on a transfer control signal; a floating diffusion region coupled to the first actuator element; a second actuator element responsive to a gain control signal, the second actuator element having a first node connected to the floating diffusion region; a third actuator element responsive to a reset control signal, the third actuator element having a first node coupled to the second node of the second actuator element and a second node coupled to a voltage supply; a capacitor having a first node connected to the second node of the second actuator element, the capacitor being operatively coupled to the first node of the third actuator element; and a readout control circuit configured to read out the charge stored in the charge storage region and the charge stored by the capacitor. During operation, in response to the gain control signal, the second actuating element is configured to electrically couple the capacitor to the floating diffusion region to receive a saturated portion of the charge generated by the photosensitive region. Accumulation for imaging is time-gated to correspond to pulsing by the illumination module, thereby achieving a selected range of distances detectable by the image sensor element. Based on the time-gated accumulation, a high dynamic range image can be constructed from the readout of the charge stored in the charge storage region and the charge stored by the capacitor.

[0015] In one example, the second actuation element is configured to set a selectable overflow threshold for an amount of the saturated portion of the charge to be received by the capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1

[0014] Exemplary imaging systems illustrating aspects of the present technology are described.

[0017] Figure 2 Example image capture scenarios in accordance with aspects of the present technology are illustrated.

[0018] Figure 3 is a block diagram of a pixel array and readout components for an image sensor in accordance with aspects of the present technology.

[0019] Figures 4A to 4B Circuit diagrams according to various aspects of the present technique are illustrated.

[0020] Figure 5A Examples of shutter and accumulation timing according to aspects of the present technology are illustrated.

[0021] Figure 5B An example of readout timing according to aspects of the present technology is illustrated.

[0022] Figure 5C Examples of time-gated operations according to aspects of the present technology are illustrated.

[0023] Figure 6 is another circuit diagram in accordance with aspects of the present technique.

[0024] Figure 7 is yet another circuit diagram according to aspects of the present technology.

[0025] Figure 8A is yet another circuit diagram according to aspects of the present technology.

[0026] Figure 8B is with Figure 8A The operation of the circuit corresponds to the timing diagram.

[0027] Figure 9A is another circuit diagram in accordance with aspects of the present technique.

[0028] Figure 9B is with Figure 9A The operation of the circuit corresponds to the timing diagram.

[0029] Figure 10 is yet another circuit diagram according to aspects of the present technology.

[0030] Figure 11 is yet another circuit diagram according to aspects of the present technology.

[0031] Figure 12 Example methods according to aspects of the present technology are illustrated. DETAILED DESCRIPTION

[0032] As described above, the present technology provides HDR functionality to time-gated pixel imaging methods. Time-gated imaging is a way to obtain images at a certain distance from the camera and its light source. In time-gated imaging, the shutter can be opened only when reflected light is expected to return to the image sensor. For example, if it is desired to detect an object 50-100 meters away, the shutter is timed to open to account for the round-trip time it will take for light to travel that distance from the light source and return to be received by the image sensor. Objects farther (or closer) illuminated by the light source will not be captured by the image because the shutter will be closed when the reflected light will reach the image sensor.

[0033] In a global shutter approach, every pixel in an image sensor is configured to capture an image simultaneously. All pixels can be reset simultaneously. A charge transfer operation is then performed to simultaneously transfer the charge collected in the photodiode of each image pixel to an associated charge storage area. The data from each storage area can then be read out on a per-row basis.

[0034] Time-gated imaging allows the imaging system to create a scene in different "slices" in which images are captured at different distances. The light source can be made brighter for slices farther away, which can be done to achieve equal brightness at different distances. The light level can also be increased as needed depending on environmental conditions (such as in the presence of heavy snow, rain, etc.). The pixels should be configured with a very fast shutter (e.g., modulated to up to 100 MHz or higher).

[0035] Time-gated imaging synchronizes a (global shutter) sensor with light pulses sent from a light source. This light source can be an IR light source. By synchronizing the sensor with the light source, the time-gated sensor only captures light reflected from a certain distance range. This makes the sensor less sensitive to reflections from nearby objects (e.g., nearby raindrops).

[0036] This mechanism allows for the capture of excellent images in adverse weather conditions such as rain, snow, or fog. It also allows the system to capture images that are uniformly illuminated over distance at night or in other low-light conditions by increasing the intensity of the light pulses as the distance of the slice of the scene being captured increases. A time-gated image sensor can accumulate light from several consecutive light pulses sent from a source to achieve a sufficient signal, such as 5-10 consecutive light pulses or more.

[0037] The light pulse intensity and / or number of pulses can be adjusted with distance so that reflections from a white surface or another reflective surface do not saturate the sensor. However, in the presence of highly reflective surfaces or emitting sources (e.g., IR sources on nearby vehicles along the road), sensors with conventional dynamic range may become saturated. In addition, the desired intensity or number of light pulses can be increased to see very dark objects while still saturating light objects. HDR time-gated sensors address this issue, providing a robust imaging solution when operating under challenging conditions. This approach (including various device configurations) is discussed further herein.

[0038] Example Imaging System

[0039] Figure 1 1 is a block diagram 100 of an exemplary imaging system, such as an electronic device that employs sensor circuitry (also referred to as a sensor module) to capture images. Imaging system 100 may include, or be part of, a still or video camera, a webcam, a mobile phone, a laptop or tablet computer, a video surveillance system, a vehicle imaging system, a video gaming system with imaging capabilities, an augmented reality (AR) and / or virtual reality (VR) system, an unmanned aerial vehicle system (such as a drone), a commercial or industrial system, and the like. Camera (or imaging) module 102 is configured to convert incoming / received light into digital image data. Camera module 102 includes one or more image sensors (or sensor modules) 104.

[0040] During the image capture process, light from the scene is focused onto image sensor 104 through one or more corresponding lenses 106. Image sensor 104 may include circuitry for generating analog pixel image signals and circuitry for converting those image signals into corresponding digital image data. The digital image data may be provided to storage and processing circuitry 108.

[0041] Storage and processing circuitry 108 may include, for example, one or more integrated circuits (ICs) such as image processing circuitry, a microprocessor, a storage device such as random access memory (RAM) and / or non-volatile memory (NVM), etc. This circuitry may be implemented using components that are separate from camera module 102 or that form part of camera module 102. When storage and processing circuitry 108 is implemented on a different IC than those that implement camera module 102, the IC with circuitry 108 may be stacked or otherwise packaged together with the IC for camera module 102.

[0042] Image data captured by camera module 102 may be processed and stored using processing circuitry 108 (e.g., using an image processing engine of processing circuitry 108, using an imaging mode selection engine on processing circuitry 108, etc.). The processed image data may be provided to external equipment, such as a computer, a vehicle control system, an external display, or other device, using a wired or wireless communication path (not shown) coupled to processing circuitry 108.

[0043] exist Figure 1 In the example of FIG, camera module 102 includes an illumination module 110 configured to emit light for illuminating objects in an image scene. Image sensor 104 can be configured to capture a reflected version of the emitted light and generate image information for the scene. By way of example only, such image information can include depth or distance information for one or more objects, a depth or distance map of the image scene, an image of the image scene, and the like.

[0044] The lighting module 110 (such as a light emitter controlled by a driver circuit) can emit light having any suitable characteristics. This can include any suitable waveform, peak amplitude or power, periodicity or frequency, light pulses, light with modulated amplitude and modulation frequency, etc. The emitted light can be in the infrared (IR) band and / or the optical band and can be generated by an LED or laser configured to emit one or more light pulses (such as in a light pulse train). The emitted light can strike one or more objects in the image scene and reflect from such objects, thereby returning to the camera module 102 as reflected light. The object 13 can include any suitable fixed or moving object. By way of example only, in a driving scene for a vehicle operating in an autonomous (or manual) driving mode, the objects can include signs, streetlights, a driveway or bike lane, a curb or sidewalk, other road users (e.g., other vehicles, cyclists, or pedestrians), trees or shrubs, etc.

[0045] Reflected light may be received at image sensor 104 (e.g., at one or more active image pixels, at one or more photosensitive elements in an active image pixel, etc.). Driver circuitry and / or control circuitry may control the pixel to generate one or more image frames based on the reflected light, such as by providing a control signal to a transistor or other actuating element (e.g., a switching element) coupled to the pixel. Specifically, based on the control signal received from the driver circuitry and / or control circuitry, the pixel may generate different portions of charge in response to the reflected light (e.g., during an accumulation or exposure time period), may perform one or more readout operations on the generated portions of charge (e.g., during a readout time period), or may perform other operations during other time periods.

[0046] In a configuration in which the lighting module 14 and the sensor module 16 operate in an indirect time-of-flight (TOF) sensing scheme, processing circuitry for a TOF sensor (e.g., coupled to the sensor module 16) can determine (e.g., calculate or look up) TOF information for a scene using a phase difference between the emitted light signal 15 and the reflected light signal 17 (collected by the sensor module 16).

[0047] The processing circuitry in camera module 102 or the processing circuitry in imaging system 100 can control illumination module 110 and know the characteristics of the emitted light signal. The processing circuitry can then control image sensor 104 to generate image signals for one or more image frames that indicate the characteristics of the reflected light signal. The system can process (e.g., compare and correlate) the generated image signals for these image frames to the reflected and emitted light to determine phase differences and / or time-of-flight information.

[0048] Example saturation scene

[0049] Figure 2 An exemplary image sensing scene 200 is illustrated, in which an image sensor is part of a perception system of a vehicle 202. The perception system can be configured to obtain images from one or more fields of view of the vehicle, such as a forward-facing field of view indicated by dashed line 204, or a side-facing field of view indicated by dashed-dotted line 206. Note that in this example, fields of view 204 and 206 overlap. As shown, several objects are present in the surrounding environment near vehicle 202. Those objects include pedestrians 208, a crosswalk 210, a traffic light 212 at the southeast corner of the intersection, westbound vehicles 214, eastbound vehicles 216, trees 218, a traffic light 220 at the northwest corner, and stores 222.

[0050] The image sensors arranged along the vehicle to provide different fields of view can each have an illumination module. The light emitted from the illumination module can be modulated or otherwise controlled so that the reflected light received from the external environment corresponds to an object at a specific distance or within a specific range. As an example, this can be accomplished using a forward-facing image sensor to obtain an image that includes pedestrian 208 (which may be 10-15 meters from the vehicle) and vehicle 214 (which may be 25-40 meters from the vehicle). Similarly, this can be accomplished using a side-facing image sensor to obtain an image of vehicle 216 (which may be 50-60 meters away), traffic light 220 (which may be 60-75 meters away), and store 222 (which may be 80-100 meters from the vehicle).

[0051] The returning light is focused onto the image sensor. As described above, reflections on white or other light-colored surfaces may or may not saturate the sensor. Therefore, crosswalk 210, which may include retroreflective white paint, may adversely affect sensor operation. In addition, headlights, reflectors, or IR emitters from vehicles 214 and / or 216 (e.g., in the case where those vehicles include a lidar sensor or IR illuminator for their onboard perception system) may also produce saturation. This may adversely affect the image sensor of vehicle 202 from capturing images containing pedestrian 208 or the color of traffic lights 212 and / or 220.

[0052] Example pixel array and readout components

[0053] Figure 3 is used for Figure 1 FIG300 is a diagram of an exemplary configuration of a pixel array and readout components of an image sensor 104. Figure 3 As shown, assembly 300 includes a pixel array 302 containing sensor pixels 304 arranged in rows and columns, and control and processing circuitry in module 306. Array 302 may contain, for example, tens, hundreds, or thousands of rows and columns of sensor pixels 304. Module 306 may be coupled to row control circuitry 308 (sometimes referred to as row driver circuitry or pixel driver circuitry) and column control and readout circuitry 310 (sometimes referred to as column readout circuitry or column control circuitry, readout circuitry, or column decoder circuitry). Control module 306 may receive a (row) address from row control circuitry 308 and provide corresponding (row) control signals (such as a reset control signal, an anti-blooming control signal, a row select (or pixel select) control signal, a modulation control signal, a storage control signal, a charge transfer control signal, a readout control signal, a sample-and-hold control signal, and / or a storage control signal) to pixels 304 via a (row) control path 312.

[0054] One or more lines, such as column lines 314, can be coupled to each column of pixels 304 in array 302. Column lines 314 can be used to read out image signals from pixels 304 and to provide bias signals (e.g., bias currents or bias voltages) to pixels 304. Column control and readout circuitry 310 can receive image signals (e.g., analog pixel values ​​generated by pixels 304) via lines 314. This circuitry 310 can include memory circuitry for storing calibration signals (e.g., reset level signals, reference level signals) and / or image signals (e.g., image level signals) read out from array 302, amplifier circuitry or multiplier circuitry, analog-to-digital conversion (ADC) circuitry, bias circuitry, latch circuitry for selectively enabling or disabling portions of circuitry 310 (columns), or other circuitry coupled to one or more pixels in array 302 for operating pixels 304 and for reading out image signals from pixels 304. ADC circuitry in circuitry 310 may convert analog pixel values ​​received from array 302 into corresponding digital pixel values ​​(sometimes referred to as digital image data or digital pixel data). Circuitry 310 may supply digital pixel data for pixels 304 (e.g., in one or more pixel columns) to control / processing module 306.

[0055] Pixel array 302 may also be provided with a filter array having multiple (color) filter elements (each filter element corresponding to a respective pixel) that allows a single image sensor to sample light of different colors or different sets of wavelengths. In general, filter elements of any desired color and / or wavelength (e.g., optical wavelengths or infrared wavelengths) and in any desired pattern may be formed over any desired number of image pixels 304. As an example, for use with (e.g., Figure 1 For time-of-flight sensing of an illumination source (in the illumination module 110 in FIG), the pixel array 302 may be provided with a corresponding filter array that passes light having a color and / or frequency emitted from the illumination source.

[0056] Camera module 102 ( Figure 1) may include one or more arrays 302 of image pixels 304. Image pixels 304 may be formed in a semiconductor substrate using complementary metal oxide semiconductor (CMOS) technology, charge coupled device (CCD) technology, or any other suitable photosensitive device technology. Image pixels 304 may be front side illuminated (FSI) image pixels or back side illuminated (BSI) image pixels. Furthermore, array 302 may include different types of pixels 304, such as active pixels, optically shielded pixels, reference pixels, etc. If desired, the image sensor may include an integrated circuit package or another structure in which multiple integrated circuit substrate layers or chips (e.g., from multiple wafers) are vertically stacked or otherwise arranged relative to each other.

[0057] Example Imaging Circuit

[0058] There are various circuit configurations that can be used to implement high dynamic range functionality using time-gated pixels. The following discussion presents several different circuit configurations, but the invention is not limited to these specific configurations.

[0059] Figure 4A is an exemplary image sensor pixel (e.g., Figure 3 4 . A circuit diagram 400 of a pixel 304 of a camera is shown. The pixel includes a photosensitive area (e.g., a photodiode 402). The photodiode 402 can receive incident light for a period of time (exposure time) and generate an image signal corresponding to the incident light during the exposure time. In some imaging systems, image artifacts may be caused by moving objects, movement or jitter of the image sensor, flickering of the illumination, and / or objects with variable illumination in the image frame. Such artifacts may include, for example, missing portions of objects, edge color artifacts, object distortion, etc. Examples of objects with varying illumination may include light emitting diode (LED) signs (which may flash hundreds of times per second) and LED brake lights or headlights of a vehicle. Further presented below are diagrams illustrating the timing of illumination for the light source and the accumulation of charge accumulation corresponding to a particular distance.

[0060] An image signal generated with a short accumulation time and a short exposure time may miss flicker light (e.g., LED pulsing at a given frequency). However, by spreading the short accumulation time over a longer exposure time, the likelihood of missing signals from flicker light is reduced. The pixel can be configured to reduce artifacts caused by light flicker by spreading the short accumulation time over a longer exposure time. The photodiode (PD) 402 may be coupled to a transistor having a first supply voltage V through a photodiode reset transistor 406 (sometimes referred to as an anti-blooming transistor). dd1When a control signal (eg, a reset photodiode or “reset_pd” signal) is asserted (eg, pulsed high) at the photodiode reset transistor 406, the photodiode 402 may be reset to a first supply voltage V dd1 When the control signal reset_pd is deasserted (eg, pulsed low), the photodiode 402 may begin accumulating charge from incident light.

[0061] After the photodiode is reset, a given accumulation period can begin, and the photodiode 402 can begin generating and storing an image signal. The pixel can include a first transfer transistor 408 and a storage region such as a storage gate (SG) 410. Although shown as a storage gate 410, the storage region can alternatively include a storage diode or a floating diffusion region.

[0062] When a given accumulation period ends, the first transfer transistor 408 can transfer the image signal stored at the photodiode 402 to the storage gate 410 (or another storage element). The time between the start and end of a given accumulation period may be referred to as a first accumulation time period. The transfer transistor 408 may include a source terminal, a drain terminal, a gate terminal, and a channel region. Depending on the configuration, the storage gate or the other storage region 410 may be a doped semiconductor region (e.g., a doped silicon region formed in a silicon substrate by ion implantation, impurity diffusion, or other doping techniques) having charge storage capability (e.g., capacitance). One or more accumulations may be performed during system operation. Time gating involves the operation of the reset transistor 406 (with reset_pd) and the transfer transistor 408 (with Tx1). As described below with respect to Figure 5C As discussed further in the timing diagram of FIG, the accumulation is time-gated, where the accumulation is time-gated according to the desired distance (range) to be detected, and ... Figure 1 The light emitted by module 110) switches transistors 406 and 408 back and forth synchronously.

[0063] Photodiode 402 can be connected to a first terminal (e.g., a source terminal or a drain terminal) of transfer transistor 408. Storage gate 410 can be connected to a second terminal opposite the first terminal of transfer transistor 408. For example, if the first terminal is a source terminal, the second terminal can be a drain terminal, or vice versa. An applied control signal Tx1 can control the flow of charge across the channel of transistor 408 and into storage gate 410. When control signal Tx1 is asserted, the image signal stored in photodiode 402 can pass through the channel region of transistor 408 and into storage gate 410. Control signal Tx1 can then be deasserted, and photodiode 402 can be reset to a supply voltage using control signal reset_pd.

[0064] A second accumulation period may follow the first accumulation period. Photodiode 402 may generate an image signal corresponding to the second accumulation period. The image signal from the second accumulation period may be transferred to storage gate 410 using control signal Tx1. The image signal from the second accumulation period may be accumulated (e.g., summed or added) with the image signal from the first accumulation period. The accumulated image signal stored at storage gate 410 may be said to have an effective accumulation time period. The effective accumulation time period is the sum of the first accumulation time period and the second accumulation time period (corresponding to the time between the start and end of the second accumulation period).

[0065] In general, any number of desired accumulation processes can occur (e.g., transferring image signals from different accumulation periods to storage gate 410 for summation). The effective accumulation period can generally be defined as the sum of all different accumulation time periods during which all corresponding individual image signals are generated. After the desired number of accumulation periods and the accumulation of corresponding image signals at storage gate 410, control signal Tx1 can be deactivated to add the last image signal. By breaking up the effective accumulation period during an image frame into shorter, non-contiguous accumulation periods spanning a longer exposure time (using time gating), flickering lighting and / or objects with varying illumination can be minimized without compromising pixel accumulation time (in other words, while maintaining the desired total accumulation time).

[0066] As shown, the pixel in this configuration includes a second transfer transistor 412. Transfer transistor 412 has a gate terminal controlled by a second transfer control signal Tx2. Transfer control signal Tx2 can be pulsed high to transfer charge from storage gate 410 to node 414 (e.g., a floating diffusion ("fd") region). Node 414 can be a doped semiconductor region (e.g., a region in a silicon substrate doped by ion implantation, impurity diffusion, or other doping processes). This node 414 can serve as another storage region for storing charge during image data acquisition operations and can have a charge storage capacity (capacitance).

[0067] The pixel can include a readout circuit that includes a source follower transistor 416 and a row select transistor 418. Transistor 418 can have a gate controlled by a row select control signal sel. When the control signal sel is asserted, transistor 418 is turned on, and a corresponding output signal (e.g., an output signal whose amplitude is proportional to the amount of charge at the floating diffusion node 414) is passed to a column readout path or bus 420. The pixel can include a floating diffusion reset transistor 422. This transistor 422 can have a gate controlled by a floating diffusion reset control signal reset_fd. Transistor 422 couples the floating diffusion region 414 to a second supply voltage 424 (e.g., Vdd2 ), the second supply voltage can be dd1 When the control signal reset_fd is asserted, transistor 422 is turned on and floating diffusion node 414 is reset to the second supply voltage level.

[0068] like Figure 4A As shown, the pixel includes a gain select transistor 426 and a low gain capacitor 428. Transistor 426 may have a gate terminal controlled by a gain select control signal gain_ctrl. When the control signal gain_ctrl is asserted, transistor 426 is turned on and low gain capacitor 428 is coupled to floating diffusion node 414. Note that turning on reset_fd will only reset capacitor 428, but will not reset floating diffusion node 414. Both the control signals reset_fd and gain_ctrl are asserted to reset floating diffusion node 414 to a supply voltage level (e.g., V dd2 ).

[0069] When the signal on the accumulation node (storage gate 410) saturates during the accumulation time, the signal will overflow through transfer transistor 412 and transistor 426 (gain control) onto low gain capacitor 428. Tx2 sets the overflow barrier. Tx2 does not need to be pulsed high for this. It can be pulsed to an intermediate level, or it can be held at a fixed barrier level. The gain_ctrl signal does not need to be fully on, but it should be held at a level that allows further overflow from floating diffusion node 414 to capacitor 428. This capacitor will then be used to accumulate the overflow current.

[0070] During operation of the pixel, the second transfer transistor 412 can be set with an overflow threshold. The storage gate 410 can be configured to store an accumulated image signal that combines the individual signals within a plurality of different accumulation cycles. When the accumulated image signal at the storage gate 410 exceeds the overflow threshold, charge is able to overflow to the floating diffusion region at the node 414. During any accumulation process performed at the storage gate 410, the transistor 426 will remain on. Note that the transistor 426 may not be fully turned on. When the floating diffusion voltage becomes low enough, the transistor can set another overflow barrier that allows charge to flow from the floating diffusion node 414 to the capacitor. Since the transistor 426 is conductive, the overflow charge will be stored by the low gain capacitor 428, while the charge below the overflow threshold remains in the storage gate 410. As shown, the transistor 416 is coupled to a third supply voltage source 430V dd3 , the third supply voltage source can be connected to V dd1 or V dd2 Same or different.

[0071] During readout, the image signal can be sampled on both low-gain capacitor 428 and storage gate 410. Specifically, the low-gain image signal stored by capacitor 428 can be sampled by the readout circuitry, which includes transistors 416 and 418 and bus 420. At the time of sampling, the floating diffusion can be reset via the reset_fd signal, and the reset voltage level (e.g., V dd2 ). The reset voltage level can be subtracted from the low gain image signal to serve as a double sampling readout with uncorrelated noise of the low gain image signal. Alternatively, an external offset calibrated for the reset voltage level can be used for the low gain image signal. After sampling the reset voltage level, the high gain image signal (at the storage gate 410) can be sampled. Before reading out the high gain image signal, the control signal gain_ctrl can be deactivated. The high gain image signal readout can be a correlated double sampling (CDS) readout. The low gain image signal and the high gain image signal can then be used to construct a high dynamic range image.

[0072] Note that the readout can be performed using an origin mode approach, where each signal readout will have a response starting at the origin. Alternatively, the readout can be performed using a hockey stick mode approach, where the signal from storage gate 410 has an immediate response, but the overflow from capacitor 428 will only have a response if there is overflow.

[0073] Thus, in this configuration, the time-gated sensor includes a photodiode 402 that can be refreshed to a supply voltage via reset_pd or connected to an accumulation node at gate 410. When accumulation is not needed, photodiode 402 can remain reset. With time-gated sensing, accumulation can occur for each light pulse emitted. A small amount of additional charge can be added to the storage gate with each cycle. In this way, multiple light pulses can be accumulated by toggling reset_pd back and forth at transistor 406.

[0074] From the accumulation node (gate 410), there is an overflow path via transistors 412 and 416 to low-gain capacitor 428. The low level of Tx2 is the level that sets the overflow barrier. When the accumulation node is saturated, excess photocharge flows through the barrier of transistor 412 to the floating diffusion region at node 414 and then to capacitor 428. At the end of the accumulation time, the photodiode 402 can remain reset until readout is complete and the next frame can be captured in global shutter operation. In some arrangements, circuitry can be included to implement pipeline accumulation during read operations.

[0075] The capacitance of capacitor 428 can be selected based on the storage capacity of the accumulation node (gate 410). By way of example only, accumulation node 410 may be limited to handling approximately 10,000-20,000 electrons (assuming approximately 1.6 microvolts associated with each electron). In this case, capacitor 428 may be selected to handle approximately 1,000,000 electrons.

[0076] Note that even when no light enters the sensor, dark current (leakage current) can flow through certain components of the circuit. For example, photodiode 402, storage gate 410, and capacitor 428 can each have a corresponding dark current. While typically very small, dark current increases as temperature rises.

[0077] Figure 4B Illustrated Figure 4A An alternative configuration 450 to the illustrated configuration. Here, the gain control transistor and storage capacitor are arranged in parallel with the floating diffusion reset transistor 452. Figure 4A , the pixel includes a gain select transistor 454 and a low gain capacitor 456. Transistor 454 may have a gate terminal controlled by a gain select control signal gain_ctrl. When the control signal gain_ctrl is asserted, transistor 454 is turned on and low gain capacitor 456 is coupled to the floating diffusion region. Note that turning on reset_fd will only reset the floating diffusion region (node ​​414). Resetting the capacitor involves turning on both reset_fd and gain_ctrl. Therefore, Figure 4B The circuit is based on Figure 4A Furthermore, corresponding parallel circuit configurations can be employed with any of the other examples discussed with respect to subsequent figures. All such corresponding configurations are embodiments of the present technology.

[0078] Figure 5A Illustrate the shutter and accumulation timing (“T int During the accumulation time, the gating operations provided by the reset_pd signal and the Tx1 signal are complementary. During the accumulation time, there may be many cycles of reset_pd / Tx1, in particular multiple cycles, such as 2, 3, 5, 10 or more cycles.

[0079] Figure 5BAn example 510 of a readout timing applied row by row (rolling readout) is illustrated. This example timing results in an origin mode readout where the high gain contains the storage gate charge (at gate 410) and the low gain read contains all the charge stored on the storage gate (gate 410) plus the overflow capacitor (capacitor 428). As described above, the low level signal Tx2 is the level that sets the overflow barrier. After readout, the high gain signal and the low gain signal are combined by the imaging system to generate an HDR signal. Figure 5B In the MCG, HCG means high conversion gain, LCG means low conversion gain, SH means sample hold, SHR means sample hold reset, and SHS means sample hold signal. Figure 9B ) means medium conversion gain.

[0080] In origin mode readout, all charge from the photodiode, floating diffusion node, and overflow capacitor is in the LCG (low gain) read. Therefore, for the correlated double sampling HCG read from the photodiode that occurs first, the floating diffusion node is not actually reset before readout. Instead, the floating diffusion node is connected to a capacitor so that the charge is redistributed between the floating diffusion node and the capacitor. In the absence of overflow, the reset level will be almost unaffected by this, and the CDS read will operate as expected. Note that the exact reset level is not critical, as it is read and subtracted from the signal level by the CDS operation. When there is overflow, the high gain read will not be used for the HDR signal. Instead, a gain version of the low gain signal will be used.

[0081] Figure 5C 5 is a timing diagram 520 that provides an example of time-gated operation according to various aspects of the present technology. In this example, a light source (e.g., an LED or a laser) emits a train of light pulses, such as two or more pulses. The light pulses can each be reflected from an object (or multiple objects) in the environment of the imaging system. Depending on the distance at which the reflection occurs, there will be a delay between the emitted pulse and the return pulse. Therefore, the delay indicates the distance to the object. By modulating the reset_pd signal and the Tx1 signal associated with transistors 406 and 408, the time of pixel accumulation can be controlled. When reset pd is in effect, there is no accumulation. When Tx1 is in effect, there is accumulation (corresponding to gate open). Only the reflected light pulses that return when Tx1 is in effect will be accumulated, and therefore only pulses reflected within a certain distance range will be accumulated. Many pulses can be emitted (and accumulated) within a frame (image).

[0082] For example, this method can be used to reject light reflected from very close objects, such as snowflakes (or raindrops or dust particles) right in front of a car or another vehicle. In conventional methods, reflections due to nearby snowflakes (or raindrops or dust particles) can quickly saturate the image sensor and make it difficult or impossible to see weaker reflections from more distant objects (such as stop signs, other vehicles, pedestrians, etc.). By rejecting light from nearby reflections through time gating, signals from farther away become visible. In adverse weather scenarios, this can effectively allow the image sensor to see through snow, heavy rain, fog, etc.

[0083] Another example involves collecting signals from returning light pulses at different distances with different optical powers / intensities (or varying numbers of pulses). For example, signals collected from a nearby range window (such as 2-5 meters) can have more optical power than signals collected from farther away (such as 25-50 meters). Since the returning light pulses reflected from farther away will be weaker (have lower illumination), this allows the system to balance illumination across different distances / ranges. This can be accomplished by varying the intensity of the emitted light pulses for the corresponding distances. In this way, objects up to a certain maximum distance will appear equally well illuminated (having substantially similar illumination levels).

[0084] Figure 6 An alternative circuit configuration 600 is illustrated. This configuration is similar to Figure 4A However, the storage gate and the second transfer transistor are omitted. Specifically, the pixel includes a photosensitive region (e.g., photodiode 602). As shown, the photodiode 602 is coupled to a first supply voltage V through a photodiode reset transistor 606 (sometimes referred to as an anti-blooming transistor). dd1 The voltage source 604. Figure 4A Similarly, when a control signal (eg, a reset photodiode or “reset_pd” signal) is asserted (eg, pulsed high) at the photodiode reset transistor 606, the photodiode 602 may be reset to the first supply voltage V dd1 When the control signal reset_pd is deasserted (eg, pulsed low), the photodiode 602 may begin accumulating charge from incident light.

[0085] Here, photodiode 602 can also be connected to a first terminal (e.g., source terminal or drain terminal) of transfer transistor 608. The second terminal of transfer transistor 608 is directly connected to node 610, which serves as a floating diffusion region. In this case, the applied control signal Tx can control the flow of charge across the channel of transistor 608 and into the floating diffusion region of node 610. When control signal Tx is asserted, the image signal stored in photodiode 602 can pass through the channel region of transistor 608 and into the floating diffusion region. Control signal Tx can then be deasserted, and photodiode 602 can be reset to the supply voltage using control signal reset_pd.

[0086] In general, any number of desired accumulation processes may occur (e.g., transferring image signals from different accumulation periods to the floating diffusion region for summing). The effective accumulation period may generally be defined as the sum of all different accumulation time periods during which all corresponding individual image signals are generated. After the desired number of accumulation periods and accumulation of corresponding image signals at the floating diffusion region, the control signal Tx may be deactivated to add the last image signal. Figure 4A By breaking up the active accumulation period during an image frame into shorter, non-contiguous accumulation periods spanning a longer exposure time, as with the circuitry of FIG. 1 , image artifacts caused by moving objects, flickering lighting, and / or objects with varying illumination can be minimized without compromising pixel accumulation time (in other words, while maintaining a desired total accumulation time).

[0087] The floating diffusion region's node 610 may be a doped semiconductor region (e.g., a region doped in a silicon substrate by ion implantation, impurity diffusion, or another doping process). This node 610 in this circuit may serve as a primary storage region for storing charge during image data acquisition operations and may have a charge storage capacity (capacitance).

[0088] The pixel may include a readout circuit comprising a source follower transistor 612 and a row select transistor 614. Transistor 614 may have a gate controlled by a row select control signal sel. When the control signal sel is asserted, as described above with respect to Figure 4A As discussed above with respect to transistor 418, transistor 614 is turned on and a corresponding output signal (e.g., an output signal whose amplitude is proportional to the amount of charge at the floating diffusion region of node 610) is passed to a column readout path or bus 616. As shown, transistor 612 is coupled to a third supply voltage source 624V. dd3 , the third supply voltage source can be connected to V dd1 or V dd2 Same or different.

[0089] The pixel may include a floating diffusion reset transistor 618. This transistor 618 may have a gate controlled by a floating diffusion reset control signal reset_fd. Transistor 618 couples the floating diffusion node 610 to a second supply voltage 620 (eg, V dd2 ), the second supply voltage can be dd1 When control signal reset_fd is asserted, transistor 618 is turned on, which resets capacitor 624. Then, when gain_ctrl is asserted and reset_fd remains asserted, floating diffusion node 610 is reset to the second supply voltage level.

[0090] like Figure 6 As shown, it is equivalent to Figure 4A , the pixel includes a gain select transistor 622 and a low gain capacitor 624. Transistor 622 may have a gate terminal controlled by a gain select control signal gain_ctrl. When the control signal gain_ctrl is asserted, transistor 622 is turned on and low gain capacitor 624 is coupled to the floating diffusion region at node 610. Both control signals reset_fd and gain_ctrl may be asserted to reset the floating diffusion node to a supply voltage level (e.g., V dd2 ).

[0091] Transistor 622 sets the overflow barrier during the accumulation time. This transistor turns on only when the voltage on the floating diffusion becomes low enough. Since transistor 622 is conductive, the overflow charge will be stored by low-gain capacitor 624, while the charge below the overflow threshold remains in the floating diffusion region at node 610.

[0092] During readout, the image signal on the low gain capacitor 624 and the floating diffusion region of node 610 is sampled. The low gain image signal and the high gain image signal can then be used to construct a high dynamic range image. Specifically, in this example configuration, the origin mode readout sequence follows the last Tx pulse, where Tx, gain_ctrl, and reset_fd are all disconnected. The process reads the HCG (S) signal, which is accumulated on the floating diffusion. Then, gain_ctrl is asserted and deasserted. This may not give a true reset value to the floating diffusion, but rather a strongly attenuated version of S, which is sufficient. The HCG reset (R) signal is then read, followed by gain_ctrl being asserted. Then, the LCG S signal is read. Note that no charge has been lost yet, so this is an origin mode S read. Then, reset_fd is asserted and deasserted, followed by a read of the LCG R signal. Note that during Figure 6 In the configuration of Figure 4AThe configuration is more susceptible to noise. This can be attributed to noise in the high gain signal of the floating diffusion region at node 610 and occurs from reset noise. It should also be noted that the last sample LCG R can be replaced by an external offset calibration.

[0093] Figure 7 Illustrated Figure 4A An alternative circuit configuration 700 of the circuit of FIG. 1 is provided, which can further extend the dynamic range without degrading the signal-to-noise ratio (SNR). As shown in the figure, a pair of low-gain capacitors are used in this configuration. For ease of representation, in addition to the gain control transistor and capacitor, the same circuit configuration as in FIG. Figure 4A The same reference numerals are used in the drawings.

[0094] In this configuration, circuit 700 includes a first gain control transistor 702 configured to apply a first gain control signal gain_ctrl1 for a first capacitor 704 , and a second gain control transistor 706 configured to apply a second gain control signal gain_ctrl2 for a second capacitor 708 .

[0095] Specifically, if Figure 7 As shown, transistor 702 can have a gate terminal controlled by a first gain selection control signal, gain_ctrl1. When the control signal, gain_ctrl1, is asserted, transistor 702 is turned on, and a low gain capacitor 704 is coupled to the floating diffusion node 414. Similarly, transistor 706 can have a gate terminal controlled by a second gain selection control signal, gain_ctrl2. When the control signal, gain_ctrl2, is asserted, transistor 706 is turned on, and a low gain capacitor 708 is coupled to the floating diffusion node 414. The control signals, reset_fd, gain_ctrl1, and gain_ctrl2, can be asserted to reset the floating diffusion node 414 to a supply voltage level (e.g., V dd2 ). Figure 7 A double overflow in a series configuration is shown. It is also possible to have a double overflow in a parallel configuration where both gain_ctrl1 and gain_ctrl2 are connected to floating diffusion node 414. The order in which the overflow first reaches, for example, capacitor 704 and then only reaches capacitor 708 in this case results from having two different overflow barriers in gain_ctrl1 and gain_ctrl2, for example, by applying different control voltages or by differences in the layout or process of the two transistors.

[0096] During operation of the pixel, the second transfer transistor 412 can be configured with an overflow threshold. The storage gate 410 can be configured to store an accumulated image signal that combines individual signals from multiple different accumulation periods. When the accumulated image signal at the storage gate 410 exceeds the overflow threshold, charge can overflow into the floating diffusion region at node 414. During any accumulation process performed at the storage gate 410, transistor 702 will remain on. For example, transistor 702 can remain on during accumulation, but typically it will set an additional overflow barrier. Transistor 706 sets the additional overflow barrier, otherwise 708 and 704 would have the same signal. The overflow charge will be stored by low-gain capacitors 704 and / or 708, while the charge below the overflow threshold will remain in the storage gate 410.

[0097] Figure 7 A dual overflow configuration is shown in which the capacitance of the first capacitor and the second capacitor can be selected to obtain an enhanced SNR. When the voltage on capacitor 704 drops too far, the second capacitor 708 receives the overflow current. As the capacitance becomes larger, the gain becomes lower. Therefore, for the same signal, the noise will become worse with a larger capacitor. However, the circuit can use a smaller capacitor to reduce noise. As an example, the capacitance of capacitor 708 can be significantly higher than the capacitance of capacitor 704 (e.g., one or more orders of magnitude higher). By way of example only, capacitor 704 can be approximately 30fF, while capacitor 708 can be approximately 1pF, and floating diffusion 414 can be approximately 1fF.

[0098] During readout, the image signal on each of capacitors 704 and 708 and storage gate 410 is sampled. Thus, three signals are read out and then added together. This can involve obtaining the corresponding signals before adding them together. For example, the three signals can each be amplified so that their total conversion gain is the same, e.g., each incoming electron has the same number of bits. In one example, the image signal stored by capacitor 704 can first be sampled by the readout circuit, which includes transistors 416 and 418 and bus 420. Then, the image signal stored by capacitor 708 can be sampled by the readout circuit. This can be done so that no charge is lost. In other examples, the sampling order can be reversed or performed simultaneously.

[0099] When sampling from both capacitors, the floating diffusion 414 may be reset via the reset_fd signal, and the reset voltage level may be sampled (eg, V dd2 ). For a double sample readout with uncorrelated noise of a low gain image signal, the reset voltage level can be subtracted from the image signal for capacitors 704 and / or 708. Alternatively, an external offset calibrated for the reset voltage level can be used for the low gain image signal.

[0100] After sampling the reset voltage level, the high-gain image signal (at storage gate 410) can be sampled. Before reading out the high-gain image signal, control signals gain_ctrl1 and / or gain_ctrl2 can be deactivated. The high-gain image signal readout can be a correlated double sampling readout. The low-gain image signal and the high-gain image signal can then be used to construct a high dynamic range image.

[0101] Note that the readout can be performed using an origin mode approach, where each signal readout will have a response starting at the origin. Alternatively, the readout can be performed using a hockey stick mode approach, where the signal from storage gate 410 has an immediate response, but the overflow from capacitors 704 and 708 will only have a response if there is overflow.

[0102] Figure 8A Another circuit configuration 800 is illustrated in which the dual overflow approach can be extended with a coupled gate arrangement configured to modulate the overflow current in the time domain. In this configuration, most of the current can be routed to the power supply (e.g., V dd2 and / or V dd3 ), only a small portion of the current is stored on the second capacitor. This allows the capacitance of the second capacitor to be reduced, or otherwise further extend the dynamic range while maintaining the same capacitance.

[0103] As shown, the left side of the circuit configuration 800 is connected to Figure 4A On the right side, starting from the floating diffusion region at node 414, the circuit has additional features to provide dual conversion gain characteristics and overflow modulation characteristics. Figure 4A When the accumulated image signal at storage gate 410 exceeds the overflow threshold, charge can overflow into the floating diffusion region at node 414. The overflowing charge will be stored by the dual overflow capacitor as discussed below, while the charge below the overflow threshold remains in storage gate 410. As shown, transistor 416 is coupled to a third supply voltage source 430V. dd3 , the third supply voltage source can be connected to V dd1 or V dd2 Same or different. Similar to Figure 4A As discussed in connection with readout in the preceding text, transistor 418 may have a gate controlled by a row select control signal sel. When the control signal sel is asserted, transistor 418 is turned on, and a corresponding output signal (e.g., an output signal whose amplitude is proportional to the amount of charge at floating diffusion node 414) is passed to a column readout path or bus 420.

[0104] In the right side of this configuration, circuit 800 includes a transistor 802 configured to apply a dual conversion gain (DCG) signal, and a first gain control transistor 804 configured to apply a gain control signal, gain_ctrl, for a first capacitor 806. The DCG signal is used to reduce the conversion gain of diffusion node 414 by adding a small capacitance to the diffusion node. In this case, the gate capacitance of transistor 802 is the added capacitance. Alternatively, the device corresponding to transistor 802 can be configured as a switch to connect floating diffusion node 414 to the additional capacitor.

[0105] This configuration has a coupled gate arrangement 808 as shown by the dashed area, which includes a transistor 810 configured to apply the CG_barrier signal, a transistor 812 configured to apply the CG_integrate signal, and a transistor 814 configured to apply the CG_reset signal. Transistor 812 is coupled to a second capacitor 816, while transistor 814 is coupled to a power supply (here, V dd2 , 424). The purpose of the coupled gate arrangement in 808 is to modulate the overflow current in the time domain. A small portion of the charge is accumulated, and most of the charge goes to the voltage supply. The CG_barrier device (transistor 810) sets an overflow barrier, and when the voltage on 806 drops low enough, current will start to flow through the overflow barrier. Where the overflow current flows in response to the CG_barrier signal depends on the CG_integrate signal and the CG_reset signal. The control signals of the CG_integrate device and the CG_reset device are complementary because only one device is turned on at a time. Most of the current will flow to the power supply, so CG_reset will have a large duty cycle, while CG_integrate has a small duty cycle. In order to reset capacitor 806 or floating diffusion node 414, the transistors for both CG_reset and CG_barrier need to be fully turned on. For the floating diffusion node 414, the transistor for gain_ctrl also needs to be fully turned on. In order to reset capacitor 816, the transistors for both CG_reset and CG_integrate need to be fully turned on. Additionally, the transistor used for the CG_barrier may need to be fully turned on.

[0106] Figure 8B An example timing diagram 850 illustrates this operation of circuit 800. Note that reset_pd and Tx1 are not explicitly shown in this figure; however, they are modulated during the accumulation time, as shown in FIG. Figure 5CSince both reset_pd / Tx1 and CG_reset / CG_integrate are modulated, the relationship between the two modulations is important. As an example, CG_integrate may accumulate the overflow signal during only 1 cycle (or more or less) out of 10 cycles, where Tx1 is accumulating the PD signal on the storage gate.

[0107] During operation of the pixel, the second transfer transistor 412 can be provided with an overflow threshold. The storage gate 410 can be configured to store an accumulated image signal that is a combination of individual signals from a plurality of different accumulation periods. When the accumulated image signal at the storage gate 410 exceeds the overflow threshold, charge can overflow to the floating diffusion region at the node 414. The overflowing charge will be stored by the low gain capacitors 806 and / or 816, while the charge below the overflow threshold will remain in the storage gate 410. In this configuration, most of the current flowing through the first capacitor 806 can be routed to a power supply (e.g., V dd2 ), only a small portion of the current is stored on the second capacitor 816. This allows the capacitance of the second capacitor 816 to be reduced, or otherwise further extend the dynamic range, while maintaining the same capacitance. Specifically, this configuration can accumulate only a portion (e.g., approximately 10%, or more or less) of the overflow current on the second capacitor 816, while draining the unwanted current to the power supply.

[0108] During readout, the image signal is sampled on each of capacitors 806 and 816 and storage gate 410. Figure 7 As with the configuration of FIG4 , three signals are read out, appropriately acquired, and then added together. In one example, the image signal stored by capacitor 806 can first be sampled by the readout circuit, which includes transistors 416 and 418 and bus 420. Then, the image signal stored by capacitor 816 can be sampled by the readout circuit. This can be done without charge loss.

[0109] When sampling from both capacitors, the floating diffusion 414 may be reset via the reset_fd signal, and the reset voltage level may be sampled (eg, V dd3 or V dd2 For a double sample readout with uncorrelated noise of a low gain image signal, the reset voltage level can be subtracted from the image signal for capacitors 806 and / or 816. Alternatively, an external offset calibrated for the reset voltage level can be used for the low gain image signal.

[0110] After sampling the reset voltage level, the high-gain image signal (at storage gate 410) can be sampled. Before reading out the high-gain image signal, the control signal gain_ctrl can be deactivated. The high-gain image signal readout can be a correlated double sampling readout. The low-gain image signal and the high-gain image signal can then be used to construct a high dynamic range image.

[0111] As discussed above, readout can be performed using an origin mode approach, where each signal readout will have a response starting at the origin. This will occur between reads from 410 to 806. Reads from 816 will always be performed in hockey stick mode. Alternatively, readout can be performed using a hockey stick mode approach, where the signal from storage gate 410 has an immediate response, but overflows from capacitors 806 and 816 will only have a response if there is overflow.

[0112] Figure 9A Another circuit configuration 900 is illustrated in which the overflow current can also be modulated directly at the first overflow from the floating diffusion node 916. In this case, the modulation of the overflow current is synchronized with the gating of the accumulation itself. A key benefit of this configuration is that the system can decide whether the charge goes to the source, the first capacitor, or the second capacitor. As a result, the image sensor can store most of the charge on one capacitor and only a small portion of the charge on the other capacitor (e.g., 10%-20% or less of the charge on the other capacitor).

[0113] As shown, the left side of the circuit configuration 900 is similar to Figure 4A , up to and including storage gate 410. On the right, between storage gate 410 and node 414, there is transistor 902 that provides the Tx2 signal.

[0114] In this configuration, there is a coupled gate set 904, which includes transistor 902 and transistors 906, 908 and 910. Transistor 906 is configured to apply a floating diffusion signal (Tx_fd). Transistor 908 is configured to apply a first modulation signal (Tx_Clg1) for a first capacitor 912 (Clg1), while transistor 910 is configured to apply a second modulation signal (Tx_Clg2) for a second capacitor 914 (Clg2). Tx_Clg1 and Tx_Clg2 are modulation signals that determine where the overflow signal is accumulated during the accumulation time. Tx_fd can be selected during the accumulation time to drain the overflow current to the power supply. Tx_fd is also used for high-gain CDS readout of the signal on the storage gate 410. In order to transfer from the storage gate 410 to the floating diffusion node 416, both Tx2 and Tx_fd need to be turned on. Thus, in this configuration, one capacitor may be saturated (eg, “Clg1” or capacitor 912 ), but the other capacitor will not be saturated (eg, “Clg2” or capacitor 914 ). Figure 9B A timing diagram 950 showing shutter operation, accumulation, and readout according to this configuration is illustrated.

[0115] Figure 10 Yet another circuit configuration 1000 is illustrated in which a pixel can support pipelined global shutter operation (accumulation while performing a read operation) and / or subtraction of R (reset) and S (set) signals in the pixel for correlated double sampling operation.

[0116] As shown, coupled to the floating diffusion region at node 414 is transistor 1002, which is configured to apply a signal (SF1). Transistor 1002 is also coupled to a source (e.g., V dd3 , 430) and a transistor 1004 configured to apply a sampling signal (sample). The transistor 1004 is coupled to a storage circuit 1006.

[0117] The storage circuit 1006 includes a set of capacitors 1008 A 、1008 B ...1008 N , each of these capacitors is configured to store a voltage corresponding to a different image frame. Figure 10 In the example of FIG. 1 , storage circuit 1006 is shown as having four such capacitors, but more or fewer capacitors may be used, each of which is configured to store any corresponding voltage associated with one or more image frames.

[0118] As shown, each capacitor 1008 has a voltage terminal V coupled to it. memThis voltage terminal can supply any suitable fixed voltage or variable voltage signal. Each capacitor 1008 is coupled to a corresponding transistor 1010 (e.g., 1010) that selectively provides access to the storage terminal of the corresponding capacitor. A 、1010 B ...1010 N ). For example, transistor 1010 A Can be activated to access capacitor 1008 A storage terminals, etc.

[0119] As shown, storage circuit 1006 includes transistor 1012, which couples the output of transistor 1004 to one of the corresponding capacitor access transistors 1010. A control signal can be used to selectively activate transistor 1010 to store the output signal from transistor 1004 on the corresponding storage capacitor 1008. Storage circuit 1006 is coupled to row select transistor 418 and readout line 420 via transistor 1014, which is configured to apply signal (SF2).

[0120] SF1 is used to separate the different stages of readout (such as Figure 5B The FD voltage in (in) is written onto capacitor 1008. Transistor 1012 has two operating modes. One operating mode is as a bias current source for SF1 (transistor 1002). In this case, when one of the 1010 sampling transistors is turned on, transistor 1002 settles to the correct value and that value is sampled during the sample / hold by turning off transistor 1010. In the other operating mode, transistor 1012 acts as a precharge ("pc") switch to precharge capacitor 1008 to a low voltage (V pc ). SF1 transistor 1002 can only pull the capacitor to a higher voltage. Eventually, as the voltage increases, SF becomes slower until it switches itself (at about V GS =V t 1008 and stay there until readout. For the readout sampling, transistor 1004 is turned off, and transistor 1012 is used to precharge the gate of one of the capacitors 1008 to V before connecting it to the SF2 transistor 1014. pc The voltage on each capacitor 1008 is read out via 1014 , 418 , and 420 .

[0121] Figure 11 Illustrated Figure 10A variation of the circuit 1100 incorporating an in-pixel CDS and a sample-and-hold circuit for storing a signal for a global shutter is shown. Figure 10 Everything to the left of node 414. As shown, transistor 1004 is configured to apply a first sampling signal (sample1) and is indirectly coupled to storage circuit 1006 via a correlated double sampling (CDS) portion. This portion includes a transistor 1102 associated with a precharge signal pc1, which is connected to a first capacitor 1104 and a second capacitor 1106. Capacitor 1106 is coupled to transistor 1108, which has a gate controlled by a calibration control signal calib. Capacitor 1106 is also coupled to transistor 1110, which is connected to another transistor 1112 configured to apply a second sampling signal (sample2). Transistor 1112 is coupled to storage circuit 1006. In this configuration, transistor 1012 is associated with another precharge signal pc2.

[0122] The CDS circuit between sample1 and sample2 operates as follows. The circuit subtracts the two samples on the series capacitor 1106. For example, when the R signal comes first and the S signal comes second, the SF1 transistor 1002 writes R on the left side of the capacitor 1106, while the right side is connected to V through 1108, which is turned on when calib is in effect. dd2 Next, calib fails and R and V dd2 The voltage difference between 1 and 1 is stored on capacitor 1106. This reference signal will be stored on 1006. Next, SF1 writes S to the left side of 1106 when 1108 is disconnected. When the left side of 1106 drops from R level to S level, the right side will follow. On the right side, the result will have ref-(RS). Therefore, this provides the subtraction signal required for the CDS operation within the pixel. This signal can now also be stored at block 1006. Read out the above text about Figure 10 The discussed method occurs.

[0123] Thus, it can be seen that the circuits illustrated in the figures and described herein provide significant technical benefits, such as enabling high dynamic range (HDR) functionality utilizing a time-gated pixel architecture.

[0124] Figure 12Method 1200 is illustrated and includes, at block 1202, causing an illumination module of an imaging system to emit one or more light pulses. At block 1204, the method includes modulating a reset signal and a transfer signal for an image sensor element to selectively cause a time-gated charge to accumulate in a photosensitive region of the image sensor element in response to incident light on the image sensor element. The time-gated charge corresponds to a selected distance range for the imaging system. At block 1206, the method includes transferring the time-gated charge to a charge storage region of the image sensor element. At block 1208, the method includes storing a saturated portion of the time-gated charge accumulated by the photosensitive region in a capacitor of the image sensor element. Furthermore, at block 1210, the method includes constructing a high dynamic range image from a readout of any time-gated charge stored in the charge storage region and the saturated portion of the time-gated charge stored by the capacitor, according to the selected distance range.

[0125] Although the technology herein has been described with reference to specific embodiments / configurations, it should be understood that these are merely illustrative of the principles and applications of the technology. Therefore, it should be understood that numerous modifications may be made to the illustrative embodiments, and other arrangements may be devised, without departing from the spirit and scope of the technology as defined by the appended claims. By way of example only, components illustrated as being arranged in series may have a complementary parallel configuration; similarly, components illustrated as being arranged in parallel may have a complementary series configuration.

Claims

1. An image sensor element, comprising: a photosensitive region configured to generate charge in response to incident light on the image sensor element; a charge storage region configured to store at least a portion of the charge generated by the photosensitive region; a first actuating element electrically coupling the photosensitive region to the charge storage region, the first actuating element being configured to effect charge transfer from the photosensitive region to the charge storage region according to a transfer control signal; a floating diffusion region coupled to the first actuating element; a second actuator element responsive to a gain control signal, the second actuator element having a first node connected to the floating diffusion region; a third actuation element responsive to a reset control signal, the third actuation element having a first node coupled to the second node of the second actuation element and a second node coupled to a voltage supply; a capacitor having a first node connected to the second node of the second actuating element, the capacitor operatively coupled to the first node of the third actuating element; and a readout control circuit configured to read out the charge stored in the charge storage region and the charge stored by the capacitor; in: In response to the gain control signal, the second actuation element is configured to electrically couple the capacitor to the floating diffusion region to receive a saturation portion of the charge generated by the photosensitive region; time-gating the accumulation for imaging to correspond with a pulsed light source to achieve a selected range of distances detectable by the image sensor element; and According to time-gated accumulation, a high dynamic range image can be constructed from the readout of the charge stored in the charge storage region and the charge stored by the capacitor.

2. The image sensor element according to claim 1 , wherein in response to the reset control signal, the third actuation element is configured to: resetting the capacitor but not the floating diffusion in a first mode; and At least both the floating diffusion region and the capacitor are reset in a second mode.

3. The image sensor element according to claim 1, wherein The second actuation element is configured to set a selectable overflow threshold for an amount of the saturated portion of charge to be received by the capacitor.

4. The image sensor element according to claim 1, wherein: The charge stored by the capacitor represents a low gain image signal; and When read out by the readout control circuit, a reset voltage level is subtracted from the low gain image signal for double sampling reading of the low gain image signal with uncorrelated noise.

5. The image sensor element according to claim 1, wherein The readout control circuit is configured to first read out the charge stored in the charge storage region and then read out the charge stored by the capacitor. 6 . The image sensor element according to claim 1 , wherein the readout control circuit is configured to first read out the charge stored by the capacitor and then read out the charge stored in the charge storage region.

7. The image sensor element according to claim 1 , further comprising: a fourth actuating element disposed between the floating diffusion region and the charge storage region; in: the transfer control signal for the first actuating element is a first transfer control signal; The fourth actuating element is responsive to a second transfer control signal; and The level of the second transfer control signal sets an overflow threshold for an amount of the saturated portion of charge to be received by the capacitor.

8. The image sensor element according to claim 7, wherein: The capacitor is a first capacitor and the gain control signal is a first gain control signal, and the image sensor element further comprises: a fifth actuation element responsive to a second gain control signal, the fifth actuation element having a first node connected to the second node of the second actuation element; and a second capacitor having a first node connected to a second node of the fifth actuator element; in: a first node of the third actuator element coupled to the second node of the fifth actuator element and to the first node of the second capacitor; The first gain control signal is used to read out charge from the first capacitor; and The second gain control signal is used to read out charge from the second capacitor.

9. The image sensor element according to claim 8, wherein Overflowing charges from the charge storage region can flow into the second capacitor when the first capacitor overflows.

10. The image sensor element according to claim 8, wherein The capacitance of the second capacitor is greater than the capacitance of the first capacitor.

11. The image sensor element according to claim 8, wherein The high dynamic range image can be constructed from the readout of the charge stored in the charge storage region, the charge stored by the first capacitor, and the charge stored by the second capacitor.

12. The image sensor element according to claim 8, wherein The fifth actuation element has a coupled gate arrangement and is configured to modulate the overflow current in the time domain.

13. The image sensor element according to claim 12, wherein: Modulation of the overflow current is performed synchronously with the accumulation gating.

14. The image sensor element according to claim 1, wherein The image sensor element is configured to perform a global shutter operation.

15. A method comprising: causing an illumination module of the imaging system to emit one or more light pulses; modulating a reset signal and a transfer signal for an image sensor element to selectively cause a time-gated charge to accumulate in a photosensitive region of the image sensor element in response to incident light on the image sensor element, the time-gated charge corresponding to a selected distance range for the imaging system; transferring the time-gated charge to a charge storage region of the image sensor element; storing a saturated portion of the time-gated charge accumulated by the photosensitive region in a capacitor of the image sensor element; as well as A high dynamic range image is constructed from a readout of any time-gated charge stored in the charge storage region and the saturated portion of the time-gated charge stored by the capacitor, according to the selected distance range. 16 . The method of claim 15 , further comprising selectively setting an overflow threshold for an amount of the saturated portion of the time-gated charge to be received by the capacitor.

17. The method of claim 15, wherein: The charge stored by the capacitor represents a low gain image signal; and During readout by a readout control circuit of the image sensor element, a reset voltage level is subtracted from the low gain image signal for double sampling readout of the low gain image signal with uncorrelated noise.

18. The method of claim 15, further comprising performing, by a readout control circuit of the image sensor element, reading out the charge stored in the charge storage region and then performing reading out the charge stored by the capacitor.

19. An imaging system comprising: an illumination module configured to emit one or more light pulses; and An image sensor element, the image sensor element comprising: a photosensitive region configured to generate charge in response to incident light on the image sensor element; a charge storage region configured to store at least a portion of the charge generated by the photosensitive region; a first actuating element electrically coupling the photosensitive region to the charge storage region, the first actuating element being configured to effect charge transfer from the photosensitive region to the charge storage region according to a transfer control signal; a floating diffusion region coupled to the first actuating element; a second actuator element responsive to a gain control signal, the second actuator element having a first node connected to the floating diffusion region; a third actuation element responsive to a reset control signal, the third actuation element having a first node coupled to the second node of the second actuation element and a second node coupled to a voltage supply; a capacitor having a first node connected to the second node of the second actuating element, the capacitor operatively coupled to the first node of the third actuating element; and a readout control circuit configured to read out the charge stored in the charge storage region and the charge stored by the capacitor; in: In response to the gain control signal, the second actuation element is configured to electrically couple the capacitor to the floating diffusion region to receive a saturated portion of the charge generated by the photosensitive region; time-gating accumulation for imaging to correspond with pulsing by the illumination module to achieve a selected range of distances detectable by the image sensor element; and According to time-gated accumulation, a high dynamic range image can be constructed from the readout of the charge stored in the charge storage region and the charge stored by the capacitor.

20. The imaging system of claim 19, wherein: The second actuation element is configured to set a selectable overflow threshold for an amount of the saturated portion of charge to be received by the capacitor.

Images