Equipment and method for upgrading logic chip system software thereof

Abstract

The invention provides equipment and a method for upgrading logic chip system software thereof. The method comprises the following steps: acquiring a system software package, and reading a version number and compiling time of a flash memory high-end address record of a gated logic chip; searching an incremental update comparison bitmap of the historical system software and the current system software at a second package head of the system software package, and identifying more than one update sector in the incremental update comparison bitmap; erasing each identified update sector at the corresponding storage position of the flash memory of the gated logic chip, and writing one version data piece of the version data of the system software package corresponding to each update sector into the corresponding storage position of each update sector at the flash memory of the gated logic chip.

Description

Technical Field

[0001] The present application relates to communication technology, and more specifically to a device and a method for upgrading logic chip system software. Background Art

[0002] After the system software of a communication device is upgraded, the management CPU sends the identifier of the target logic chip to the CPLD. The CPLD activates the CS (Chip Select) signal of the target logic chip, and the management CPU writes the new version of the system software to the Flash area of ​​the target logic chip via the SPI bus. After the CPU completes writing the new version of the system software, it notifies the CPLD to release the CS signal of the target logic chip. It then sends the identifier of another target logic chip to the CPLD, selects different logic chips one by one, and then writes the new version of the system software to the Flash area of ​​each logic chip via the SPI bus. The management CPU then powers on or hot-restarts each logic chip to run the updated system software.

[0003] However, the speed at which these communication devices update the system software on each logic chip is primarily limited by the data write rate of the communication device's management CPU to the flash memory area of ​​each logic chip and the SPI (Serial Peripheral Interface) channel rate. This speed significantly impacts the system's boot time.

[0004] Currently, when the management CPU of a communication device upgrades the system software of each logic chip, it completely burns the new version of the system software stored in the main memory into the flash memory of each logic chip. As the system architecture of switch equipment continues to develop and update, more and more logic chips will be integrated into the equipment. At the same time, the size of the system software package will also increase. Since the structure of the system software package is:

[0005] [System package 1 data] + [Placeholder 1] [System package 2 data] + [Placeholder 2] [System package n] + [Placeholder n] For some logic chips, if the system software only updates a small part of the data, writing the updated system software completely to the Flash area of ​​the logic chip and updating these placeholders together will not only result in invalid data being written, but also increase the system software upgrade time of the entire device if the number of SPI channels remains unchanged. Summary of the Invention

[0006] The purpose of this application is to provide a device and a method for upgrading the system software of a logic chip, thereby reducing the burning time of the system software update of the memory of the logic chip.

[0007] To achieve the above-mentioned purpose, the present application provides a method for upgrading the system software of a logic chip of a device, the method comprising: obtaining a system software package; wherein a first header portion of the system software package having a fixed length comprises a first version number, a first compilation time, a number of bitmaps, a total header length, a cyclic redundancy CRC check code, and a minimum unit of data update; a second header portion of the system software package having a variable length comprises one or more incremental update comparison bitmap tables arranged in a specified order; the version data of the system software package comprises a plurality of version data slices, and the size of a version data slice is equal to the minimum unit of data update; and reading the high-end address record of the flash memory of the selected logic chip. The second version number and the second compilation time; searching the incremental update comparison bitmap table of the historical system software and the current system software to see whether they are recorded in the second packet header; wherein the historical system software is the system software with the second version number and the second compilation time; the current system software is the system software with the first version number and the first compilation time; if so, identifying one or more update sectors in the searched incremental update comparison bitmap table; wherein the storage space of each update sector is equal to the minimum unit of data update; erasing each identified update sector at the corresponding storage location of the flash memory of the enabled logic chip, and writing the identified update sector into a corresponding version data slice in the version data.

[0008] To achieve the above-mentioned object, the present application further provides a device comprising a management processor, a main memory, and a memory. The main memory stores an acquisition system software package. The memory is used to store processor executable instructions. The management processor executes processor-executable instructions in the memory to perform the following operations: retrieve a system software package from the main memory; wherein a fixed-length first header portion of the system software package includes a first version number, a first compile time, a number of bitmaps, a total header length, a cyclic redundancy check code (CRC), and a minimum data update unit; wherein a variable-length second header portion of the system software package includes one or more incremental update comparison bitmap tables arranged in a specified order; wherein the version data of the system software package includes multiple version data slices, and the size of each version data slice is equal to the minimum data update unit; read the second version number and the second compile time recorded in the high-end address of the flash memory of the enabled logic chip; search for the incremental update comparison bitmap table of the historical system software and the current system software to determine whether they are recorded in the second header portion; wherein the historical system software is system software having the second version number and the second compile time; and wherein the current system software is system software having the first version number and the first compile time; and if so, identify one or more update sectors in the searched incremental update comparison bitmap table; wherein the storage space of each update sector is equal to the minimum data update unit; and erase each identified update sector at a corresponding storage location in the flash memory of the enabled logic chip and write a corresponding version data slice of the version data of the identified update sector.

[0009] The beneficial effect of the present application is that the system software of the memory of the logic chip in the communication device is incrementally updated, and the written system software does not contain placeholders, thereby avoiding frequent writing of invalid data. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A flowchart of an embodiment of a method for upgrading logic chip system software of a device is provided for this application;

[0011] Figure 2 A schematic block diagram of upgrading the logic chip system software in a communication device;

[0012] Figure 3 A schematic diagram of the spatial structure of the memory of the logic chip provided in an embodiment of the present application is shown;

[0013] Figures 4A-4B Shown is a schematic diagram of the structure of the system software package provided by this application;

[0014] Figure 5 A schematic structural diagram of a device embodiment is provided for this application. DETAILED DESCRIPTION

[0015] The present invention will be described in detail with reference to a plurality of examples shown in the accompanying drawings. In the following detailed description, a number of specific details are provided to provide a comprehensive understanding of the present invention. Known methods, steps, components, and circuits are not described in detail in the examples to avoid obscuring the understanding of the examples.

[0016] Among the terms used, the term "including" means including but not limited to; the term "containing" means including but not limited to; the terms "above," "within," and "below" are inclusive; the terms "greater than" and "less than" are exclusive. The term "based on" means based on at least a portion.

[0017] Figure 1 The flowchart of an embodiment of a method for upgrading logic chip system software of a device provided by the present application is shown, and the method includes:

[0018] Step 101: Obtain the system software package;

[0019] The fixed-length first header portion of the system software package includes a first version number, a first compilation time, a number of bitmaps, a total header length, a cyclic redundancy check code (CRC), and a minimum data update unit. The variable-length second header portion of the system software package includes one or more incremental update comparison bitmap tables arranged in a specified order. The version data of the system software package includes multiple version data slices, and the size of each version data slice is equal to the minimum data update unit.

[0020] Step 102, reading the second version number and the second compile time recorded in the high-end address of the flash memory of the selected logic chip;

[0021] Step 103: Find the incremental update comparison bitmap table of the historical system software and the current system software in the second packet header;

[0022] The historical system software is the system software having the second version number and the second compilation time; the current system software is the system software having the first version number and the first compilation time;

[0023] Step 104: identifying one or more update sectors in the searched incremental update comparison bitmap table; wherein the storage space of each update sector is equal to the minimum unit of data update;

[0024] In this application, in the incremental update comparison bitmap table, each bit mapping logic chip has a storage space in the memory that is equal to the minimum unit (granularity) of data update.

[0025] Step 105 : Erasing each identified update sector at a corresponding storage location of the flash memory of the enabled logic chip, and writing a version data slice of the version data corresponding to the identified update sector.

[0026] Figure 1 The beneficial effect of the illustrated example is that the system software of the memory of the logic chip in the communication device is incrementally updated, and the written system software does not contain placeholders, thereby avoiding frequent writing of invalid data.

[0027] Figure 2 A schematic block diagram of upgrading the logic chip system software in a communication device;

[0028] Figure 2 In the example, after the system software in main memory 22 is upgraded, management CPU 21 reads system software package 200 from main memory 22. Management CPU 21 sends the identifier of target logic chip 24 to CPLD 23. CPLD 23 activates the CS signal of logic chip 24, and management CPU 21 writes the version data of system software package 200 to Flash 241 of logic chip 24 via the SPI bus. When CPU 22 completes writing the system software to Flash 241 of logic chip 24, it notifies CPLD 23 to release the CS signal of logic chip 24 and then sends the identifier of the next logic chip, 25, to CPLD 23. In this way, Flash 251 of logic chip 25 and Flash 261 of logic chip 26 are both written with the version data of system software package 200, and logic chips 24 and 26 are all updated to the same version of system software.

[0029] This application is for Figure 2The hardware architecture of the management CPU 21 selecting the logic chips 24-26 one by one through the CPLD 23 has not been improved. However, this application has improved the structure of the system software package 200, the burning method of the version data in flash 241, flash 251, and flash 261, the address space division method of flash 241, flash 251, and flash 261, and the method by which the management CPU 21 determines whether the version data in flash 241, flash 251, and flash 261 needs to be updated.

[0030] Figure 3 The figure shows a schematic diagram of the spatial structure of the memory of the logic chip provided in an embodiment of the present application. Figure 3 In the example, the addresses of the storage space 300 of flash 241, flash 251, and flash 261 are 0-XXX.

[0031] The lower address 0 to address xxx-8 of the storage space 300 is used to store version data; the upper 8-bit address of the storage space 300, i.e. address xxx-8 to address xxx, is used to record the version number and compilation time of the system software corresponding to the version data stored at address 0 to address xxx-8.

[0032] Figure 3 In the present application, the memory (flash) space structure of the logic chip is improved, and there is no need to reserve space. The system software package 200 does not need to include placeholder data packaged for the reserved space, nor does it need to write placeholder data to the memory of the logic chip.

[0033] Figures 4A-4B Shown is a schematic diagram of the structure of the system software package provided by this application.

[0034] Figure 4A In the example, system software package 200 includes a first packaging header 20a, a second packaging header 20b, and version data 20c. The first packaging header 20a and the second packaging header 20b constitute the packaging header of system software package 200. System software package 200 can be implemented by a packaging script program running on a software compilation device according to the structure of the system software package 200 in the embodiment of the present application.

[0035] The first part of the packet header 20a includes: a version number field 41, a compilation time field 42, a bitmap quantity field 43, a packet header total length field 44, a cyclic redundancy CRC check code field 45, and a granularity field 46.

[0036] The second portion of the packing header 20b includes: one or more incremental update comparison bitmap tables arranged in a specified order.

[0037] In this application, the structure of the version data 20c is [version data piece 1] [version data piece 2] ... [version data piece n]. The version data 20c includes n version data pieces, and the size of each version data piece is equal to the minimum unit of data update.

[0038] Figure 4A If the version number field 41 records version 3, the second part of the packaging header 20b records the incremental update bitmap table 47 of system software version 3 and historical version 2, and the incremental update bitmap table 48 of system software version 3 and historical version 1, arranged in the specified order.

[0039] Figure 4B for Figure 4A Incremental update bitmap tables 47 and 48 are shown in the schematic diagram, arranged in a specified order from higher to lower versions in the second portion of the packaging header 20b. The plurality of incremental update bitmap tables in the second portion of the packaging header 20b can also be arranged in an order from lower to higher versions, but this application does not impose this limitation. Any arrangement rule that can find a corresponding incremental update bitmap table in the order of version updates can be applied.

[0040] The minimum unit of data update recorded in the granularity field 46 is an integer multiple of a sector of flash 241 , flash 251 , and flash 261 .

[0041] In one example, if the minimum unit of data update recorded in granularity field 46 is one sector, flash 241, flash 251, and flash 261 are updated at the minimum unit (granularity) of one sector. Each bit in incremental update bitmap table 47 and incremental update bitmap table 48 maps to the storage space of 11 sectors in flash 241, flash 251, and flash 261. The size of each version data piece in version data 20c is equal to one sector.

[0042] In one example, if the minimum data update unit recorded in granularity field 46 is two sectors, flash 241, flash 251, and flash 261 are updated at a granularity of two sectors. Each bit in incremental update bitmap table 47 and incremental update bitmap table 48 maps to the storage space of two sectors of flash 241, flash 251, and flash 261. The size of each version data piece in version data 20c is equal to two sectors.

[0043] In the incremental update bit table 47 and the incremental update bit table 48 , the version data slice of the version data 20 c corresponding to the bit value equal to 1 needs to be updated to the mapped sectors of the flash 241 , the flash 251 , and the flash 261 .

[0044] Taking the burning process of system software update in flash241 as an example, the implementation method includes:

[0045] The management CPU 21 reads the version number v1 and compile time time1 recorded in the high-end address xxx-8 to XXX of the flash 241 of the selected logic chip 24, and determines that an update is required based on the version number v3 in the version number field 41 and the compile time time3 in the compile time field 42.

[0046] The management CPU 21 searches the second header 20b for the incremental update comparison bitmap of the historical system software v1 and the current system software v3. The management CPU 21 calculates the length of the second header 20b by subtracting the fixed length of the first header 20a from the total header length field 44.

[0047] The management CPU 21 calculates the size of each incremental update comparison bitmap table of the second header part 20b by dividing the length of the second header part 20b by the number of bitmaps 2 recorded in the bitmap number field 43.

[0048] The management CPU 21 calculates the size of the incremental update comparison bitmap table according to the specified arrangement order of the incremental update comparison bitmap table in the second packet header part 20b, and checks whether the second incremental update comparison bitmap table 408 is the incremental update comparison bitmap table between the historical system software 1 and the current system software version 3.

[0049] The management CPU 21 recognizes that six update sectors are required based on the increment.

[0050] In this application, the storage space of the updated sector is equal to the minimum unit of data update of the granularity field 46 .

[0051] In one example, the minimum unit of data update in the granularity field 46 is 1 sector. The CPU 21 compares the bit value 1 in the bit table 48 based on the incremental update, and reads version data piece 2 (bit value 1 of the second bit in the first row), version data piece 5 (bit value 1 of the first bit in the second row), version data piece 13, version data piece 14, version data piece 15, and version data piece 16 (bit value 1 of the 1st to 4th bits in the fourth row) from the version data 20c.

[0052] The management CPU 21 erases a sector with each bit value 1 in the mapping update comparison bit table 48 in the flash 241 and writes the corresponding version data piece 2, version data piece 5, version data piece 13, version data piece 14, version data piece 15, and version data piece 16.

[0053] In another example, if the minimum unit of data update is two sectors, management CPU 21 reads version data slice 2 (bit value 1, second in the first row), version data slice 5 (bit value 1, first in the second row), version data slice 13, version data slice 14, version data slice 15, and version data slice 16 (bit values ​​1, first to fourth in the fourth row) from version data 20c based on the bit value 1 in the incremental update comparison bit table 48. The size of each version data slice is equal to the size of two physical sectors. Management CPU 21 erases the two sectors (i.e., one updated sector) mapped to each bit value 1 in comparison bit table 48 in flash 241 and writes the corresponding version data slices 2, 5, 13, 14, 15, and 16.

[0054] After the management CPU 21 completes the incremental update of the system software of some sectors of the flash 241 , it updates the version number v1 and the compile time time1 recorded in the high-end addresses xxx-8 to XXX of the Flash 241 of the logic chip 24 to the version number v3 and the compile time time3 .

[0055] The management CPU 21 can also calculate the CRC (Cyclic Redundancy Check) check code based on the version data packet 203 before reading the version number v1 and compilation time time1 recorded in the high-end address xxx-8 to XXX of the Flash 241 of the logic chip 24, or before erasing the mapped sector of the Flash 241, and compare it with the CRC check code carried by the CRC check code field 45 of the first packet header part 20a. If they are consistent, subsequent processing will be performed.

[0056] After completing the on-demand incremental update of the Flash 241 of the logic chip 24 , the management CPU 21 performs on-demand incremental updates on the Flash 251 and the Flash 261 in the same manner, and burns part of the version data of the system software package 200 into the Flash 251 and the Flash 261 .

[0057] In this application, if the flash 241, flash 251, and flash 261 of logic chips 24-26 do not have a historical version of system software package 200 written into them, and management CPU 21 does not find the update comparison bitmap table in the second header 20b, management CPU 21 erases all sectors of the version data from low-order addresses 0 to xxx-8 of flash 241, flash 251, and flash 261 of logic chips 24-26, and writes version data 20C. Management CPU 21 then updates the version numbers and compile times recorded at high-order addresses xxx-8 to xxx of flash 241, flash 251, and flash 261 of logic chips 24-26, respectively, to version number v3 based on version number field 41 and compile time time3 based on compile time field 42. In this way, the version data of flash 241, flash 251, and flash 261 of logic chips 24-26 can be updated on an on-demand basis, improving the system software update rate of the logic chips. Figure 3-Figure 5 In the embodiment, the management CPU needs to follow the instructions before updating the Flash of each logic chip. Figure 2 Select first using the method in .

[0058] The logic chips 24 - 26 in the embodiments of the present application are not limited to chips such as CPU, GPU, FPGA, ASIC, etc. with memory.

[0059] Figure 5 The present application provides a schematic diagram of a device embodiment. The device 50 includes a management processor 51, a main memory 52, and a memory 53. The main memory 52 stores a system software package. The memory 53 is used to store processor-executable instructions.

[0060] The management processor 51 executes the following operations by running the processor executable instructions in the memory 53: obtaining the system software package from the main memory 52; wherein the first header portion of the system software package, which has a fixed length, includes a first version number, a first compilation time, a number of bitmaps, a total header length, a cyclic redundancy check code (CRC), and a minimum data update unit; the second header portion of the system software package, which has a variable length, includes one or more incremental update comparison bitmap tables arranged in a specified order; the version data of the system software package includes multiple version data slices, and the size of each version data slice is equal to the minimum data update unit; and reading the high-end address memory of the flash memory of the selected logic chip. The second version number and the second compilation time of the record are recorded; the incremental update comparison bitmap table of the historical system software and the current system software is searched to see whether they are recorded in the second packet header; wherein the historical system software is the system software with the second version number and the second compilation time; the current system software is the system software with the first version number and the first compilation time; if so, one or more update sectors are identified in the searched incremental update comparison bitmap table; wherein the storage space of each update sector is equal to the minimum unit of data update; each identified update sector is erased at the corresponding storage location of the flash memory of the enabled logic chip, and a corresponding version data piece of the version data of the identified update sector is written.

[0061] The management processor 51 is also used to perform the following operations by running the processor executable instructions in the memory 53: searching the incremental update comparison bitmap table of the historical system software and the current system software, which is not recorded in the second packet header; erasing the flash memory of the enabled logic chip and writing the version data packet.

[0062] The management processor 51 is further configured to perform the following operations by running the processor executable instructions in the memory 53: updating the second version number and the second compile time recorded in the high-end address of the flash memory of the enabled logic chip to the first version number and the first compile time.

[0063] The management processor 51 executes the processor executable instructions in the memory 53 to read the second version number and the second compilation time recorded in the high-end address of the flash memory of the enabled logic chip, and also performs the following operations including: calculating the CRC check code based on the version data packet; and determining that the calculated CRC check code is consistent with the CRC check code of the first packet header part.

[0064] The management processor 51 executes the operations of searching the incremental update comparison bitmap table between the historical system software and the current system software in the second packet header by running the processor executable instructions in the memory 53, including: calculating the length of the second packet header part according to the total length of the packet header and the length of the first packet header part; calculating the size of each incremental update comparison bitmap table according to the length of the second packet header part divided by the number of bitmaps; checking each incremental update comparison bitmap table to see whether it is an incremental update comparison bitmap table between the historical system software and the current system software in accordance with the specified order and the calculated size of each incremental update comparison bitmap table.

[0065] In this application, a machine-readable storage medium may be any electronic, magnetic, optical, or other physical storage device for storing or containing information (e.g., executable instructions, data, etc.). For example, any machine-readable storage medium herein may be any type of random access memory (RAM), volatile memory, non-volatile memory, flash memory, storage drive (e.g., hard drive), solid-state drive, any type of storage optical disc (e.g., optical disc, DVD, etc.), and similar devices, or a combination thereof. In addition, any machine-readable storage medium herein may be a non-transitory machine-readable storage medium.

[0066] The above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A method for upgrading logic chip system software of a device, characterized in that: The method comprises, Get the system software package; The first header portion of the system software package, which has a fixed length, includes a first version number, a first compilation time, a number of bitmaps, a total header length, a cyclic redundancy check code (CRC), and a minimum unit of data update; the second header portion of the system software package, which has a variable length, includes one or more incremental update comparison bitmap tables arranged in a specified order; the version data of the system software package includes multiple version data slices, and the size of each version data slice is equal to the minimum unit of data update; Reading a second version number and a second compile time recorded in a high-end address of the flash memory of the selected logic chip; Searching a table of incremental update comparisons between historical system software and current system software to determine whether the table is recorded in the second packet header; wherein the historical system software is system software having the second version number and the second compilation time; and the current system software is system software having the first version number and the first compilation time; If so, identifying more than one update sector in the searched incremental update comparison bitmap table; wherein the storage space of each of the update sectors is equal to the minimum unit of data update; Each identified update sector is erased from a corresponding storage location of the flash memory of the enabled logic chip, and a version data slice of the version data corresponding to the identified update sector is written.

2. The method according to claim 1, characterized in that The method further comprises, Searching for a comparison bitmap of incremental updates between historical system software and current system software, which is not recorded in the second packet header; The flash memory of the selected logic chip is erased and the version data packet is written.

3. The method according to claim 1 or 2, characterized in that The method further comprises, The second version number and the second compile time recorded in the high-end address of the flash memory of the selected logic chip are updated to the first version number and the first compile time.

4. The method according to claim 1, wherein Before reading the second version number and the second compile time recorded in the high-end address of the flash memory of the enabled logic chip, the method further includes: Calculating a CRC check code based on the version data packet; Determine whether the calculated CRC check code is consistent with the CRC check code of the first packet header part.

5. The method according to claim 1, wherein The step of searching for the incremental update comparison bitmap of the historical system software and the current system software, and whether the incremental update comparison bitmap is recorded in the second packet header, includes: Calculating the length of the second header part according to the total length of the header and the length of the first header part; Calculate the size of each incremental update comparison bitmap table according to the length of the second packet header divided by the number of bitmaps; According to the specified order and the calculated size of each incremental update comparison bitmap table, each incremental update comparison bitmap table is checked to determine whether it is an incremental update comparison bitmap table between the historical system software and the current system software.

6. A device, characterized in that The device comprises a management processor, a memory, and a main memory; the main memory stores a system software package; the memory is used to store processor-executable instructions; wherein the management processor executes the following operations by running the processor-executable instructions in the memory: Retrieving a system software package from a main memory; wherein a first header portion of the system software package having a fixed length includes a first version number, a first compilation time, a number of bitmaps, a total header length, a cyclic redundancy check code (CRC), and a minimum data update unit; a second header portion of the system software package having a variable length includes one or more incremental update comparison bitmap tables arranged in a specified order; and the version data of the system software package includes multiple version data slices, and a size of each version data slice is equal to the minimum data update unit. Reading a second version number and a second compile time recorded in a high-end address of the flash memory of the selected logic chip; Searching a table of incremental update comparisons between historical system software and current system software to determine whether the table is recorded in the second packet header; wherein the historical system software is system software having the second version number and the second compilation time; and the current system software is system software having the first version number and the first compilation time; If so, identifying more than one update sector in the searched incremental update comparison bitmap table; wherein the storage space of each of the update sectors is equal to the minimum unit of data update; Each identified update sector is erased at a corresponding storage location of the flash memory of the enabled logic chip, and a corresponding version data piece of the version data corresponding to the identified update sector is written.

7. The device according to claim 6, characterized in that The management processor is further configured to perform the following operations by running the processor-executable instructions in the memory: Searching for a comparison bitmap of incremental updates between historical system software and current system software, which is not recorded in the second packet header; The flash memory of the selected logic chip is erased and the version data packet is written.

8. The device according to claim 6 or 7, characterized in that The management processor further performs the following operations by running the processor executable instructions in the memory: The second version number and the second compile time recorded in the high-end address of the flash memory of the selected logic chip are updated to the first version number and the first compile time.

9. The device according to claim 6, characterized in that Before the management processor executes the processor executable instructions in the memory to read the second version number and the second compile time recorded in the high-end address of the flash memory of the enabled logic chip, the management processor further performs the following operations: Calculating a CRC check code based on the version data packet; Determine whether the calculated CRC check code is consistent with the CRC check code of the first packet header part.

10. The device according to claim 6, characterized in that The management processor executes the processor executable instructions in the memory to perform an operation of searching the incremental update comparison bitmap table of the historical system software and the current system software in the second packet header, including: Calculating the length of the second header part according to the total length of the header and the length of the first header part; Calculate the size of each incremental update comparison bitmap table according to the length of the second packet header divided by the number of bitmaps; According to the specified order and the calculated size of each incremental update comparison bitmap table, each incremental update comparison bitmap table is checked to determine whether it is an incremental update comparison bitmap table between the historical system software and the current system software.

Images