Design method, prediction system and equipment of advanced branch target address buffer

Abstract

The invention discloses a design method of an advanced branch target address buffer area, which comprises the following steps of: S1, judging whether a first group of jumped branch instructions are unconditional direct branches or not, if so, entering S5; if not, entering S2; s2, judging whether the branch is a conditional direct branch, if so, entering S5; if not, entering S3; s3, when the first group of jump branch instructions are unconditional indirect branches, entering S4; s4, judging whether the actual jump address is the same as the address provided by the leading branch target address buffer area or not, and if not, resetting a saturation counter; if yes, the saturation counter counts, the first instruction block is expanded, and S5 is executed; and S5, linking the two instruction blocks. The invention further discloses a prediction system, and the flow predictor is introduced into the decoupling predictor. According to the method, the operation logic of the advanced branch target address buffer area is optimized, instruction parallel and instruction block extension connection are allowed, and the prediction efficiency is improved; the flow predictor is additionally arranged, the bubble waiting problem is solved, and the prediction speed is increased.

Description

Technical Field

[0001] The present invention relates to the technical field of processor branch prediction, and in particular to a design method, prediction system and device for an advance branch target address buffer. Background Art

[0002] Decoupled Branch Predictor, that is, decoupling predictor, can perform branch prediction and instruction fetch decoupling, that is, the execution of BPU no longer depends on the result of instruction fetch. BPU is branch predictor. Figure 1 Figure 1 shows the basic principle of a decoupled predictor. When an instruction cache miss occurs in the instruction storage system or an execution unit stalls in the processor, the multi-level branch predictor can outperform the instruction fetch unit and store the predicted instruction stream in the fetch queue, thus filling the bubble caused by branch prediction delays. The fetch queue is also known as the instruction fetch stack. Decoupled predictors are currently widely used in commercial processor designs.

[0003] As CPU performance improves, the number of instructions processed per CPU clock cycle also increases, making branch predictor throughput a design bottleneck. The current Branch Target Buffer (Btb), or branch prediction cache or branch target address buffer, can only provide instructions within the current instruction block. If a jump branch instruction appears within the instruction block, the number of instructions provided by the entire branch prediction system will decrease, thus affecting overall CPU performance.

[0004] like Figure 2 As shown in the figure, it is a schematic diagram of the framework structure of a decoupling predictor; Figure 3 The figure shows the basic principle diagram of a decoupling predictor, which marks the jump conditions under different addresses. Figure 2 and Figure 3As shown, the decoupled predictor primarily consists of a multi-level branch predictor (BPU), a Fetch Queueu instruction stack, an instruction storage system, and an execution unit. It can process different instruction streams in parallel. For example, the loop start address is c, 18 is a predicted branch instruction, which then jumps to address 11c; 124 stores the predicted branch instruction, which jumps to address 220; the branch at address 228 is predicted to jump to address 318; and the branch at address 32c is predicted to jump back to address c. Therefore, in a traditional BTB-based branch prediction system, four predictions are required, each providing a basic block. The first prediction provides instructions: {3, 4, 5, 6}, for a total of four instructions; the second prediction provides instructions: {23, 24, 25}, for a total of three instructions; the third prediction provides instructions: {40, 41, 42}, for a total of three instructions; and the fourth prediction provides instructions: {54, 55, 56, 57, 58, 59}, for a total of six instructions. In this loop, the branch prediction system can only provide an average of 4 instructions to the backend each time, which is far lower than the processing and execution capabilities of the CPU. The prediction throughput and speed are very limited, and throughput is efficiency.

[0005] Each entry in the traditional branch target address buffer consists of two parts: a tag field, which is used to match whether the current branch target address buffer has hit; N branch information, the branch target address buffer needs to contain the branch information of instruction 6 and instruction 12; each set of branch information includes a branch type (br_type), b branch offset position in the current area (br_offset), and c branch target address (br_tar). Figure 3 As shown in FIG. 1 , a data structure diagram of a standard target address buffer is shown. In this case, N=2, which means that there are two branch information, 0 and 1.

[0006] Based on the above, we can see that there are at least two problems in the existing technology of Btb prediction: 1) Btb can predict one aligned region at a time, but the target buffer only provides the region where the current value address is located. It cannot provide the target address after the branch instruction in the region jumps. This results in a low number of instructions predicted each time and low CPU execution parallelism. 2) To balance prediction speed and accuracy, a multi-level branch target buffer is commonly used, with smaller levels serving as fast buffers that prioritize prediction speed, and larger levels serving as primary buffers that prioritize accuracy and throughput. However, current multi-level branch target buffers do not consider the impact of structure on prediction speed and efficiency. In other words, each level of the multi-level branch target buffer uses the same structure, making it impossible to achieve a better balance between prediction speed and efficiency. Summary of the Invention

[0007] In response to the above two problems, the purpose of the present invention is to propose a design method and prediction system for an advance branch target address buffer, which performs instruction fetching based on a decoupled predictor, allowing different branch instructions to be processed in parallel. The advance branch target address buffer also provides instruction blocks corresponding to the number of branch instructions, supports linking different instruction blocks, and greatly improves throughput, that is, prediction efficiency. At the same time, the drainage predictor optimizes the decoupled predictor, eliminating the waiting time of three bubbles after the main predictor completes the prediction in conventional technology, effectively improving the prediction speed while ensuring prediction accuracy.

[0008] This is achieved through the following technical solutions: A method for designing an advance branch target address buffer comprises the following steps: S1, using a decoupled predictor to fetch instructions and obtain two groups of branch instructions that will jump; firstly, determining whether the first group of branch instructions that will jump are unconditional direct branches; if so, proceeding to step S5; if not, proceeding to step S2; S2, determining whether the first group of branch instructions that will jump are conditional direct branches; if so, executing them according to the current conditions, confirming that a jump has occurred, and then proceeding to step S5; if not, proceeding to step S3; S3, if the first group of branch instructions that will jump are unconditional indirect branches, proceeding to step S4. Step S4; S4, determine whether the actual jump address is the same as the address provided by the advance branch target address buffer. If not, the saturation counter is cleared; if so, the saturation counter counts, and the first instruction block where the first group of branch instructions that jump is located after the jump is expanded to support the second instruction block to which the second group of branch instructions that jump is to jump, and then jump to step S5; S5, link the two instruction blocks, assign the same ID number to both instruction blocks and pull them high respectively, to indicate that the advance branch target address buffers corresponding to the two groups of branch instructions that jump have completed the link.

[0009] Preferably, the data structure of the advance branch target address buffer includes: a Tag field, branch information 1, branch information 2, extended information 1 and extended information 2; wherein, branch information 1 includes entry information of the first group of branch instructions that jump; branch information 2 includes entry information of the second group of branch instructions that jump; extended information 1 and extended information 2 are used to support linking when expanding in step S4.

[0010] Preferably, any entry information is provided with three parameters: a branch type parameter br_type, an offset position parameter br_offset, and a branch target address parameter br_tar.

[0011] Preferably, the parameters included in the first extended information are: the indirect branch fixed parameter br0_indir_tar_is_stable, the supported region link indication parameter br0_region_link_id; the parameters included in the second extended information are: the completed region link indication parameter two_region_are_linked, the supported region link indication parameter br1_region_link_id.

[0012] Furthermore, a prediction system is proposed that supports the operation of any of the aforementioned design methods for an advance branch target address buffer. The prediction system uses a heterogeneous predictor for prediction, and the heterogeneous predictor includes a decoupled predictor and a stream predictor arranged in the decoupled predictor; the decoupled predictor includes a branch predictor and an instruction stack, and the branch predictor is provided with an advance branch target address buffer, a main predictor and a program counter check unit; wherein, the advance branch target address buffer is used to cache the target address of the historical branch instruction stream; the main predictor predicts the value I of the next program counter based on each branch instruction stream to be processed by the branch predictor; after the stream predictor obtains each branch instruction stream to be processed by the branch predictor, it hashes the starting address and the target address of the historical branch instruction stream, and then outputs the predicted value II of the next program counter; the program counter check unit selects the prediction result based on the comparison of value I and value II; the instruction stack fetches instructions based on the prediction result.

[0013] Preferably, the primary predictor comprises a direction predictor or an indirect address predictor or a return stack.

[0014] Preferably, after the stream predictor obtains any branch instruction stream, the data structure used to store the any branch instruction stream includes: a corresponding Tag field and a final jump address.

[0015] Preferably, when the program counter selects a prediction result, if value I and value II are the same, the address corresponding to value I or the address corresponding to value II is selected as the prediction result; if value I and value II are different, the address corresponding to value II is replaced by the address corresponding to value I and used as the prediction result.

[0016] Furthermore, an electronic device is proposed, comprising a processor, a storage medium and a computer program, wherein the computer program is stored in the storage medium and when the computer program is executed by the processor, any of the aforementioned methods for designing an advance branch target address buffer is implemented.

[0017] In addition, a computer-readable storage medium is also proposed, on which a computer program is stored. When the computer program is executed, it is used to implement any of the aforementioned design methods for the advance branch target address buffer.

[0018] Compared with the prior art, the present invention has the following beneficial effects: The technical solution of the present invention is based on a decoupled predictor for instruction fetching, allowing different branch instructions to be processed in parallel. The advance branch target address buffer also provides instruction blocks corresponding to the number of branch instructions, supporting the linking of different instruction blocks, greatly improving throughput, that is, prediction efficiency; at the same time, the drainage predictor optimizes the decoupled predictor, eliminating the waiting time of three bubbles after the main predictor completes the prediction in conventional technology, effectively improving the prediction speed while ensuring prediction accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A flow chart of an advanced branch target address buffer operation; Figure 2 This is a schematic diagram of the framework structure of a decoupling predictor; Figure 3 This is a basic principle diagram of a decoupled predictor; Figure 4 A data structure diagram of a target address buffer; Figure 5 A data structure diagram of an advance branch target address buffer; Figure 6 A schematic diagram of the framework of a decoupled predictor before the introduction of a flow predictor; Figure 7 A schematic diagram of the framework of a decoupled predictor after the flow predictor is introduced; Figure 8 This is a principle framework diagram of a flow predictor. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present invention will be described in detail below with reference to the accompanying drawings in the embodiments of the present invention.

[0021] like Figure 1 As shown, it is a flow chart of the operation of the advance branch target address buffer. It performs instruction fetching based on the decoupled predictor, allowing different branch instructions to be processed in parallel. The advance branch target address buffer also provides instruction blocks corresponding to the number of branch instructions, supports linking of different instruction blocks, and greatly improves the throughput, that is, the prediction efficiency.

[0022] The design method of the advance branch target address buffer includes the following steps: S1. Use the decoupled predictor to fetch instructions and obtain two groups of branch instructions that jump. First, determine whether the first group of branch instructions that jump is an unconditional direct branch, that is, an uncond direct branch. If so, go to step S5; if not, go to step S2.

[0023] S2. Determine whether the first group of branch instructions that cause a jump are conditional direct branches, i.e., conddirect branches. If so, execute according to the current conditions, confirm that a jump occurs, and then proceed to step S5; if not, proceed to step S3.

[0024] S3. If the first set of branch instructions is an unconditional indirect branch, the process proceeds to step S4. An unconditional indirect branch is an uncond indirect branch. If the first set of branch instructions is not an unconditional indirect branch, the second set of branch instructions is executed after the first set of branch instructions is executed, i.e., they are executed one after the other.

[0025] S4. Determine whether the actual jump address is the same as the address provided by the advance branch target address buffer. If not, the saturation counter br0_indir-tar_is_stable is cleared to zero; if so, the saturation counter counts br0_indir_tar_is_stable++, where ++ indicates an increase in the count. The first instruction block where the first group of branch instructions that jump occurs is expanded to support the second instruction block to which the second group of branch instructions that jump occurs is to be jumped, for example, expanded to br0_indir_tar_is_stable[5]==1, and then jump to step S5.

[0026] The saturation counter can be used to measure credibility. If the addresses are the same, it means that the credibility is high and the counter will count normally. If the addresses are different, the counter will be cleared and will not run. At the same time, a clearing mechanism is set to avoid linking branches with unstable target addresses, stopping the expansion and avoiding performance degradation caused by incorrect links.

[0027] S5. Link the two instruction blocks, assign the same ID number to both instruction blocks and pull them high respectively, to indicate that the advance branch target address buffers corresponding to the two groups of branch instructions that jump have completed linking.

[0028] like Figure 4 As shown in FIG, it is a data structure diagram of a target address buffer, including a Tag field, a branch type parameter br_type, an offset position parameter br_offset, and a branch target address parameter br_tar; Figure 5 As shown in the figure, it is a data structure diagram of the advance branch target address buffer. Figure 4 Based on the above, additional information is extended for each branch to support the link.

[0029] The data structure of the advance branch target address buffer includes: a Tag field, branch information 1, branch information 2, extended information 1, and extended information 2. Branch information 1 includes entry information of the first group of branch instructions that jump, including br0_type, br0_offset, and br0_tar. Branch information 2 includes entry information brX_type, brX_offset, and brX_tar of the second group of branch instructions that jump, where X indicates that the instruction stream corresponding to the second branch is undetermined. Extended information 1 and extended information 2 are used to support linking when expanding in step S4. The parameters included in extended information 1 are: an indirect branch fixed parameter br0_indir_tar_is_stable, and a support region link indication parameter br0_region_link_id; the parameters included in extended information 2 are: a completion region link indication parameter two_region_are_linked, and a support region link indication parameter br1_region_link_id. The indirect branch fixed parameter br0_indir_tar_is_stable is used to determine whether the link condition is met; the completion region link indication parameter two_region_are_linked provides the destination address of the second branch instruction to jump; the two support region link indication parameters are used to indicate that two branches have appeared in the same target address buffer item and can be fetched.

[0030] That is to say, two non-contiguous instruction blocks are linked as long as any of the following conditions are met: 1) If the first group of branch instructions is an unconditional direct jump, then a direct jump is performed, and the instruction block corresponding to the second group of branch instructions is linked to the instruction block corresponding to the first group of branch instructions; 2) If the first group of branch instructions is a conditional direct jump, then a direct jump is also performed after executing the corresponding conditions; 3) If the first group of branch instructions is an unconditional indirect jump, then an indirect jump is performed, and when the provided address and the actual address are the same, a corresponding extended link is performed.

[0031] Furthermore, a prediction system is proposed that supports the operation of any of the aforementioned design methods for an advance branch target address buffer, wherein the prediction system uses a heterogeneous predictor for prediction, the heterogeneous predictor including a decoupled predictor and a stream predictor arranged in the decoupled predictor; the decoupled predictor includes a branch predictor and an instruction stack, and the branch predictor is provided with an advance branch target address buffer, a main predictor and a program counter check unit; wherein the advance branch target address buffer is used to cache the target address of the historical branch instruction stream; the main predictor predicts the value I of the next program counter based on each branch instruction stream to be processed by the branch predictor; after the stream predictor obtains each branch instruction stream to be processed by the branch predictor, it hashes the starting address and the target address of the historical branch instruction stream, and then outputs the predicted value II of the next program counter; the program counter check unit selects the prediction result based on the comparison of value I and value II; the instruction stack fetches instructions based on the prediction result.

[0032] In this embodiment, when the program counter selects a prediction result, if value I and value II are the same, the address corresponding to value I or the address corresponding to value II is selected as the prediction result; if value I and value II are different, the address corresponding to value II is replaced by the address corresponding to value I and used as the prediction result.

[0033] In this embodiment, the main predictor is a core component used to predict whether a branch instruction stream will jump. It can use a direction predictor, an indirect address predictor, or a return stack. The direction predictor can determine whether to branch based on historical information, thereby predicting the next program counter value I when a branch jump is performed, that is, the address to jump to. The indirect address predictor is specifically used to process indirect branch instructions. The return stack is suitable for predicting function return addresses.

[0034] like Figure 8 The figure shows the principle framework of a stream predictor. 4-way refers to four channels; Stream TargetAddress refers to the final jump address; 16-set indicates a total of 16 entries; "Group Pc" hashes "historical information," which hashes the start address and target address of the historical branch instruction stream. The resulting hash is the predicted Pc value. Group Pc is the address of the instruction fetch; Pc represents the instruction. Because each instruction fetch corresponds to a block of instructions, Group encompasses both group and cluster, so it is represented by Group Pc. Historical information, also known as ghr, is a common technique in branch prediction. Different historical information hashed with the same Group Pc can predict different target addresses. After the stream predictor obtains any branch instruction stream, it uses a data structure to store the branch instruction stream, including the corresponding Tag field and the final jump address. This data structure optimizes prediction granularity and accelerates execution.

[0035] like Figure 6 As shown in FIG, it is a schematic diagram of the framework of a decoupling predictor before the flow predictor is introduced; Figure 7 The figure shows a schematic diagram of the framework of the decoupled predictor after the stream predictor is introduced; BPU represents a branch predictor in the decoupled predictor, Stage represents the stage of the instruction stream runtime, Next Pc Gen represents the generation of the next program counter value, and Next Pc Check represents the detection of the next program counter value. Figure 6 The arrow in the figure that goes from Next PC Gen to BPU in reverse direction indicates the redirection operation. Figure 6 and Figure 7 As shown in the figure, before the introduction of the stream predictor, if the main predictor completes the prediction, it is necessary to wait for the interval of 3 bubbles when generating the value of the next program counter to wait for the generation of the value, resulting in a lot of time wasted in the calculation process; after the introduction of the stream predictor, if the main predictor completes the prediction, the stream predictor will omit the process of generating the value of the next program counter, and use the aforementioned hash calculation for redirection, quickly providing the predicted value of the next program counter, reducing the interval time of waiting for 3 bubbles.

[0036] Combine Figure 7 As shown, in terms of the timeline: Cycle 1: Parallel access to the lookahead BTB, main predictor, and stream predictor. Since the stream predictor is fast, address redirection can be triggered immediately. Second cycle: The BPU completes address redirection, and the main predictor and advance BTB obtain prediction results. This result is then compared with the result of the stream predictor for confirmation. If this result is consistent with the result of the stream predictor, then the redirection of the first cycle is valid; otherwise, BPU Stage 1 is flushed, and redirection is performed again based on the prediction results of the main predictor and advance BTB.

[0037] Furthermore, an electronic device is proposed, comprising a processor, a storage medium and a computer program, wherein the computer program is stored in the storage medium and when the computer program is executed by the processor, any of the aforementioned methods for designing an advance branch target address buffer is implemented.

[0038] In addition, a computer-readable storage medium is also proposed, on which a computer program is stored. When the computer program is executed, it is used to implement any of the aforementioned design methods for the advance branch target address buffer.

[0039] In summary, the present invention performs instruction fetching based on a decoupled predictor, allowing different branch instructions to be processed in parallel. The look-ahead branch target address buffer also provides instruction blocks corresponding to the number of branch instructions, supporting the linking of different instruction blocks, thereby greatly improving throughput, that is, prediction efficiency. At the same time, the drainage predictor optimizes the decoupled predictor, eliminating the waiting time of three bubbles after the main predictor completes the prediction in conventional technology. This effectively improves the prediction speed while ensuring prediction accuracy, thus demonstrating significant progress.

[0040] The above embodiments are only for illustrating the technical idea of ​​the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the present invention.

Claims

1. A method for designing an advance branch target address buffer, characterized in that: The steps include: S1. Use the decoupled predictor to fetch instructions and obtain two groups of branch instructions that will jump. First, determine whether the first group of branch instructions that will jump are unconditional direct branches. If so, proceed to step S5. If not, go to step S2; S2. Determine whether the first group of branch instructions that cause a jump are conditional direct branches. If so, execute them according to the current conditions, confirm that a jump has occurred, and then proceed to step S5. If not, go to step S3; S3. If the first group of branch instructions that jump is an unconditional indirect branch, go to step S4; S4. Determine whether the actual jump address is the same as the address provided by the look-ahead branch target address buffer. If not, clear the saturation counter. If so, count the number of times the saturation counter is used. Expand the first instruction block where the first group of branch instructions are jumped to a second instruction block that can support linking to the second group of branch instructions, and then jump to step S5. S5. Link the two instruction blocks, assign the same ID number to both instruction blocks and pull them high respectively, to indicate that the advance branch target address buffers corresponding to the two groups of branch instructions that jump have completed linking.

2. The method for designing a look-ahead branch target address buffer according to claim 1, wherein: The data structure of the advance branch target address buffer includes: Tag field, branch information 1, branch information 2, extended information 1 and extended information 2; wherein, branch information 1 includes entry information of the first group of branch instructions that jump; branch information 2 includes entry information of the second group of branch instructions that jump; extended information 1 and extended information 2 are used to support linking when expanding in step S4.

3. The method for designing a look-ahead branch target address buffer according to claim 2, wherein: Three parameters are set in any entry information: branch type parameter br_type, offset position parameter br_offset and branch target address parameter br_tar.

4. The method for designing a look-ahead branch target address buffer according to claim 2, wherein: The parameters included in the extended information 1 are: the indirect branch fixed parameter br0_indir_tar_is_stable, and the supported region link indication parameter br0_region_link_id; the parameters included in the extended information 2 are: the completed region link indication parameter two_region_are_linked, and the supported region link indication parameter br1_region_link_id.

5. A prediction system supporting the design method of the look-ahead branch target address buffer according to any one of claims 1 to 4, characterized in that: The prediction system uses a heterogeneous predictor for prediction, which includes a decoupled predictor and a stream predictor set in the decoupled predictor; the decoupled predictor includes a branch predictor and an instruction stack, and the branch predictor is provided with a look-ahead branch target address buffer, a main predictor and a program counter check unit; Among them, the advance branch target address buffer is used to cache the target address of the historical branch instruction stream; the main predictor predicts the value I of the next program counter based on each branch instruction stream to be processed by the branch predictor; after the stream predictor obtains each branch instruction stream to be processed by the branch predictor, it hashes the starting address and the target address of the historical branch instruction stream, and then outputs the predicted value II of the next program counter; the program counter check unit selects the prediction result based on the comparison of value I and value II; the instruction stack fetches instructions based on the prediction result.

6. A prediction system according to claim 5, characterized in that: The main predictor includes the direction predictor or the indirect address predictor or the return stack.

7. A prediction system according to claim 5, characterized in that: After the stream predictor obtains any branch instruction stream, the data structure used to store the arbitrary branch instruction stream includes: a corresponding Tag field and a final jump address.

8. A prediction system according to claim 5, characterized in that: When the program counter selects the prediction result, if value I and value II are the same, the address corresponding to value I or the address corresponding to value II is selected as the prediction result; if value I and value II are different, the address corresponding to value II is replaced by the address corresponding to value I and used as the prediction result.

9. An electronic device comprising a processor, a storage medium, and a computer program, wherein the computer program is stored in the storage medium, When the computer program is executed by a processor, the method for designing a look-ahead branch target address buffer according to any one of claims 1 to 4 is implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed, it is used to implement the design method of the advance branch target address buffer according to any one of claims 1 to 4.

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