GPU-based shortest path calculation method and device, electronic equipment and medium

Abstract

The invention relates to the technical field of graph theory algorithms, and discloses a shortest path calculation method and device based on a GPU (Graphics Processing Unit), electronic equipment and a medium. The method comprises the following steps: calling different CUDA thread blocks to obtain first graph information of different target graphs from a GPU global memory; for each target graph, second graph information of the target graph is calculated through a Bellman-Ford algorithm based on the first graph information of the target graph by using the corresponding CUDA thread block, the second graph information is stored in a GPU shared memory, and the second graph information comprises a target weight of each edge in the target graph and a precursor node of each vertex; and calculating the shortest path of each vertex pair in the target graph by using the corresponding CUDA thread block based on a Dijkstra algorithm and the second graph information. According to the method, frequent access to the global memory of the GPU can be reduced, extra overhead of reading and writing the global memory for multiple times is avoided, the memory bandwidth pressure is reduced, and the calculation efficiency is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of graph theory algorithm technology, and in particular to a GPU-based shortest path calculation method, device, electronic device, and medium. Background Art

[0002] In applications involving graphs, solving the shortest path problem remains a core and critical task. Whether it's finding the optimal route between two points in path planning, determining the shortest path for data packet transmission in communication networks, or planning the shortest routes for vehicles in logistics and distribution, shortest path algorithms play an indispensable role.

[0003] The Johnson algorithm, a classic algorithm for computing the shortest paths between all pairs of vertices in a directed graph, was proposed to solve the shortest path problem. With the increasing parallel computing capabilities of GPUs, accelerating graph algorithms using GPUs has become a new trend. However, porting the Johnson algorithm directly to GPUs is not easy. Summary of the Invention

[0004] In response to the above situation, embodiments of the present application provide a GPU-based shortest path calculation method, device, electronic device, and medium, which aim to solve the above problems or at least partially solve the above problems.

[0005] In the first aspect, an embodiment of the present application provides a GPU-based shortest path calculation method, the method comprising: calling different CUDA thread blocks to obtain first graph information of different target graphs from the GPU global memory, the first graph information including the vertices, edges and initial weights of the edges; for each target graph, using the corresponding CUDA thread block to calculate the second graph information of the target graph based on the first graph information of the target graph through the Bellman-Ford algorithm, and storing the second graph information in the GPU shared memory, the second graph information including the target weight of each edge in the target graph and the predecessor node of each vertex; using the corresponding CUDA thread block based on the Dijkstra algorithm and the second graph information to calculate the shortest path of each vertex pair in the target graph.

[0006] In some embodiments, the use of the corresponding CUDA thread block to calculate the second graph information of the target graph based on the first graph information of the target graph through the Bellman-Ford algorithm includes: using the corresponding CUDA thread block to determine the initial weight of each edge in the target graph and the shortest distance from the first vertex to the source point in each edge; based on the shortest distance from the first vertex to the source point and the initial weight of the edge, calculating the candidate distance from the second vertex to the source point in each edge; if the candidate distance from the second vertex to the source point is less than the shortest distance from the second vertex to the source point, determining the shortest distance from the second vertex to the source point as the candidate distance from the second vertex to the source point, and determining the predecessor node of the second vertex to be the first node; determining the target weight of the edge based on the shortest distance from the second vertex to the source point.

[0007] In some embodiments, a CUDA thread block includes multiple threads, and the multiple threads calculate target weights of multiple edges in a target graph in parallel.

[0008] In some embodiments, a flag is set in the shared memory, and the flag is used to detect whether the distances of all vertices in the target graph are updated; the method also includes: determining whether the distance of each vertex is updated based on the flag of each vertex; if it is determined that the distance of each vertex has not been updated, terminating the Bellman-Ford algorithm.

[0009] In some embodiments, the corresponding CUDA thread block is used to calculate the shortest path of each vertex in the target graph based on the Dijkstra algorithm and the second graph information, including: determining the target vertex with the smallest distance among the unvisited vertices; traversing each edge starting from the target vertex, reading the target weight of each edge and the distance to the target vertex; if the sum of the target weight of the target edge and the distance to the target vertex is less than the distance to the third vertex in the target edge, then determining the shortest path to the target vertex based on the target weight and the distance to the third vertex, and updating the predecessor node of the third vertex to the target node.

[0010] In some embodiments, an access flag is set in the GPU shared memory, and the access flag is used to indicate whether the shortest path of the vertex in the target graph has been determined; the method also includes: if the shortest path of the vertex in the target graph has been determined, updating the access flag to visited.

[0011] In some embodiments, determining the target vertex with the smallest distance among the unvisited vertices includes: searching for the target vertex with the smallest distance among the unvisited vertices in parallel using access flags in a GPU shared memory based on warp-level reduction.

[0012] In a second aspect, an embodiment of the present application further provides a GPU-based shortest path calculation device, the device comprising:

[0013] A calling module, configured to call different CUDA thread blocks to obtain first graph information of different target graphs from a GPU global memory, wherein the first graph information includes vertices, edges, and initial weights of the edges;

[0014] A processing module is used to calculate, for each target graph, second graph information of the target graph using a Bellman-Ford algorithm based on the first graph information of the target graph using a corresponding CUDA thread block, and store the second graph information in a GPU shared memory, where the second graph information includes a target weight of each edge in the target graph and a predecessor node of each vertex; and calculate the shortest path of each vertex pair in the target graph using a Dijkstra algorithm and the second graph information using a corresponding CUDA thread block.

[0015] In some embodiments, the processing module is specifically used to determine the initial weight of each edge in the target graph and the shortest distance from the first vertex to the source point in each edge using the corresponding CUDA thread block; based on the shortest distance from the first vertex to the source point and the initial weight of the edge, calculate the candidate distance from the second vertex to the source point in each edge; if the candidate distance from the second vertex to the source point is less than the shortest distance from the second vertex to the source point, determine the shortest distance from the second vertex to the source point as the candidate distance from the second vertex to the source point, and determine the predecessor node of the second vertex as the first node; determine the target weight of the edge based on the shortest distance from the second vertex to the source point.

[0016] In some embodiments, a CUDA thread block includes multiple threads, and the multiple threads calculate target weights of multiple edges in a target graph in parallel.

[0017] In some embodiments, a flag is set in the shared memory, and the flag is used to detect whether the distances of all vertices in the target graph are updated; the processing module is also used to determine whether the distance of each vertex is updated based on the flag of each vertex; if it is determined that the distance of each vertex has not been updated, the Bellman-Ford algorithm is terminated.

[0018] In some embodiments, the processing module is specifically used to determine the target vertex with the smallest distance among the unvisited vertices; traverse each edge starting from the target vertex, read the target weight of each edge and the distance to the target vertex; if the sum of the target weight of the target edge and the distance to the target vertex is less than the distance to the third vertex in the target edge, determine the shortest path to the target vertex based on the target weight and the distance to the third vertex, and update the predecessor node of the third vertex to the target node.

[0019] In some embodiments, an access flag is set in the GPU shared memory, and the access flag is used to indicate whether the shortest path of the vertex in the target graph has been determined; the processing module is also used to update the access flag to visited if the shortest path of the vertex in the target graph has been determined.

[0020] In some embodiments, the processing module is further configured to search in parallel for a target vertex with the smallest distance among unvisited vertices by using access flags in the GPU shared memory based on warp-level reduction.

[0021] In a third aspect, an embodiment of the present application further provides an electronic device comprising: a processor; and a memory arranged to store computer-executable instructions, wherein the executable instructions, when executed, cause the processor to perform the steps of the first aspect described above.

[0022] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, which stores one or more programs. When the one or more programs are executed by an electronic device including multiple applications, the electronic device performs the steps of the first aspect above.

[0023] At least one of the above technical solutions adopted in the embodiments of the present application can achieve the following beneficial effects: the embodiments of the present application store graph data in the GPU global memory, use different CUDA thread blocks to obtain the first graph information of different target graphs from the GPU global memory, and multiple CUDA thread blocks process multiple graphs in parallel, and each thread block is responsible for the calculation of a group of graphs, thereby improving the calculation speed. Further, the corresponding CUDA thread block is used to calculate the second graph information of the target graph based on the first graph information of the target graph through the Bellman-Ford algorithm, and the second graph information is stored in the GPU shared memory, and the shortest path of each vertex pair in the target graph is calculated based on the Dijkstra algorithm and the second graph information. By storing the intermediate data (first graph information) of the Bellman-Ford algorithm in the GPU shared memory, the Dijkstra algorithm can directly call the data stored in the GPU shared memory, reduce the frequent access to the GPU global memory, avoid the additional overhead of multiple reading and writing of the global memory, reduce the pressure on the memory bandwidth, and greatly shorten the delay of the Bellman-Ford algorithm and the Dijkstra algorithm, thereby improving the calculation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0025] Figure 1 A schematic diagram of a process for calculating the shortest path based on a GPU according to an embodiment of the present application is shown;

[0026] Figure 2 A flowchart of a GPU-based shortest path calculation method provided by another embodiment of the present application is shown;

[0027] Figure 3 A flowchart of a GPU-based shortest path calculation method according to another embodiment of the present application is shown;

[0028] Figure 4 The following is a structural diagram of a GPU-based shortest path calculation device provided in an embodiment of the present application;

[0029] Figure 5 A schematic structural diagram of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0030] To make the purpose, technical solutions, and advantages of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the specific embodiments of this application and the corresponding drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0031] It should be noted that the terms "first," "second," and the like in the specification and claims of this application and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that such usage is interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the term "including" and its variations are to be interpreted as open-ended terms meaning "including but not limited to."

[0032] As mentioned in the background, with the increasing parallel computing capabilities of graphics processing units (GPUs), using GPUs to accelerate graph algorithms has become a new trend. However, porting the Johnson algorithm directly to GPUs is not easy. The Johnson algorithm takes too long to compute on large graphs, making it difficult to meet practical needs.

[0033] Based on this, the present application proposes a GPU-based shortest path calculation method, which stores graph data in the GPU global memory, uses different compute unified device architecture (CUDA) thread blocks to obtain the first graph information of different target graphs from the GPU global memory, and multiple CUDA thread blocks process multiple graphs in parallel. Each thread block is responsible for the calculation of a group of graphs, thereby improving the calculation speed. Furthermore, the corresponding CUDA thread block is used to calculate the second graph information of the target graph based on the first graph information of the target graph through the Bellman-Ford algorithm, and the second graph information is stored in the GPU shared memory. Based on the Dijkstra algorithm and the second graph information, the shortest path of each vertex pair in the target graph is calculated. By storing the intermediate data (first graph information) of the Bellman-Ford algorithm in the GPU shared memory, the frequent access to the GPU global memory is reduced, the additional overhead of multiple reading and writing of the global memory is avoided, the memory bandwidth pressure is reduced, and the delay of the Bellman-Ford algorithm and the Dijkstra algorithm is greatly shortened, thereby improving the calculation efficiency.

[0034] The present application is described in detail below through specific embodiments.

[0035] Figure 1 The flowchart of the GPU-based shortest path calculation method provided by the embodiment of the present application is shown. Figure 1 It can be seen that this application at least includes steps S101 to S103:

[0036] Step S101: different CUDA thread blocks are called to obtain first graph information of different target graphs from the GPU global memory, where the first graph information includes vertices, edges and initial weights of the edges.

[0037] In traditional graph computing, processing multiple graphs usually requires computing each graph one by one, which is inefficient. The present application proposes a multi-graph parallel processing method that stores the first graph information of multiple graphs in the GPU global memory and uses CUDA kernel functions to call the first graph information of different target graphs through different CUDA thread blocks, thereby processing multiple graphs in parallel at one time through different CUDA thread blocks.

[0038] Specifically, before processing the graphs, the vertex, edge, and weight data of multiple graphs are stored in compressed form in the GPU global memory. A fixed amount of memory is allocated to each graph as shared memory to store temporary data generated during the shortest path calculation process, such as vertex distances, predecessor nodes, and access flags. This layout ensures the compactness and accessibility of graph data in the graphics memory.

[0039] In an embodiment of the present application, each CUDA thread block is responsible for processing the calculation of a set of graphs. By setting the number of thread blocks and the number of graphs each thread block is responsible for (for example, by setting the graphsPerBlock parameter), the computing resources of the GPU can be efficiently utilized to achieve parallel processing of multiple graphs. For example, if there are 10 graphs that need to be calculated for the shortest path, 10 thread blocks can be set, one thread block is responsible for the calculation of one graph, and parallel processing of 10 graphs can be achieved; or 5 thread blocks can be set, each thread block is responsible for the calculation of two graphs, and parallel processing of 5 graphs can be achieved.

[0040] Furthermore, within each graph, each thread in a CUDA thread block is responsible for computing one or more vertices or edges. Thread collaboration is achieved through shared memory and warp-level synchronization, avoiding cross-thread block communication overhead.

[0041] Step S102: For each target graph, use the corresponding CUDA thread block to calculate the second graph information of the target graph based on the first graph information of the target graph through the Bellman-Ford algorithm, and store the second graph information in the GPU shared memory. The second graph information includes the target weight of each edge in the target graph and the predecessor node of each vertex.

[0042] In step S102, information such as the distance and predecessor nodes of each graph is stored in the GPU shared memory instead of the global memory. Since the shared memory has a lower access latency, the memory access overhead in each relaxation operation is significantly reduced.

[0043] Calculating the second graph information using the Bellman-Ford algorithm in step S102 can be specifically implemented as steps S1021-S1024:

[0044] Step S1021: using the corresponding CUDA thread block to determine the initial weight of each edge in the target graph and the shortest distance from the first vertex of each edge to the source point.

[0045] Step S1022: Based on the shortest distance from the first vertex to the source point and the initial weight of the edge, calculate the candidate distance from the second vertex to the source point in each edge.

[0046] Step S1023: If the candidate distance from the second vertex to the source point is less than the shortest distance from the second vertex to the source point, determine the shortest distance from the second vertex to the source point as the candidate distance from the second vertex to the source point, and determine the predecessor node of the second vertex as the first node.

[0047] Step S1024: Determine the target weight of the edge based on the shortest distance from the second vertex to the source point.

[0048] In step S102, a flag bit is set in the shared memory, and the flag bit is used to detect whether the distances of all vertices in the target graph have been updated. In each iteration, the flag bits (such as anyChange and shouldExit) in the shared memory are used to detect whether the distances of all vertices have converged. If the distances of all vertices have not changed, the iteration is exited early to avoid unnecessary calculations. Compared with the traditional implementation where the Bellman-Ford algorithm needs to perform (V - 1) fixed iterations, the present invention reduces the number of iterations through this mechanism.

[0049] During the relaxation process of the Bellman-Ford algorithm, warp-level synchronization operations (such as __shfl_*) are used to efficiently exchange thread data within the warp and reduce the overhead of thread synchronization.

[0050] Reference Figure 2 As shown, the calculation process of the embodiment of the present application using the optimized Bellman-Ford algorithm is as follows:

[0051] Initialization phase: Initialize the distance array (distances), the predecessor node array (predecessors), and the flag bit (anyChange = false) in the thread block.

[0052] Parallel edge processing: Each thread traverses an edge in the graph in parallel, reads the start point (src), end point (dst), weight (weight), and the current distance value of the start point.

[0053] Relaxation operation: Calculate the new path distance (newDist = distances[src] + weight). If the new distance is less than the current distance of the end point (newDist < distances[dst]), update the distance value and the predecessor node of the end point, and mark anyChange = true to indicate a state change. <![CDATA[ ]]>

[0054] Synchronization and termination judgment: Synchronize all threads through the shared memory and check the anyChange flag. If no update has occurred (anyChange == false), set shouldExit = true and exit the loop early; otherwise, reset the flag and continue the iteration.

[0055] Dynamic weight adjustment: Recalculate the edge weights after synchronization. Data is communicated between threads through the shared memory, and the final result is stored in the GPU global memory.

[0056] Step S103: Calculate the shortest paths between each pair of vertices in the target graph using the corresponding CUDA thread block based on the Dijkstra algorithm and the second graph information.

[0057] Specifically, determine the target vertex with the smallest distance among the unvisited vertices; traverse each edge starting from the target vertex, read the target weight of each edge and the distance to the target vertex; if the sum of the target weight of the target edge and the distance to the target vertex is less than the distance to the third vertex in the target edge, determine the shortest path to the target vertex based on the target weight and the distance to the third vertex, and update the predecessor node of the third vertex to the target node.

[0058] An access flag is set in the GPU shared memory to indicate whether the shortest path to a vertex in the target graph has been determined. If the shortest path to a vertex in the target graph has been determined, the access flag is updated to "visited." This embodiment of the application stores data such as the distance, predecessor, and access flag of each graph in shared memory to avoid frequent access to global memory. The access flag in shared memory is used to mark vertices that have been visited, thereby avoiding repeated calculations.

[0059] Based on warp-level reduction, the target vertex with the smallest distance among the unvisited vertices is searched in parallel in the GPU shared memory through the access flag. In each iteration, the vertex with the smallest distance among the unvisited vertices needs to be selected. The embodiment of the present application uses warp-level reduction operations, and through CUDA primitives such as __shfl_xor_sync, it efficiently exchanges data between threads within the warp and completes the reduction, thereby quickly finding the minimum distance vertex. This operation avoids the reduction operation that relies on shared memory or global memory in traditional implementations, significantly reducing latency.

[0060] After the Dijkstra algorithm completes, the calculated shortest path distance is uniformly adjusted to avoid repeated distance adjustments in each iteration. This design avoids additional computational overhead while maintaining the accuracy of the algorithm results.

[0061] refer to Figure 3 FIG. 4 shows the calculation process of the optimized Dijkstra algorithm according to the embodiment of the present application, which is as follows:

[0062] Initialization: Initialize distances (distance array), predecessors (predecessors array), and anyChange (status flag).

[0063] Set the initial state: anyChange = false (marks whether an update occurs).

[0064] Parallel loop processes all edges: read the edge's starting point src, end point dst, weight weight, and distances[src] (current starting point distance value).

[0065] Calculate the new distance newDist = distances[src] + weight.

[0066] Conditional judgment: If newDist < distances[dst] (the new distance is better), update distances[dst] = newDist, and update predecessor[s][dst] = src (record the predecessor node). Set anyChange = true (mark the status change).

[0067] Thread synchronization: All threads are synchronized to ensure data consistency. Check the anyChange flag in the shared memory.

[0068] Exit condition judgment: If anyChange == false (no updates have occurred), set shouldExit = true (mark early exit). Break out of the loop and terminate the algorithm.

[0069] From Figure 1 As can be seen from the method shown above, in this application, the graph data is stored in the GPU global memory, and different CUDA thread blocks are used to obtain the first graph information of different target graphs from the GPU global memory. Multiple CUDA thread blocks process multiple graphs in parallel, and each thread block is responsible for the calculation of a group of graphs, improving the calculation speed. Further, using the corresponding CUDA thread block, based on the first graph information of the target graph, the second graph information of the target graph is calculated through the Bellman - Ford algorithm, and the second graph information is stored in the GPU shared memory. Based on the Dijkstra algorithm and the second graph information, the shortest paths between each pair of vertices in the target graph are calculated. By storing the intermediate data (the first graph information) of the Bellman - Ford algorithm in the GPU shared memory, the frequent access to the GPU global memory is reduced, avoiding the additional overhead of multiple read - writes to the global memory, reducing the memory bandwidth pressure, significantly shortening the latency of the Bellman - Ford algorithm and the Dijkstra algorithm, and improving the calculation efficiency.

[0070] In the traditional implementation of GPU graph algorithms, the logic of different stages is usually split into multiple kernel functions, and multiple kernel function calls are initiated by the CPU between stages. However, this method has the following problems: Each kernel function call introduces additional CPU - GPU synchronization overhead. The data between different stages needs to be written back to the global memory multiple times, increasing the overhead of global memory access.

[0071] The embodiment of this application proposes a single kernel function implementation method, which integrates the logic of the Bellman - Ford algorithm and the Dijkstra algorithm into a single CUDA kernel function, avoiding the overhead of multiple kernel function calls. The specific implementation is as follows:

[0072] Logical integration: In a single-core function, the Bellman-Ford algorithm is first executed to calculate the reweighted distance, then all edges are reweighted, and finally the Dijkstra algorithm is executed to calculate the shortest path.

[0073] Memory reuse: Data areas in shared memory and global memory are reused across different phases to reduce video memory usage. For example, the distance array in the Bellman-Ford phase can continue to be used as the distance array for shortest path calculation in the Dijkstra phase.

[0074] Inter-stage dependency optimization: Data dependencies between stages are directly passed through shared memory, avoiding multiple writes and reads to global memory.

[0075] This design not only reduces the CPU-GPU communication overhead, but also improves the overall running efficiency of the kernel function.

[0076] In some embodiments of the present application, a device for calculating the shortest path in a graph is provided, and the device for calculating the shortest path in the graph corresponds one-to-one to the method for calculating the shortest path in the graph in the above embodiment. Figure 4 As shown in the figure, the shortest path calculation device includes a calling module 101 and a processing module 102.

[0077] A calling module 101 is configured to call different CUDA thread blocks to obtain first graph information of different target graphs from a GPU global memory, where the first graph information includes vertices, edges, and initial weights of the edges;

[0078] Processing module 102 is used to calculate, for each target graph, second graph information of the target graph using the Bellman-Ford algorithm based on the first graph information of the target graph using the corresponding CUDA thread block, and store the second graph information in the GPU shared memory, where the second graph information includes the target weight of each edge in the target graph and the predecessor node of each vertex; and calculate the shortest path of each vertex pair in the target graph using the Dijkstra algorithm and the second graph information using the corresponding CUDA thread block.

[0079] In some embodiments of the present application, in the above-mentioned device, the processing module 102 is specifically used to use the corresponding CUDA thread block to determine the initial weight of each edge in the target graph and the shortest distance from the first vertex to the source point in each edge; based on the shortest distance from the first vertex to the source point and the initial weight of the edge, calculate the candidate distance from the second vertex to the source point in each edge; if the candidate distance from the second vertex to the source point is less than the shortest distance from the second vertex to the source point, determine the shortest distance from the second vertex to the source point as the candidate distance from the second vertex to the source point, and determine the predecessor node of the second vertex as the first node; determine the target weight of the edge based on the shortest distance from the second vertex to the source point.

[0080] In some embodiments of the present application, in the above-mentioned apparatus, a CUDA thread block includes multiple threads, and the multiple threads calculate target weights of multiple edges in a target graph in parallel.

[0081] In some embodiments of the present application, in the above-mentioned device, a flag is set in the shared memory, and the flag is used to detect whether the distances of all vertices in the target graph are updated; the processing module 102 is also used to determine whether the distance of each vertex is updated based on the flag of each vertex; if it is determined that the distance of each vertex has not been updated, the Bellman-Ford algorithm is terminated.

[0082] In some embodiments of the present application, in the above-mentioned device, the processing module 102 is specifically used to determine the target vertex with the smallest distance among the unvisited vertices; traverse each edge starting from the target vertex, and read the target weight of each edge and the distance to the target vertex; if the sum of the target weight of the target edge and the distance to the target vertex is less than the distance to the third vertex in the target edge, then determine the shortest path to the target vertex based on the target weight and the distance to the third vertex, and update the predecessor node of the third vertex to the target node.

[0083] In some embodiments of the present application, in the above-mentioned device, an access flag is set in the GPU shared memory, and the access flag is used to indicate whether the shortest path has been determined for the vertex in the target graph; the processing module 102 is also used to update the access flag to visited if the shortest path has been determined for the vertex in the target graph.

[0084] In some embodiments of the present application, in the above apparatus, the processing module 102 is further configured to search in parallel for a target vertex with the smallest distance among unvisited vertices by using access flags in the GPU shared memory based on warp-level reduction.

[0085] It should be noted that any of the above-mentioned devices for calculating the shortest path in a graph can implement the above-mentioned method for calculating the shortest path in a graph in a one-to-one correspondence, which will not be repeated here.

[0086] Figure 5FIG. 1 shows a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Figure 5 As shown, at the hardware level, the electronic device includes a processor and, optionally, an internal bus, a network interface, and memory. The memory may include internal memory, such as high-speed random-access memory (RAM), and may also include non-volatile memory, such as at least one disk storage device. Of course, the electronic device may also include other hardware required for its services.

[0087] The processor, network interface, and memory can be interconnected through an internal bus, which can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus. Buses can be divided into address buses, data buses, control buses, etc. For ease of representation, Figure 5 Only one bidirectional arrow is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0088] The memory is used to store programs. Specifically, the program may include program code, which includes computer operating instructions. The memory may include internal memory and non-volatile memory, and provides instructions and data to the processor.

[0089] The processor reads the corresponding computer program from the non-volatile memory into the internal memory and then runs it, forming a calculation device for the shortest path in the graph at the logical level. The processor executes the program stored in the memory and is specifically used to perform the aforementioned method.

[0090] The processor may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by hardware integrated logic circuits in the processor or by software instructions. The above processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The various methods, steps, and logic block diagrams disclosed in the embodiments of this application can be implemented or executed. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the embodiments of this application can be directly implemented and executed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium mature in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0091] The electronic device can execute the method for calculating the shortest path in a graph provided by multiple embodiments of the present application, and realize the calculation device of the shortest path in the graph. Figure 4 The functions of the illustrated embodiment will not be described in detail in the embodiments of the present application.

[0092] An embodiment of the present application also proposes a computer-readable storage medium, which stores one or more programs, and the one or more programs include instructions. When the instructions are executed by an electronic device including multiple application programs, the electronic device can execute the method for calculating the shortest path in the graph provided by multiple embodiments of the present application.

[0093] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0094] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0095] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0096] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0097] In a typical configuration, a computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory.

[0098] Memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0099] Computer-readable media includes permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. The information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory computer-readable media (transitory media), such as modulated data signals and carrier waves.

[0100] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0101] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0102] The above are merely embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

Claims

1. A GPU-based shortest path calculation method, characterized in that: The method comprises: Calling different CUDA thread blocks to obtain first graph information of different target graphs from the GPU global memory, where the first graph information includes vertices, edges, and initial weights of the edges; For each target graph, using a corresponding CUDA thread block to calculate second graph information of the target graph based on the first graph information of the target graph using the Bellman-Ford algorithm, and storing the second graph information in GPU shared memory, the second graph information includes the target weight of each edge in the target graph and the predecessor node of each vertex; The corresponding CUDA thread block is used to calculate the shortest path of each vertex pair in the target graph based on the Dijkstra algorithm and the second graph information.

2. The method according to claim 1, characterized in that The calculating the second graph information of the target graph by using the corresponding CUDA thread block based on the first graph information of the target graph by using the Bellman-Ford algorithm includes: Use the corresponding CUDA thread block to determine the initial weight of each edge in the target graph and the shortest distance from the first vertex of each edge to the source point; Based on the shortest distance from the first vertex to the source and the initial weight of the edge, calculate the candidate distance from the second vertex to the source in each edge; If the candidate distance from the second vertex to the source point is less than the shortest distance from the second vertex to the source point, determining the shortest distance from the second vertex to the source point as the candidate distance from the second vertex to the source point, and determining the predecessor node of the second vertex as the first node; A target weight of the edge is determined based on the shortest distance from the second vertex to the source point.

3. The method according to claim 2, characterized in that A CUDA thread block includes multiple threads, and the multiple threads calculate the target weights of multiple edges in the target graph in parallel.

4. The method according to any one of claims 1 to 3, characterized in that A flag is set in the shared memory, and the flag is used to detect whether the distances of all vertices in the target graph are updated; The method further comprises: Determine whether the distance of each vertex is updated based on the flag bit of each vertex; If it is determined that the distance of each vertex has not been updated, terminate the Bellman-Ford algorithm.

5. The method according to claim 1, wherein Utilizing the corresponding CUDA thread block based on the Dijkstra algorithm and the second graph information, the shortest path of each vertex in the target graph is calculated, including: Determine the target vertex with the smallest distance among the unvisited vertices; Traverse each edge starting from the target vertex and read the target weight of each edge and the distance to the target vertex; If the sum of the target weight of the target edge and the distance to the target vertex is less than the distance to the third vertex in the target edge, the shortest path to the target vertex is determined based on the target weight and the distance to the third vertex, and the predecessor node of the third vertex is updated to the target node.

6. The method according to claim 5, characterized in that An access flag is set in the GPU shared memory, and the access flag is used to indicate whether the shortest path of the vertex in the target graph has been determined; the method further includes: If the shortest path has been determined for the vertex in the target graph, the visit flag is updated to visited.

7. The method according to claim 6, characterized in that Determining the target vertex with the smallest distance among the unvisited vertices includes: Based on warp-level reduction, the target vertex with the smallest distance among the unvisited vertices is searched in parallel in the GPU shared memory using the access flag.

8. A GPU-based shortest path calculation device, characterized in that: The device comprises: A calling module, configured to call different CUDA thread blocks to obtain first graph information of different target graphs from a GPU global memory, wherein the first graph information includes vertices, edges, and initial weights of the edges; A processing module is used to calculate, for each target graph, second graph information of the target graph using a Bellman-Ford algorithm based on the first graph information of the target graph using a corresponding CUDA thread block, and store the second graph information in a GPU shared memory, where the second graph information includes a target weight of each edge in the target graph and a predecessor node of each vertex; and calculate the shortest path of each vertex pair in the target graph using a Dijkstra algorithm and the second graph information using a corresponding CUDA thread block.

9. An electronic device comprising: processor; as well as A memory arranged to store computer-executable instructions, wherein when the instructions are executed, the processor performs the steps of the GPU-based shortest path calculation method according to any one of claims 1 to 7.

10. A computer-readable storage medium storing one or more programs, which, when executed by an electronic device including a plurality of application programs, enable the electronic device to perform the steps of the GPU-based shortest path calculation method according to any one of claims 1 to 7.

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