Variable cache system

Abstract

The application relates to the technical field of cache management, in particular to a variable cache system. When a data access request is missed, the system determines a reference cache line from all cache lines according to a first size and a second size, guarantees that the reference cache line is aligned, improves the efficiency of cache replacement based on the reference cache line, and the cache line corresponds to a data type identifier used to indicate whether the corresponding cache line is a main cache line. The main cache line and the slave cache line can jointly store a single data, so that a larger data size can be realized with a smaller second size, the utilization rate of the cache space is improved, and in addition, whether the target cache line and the associated cache line are replaced to store target data is determined according to the state identifier of the target cache line and the associated cache line determined from the reference cache line, so that the target data of different first sizes can be flexibly stored in the target cache, and the compatibility of the target cache for the data size is guaranteed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of cache management, in particular to a variable cache system. BACKGROUND

[0002] At present, in the scene of implementing the function of graphics processing by GPU chip, the cache needs to store the attribute data of the vertex to improve the reading efficiency of the attribute data of the vertex, and then improve the efficiency of executing the function of graphics processing.

[0003] The size of the attribute data of the vertex is usually configurable, for example, the user can configure the size of the attribute data of the vertex to be 0 bytes to 128 bytes. In the prior art, in order to support the storage of attribute data of different sizes, the data size that can be cached by a single cache line in the cache is usually determined according to the maximum size of the attribute data.

[0004] However, in the case that most of the attribute data has a small size, for example, most of the attribute data has a size of 32 bytes, the size of the data stored by a single cache line may only account for 1 / 4 of the storage capacity of the cache line. Obviously, such a situation will result in low utilization of cache space.

[0005] Therefore, how to improve the utilization of cache space has become a problem to be solved. SUMMARY

[0006] In order to solve the above technical problems, the technical scheme adopted by the present application is as follows:

[0007] A variable cache system, the system comprises a target cache, a processor and a memory storing a computer program, wherein the target cache comprises M cache lines, the cache line comprises cache identification information and a cache data block, the cache identification information comprises data type identification and state identification, the cache data block corresponds to a first size, and M is a positive integer. When the computer program is executed by the processor, the following steps are implemented:

[0008] S101, when receiving a data access request, determining a first hit condition of target data corresponding to the data access request in the target cache.

[0009] S102, if the first hit condition is a miss, determining a plurality of reference cache lines from the M cache lines according to the first size and a second size of the target data corresponding to the data access request.

[0010] S103, determining a target cache line from each reference cache line whose data type identification is a first preset value.

[0011] S104, determining a plurality of associated cache lines corresponding to the target cache line according to the first size and the second size.

[0012] S105, if the state identifier of the target cache line and the state identifier of the associated cache line corresponding to the target cache line both satisfy a first preset condition, taking the target cache line and the associated cache line as replacement cache lines, and taking each replacement cache line as a target cache space for storing the target data.

[0013] S106, if any of the state identifier of the target cache line and the state identifier of the associated cache line corresponding to the target cache line does not satisfy the first preset condition, returning to execute the step of determining the target cache line from each reference cache line with the data type identifier being the first preset value until the target cache space is obtained.

[0014] Compared with the prior art, the variable cache system provided by the application has obvious beneficial effects, and has the following beneficial effects at least:

[0015] When the data access request does not hit in the target cache, the reference cache line is determined from all cache lines according to the first size of the cache data block and the second size of the target data, the reference cache line is guaranteed to be aligned, the efficiency of cache replacement based on the reference cache line is improved, the cache line has a data type identifier to indicate whether the corresponding cache line is a main cache line, the main cache line and the slave cache line can store a single data together, so that a larger data size can be stored with a smaller second size, the utilization rate of the cache space is improved, and whether the target cache line and the associated cache line are replaced to store the target data is determined according to the state identifier of the target cache line and the associated cache line determined from the reference cache line, so that different first sizes of the target data can be stored in the target cache flexibly, and the compatibility of the target cache for the data size is guaranteed. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0017] Figure 1 A flowchart of a computer program in a variable cache system provided by the embodiment of the application when executed by a processor. DETAILED DESCRIPTION

[0018] With reference to the accompanying drawings, the technical solutions in the embodiments of the present application will be clearly and completely described below, obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0019] The embodiment provides a variable cache system, see Figure 1 A flowchart of a computer program in a variable cache system provided by the embodiment of the present application is executed by a processor, the system comprises a target cache, a processor and a memory storing a computer program, wherein the target cache comprises M cache lines, the cache line comprises cache identification information and a cache data block, the cache identification information comprises data type identification and state identification, the cache data block corresponds to a first size, M is a positive integer, when the computer program is executed by the processor, the following steps are realized:

[0020] S101, when receiving a data access request, determining a first hit condition of target data corresponding to the data access request in the target cache;

[0021] S102, if the first hit condition is a miss, determining a plurality of reference cache lines from the M cache lines according to the first size and a second size of the target data corresponding to the data access request;

[0022] S103, determining a target cache line from each reference cache line whose data type identification is a first preset value;

[0023] S104, determining a plurality of associated cache lines corresponding to the target cache line according to the first size and the second size;

[0024] S105, if the state identification of the target cache line and the state identification of the associated cache lines corresponding to the target cache line both satisfy a first preset condition, taking the target cache line and the associated cache lines as replacement cache lines, and taking each replacement cache line as a target cache space for storing the target data;

[0025] S106, if any of the state identification of the target cache line and the state identification of the associated cache lines corresponding to the target cache line does not satisfy the first preset condition, returning to execute the step of determining a target cache line from each reference cache line whose data type identification is a first preset value until the target cache space is obtained.

[0026] The target cache can be used to store data frequently accessed by a GPU chip in a graphics processing task, such as vertex data, texture data, etc.

[0027] The cache identification information can be used to determine whether the data in the corresponding cache line is required by the data access request when the data access request is received, and to perform lookup, comparison and replacement operations in cache management.

[0028] The data access request can refer to an access request for target data. The data access request can include a request address of the target data, a request type identifier, and a request sub-identifier quantity. In this embodiment, the target data can be stored in a plurality of consecutive cache lines. Therefore, the data access request corresponds to a main cache line in which the target data is stored.

[0029] The first hit condition can represent a hit condition of the target data corresponding to the data access request in the target cache, that is, whether the target data is stored in the target cache. When the target data is stored in the target cache, the first hit condition is a hit. When the target data is not stored in the target cache, the first hit condition is a miss.

[0030] The reference cache line can be a cache line that can serve as a main cache line for storing the target data. The first preset value can be 1. When the data type identifier is 1, the data type identifier corresponds to a main identifier, indicating that the corresponding cache line is a main cache line for storing data. When the data type identifier is 0, the data type identifier corresponds to a sub-identifier, indicating that the corresponding cache line is a sub-cache line for storing data.

[0031] The associated cache line can be a sub-cache line associated with the target cache line when the target cache line serves as a main cache line for storing the target data. A single main cache line can correspond to 0 to K / M-1 sub-cache lines. K is the maximum data storage size supported in this embodiment.

[0032] The first preset condition can be used to determine whether the target cache line and its associated cache line are replaceable. The target cache space is used for replacement to store the target data read from the memory, thereby realizing caching of the target data.

[0033] In a specific implementation, when the data access request is received, the first hit condition of the target data corresponding to the data access request in the target cache is determined, including:

[0034] When the data access request is received, a plurality of temporary cache lines are determined from the M cache lines according to the first size and a second size of the target data corresponding to the data access request.

[0035] According to the request identification information corresponding to the data access request and the cache identification information corresponding to each temporary cache line, respectively, the second hit condition of each temporary cache line is determined.

[0036] If the second hit condition of any temporary cache line is hit, it is determined that the first hit condition is hit, and the access result of the data access request is determined according to the temporary cache line with the second hit condition being hit;

[0037] If the hit condition of each temporary cache line is miss, it is determined that the first hit condition is miss.

[0038] The temporary cache line can be a cache line that can be a target data storage main cache line, and the second hit condition can represent the hit condition of the corresponding temporary cache line. When the second hit condition of the temporary cache line is hit, it means that the temporary cache line is a main cache line for storing target data, and the temporary cache line and each sub-cache line corresponding thereto have stored target data. At this time, the target data can be directly obtained from the target cache without reading from the memory.

[0039] Specifically, the cache line index included in the cache identification information corresponding to each cache line can represent the position of the cache line in the target cache. In general, each cache line is arranged continuously in the target cache. According to the temporary cache line with the second hit condition being hit, the cache line index corresponding to the temporary cache line with the second hit condition being hit can be increased by 1 to obtain an updated index. The data type identifier of the cache line corresponding to the updated index is judged. If the data type identifier of the cache line corresponding to the updated index is the second preset value, the cache data block in the cache line corresponding to the updated index is taken as the target sub-data. The updated index is increased by 1 to obtain a new updated index. The step of judging the data type identifier of the cache line corresponding to the updated index is returned to be executed until the data type identifier of the cache line corresponding to the updated index is the first preset value, or the updated index exceeds the maximum cache line index. The access result of the data access request is formed by the temporary cache line corresponding to the cache data block and each target sub-data. The maximum cache line index can be determined according to the ratio of the data capacity of the target cache to the first size corresponding to the cache data block of a single cache line. The second preset value can be 0.

[0040] In a specific embodiment, the determination of the temporary cache lines from the M cache lines according to the first size and the second size of the target data corresponding to the data access request comprises:

[0041] The second size is compared with the first size to obtain a first ratio;

[0042] A plurality of temporary indexes are determined according to a preset cache line index, the first ratio, and the number M of cache lines.

[0043] Each cache line corresponding to each temporary index in the M cache lines is taken as a temporary cache line.

[0044] wherein the first ratio can be used to represent the number of cache lines required for storing the target data, and the preset cache line index can be the minimum cache line index, which can be 0 in this embodiment.

[0045] Specifically, according to the preset cache line index, the first ratio and the number of cache lines M, a plurality of temporary indexes can be determined, which can mean that the preset cache line index and the first ratio are added to obtain a first intermediate index, if the first intermediate index is less than or equal to M, the first intermediate index is determined as a temporary index, the first intermediate index and the first ratio are added to update the first intermediate index, if the first intermediate index is less than or equal to M, the first intermediate index is determined as a temporary index, and the step of adding the first intermediate index and the first ratio to update the first intermediate index is returned to be executed until the first intermediate index is greater than M, and a plurality of temporary indexes are obtained.

[0046] In a specific embodiment, the request identification information includes a request type identification, a request sub-identification number and a request address, and the cache identification information further includes a cache sub-identification number and a cache address.

[0047] The second hit condition of each temporary cache line is determined according to the request identification information corresponding to the data access request and the cache identification information corresponding to each temporary cache line, which includes:

[0048] For any temporary cache line, the request type identification and the cache type identification of the temporary cache line are compared to obtain a first comparison result;

[0049] The request sub-identification number and the cache sub-identification number of the temporary cache line are compared to obtain a second comparison result;

[0050] The request address and the cache address of the temporary cache line are compared to obtain a third comparison result;

[0051] If the first comparison result, the second comparison result and the third comparison result are all consistent, it is determined that the second hit condition of the temporary cache line is hit, otherwise, it is determined that the second hit condition of the temporary cache line is not hit.

[0052] Wherein the cache identification information of the main cache line can include a data type identification, a state identification, a cache sub-identification number and a cache address, the cache sub-identification number can be the number of cache lines associated with the corresponding sub-identification of the cache line corresponding to the main identification, and the cache address can be the corresponding memory address of the cache data block in the memory in the cache line corresponding to the main identification, and the cache identification information of the sub-cache line can include a data type identification and a state identification.

[0053] The first comparison result, the second comparison result and the third comparison result each include two cases of comparison consistency and comparison inconsistency.

[0054] In a specific embodiment, the state identifier includes a valid identifier;

[0055] Correspondingly, for any temporary cache line, the request type identifier and the cache type identifier of the temporary cache line are compared to obtain a first comparison result, including:

[0056] For any temporary cache line, if the valid identifier of the temporary cache line is a second preset value, it is determined that the second hit condition of the temporary cache line is a miss;

[0057] Otherwise, the request type identifier and the cache type identifier of the temporary cache line are compared to obtain a first comparison result.

[0058] The valid identifier can be used to represent the validity of the data in the corresponding cache line. When the valid identifier is a second preset value, it indicates that the data in the corresponding cache line is invalid. When the valid identifier is a first preset value, it indicates that the data in the corresponding cache line is valid.

[0059] Specifically, in order to improve the hit judgment efficiency, the embodiment first judges the valid identifier of the temporary cache line. When the valid identifier of the temporary cache line is a second preset value, it is determined that the second hit condition of the temporary cache line is a miss, and subsequent comparison is not required. When the valid identifier of the temporary cache line is a first preset value, subsequent comparison is performed.

[0060] In an embodiment, after obtaining the first comparison result, if the first comparison result is comparison consistency, the request sub-identifier quantity and the cache sub-identifier quantity of the temporary cache line are compared to obtain a second comparison result. After obtaining the second comparison result, if the second comparison result is comparison consistency, the request address and the cache address of the temporary cache line are compared to obtain a third comparison result, thereby further improving the hit judgment efficiency.

[0061] In a specific embodiment, after the target cache line and its associated cache lines are all taken as replacement cache lines, the method further includes:

[0062] The valid identifier of the target cache line and the valid identifiers corresponding to each cache line related to the target cache line are each set to the second preset value.

[0063] After the target cache line and its associated cache lines are all taken as replacement cache lines, the valid identifier of the target cache line and the valid identifiers corresponding to each cache line related to the target cache line are each set to the second preset value, so as to facilitate subsequent replacement of the target cache line and each cache line related thereto.

[0064] The cache lines related to the target cache line can refer to the cache lines that store the same data as the target cache line before replacement.

[0065] It should be noted that the number of the second replacement cache lines can be less than or equal to the number of the sub-cache lines related to the target cache line before replacement, so as to flexibly support the cache of data of different sizes. For example, when the second size is 32 bytes, the number of the sub-cache lines related to the target cache line before replacement is 3, that is, the data corresponding to the target cache line before replacement is 128 bytes, and the number of the second replacement cache lines can be 1 during replacement, that is, the target data is 64 bytes. At this time, the sub-cache lines related to the target cache line which are not the second replacement cache lines also need to set the valid identifier to the second preset value to avoid reading incomplete data. The reference index of the sub-cache lines related to the target cache line is greater than the reference index of the corresponding target cache line and less than the reference index of the next target cache line.

[0066] In a specific embodiment, the determining of the reference cache lines from the M cache lines according to the first size and the second size of the target data corresponding to the data access request comprises:

[0067] determining a plurality of reference indexes according to the reference cache line index, the first ratio and the number M of the cache lines;

[0068] each cache line corresponding to each reference index in the M cache lines is regarded as a reference cache line.

[0069] The reference cache line index can be the minimum cache line index, and in this embodiment, the reference cache line index can be 0.

[0070] Specifically, the determining of the plurality of reference indexes according to the reference cache line index, the first ratio and the number M of the cache lines can refer to adding the reference cache line index and the first ratio to obtain a second intermediate index. If the second intermediate index is less than or equal to M, the second intermediate index is determined as a reference index. The second intermediate index and the first ratio are added to update the second intermediate index. If the second intermediate index is less than or equal to M, the second intermediate index is determined as a reference index. The step of adding the second intermediate index and the first ratio to update the second intermediate index is returned to be executed until the second intermediate index is greater than M, and the plurality of reference indexes are obtained.

[0071] The embodiment needs to meet the cache line alignment when determining the reference cache line, so as to improve the efficiency of the cache line replacement process, and then meet the time delay limit of data reading, and avoid that the cache line replacement speed becomes the bottleneck of the data reading efficiency.

[0072] In a specific implementation, the determining the plurality of associated cache lines corresponding to the target cache line according to the first size and the second size comprises:

[0073] increasing the reference index corresponding to the target cache line by one to obtain a first associated index;

[0074] adding the reference index corresponding to the target cache line and the first ratio and then subtracting one to obtain a second associated index;

[0075] taking the cache lines corresponding to the first associated index and the second associated index respectively as the associated cache lines corresponding to the target cache line.

[0076] The cache lines corresponding to the first associated index and the second associated index respectively can be the sub-cache lines associated with the target cache line when the target cache line is taken as the main cache line storing target data.

[0077] In a specific implementation, the state identifier comprises a use identifier and an intermediate identifier.

[0078] The first preset condition is that the use identifier and the intermediate identifier are both second preset values.

[0079] The use identifier can represent whether the corresponding cache line is in use, and the intermediate identifier can represent whether the corresponding cache line is in a state of reading data from the memory. When the use identifier and the intermediate identifier are both second preset values, it can be considered that the corresponding cache line is neither in use nor in a state of reading data from the memory, and the corresponding cache line can be replaced.

[0080] Specifically, when the use identifier and the intermediate identifier in the state identifier of the target cache line are both second preset values, and the use identifier and the intermediate identifier in the state identifier of each associated cache line of the target cache line are both second preset values, it can be considered that the data stored in the target cache line and the associated cache lines can be replaced.

[0081] In the embodiment, when the data access request is not hit in the target cache, the reference cache line is determined from all cache lines according to the first size of the cache data block and the second size of the target data, the reference cache line is guaranteed to be aligned, the efficiency of cache replacement based on the reference cache line is improved, the cache line corresponds to a data type identifier, which is used to indicate whether the corresponding cache line is a main cache line, the main cache line and the slave cache line can jointly store a single data, so that a larger data size can be stored with a smaller second size, the utilization of the cache space is improved, and whether the target cache line and the associated cache line are replaced to store the target data is determined according to the state identifier of the target cache line and the associated cache line determined from the reference cache line, so that the target data of different first sizes can be flexibly stored in the target cache, and the compatibility of the target cache for the data size is guaranteed.

[0082] Although some specific embodiments of the present application have been described in detail by way of examples, it should be understood that the examples are only for illustration and not intended to limit the scope of the present application. Those skilled in the art should understand that various modifications can be made to the embodiments without departing from the scope and spirit of the present application. The scope of the present application is defined by the appended claims.

Claims

1. A variable caching system, characterized in that, The system includes: a target cache, a processor, and a memory storing a computer program. The target cache includes M cache lines, each cache line including cache identification information and a cache data block. The cache identification information includes a data type identifier and a status identifier. The cache data block corresponds to a first size, where M is a positive integer. When the computer program is executed by the processor, the following steps are implemented: S101, when a data access request is received, determine the first hit situation of the target data corresponding to the data access request in the target cache; S102, if the first hit condition is a miss, then based on the first size and the second size of the target data corresponding to the data access request, a plurality of reference cache lines are determined from the M cache lines, wherein determining the plurality of reference cache lines based on the first size and the second size of the target data corresponding to the data access request includes: Based on the reference cache line index, the first ratio, and the number of cache lines M, several reference indices are determined, and the first ratio is obtained by comparing the second size with the first size. In the M cache lines, the cache line corresponding to each reference index is used as a reference cache line; S103, determine the target cache line from each reference cache line whose data type is identified as the first preset value; S104, based on the first size and the second size, determine a plurality of associated cache lines corresponding to the target cache line, wherein determining the plurality of associated cache lines corresponding to the target cache line based on the first size and the second size includes: Increment the reference index corresponding to the target cache line by one to obtain the first associated index; Add the reference index corresponding to the target cache line to the first ratio and then subtract one to obtain the second associated index; The cache lines corresponding to the first associated index to the second associated index are respectively used as the associated cache lines corresponding to the target cache line; S105, if the status identifier of the target cache line and the status identifier of its corresponding associated cache line both satisfy the first preset condition, then the target cache line and its associated cache line are both used as replacement cache lines, and each replacement cache line is used as the target cache space for storing the target data. S106, if any of the status identifiers of the target cache line and its corresponding associated cache line does not meet the first preset condition, return to the step of determining the target cache line from each reference cache line whose data type identifier is the first preset value, until the target cache space is obtained.

2. The variable caching system according to claim 1, characterized in that, When a data access request is received, determining the first hit status of the target data corresponding to the data access request in the target cache includes: When a data access request is received, several temporary cache lines are determined from the M cache lines based on the first size and the second size of the target data corresponding to the data access request; Based on the request identifier information corresponding to the data access request and the cache identifier information corresponding to each temporary cache line, determine the second hit status of each temporary cache line; If any temporary cache line has a second hit condition, then the first hit condition is determined to be a hit, and the cache data block corresponding to the temporary cache line with the second hit condition is taken as the access result of the data access request. If all temporary cache lines are misses, then the first hit is determined to be a miss.

3. The variable caching system according to claim 2, characterized in that, The step of determining a plurality of temporary cache lines from the M cache lines based on the first size and the second size of the target data corresponding to the data access request includes: The second dimension is compared with the first dimension to obtain the first ratio value; Based on the preset cache line index, the first ratio, and the number of cache lines M, determine several temporary indexes; In the M cache lines, the cache line corresponding to each temporary index is used as a temporary cache line.

4. The variable caching system according to claim 2, characterized in that, The request identification information includes a request type identifier, a number of request sub-identifiers, and a request address; the cache identification information also includes a number of cache sub-identifiers and a cache address. The step of determining the second hit status of each temporary cache line based on the request identifier information corresponding to the data access request and the cache identifier information corresponding to each temporary cache line includes: For any temporary cache line, the request type identifier is compared with the cache type identifier of the temporary cache line to obtain a first comparison result; The number of request sub-identifiers is compared with the number of cache sub-identifiers in the temporary cache line to obtain a second comparison result; The request address is compared with the cache address of the temporary cache line to obtain a third comparison result; If the first comparison result, the second comparison result, and the third comparison result are all consistent, then the second hit condition of the temporary cache line is determined to be a hit; otherwise, the second hit condition of the temporary cache line is determined to be a miss.

5. The variable caching system according to claim 4, characterized in that, The status identifier includes a valid identifier; Accordingly, for any temporary cache line, comparing the request type identifier with the cache type identifier of that temporary cache line to obtain a first comparison result includes: For any temporary cache line, if the valid identifier of the temporary cache line is the second preset value, then the second hit condition of the temporary cache line is determined to be a miss. Otherwise, the request type identifier is compared with the cache type identifier of the temporary cache line to obtain the first comparison result.

6. The variable caching system according to claim 5, characterized in that, After treating the target cache line and its associated cache lines as replacement cache lines, the process further includes: The valid identifier of the target cache line and the valid identifiers of each cache line related to the target cache line are all set to the second preset value.

7. The variable caching system according to claim 1, characterized in that, The status identifier includes a usage identifier and an intermediate identifier; The first preset condition is that both the usage identifier and the intermediate identifier are the second preset values.

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