Parameterized modular multiplier and operation method thereof

Abstract

The invention relates to a parameterized modular multiplier and an operation method thereof. The parameterized modular multiplier comprises a parameterized partial product generation module, a dynamic Wallace tree compression module, a dynamic packet carry selection addition array and a parameterized modular reduction module. According to the parameterized modular multiplier, by introducing a parameterized Booth2 algorithm, processing of data of any bit width is achieved, and any number of partial products can be flexibly generated; by adopting a 4: 2 or 3: 2 compressor recursive structure, high-efficiency compression of variable partial product scale is supported, and the utilization rate of hardware resources is improved; an addition array is selected through dynamic grouping carry, the number of addition groups can be automatically adjusted according to different bit widths, and efficient and high-performance reconfigurable summation operation is achieved; and by adopting a parameterized K2-RED algorithm, a reduction strategy of any modulus can be supported. According to the invention, an efficient, flexible and extensible solution is provided for high-performance analog-to-digital multiplication.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design related to cryptographic security, and in particular to a parameterized modular multiplier and an operation method thereof. Background Art

[0002] Fast number-theoretic transforms (NTTs) are key tools in modern cryptography and large-scale numerical computation. Modular multiplication, as the core computational module of NTT, has a significant impact on cryptographic security, such as post-quantum cryptography and homomorphic cryptography. In NTT hardware implementations, modular multiplication is typically performed using a dedicated modular multiplier (hereinafter referred to as the modular multiplier).

[0003] However, existing modular multiplier designs typically optimize performance for a fixed number of input bits or partial products in the generation, compression, and summation of partial products. This leads to low efficiency, high hardware resource usage, and insufficient flexibility when handling large-scale numerical operations. With the continuous advancement of cryptographic technology and the increasing complexity of its application scenarios, the demand for efficient, flexible, and scalable modular multipliers is becoming increasingly urgent. Summary of the Invention

[0004] Based on this, it is necessary to provide a parameterized modular multiplier and its operation method to address the above technical problems, so as to meet the flexibility, differentiation and high performance requirements of modern advanced cryptographic algorithms for modular multipliers.

[0005] A parameterized modular multiplier, comprising a parameterized partial product generation module, a dynamic Wallace tree compression module, a dynamic grouped carry selection addition array, and a parameterized modular reduction module;

[0006] The parameterized partial product generation module is used to encode the input multiplier and multiplicand using the parameterized Booth2 algorithm, generate partial products and pass them to the dynamic Wallace tree compression module after logical flattening;

[0007] The dynamic Wallace tree compression module supports configurable data bit widths and is used to dynamically compress any number of partial products using a 4:2 or 3:2 compressor recursive structure. The carry and sum outputs generated by the compression are passed through its own two output ports to the two input ports of the dynamic grouped carry select adder array.

[0008] The dynamic grouped carry selection adder array is used to perform addition operations on the carry bits and sum bits of the inputs according to a combinational architecture including a dynamic grouping strategy and a carry look-ahead adder, generate an integer multiplication result and pass it to the parameterized modular reduction module;

[0009] The parameterized modular reduction module is used to perform modular reduction twice on the integer multiplication result using the K2-RED algorithm and output the final modular multiplication result;

[0010] Among them, the bit width of the multiplier, multiplicand and modulus, as well as the bit width of the low bit of the modulus, support flexible setting.

[0011] Furthermore, the parameterized partial product generation module includes a parameterized Booth2 encoding module and a partial product generation module; wherein the parameterized Booth2 encoding module is used to use the parameterized Booth2 encoding algorithm to encode the input multiplier M1 with a bit width of m, and output the encoding result to the partial product generation module; the partial product generation module is used to receive the encoding result and perform a multiplication operation with the multiplicand M2 with a bit width of m to generate Partial products are formed into a two-dimensional partial product matrix, where the bit width of each partial product is 2m. Represents the ceiling function.

[0012] Furthermore, the parameterized partial product generation module and the dynamic Wallace tree compression module adopt a pipeline design. In the output stage of the parameterized partial product generation module, the following steps are also included:

[0013] The logical flattening method is used to flatten the partial product matrix of the two-dimensional structure in row order and splice it into a bit width of m 2 The one-dimensional partial product vector is input into the dynamic Wallace tree compression module.

[0014] Furthermore, in the 4:2 or 3:2 compressor recursive structure adopted by the dynamic Wallace tree compression module, each level of compression processing includes:

[0015] The corresponding compression strategy is dynamically selected according to the current number of partial products. When the number of partial products is greater than or equal to 4, a 4:2 compressor is used for compression processing; when the number of partial products is 3, a 3:2 compressor is switched for compression processing; when the number of partial products is less than 3, the current partial products are directly retained and passed to the next level for processing until multiple partial products are gradually compressed into two groups of outputs: carry and sum bits; wherein the bit width of the carry and sum bits are both 2m.

[0016] Furthermore, the dynamic group carry select adder array is specifically configured to first divide the input data into groups of 4 bits using a dynamic grouping strategy, and configure two 4-bit carry lookahead adders for each group of data obtained by the division. The two 4-bit carry lookahead adders are respectively used to pre-calculate the sum output and carry output when the carry input of each group of data is 0 and the carry input is 1; then, the carry select logic is used to select the correct output path of the current group of data based on the actual carry signal of the previous group of data;

[0017] Among them, the 4-bit carry-lookahead adder consists of 4 generation signal and propagation signal generators, 1 carry generator and 4 summation generation units; among them, the generation signal and propagation signal generator is used to receive two input bits A and B, generate the propagation signal P and the generation signal G and pass them to the carry generator; the carry generator is used to calculate and generate 4 levels of carry signals from c0 to c4 according to the generation signal G, and feed the generated carry signals back to each summation generation unit in turn; the summation generation unit is used to receive the corresponding propagation signal and carry signal for summation, and output 4 groups of sum bit signals from S0 to S3.

[0018] Furthermore, the parameterized modulus reduction module is applicable to a modulus q with a bit width of m and satisfies q=q H 2 w +1 case, where q H represents the high bit of the modulus, and w represents the width of the low bit of the modulus; let the bit width of the multiplier and the multiplicand be m, and the bit width of the integer multiplication result IM output by the dynamic group carry selection addition array is 2m. Since q=q H 2 w +1, so q H 2 w ≡-1modq, based on this, the parameterized modulus reduction module performs a single modulus reduction process for the integer multiplication result IM by IM and q H Multiplication is implemented as follows:

[0019] IM[2m-1:0]≡IM[2m-1:w]·2 w +IM[w-1:0]mod q;

[0020] q H IM[2m-1:0]≡q H ·IM[2m-1:w]·2 w +q H IM[w-1:0]mod q

[0021] ≡q H ·IM[w-1:0]-IM[2m-1:w]mod q;

[0022] Among them, mod represents the modular operation, and ≡ represents the congruence relationship.

[0023] Furthermore, the input of the parameterized modular multiplier also includes pre-calculated rotation factors, which are multiplied by To eliminate the parameterized modular multiplier, for the integer multiplication result IM with a bit width of 2m, it is necessary to multiply the modulus high bit q twice H The impact of modular reduction on the final output modular multiplication result.

[0024] A calculation method based on the parameterized modular multiplier, the method comprising:

[0025] Step 1: The parameterized partial product generation module uses the parameterized Booth2 algorithm to encode the input multiplier and multiplicand, generates partial products, and passes them to the dynamic Wallace tree compression module after logical flattening;

[0026] Step 2: The dynamic Wallace tree compression module uses a 4:2 or 3:2 compressor recursive structure to dynamically compress any number of partial products of the input, and transmits the two sets of outputs of the carry and sum bits generated by the compression to the two input ports of the dynamic grouped carry selection addition array through its own two sets of output ports;

[0027] Step 3: The dynamic grouped carry selection adder array performs addition operations on the carry and sum bits of the input according to the combined architecture including the dynamic grouping strategy and the carry lookahead adder, generates an integer multiplication result and passes it to the parameterized modular reduction module;

[0028] Step 4: The parameterized modular reduction module uses the K2-RED algorithm to perform modular reduction twice on the integer multiplication result and outputs the final modular multiplication result.

[0029] The above-mentioned parameterized modular multiplier and its operation method realize the processing of data of arbitrary bit width by introducing the parameterized Booth2 algorithm in the parameterized partial product generation module, and can flexibly generate any number of partial products; utilize the 4:2 or 3:2 compressor recursive structure adopted in the dynamic Wallace tree compression module to dynamically compress any number of partial products, support efficient compression of variable partial product scales, and improve the utilization rate of hardware resources; in the dynamic group carry selection addition array, by configuring a combination architecture including a dynamic grouping strategy and a carry look-ahead adder, the number of addition groups can be automatically adjusted according to different bit widths, realizing efficient and high-performance reconfigurable summation operation; and the parameterized K2-RED algorithm is adopted in the parameterized modular reduction module to support reduction strategies of arbitrary modular numbers. The present application can overcome the shortcomings of the existing technology, and the bit widths of the multiplier, multiplicand and modulus in the parameterized modular multiplier, as well as the bit width of the low bit of the modulus, support flexible setting, providing an efficient, flexible and scalable solution for high-performance modular multiplication operations, which can meet the flexibility, differentiation and high performance requirements of modern advanced cryptographic algorithms for modular multipliers. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a schematic structural diagram of a parameterized modular multiplier in one embodiment;

[0031] Figure 2 A schematic diagram of the encoding rules of the parameterized Booth2 algorithm in one embodiment;

[0032] Figure 3 A schematic diagram of the structure of a dynamic group carry selection addition array in one embodiment;

[0033] Figure 4 Schematic diagram of the structure of a 4-bit carry-lookahead adder in one embodiment;

[0034] Figure 5 Schematic diagram of pseudo code of K2-RED algorithm in one embodiment;

[0035] Figure 6 1. A schematic diagram of an operation example of a parameterized modular multiplier according to an embodiment;

[0036] Figure 7 FIG. 4 is a flow chart of an operation method of a parameterized modular multiplier in one embodiment. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0038] In one embodiment, Figure 1 As shown, a parameterized modular multiplier is provided, including a parameterized partial product generation module, a dynamic Wallace tree compression module, a dynamic grouped carry selection addition array and a parameterized modular reduction module, and the parameterized partial product generation module, the dynamic Wallace tree compression module and the dynamic grouped carry selection addition array constitute the parameterized multiplier.

[0039] The parameterized partial product generation module is used to encode the input multiplier and multiplicand using the parameterized Booth2 algorithm, generate partial products and pass them to the dynamic Wallace tree compression module after logical flattening;

[0040] The dynamic Wallace tree compression module supports configurable data bit widths and is used to dynamically compress any number of partial products using a 4:2 or 3:2 compressor recursive structure. The carry and sum outputs generated by the compression are passed through its own two output ports to the two input ports of the dynamic grouped carry select adder array.

[0041] The dynamic grouped carry selection adder array is used to perform addition operations on the carry bits and sum bits of the inputs according to a combinational architecture including a dynamic grouping strategy and a carry look-ahead adder, generate an integer multiplication result and pass it to the parameterized modular reduction module;

[0042] The parameterized modular reduction module is used to perform modular reduction twice on the integer multiplication result using the K2-RED algorithm and output the final modular multiplication result;

[0043] Among them, the bit width of the multiplier, multiplicand and modulus, as well as the bit width of the low bit of the modulus, support flexible setting.

[0044] Furthermore, the parameterized partial product generation module includes a parameterized Booth2 encoding module and a partial product generation module. The parameterized Booth2 encoding module is used to encode the input multiplier M1[m-1:0] with a bit width of m using the parameterized Booth2 encoding algorithm and output the encoding result to the partial product generation module. The partial product generation module is used to receive the encoding result and perform a multiplication operation with the multiplicand M2[m-1:0] with a bit width of m to generate Partial products are formed into a two-dimensional partial product matrix, where the bit width of each partial product is 2m. represents the ceiling function. Figure 1 The output S_0[(m / 2)-1:0] of the parameterized Booth2 encoding module indicates whether the result after Booth2 encoding is 0, and the bit width is m / 2; the output Inv[(m / 2)-1:0] indicates whether the control signal needs to be inverted in Booth2 encoding, and the bit width is m / 2; the output M_2[(m / 2)-1:0] indicates whether the multiplicand needs to be multiplied by 2 after Booth2 encoding, and the bit width is also m / 2.

[0045] Specifically, if Figure 2 As shown, the parameterized Booth2 encoding algorithm divides the multiplier into groups of three, encodes them according to the three-bit combinations, and then performs different operations on the multiplicand based on the encoding results to generate partial products. Compared with high-radix Booth encoding, the parameterized Booth2 encoding structure is simpler and has more stable control logic, making it suitable for building flexible and configurable multiplier modules. The parameterized Booth2 algorithm also supports dynamic configurability of the number of multiplier bits, improving application flexibility.

[0046] Furthermore, the parameterized partial product generation module and the dynamic Wallace tree compression module adopt a pipeline design. In the output stage of the parameterized partial product generation module, it also includes: using a logical flattening method to flatten the partial product matrix of the two-dimensional structure in row order and splice it into a bit width of m 2 The one-dimensional partial product vector is expressed as pp_flat[(m*m)-1:0], and the one-dimensional partial product vector is input into the dynamic Wallace tree compression module, so as to achieve efficient docking between the parameterized partial product generation module and the dynamic Wallace tree compression module.

[0047] Furthermore, in the recursive 4:2 or 3:2 compressor structure used by the dynamic Wallace tree compression module, each level of compression processing involves dynamically selecting a corresponding compression strategy based on the current number of partial products. When the number of partial products is greater than or equal to 4, compression is performed using a 4:2 compressor; when the number of partial products is 3, compression is performed using a 3:2 compressor; and when the number of partial products is less than 3, the current partial products are retained and passed to the next level for processing, until multiple partial products are gradually compressed into two output sets (Carry) of carry and sum bits (Sum), represented as S[2m-1:0] and C[2m-1:0], respectively, with a bit width of 2m. This dynamic Wallace tree compression module, using a tree-like network dynamically constructed using 4:2 or 3:2 compressors based on the recursive strategy, can perform multi-level parallel compression on multiple sets of partial products, supporting efficient compression of variable partial product sizes and improving hardware resource utilization.

[0048] Furthermore, the structure of the dynamic group carry selection addition array is as follows Figure 3 As shown, the dynamic group carry selection addition array is specifically used to first use a dynamic grouping strategy to divide the input data into groups of 4 bits, and each group of data obtained by the division is correspondingly configured with two 4-bit carry lookahead adders, and the two 4-bit carry lookahead adders are used to pre-calculate the sum output and carry output when the carry input of each group of data is 0 (C0=0) and the carry input is 1 (C0=1); then, the carry selection logic is used to select the correct output path of the current group of data according to the actual carry signal Cin of the previous group of data.

[0049] Among them, the structure of the 4-bit carry-lookahead adder (CLA) is as follows Figure 4 As shown, it consists of 4 generating signal and propagation signal generators, 1 carry generator and 4 summing generation units; wherein, the generating signal and propagation signal generator is used to receive two input bits A and B, generate a propagation signal P and a generating signal G and transmit them to the carry generator; the carry generator is used to calculate and generate 4 levels of carry signals c0 to c4 according to the generating signal G, and feed the generated carry signals back to each summing generation unit in turn; the summing generation unit is used to receive the corresponding propagation signal and carry signal for summing, and output 4 groups of sum bit signals S0 to S3.

[0050] The above-mentioned dynamic group carry selection addition array, including a dynamic grouping strategy and a 4-bit carry-lookahead adder, can automatically adjust the number of addition groups according to different bit widths, realizing efficient and high-performance reconfigurable summation operations. The basic structure of the 4-bit grouping can effectively control circuit complexity and logic delay while accelerating carry propagation.

[0051] Furthermore, the parameterized modulus reduction module is applicable to a modulus q[m-1:0] with a bit width of m and satisfying q=qH 2 w +1 case, where q H represents the high bit of the modulus, and w represents the width of the low bit of the modulus; let the bit width of the multiplier and the multiplicand be m, and the bit width of the integer multiplication result IM[2m-1:0] output by the dynamic group carry selection addition array is 2m. Since q=q H 2 w +1, so q H 2 w ≡-1modq, based on this, the parameterized modulus reduction module performs a single modulus reduction process for the integer multiplication result IM by IM and q H Multiplication is implemented as follows:

[0052] IM[2m-1:0]≡IM[2m-1:w]·2 w +IM[w-1:0]mod q;

[0053] q H IM[2m-1:0]≡q H ·IM[2m-1:w]·2 w +q H IM[w-1:0]mod q

[0054] ≡q H ·IM[w-1:0]-IM[2m-1:w]mod q;

[0055] Among them, mod represents the modular operation, and ≡ represents the congruence relationship.

[0056] From the above formula, we can know that for the integer multiplication result IM with a bit width of 2m, two modulus reductions are required, so we need to multiply by Since in the process of NTT transformation, the modular multiplication data is composed of the data to be calculated and the rotation factors, wherein the rotation factors are obtained by pre-calculation and input into the modular multiplier. Therefore, further, the input of the parameterized modular multiplier also includes the pre-calculated rotation factors, which are multiplied by the rotation factors in the pre-calculation stage. To eliminate the parameterized modular multiplier, for the integer multiplication result IM with a bit width of 2m, it is necessary to multiply the modulus high bit q twice H The impact of modular reduction on the final output modular multiplication result MM[2m-1:0].

[0057] Specifically, the pseudo code of the K2-RED algorithm used by the parameterized modulus reduction module is as follows: Figure 5 As shown, for a specific form of modulus q = q H 2 w +1, which satisfies q H 2 w≡-1modq. Split IM into lower part C l and high C h , calculate the intermediate variable C sum and C diff , through two transformations, intermediate results C′ and C″ are generated, and conditional operations are performed according to the sign and size of C″ to ensure that the final result R is within the range of the modulus q.

[0058] Furthermore, Figure 6 The schematic diagram of the operation example of a parameterized modular multiplier provided by the present application is shown. In this operation example, the input multiplier is 397, the multiplicand is 675, and the bit width m of the multiplier and the multiplicand is set to 12 bits. Then the partial product The number of is 6, the bit width 2m of the integer multiplication result is 24 bits, and the modulus selection is q = 3329 = 13*2 8 +1, the bit width is 12 bits, and the operation process includes:

[0059] First, the parameterized partial product generation module encodes the multipliers using the parameterized Booth2 algorithm and generates six partial products, namely 33443, 95600, 404020, 1486400, 6637120, and 8388608. These partial products are flattened in the order pp[5] to pp[0] to form a one-dimensional partial product vector pp_flat[143:0].

[0060] Next, the dynamic Wallace tree compression module splits and compresses the flattened one-dimensional partial product vector, and the output sum is 15975623 and the carry is 1069568.

[0061] Subsequently, the dynamic packed carry selection addition array adds the sum bit and the carry bit to obtain an integer multiplication result IM=267975.

[0062] Finally, the parameterized modular reduction module performs modular reduction twice on the integer multiplication result IM. The result of the first modular reduction is 1541, and the final modular multiplication result output after the second modular reduction is MM=59.

[0063] Figure 6 The verification results shown in the figure show that the operation process of the parameterized modular multiplier provided by this application is correct, in which the modular multiplication verification result will be multiplied twice by q H =13 to verify the result.

[0064] In one embodiment, a method for operating a parameterized modular multiplier is provided, such as Figure 7 As shown, the method includes the following steps:

[0065] Step 1: The parameterized partial product generation module uses the parameterized Booth2 algorithm to encode the input multiplier and multiplicand, generates partial products, and passes them to the dynamic Wallace tree compression module after logical flattening;

[0066] Step 2: The dynamic Wallace tree compression module uses a 4:2 or 3:2 compressor recursive structure to dynamically compress any number of partial products of the input, and transmits the two sets of outputs of the carry and sum bits generated by the compression to the two input ports of the dynamic grouped carry selection addition array through its own two sets of output ports;

[0067] Step 3: The dynamic grouped carry selection adder array performs addition operations on the carry and sum bits of the input according to the combined architecture including the dynamic grouping strategy and the carry lookahead adder, generates an integer multiplication result and passes it to the parameterized modular reduction module;

[0068] Step 4: The parameterized modular reduction module uses the K2-RED algorithm to perform modular reduction twice on the integer multiplication result and outputs the final modular multiplication result.

[0069] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0070] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A parameterized modular multiplier, characterized in that The parameterized modular multiplier includes a parameterized partial product generation module, a dynamic Wallace tree compression module, a dynamic grouped carry selection addition array and a parameterized modular reduction module; The parameterized partial product generation module is used to encode the input multiplier and multiplicand using the parameterized Booth2 algorithm, generate partial products and pass them to the dynamic Wallace tree compression module after logical flattening; The dynamic Wallace tree compression module supports configurable data bit width and is used to dynamically compress any number of partial products input using a 4:2 or 3:2 compressor recursive structure, and transmits the two sets of carry and sum bit outputs generated by the compression to the two input ports of the dynamic grouped carry select addition array through its own two sets of output ports; The dynamic grouped carry select adder array is used to perform addition operations on the carry and sum bits of the inputs according to a combined architecture including a dynamic grouping strategy and a carry look-ahead adder, generate an integer multiplication result and pass it to the parameterized modular reduction module; The parameterized modular reduction module is used to perform modular reduction twice on the integer multiplication result using the K2-RED algorithm, and output a final modular multiplication result; The bit widths of the multiplier, multiplicand and modulus, as well as the bit width of the low bit of the modulus, support flexible setting.

2. A parameterized modular multiplier according to claim 1, characterized in that: The parameterized partial product generation module includes a parameterized Booth2 encoding module and a partial product generation module; wherein the parameterized Booth2 encoding module is used to use the parameterized Booth2 encoding algorithm to encode the input multiplier M1 with a bit width of m and output the encoding result to the partial product generation module; the partial product generation module is used to receive the encoding result and perform a multiplication operation with the multiplicand M2 with a bit width of m to generate Partial products are formed into a two-dimensional partial product matrix, where the bit width of each partial product is 2m. Represents the ceiling function.

3. A parameterized modular multiplier according to claim 2, characterized in that: The parameterized partial product generation module and the dynamic Wallace tree compression module adopt a pipeline design. At the output stage of the parameterized partial product generation module, the module further includes: The partial product matrix of the two-dimensional structure is flattened and spliced ​​into a matrix with a bit width of m in row order using a logical flattening method. 2 The one-dimensional partial product vector is input into the dynamic Wallace tree compression module.

4. A parameterized modular multiplier according to claim 3, characterized in that: In the 4:2 or 3:2 compressor recursive structure adopted by the dynamic Wallace tree compression module, each level of compression processing includes: A corresponding compression strategy is dynamically selected based on the current number of partial products. When the number of partial products is greater than or equal to 4, a 4:2 compressor is used for compression processing. When the number of partial products is 3, a 3:2 compressor is switched to for compression processing. When the number of partial products is less than 3, the current partial products are directly retained and passed to the next level for processing until multiple partial products are gradually compressed into two groups of outputs, carry and sum bits. The bit widths of the carry and sum bits are both 2m.

5. A parameterized modular multiplier according to claim 1, characterized in that: The dynamic group carry selection adder array is specifically configured to first divide the input data into groups of 4 bits using a dynamic grouping strategy, and configure two 4-bit carry-lookahead adders for each group of data. The two 4-bit carry-lookahead adders are respectively used to pre-calculate the sum output and carry output when the carry input of each group of data is 0 and the carry input is 1; then, the carry selection logic is used to select the correct output path for the current group of data based on the actual carry signal of the previous group of data; Among them, the 4-bit carry-lookahead adder consists of 4 generation signal and propagation signal generators, 1 carry generator and 4 summation generation units; wherein, the generation signal and propagation signal generator is used to receive two input bits A and B, generate a propagation signal P and a generation signal G and transmit them to the carry generator; the carry generator is used to calculate and generate 4 levels of carry signals c0 to c4 according to the generation signal G, and feed the generated carry signals back to each summation generation unit in turn; the summation generation unit is used to receive the corresponding propagation signal and carry signal for summation, and output 4 groups of sum bit signals S0 to S3.

6. A parameterized modular multiplier according to claim 1, characterized in that: The parameterized modulus reduction module is suitable for modulus q with a bit width of m and satisfies q=q H 2 w +1 case, where q H represents the high bit of the modulus, and w represents the width of the low bit of the modulus; assuming that the bit width of the multiplier and the multiplicand is m, the bit width of the integer multiplication result IM output by the dynamic group carry selection addition array is 2m, since q=q H 2 w +1, so q H 2 w ≡-1modq, based on this, the parameterized modulus reduction module performs a single modulus reduction process for the integer multiplication result IM by IM and q H Multiplication is implemented as follows: IM[2m-1:0]≡IM[2m-1:w]·2 w +IM[w-1:0]mod q; q H ·IM[2m-1:0]≡q H ·IM[2m-1:w]·2 w +q H ·IM[w-1:0]mod q ≡q H ·IM[w-1:0]-IM[2m-1:w]mod q; Among them, mod represents the modular operation, and ≡ represents the congruence relationship.

7. A parameterized modular multiplier according to claim 6, characterized in that: The input of the parameterized modular multiplier also includes pre-calculated rotation factors, which are multiplied by To eliminate the need for the parameterized modular multiplier to multiply the modulus high bit q twice for the integer multiplication result IM with a bit width of 2m H The impact of modular reduction on the final output modular multiplication result.

8. A method for calculating a parameterized modular multiplier according to any one of claims 1 to 7, characterized in that: The method comprises: Step 1: The parameterized partial product generation module uses the parameterized Booth2 algorithm to encode the input multiplier and multiplicand, generates partial products, and passes them to the dynamic Wallace tree compression module after logical flattening; Step 2: The dynamic Wallace tree compression module uses a 4:2 or 3:2 compressor recursive structure to dynamically compress any number of partial products input, and transmits the two sets of carry and sum outputs generated by the compression to the two input ports of the dynamic grouped carry selection addition array through its own two sets of output ports; Step 3, the dynamic grouped carry selection adder array performs addition operation on the carry and sum bits of the input according to the combined architecture including the dynamic grouping strategy and the carry look-ahead adder, generates an integer multiplication result and passes it to the parameterized modular reduction module; Step 4: The parameterized modular reduction module uses the K2-RED algorithm to perform modular reduction twice on the integer multiplication result and outputs the final modular multiplication result.

Images