Display device

Abstract

The invention provides a display device. The display device comprises a substrate, a first signal line, a second signal line, a third signal line and a plurality of isolation elements. The substrate has a first region and a second region. The second region surrounds the first region. The first signal line, the second signal line and the third signal line are arranged on the substrate and transmit the first signal, the second signal and the third signal in a time-sharing mode. The plurality of isolation elements are arranged in the first area. The first signal and the second signal respectively have a first turn-on time period. The third signal has a second turn-on time period. The first opening time period is different from the second opening time period. In the second region, the third signal line is disposed between the first signal line and the second signal line. In the first region, the second signal line is disposed between the first signal line and the third signal line. One of the plurality of isolation elements is disposed between the second signal line and a portion of the third signal line. The display device disclosed by the invention can provide a good display effect.

Description

Technical Field

[0001] The present disclosure relates to a device, and more particularly to a display device. Background Art

[0002] Typically, the aperture bezel of a HID (Hole in Display) device is designed to be as small as possible, resulting in relatively limited routing space for traces passing through the aperture boundary area of ​​the aperture bezel. In other words, the spacing between the display panel's signal lines in the aperture boundary area is smaller than the spacing within the display area. Consequently, the small spacing between the traces can cause severe signal coupling interference between the multiple signal lines in the aperture boundary area, compromising display quality. Summary of the Invention

[0003] The present disclosure is directed to a display device that can provide good display effects.

[0004] According to an embodiment of the present disclosure, a display device includes a substrate, a first signal line, a second signal line, a third signal line, and a plurality of isolation elements. The substrate has a first region and a second region. The second region surrounds the first region. The first signal line, the second signal line, and the third signal line are disposed on the substrate. The first signal line, the second signal line, and the third signal line extend from the second region to the first region, respectively. The first signal line, the second signal line, and the third signal line are used to transmit a first data signal, a second data signal, and a third data signal in a time-sharing manner. The plurality of isolation elements are disposed in the first region. The first signal and the second signal each have a first on-time period, and the third signal has a second on-time period. The first on-time period is different from the second on-time period. In the second region, the third signal line is disposed between the first signal line and the second signal line. In the first region, the second signal line is disposed between the first signal line and the third signal line. One of the plurality of isolation elements is disposed between the second signal line and a portion of the third signal line.

[0005] Based on the above, the display device disclosed herein can effectively reduce signal coupling interference between the plurality of signal lines by configuring and designing the plurality of signal lines and providing isolation elements.

[0006] In order to make the above features and advantages of the present disclosure more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a partially enlarged schematic diagram of a display device according to an embodiment of the present disclosure;

[0008] Figure 2 is a partially enlarged schematic diagram of a display device according to another embodiment of the present disclosure;

[0009] Figure 3A as well as Figure 3B is a schematic diagram of the line width of a signal line according to an embodiment of the present disclosure;

[0010] Figure 4 is a signal timing diagram of an embodiment of the present disclosure;

[0011] Figure 5 is a schematic diagram of a display device according to another embodiment of the present disclosure.

[0012] Description of Reference Numerals

[0013] 10: display device;

[0014] 100: substrate;

[0015] 110: first area;

[0016] 120, 120': second area;

[0017] 130: Third area;

[0018] 140: demultiplexer circuit;

[0019] 150: driving circuit;

[0020] B11, B21, B31, B41: Part I;

[0021] B12, B22, B32, B42: Part II;

[0022] B13, B23, B33, B43: Part III;

[0023] C1~C34: through hole;

[0024] CKH1~CKH3: clock signal;

[0025] D1~D12: display data;

[0026] DL1~DL12, SL1~SL4, L_1~L_k: signal lines;

[0027] f1, f2: reference lines;

[0028] GL1, GL2, GL_(N), GL_(N+1): gate lines;

[0029] GS_(N-1), GS_N, GS_(N+1): gate control signals;

[0030] K1~K6: isolation elements;

[0031] P(1,1)~P(2,6), P1~P24: sub-pixel unit;

[0032] ST1~ST6, T(1,1)~T(2,6), T1~T24: switch units;

[0033] R1, R2: minimum separation distance;

[0034] W1~W8: width. DETAILED DESCRIPTION

[0035] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0036] Throughout this disclosure and the appended claims, certain terms are used to refer to specific components. Those skilled in the art will appreciate that display device manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that have the same function but are named differently. In the following description and claims, the words "including" and "comprising" are open-ended and should be interpreted as meaning "including, but not limited to..."

[0037] In some embodiments of the present disclosure, terms related to bonding and connection, such as "coupled" and "interconnected," unless otherwise specified, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, with another structure positioned between them. Furthermore, such terms may include situations where both structures are movable or both structures are fixed. Furthermore, the term "coupled" encompasses any direct and indirect electrical connection means.

[0038] The ordinal numbers used in the specification and claims, such as "first" and "second", are used to modify components. They do not imply or represent any previous ordinal number of the components, nor do they represent the order of one component to another component, or the order in the manufacturing method. The use of multiple ordinal numbers is only used to clearly distinguish a component with a certain name from another component with the same name. The claims and the specification may not use the same words. Accordingly, the first component in the specification may be the second component in the claims. It should be noted that the following embodiments can replace, reorganize, and mix the technical features in several different embodiments to complete other embodiments without departing from the spirit of the present disclosure.

[0039] The display device described in the present disclosure may include a virtual reality device, an augmented reality device, a head-up display device, a transparent display device, a sensor device or a splicing device, but is not limited thereto. The display device may be a bendable or flexible electronic device. The display device may be a non-self-luminous display device or a self-luminous display device. The sensor device may be a sensor device that senses capacitance, light, heat or ultrasound, but is not limited thereto. The display device may, for example, include electronic components such as passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. The diode may include a light-emitting diode or a photodiode. The light-emitting diode may, for example, include an inorganic light-emitting diode, an organic light-emitting diode (OLED), a sub-millimeter light-emitting diode (mini LED), a micro light-emitting diode (micro LED) or a quantum dot light-emitting diode (quantum dot LED), but is not limited thereto. The splicing device may, for example, be a display splicing device, but is not limited thereto. It should be noted that the display device may be any combination of the aforementioned, but is not limited thereto.

[0040] In the present disclosure, distance, length, width, and thickness can be measured using an optical microscope or from cross-sectional images obtained using an electron microscope, but the present disclosure is not limited thereto. If a first value is equal to a second value, this implies that there may be an error of approximately 10% between the first and second values. If a first direction is perpendicular to a second direction, the angle between the first and second directions may be between 80 and 100 degrees. If the first direction is parallel to the second direction, the angle between the first and second directions may be between 0 and 10 degrees.

[0041] In addition, relative terms may be used in the embodiments, such as "below" or "bottom" and "above" or "top" to describe the relative relationship of one element of the drawings to another element. It is understood that if the device in the drawings is turned upside down, the element described on the "below" side will become the element on the "above" side. When a corresponding component (such as a film layer or area) is referred to as "on another component", it can be directly on the other component, or there can be other components between the two. On the other hand, when a component is referred to as "directly on another component", there is no component between the two. In addition, when a component is referred to as "on another component", the two have a top-down relationship in the top-down direction, and this component can be above or below the other component, and this top-down relationship depends on the orientation of the device.

[0042] It should be understood that features from several different embodiments may be replaced, recombined, or mixed to create other embodiments without departing from the spirit of the present disclosure.

[0043] Figure 1 FIG. 1 is a partially enlarged schematic diagram of a display device according to an embodiment of the present disclosure. Figure 1 , the display device 10 includes a substrate 100. The substrate 100 includes a first area 110, a second area 120 and a third area 130, wherein the substrate 100 may be formed by stacking a plurality of metal layers (for example, gold, silver, copper, aluminum, chromium, platinum, tin, alloys thereof or combinations thereof) and a plurality of insulating layers (for example, silicon dioxide, silicon nitride, silicon oxynitride, polyimide, polyester, etc. or mixed materials thereof). The second area 120 surrounds the first area 110. In this embodiment, the first area 110 may include an opening and a hole boundary area (Hole border), and the second area 120 may include a pixel area (i.e., the display area or active area (AA) of the panel). In addition, the third area 130 includes a peripheral area, for example, a peripheral area in which a driving circuit, a bonding pad and a test circuit are provided. In one embodiment, the third area may surround the second area, but the present disclosure is not limited thereto. The adjacent areas of the first area 110 and the second area 120 can be enlarged as shown in FIG. Figure 1 Shown on the right.

[0044] In this embodiment, the second region 120 may include a plurality of sub-pixel units P(1, 1) to P(2, 6) arranged in an array, a plurality of switch units T(1, 1) to T(2, 6), a plurality of signal lines DL1 to DL6, and a plurality of gate lines GL1 and GL2. The switch units T(1, 1) to T(2, 6) may be N-type transistors or P-type transistors, respectively. It should be noted that the second region 120 only represents the sub-pixel configuration relationship of a portion of the substrate 100, and the number of sub-pixel units, the number of switch units, the number of signal lines, and the number of gate lines of the substrate 100 are not limited to Figure 1 shown.

[0045] In this embodiment, the signal line DL1 is electrically connected to a portion of the sub-pixel units P(1, 1) to P(2, 6), the signal line DL2 is electrically connected to another portion of the sub-pixel units P(1, 1) to P(2, 6), and the signal line DL3 is electrically connected to another portion of the sub-pixel units P(1, 1) to P(2, 6). Similarly, the signal lines DL4 to DL6 are electrically connected to different sub-pixel units, respectively. In this embodiment, the sub-pixel units P(1, 1) to P(2, 6) may include sub-pixels of different colors, such as red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels, but the present disclosure is not limited thereto. Furthermore, a portion of the sub-pixels electrically connected to the signal line DL2 may be sub-pixels of the same color as another portion of the sub-pixels electrically connected to the signal line DL4.

[0046] Specifically, the first terminals of the switch units T(1,1) to T(2,6) are coupled to the sub-pixel units P(1,1) to P(2,6), respectively. The control terminals of the switch units T(1,1) to T(1,6) are coupled to the gate line GL1. The control terminals of the switch units T(2,1) to T(2,6) are coupled to the gate line GL2. The gate lines GL1 and GL2 can receive different gate control signals, respectively, and make the switch units T(1,1) to T(1,6) and the switch units T(2,1) to T(2,6) not overlap in their on-time intervals (i.e., high-level periods). Alternatively, in another embodiment, the on-time intervals (i.e., high-level periods) of the switch units T(2,1) to T(2,6) at least partially overlap. The second terminal of the switch unit T(1,1) is coupled to the signal line DL1. The second terminals of the switch units T(1,2) and T(2,1) are coupled to the signal line DL2. The second ends of the switch units T(1, 3) and the switch unit T(2, 2) are coupled to the signal line DL3. The second ends of the switch units T(1, 4) and the switch unit T(2, 3) are coupled to the signal line DL4. The second ends of the switch units T(1, 5) and the switch unit T(2, 4) are coupled to the signal line DL5. The second ends of the switch units T(1, 6) and the switch unit T(2, 5) are coupled to the signal line DL6. The second end of the switch unit T(2, 6) can be coupled to the next signal line (not shown). However, the electrical connection method between the sub-pixel units and the signal lines disclosed herein is not limited to Figure 1 As shown. In this embodiment, sub-pixel units P(1,1), P(2,3), and P(1,5) can be red sub-pixels. Sub-pixel units P(2,1), P(1,3), and P(2,5) can be blue sub-pixels. Sub-pixel units P(1,2), P(2,2), P(1,4), P(2,4), P(1,6), and P(2,6) can be green sub-pixels. In this regard, signal line DL2 and signal line DL3 can be electrically connected to the green sub-pixel unit P(1,2) and sub-pixel unit P(2,2), respectively, and so on.

[0047] In addition, in another embodiment, the sub-pixel units P(1,1), P(1,2), and P(1,3) may also be red sub-pixels, green sub-pixels, and blue sub-pixels in sequence, and the sub-pixel units P(2,1), P(2,2), and P(2,3) may also be red sub-pixels, green sub-pixels, and blue sub-pixels in sequence, but the present disclosure is not limited thereto. In addition, under the above-mentioned arrangement of the red sub-pixels, green sub-pixels, and blue sub-pixels, the second ends of the sub-pixels in the same row may be electrically connected to the signal lines on the left side (for example, Figure 1 The sub-pixel units P(1, 1) and P(2, 1) can be electrically connected to the signal line DL1).

[0048] In this embodiment, the third region 130 of the substrate 100 (i.e., the peripheral region below the second region 120 or outside the active region of the panel) may further include a plurality of switch units ST1 to ST6. The switch units ST1 to ST6 may form a demultiplexer (DMux) circuit. The display driver (e.g., an integrated circuit, a chip) of the display device 10 may be electrically connected to the signal lines DL1 to DL3 via the signal line SL1 and the plurality of switch units ST1 to ST3. The display driver of the display device 10 may be electrically connected to the signal lines DL4 to DL6 via the signal line SL2 and the plurality of switch units ST4 to ST6, but this embodiment is not limited thereto. The switch units ST1 to ST6 may be N-type transistors or P-type transistors, respectively. The switch units ST1 and ST4 may receive the same clock signal CKH1. The switch units ST2 and ST5 may receive the same clock signal CKH2. The switch units ST3 and ST6 may receive the same clock signal CKH3. Switch units ST1-ST3 can be sequentially turned on at different times according to clock signals CKH1-CKH3 to provide different data signals to signal lines DL1-DL3. Switch units ST4-ST6 can be sequentially turned on at different times according to clock signals CKH1-CKH3 to provide different data signals to signal lines DL4-DL6.

[0049] In this embodiment, the signal lines DL1-DL6 extend from the second region 120 to the first region 110. Since the wiring space in the first region 110 is smaller than the wiring space in the second region 120, in order to reduce signal coupling interference between the signal lines DL1-DL6, the signal lines DL1-DL6 are re-wired during the process of extending from the second region 120 to the first region 110, and isolation elements K1 and isolation elements K2 are provided, wherein the isolation elements K1 and K2 may include conductive elements, such as gold, silver, copper, aluminum, chromium, platinum, tin, alloys thereof, or combinations thereof, or insulating elements, such as silicon dioxide, silicon nitride, silicon oxynitride, polyimide, polyester, or a mixture thereof, but the present disclosure is not limited thereto.

[0050] In this embodiment, if Figure 1As shown, the routing order of signal lines DL1-DL6 can be changed in the first region 110. For example, in the second region 120 of the substrate 100, signal line DL2 is arranged between signal line DL1 and signal line DL4. Furthermore, in the first region 110 of the substrate 100, after the routing order is changed, signal line DL4 can be arranged between signal line DL1 and signal line DL2. In the first region 110, signal lines DL1 and DL4 are arranged on one side of the isolation element K1, and signal lines DL2 and DL5 are arranged on the other side of the isolation element K1. Signal lines DL2 and DL5 are arranged on one side of the isolation element K2, and signal lines DL3 and DL6 are arranged on the other side of the isolation element K2. Specifically, in the first region 110 of the substrate 100, the signal line DL1 and the signal line DL4, which write display data based on the first clock signal CKH1, can be arranged adjacent to each other, and the signal line DL2, which writes display data based on the second clock signal CKH2 (different from the signal line DL1 and the signal line DL4), can be connected to the signal line DL4 via the isolation element K1 to reduce signal coupling interference. Similarly, in the first region 110 of the substrate 100, multiple signal lines controlled by the same clock signal can be arranged adjacent to each other, and two adjacent signal lines controlled by different clock signals can be isolated from each other via the isolation element. Therefore, the signal lines DL1 to DL6 can have lower signal coupling interference in the first region 110 of the substrate 100.

[0051] Figure 2 FIG. 1 is a partially enlarged schematic diagram of a display device according to another embodiment of the present disclosure. Figure 2 , Figure 2 For illustration Figure 1 The signal line extends from the second area 120 to the first area 110, and then extends from the first area 110 to the second area 120'. Figure 2 The signal lines DL1-DL12 may extend from one side of the second region 120 through the first region 110 to the other side of another second region 120'. In one embodiment, the plurality of signal lines disposed in the first region 110 include two adjacent signal lines having a minimum spacing distance R2 (e.g., the distance between signal lines of two adjacent sub-pixels), and the plurality of signal lines disposed in the second region 120 include two adjacent signal lines having a minimum spacing distance R1 (e.g., the distance between two adjacent signal lines in the third metal layer), wherein the minimum spacing distance R2 is less than the minimum spacing distance R1, but the present disclosure is not limited thereto.

[0052] In this embodiment, signal lines DL1-DL12 are electrically connected to one end of switch units T1-T12 in the second region 120, and the other ends of switch units T1-T12 are electrically connected to sub-pixel units P1-P12, respectively. The control ends of switch units T1-T12 are electrically connected to gate line GL_(N+1), where N is a positive integer. Signal lines DL1-DL12 may also be electrically connected to switch units ST1-ST12 in the third region 130 (i.e., below the second region 120 or in the peripheral region outside the active area of ​​the panel). In this embodiment, signal lines DL1-DL12 are electrically connected to one end of switch units T13-T24 in the second region 120', and the other ends of switch units T13-T24 are electrically connected to sub-pixel units P13-P24, respectively. The control ends of switch units T13-T24 are electrically connected to gate line GL_N. Switch units T1-T24 can be either N-type transistors or P-type transistors.

[0053] In this embodiment, sub-pixel units P1, P5, P9, P13, P17, and P21 may be, for example, red sub-pixel units. Sub-pixel units P2, P4, P6, P8, P10, P12, P14, P16, P18, P20, P22, and P24 may be, for example, green sub-pixel units. Sub-pixel units P3, P7, P11, P15, P19, and P23 may be, for example, blue sub-pixel units. In another embodiment, sub-pixel units P1, P4, P7, P10, P13, P16, P19, and P22 may be, for example, red sub-pixel units. Sub-pixel units P2, P5, P8, P11, P14, P17, P20, and P23 may be, for example, green sub-pixel units. Sub-pixel units P3, P6, P9, P12, P15, P18, P21, and P24 may be, for example, blue sub-pixel units. In other words, the sub-pixel units in the same row may be arranged in RGB, but the present disclosure is not limited thereto.

[0054] In this embodiment, switch units ST1-ST3 can also be electrically connected to the same signal line SL1 to receive the same data signal S1. Switch units ST4-ST6 can also be electrically connected to the same signal line SL2 to receive the same data signal S2. Switch units ST7-ST9 can also be electrically connected to the same signal line SL3 to receive the same data signal S3. Switch units ST10-ST12 can also be electrically connected to the same signal line SL4 to receive the same data signal S4. In this embodiment, switch units ST1, ST4, ST7, and ST10 can receive the same clock signal CKH1. Switch units ST2, ST5, ST8, and ST11 can receive the same clock signal CKH2. Switch units ST3, ST6, ST9, and ST12 can receive the same clock signal CKH3. Switch units ST1-ST12 can each be an N-type transistor or a P-type transistor.

[0055] In one embodiment of the present disclosure, the substrate further includes a composite layer. The composite layer may, for example, include a first metal layer M1, a second metal layer M2, and a third metal layer M3, wherein the second metal layer M2 may be disposed between the first metal layer M1 and the third metal layer M3, but the present disclosure is not limited thereto, and multiple insulating layers and multiple through-holes connecting the two adjacent metal layers may also be disposed between any two adjacent metal layers. The signal lines DL4-DL5, DL6-DL12 may respectively extend to different metal layers through corresponding through-holes, and then, through wiring, a portion of the signal lines DL1-DL12 may be arranged in a different order in the first region 110 than in the second region 120, 120', and the signal lines DL1-DL12 may be further extended to another metal layer through another through-hole and the arrangement order of the signal lines DL1-DL12 may be restored, but the present disclosure is not limited thereto. In addition, the gate line GL_N and the gate line GL_(N+1) may be formed in the second metal layer M2, but the present disclosure is not limited thereto.

[0056] For example, on the side of the first region 110 near the second region 120, the signal lines DL1-DL6 may be first disposed in the second metal layer M2 of the substrate, wherein the signal lines DL4 and DL5 may extend to the third metal layer M3 through vias C1 and C3, respectively, and then transfer to the second metal layer M2 through vias C2 and C4, respectively. On the side of the first region 110 near the second region 120', the signal lines DL4 and DL5 may extend to the third metal layer M3 through vias C19 and C21, respectively, and then transfer to the second metal layer M2 through vias C18 and C20, respectively, but the present disclosure is not limited to this. The signal lines DL1-DL3 and DL6 may be disposed in the second metal layer M2 in both the first region 110 and the second region 120, but the present disclosure is not limited to this. It should be noted that the “side of the first region 110 close to the second region 120′” mentioned above is a line dividing the first region 110 into two sides at half the distance in the Y-axis direction or the direction perpendicular to the gate line in the first region 110, one of which is closer to the “second region 120′”, but the present disclosure is not limited thereto.

[0057] In the side of the first region 110 close to the second region 120, the signal lines DL7 to DL12 can, for example, be first set in the second metal layer M2 of the substrate. Then, the signal lines DL_7 to DL_9 and DL12 are transferred to the first metal layer M1 through the through holes C5, C6, C8, and C16 respectively. In addition, the signal lines DL10 and DL11 can extend to the third metal layer M3 through the through holes C10 and C13 respectively, and then transfer to the second metal layer M2 through the through holes C11 and C14 respectively, and then transfer to the first metal layer M1 through the through holes C12 and C15 respectively, but the present disclosure is not limited to this. In the side of the first region 110 close to the second region 120', the signal lines DL_7 to DL_9 and DL12 are transferred to the second metal layer M2 through the through holes C22, C23, C25, and C33 respectively, and the signal lines DL10 and DL11 are transferred to the second metal layer M2 through the through holes C28 and C32 respectively. Next, the signal lines DL10 and DL11 extend to the third metal layer M3 through the vias C27 and C31 respectively, and then transfer to the second metal layer M2 through the vias C26 and C30 respectively.

[0058] On the side of first region 110 near second region 120, signal lines DL4, DL5, DL10, and DL11, respectively, include first portions B11, B21, B31, and B41 disposed on second metal layer M2, second portions B12, B22, B32, and B42 disposed on third metal layer M3, and third portions B13, B23, B33, and B43 disposed on second metal layer M2, but the disclosure is not limited thereto. Second portions B12, B22, B32, and B42 of signal lines DL4, DL5, DL10, and DL11 are connected between first portions B11, B21, B31, and B41 and third portions B13, B23, B33, and B43, respectively. In another embodiment (not shown), the first portions B11, B21, B31, and B41 of the signal lines DL4, DL5, DL10, and DL11 and the second portions B12, B22, B32, and B42 of the signal lines DL4, DL5, DL10, and DL11 may be disposed on the same metal layer of the substrate 100. The second portions B12, B22, B32, and B42 of the signal lines DL4, DL5, DL10, and DL11 and the third portions B13, B23, B33, and B43 of the signal lines DL4, DL5, DL10, and DL11 may be disposed on the same or different metal layers of the substrate 100, depending on device requirements. Furthermore, the second portions B12, B22, B32, and B42 of the signal lines DL4, DL5, DL10, and DL11, respectively, may be separated from each other when viewed from above the substrate 100. In one embodiment, the extension direction of a portion of the second portions B12, B22, B32, and B42 of the signal lines DL4, DL5, DL10, and DL11 may be perpendicular to the extension direction of the first portions B11, B21, B31, and B41 of the signal lines DL4, DL5, DL10, and DL11, or to the third portions B13, B23, B33, and B43 of the signal lines DL4, DL5, DL10, and DL11, respectively, but the present disclosure is not limited thereto. It should be noted that the "side of the first region 110 closer to the second region 120" described above refers to the first region 110 being divided into two sides by a point half the distance in the Y-axis direction or the direction perpendicular to the gate lines in the first region 110, one of which is closer to the "second region 120," but the present disclosure is not limited thereto.

[0059] Between the first region 110 and the second region 120, the first portion B11 of the signal line DL4 extends through the through hole C1 to the second portion B12 located in a different metal layer (e.g., the third metal layer M3). The second portion B12 of the signal line DL4 can pass through at least one signal line (e.g., signal line DL2, signal line DL3) in the top view direction, and then transfer to a different metal layer (e.g., the second metal layer M2) through the through hole C2. In this way, the arrangement order of multiple signal lines (e.g., signal lines DL1 to DL4) in the first region 110 (e.g., signal line DL1, signal line DL4, signal line DL2, signal line DL3) can be different from the arrangement order in the second region 120 (e.g., signal line DL1, signal line DL2, signal line DL3, signal line DL4), but the present disclosure is not limited to this. Furthermore, on the side of the first region 110 near the second region 120', the signal line DL4 can extend through the second metal layer M2 to the via C19, transfer to the third metal layer M3 through the via C19, and then transfer to the second metal layer M2 through the via C18. The routing configuration of the signal line DL4 between the first region 110 and the second region 120' can be symmetrical to the routing configuration on the side of the first region 110 near the second region 120, so that the signal line DL4 can be again arranged between the signal line DL3 and the signal line DL5.

[0060] In the first region 110 , the partial signal line DL1 and the partial signal line DL4 may be disposed on the same side of the isolation element K1 , and the partial signal line DL1 and the partial signal line DL4 may be disposed adjacent to each other.

[0061] Between the first region 110 and the second region 120, the first portion B21 of the signal line DL5 extends through the through-hole C3 to the second portion B22 located in a different metal layer (e.g., the third metal layer M3). The second portion B22 of the signal line DL5 can pass through at least one signal line (e.g., the signal line DL3) in the top view direction, and then transfer to a different metal layer (e.g., the second metal layer M2) through the through-hole C4. In this way, the arrangement order of multiple signal lines (e.g., signal lines DL3 to DL6) in the first region 110 (e.g., signal lines DL4, DL5, DL3, DL6) can be different from the arrangement order in the second region 120 (e.g., signal lines DL3, DL4, DL5, DL6), but the present disclosure is not limited to this. In addition, on the side of the first region 110 close to the second region 120', the signal line DL5 can extend through the second metal layer M2 to the through-hole C21, and transfer to the third metal layer M3 through the through-hole C21, and then transfer to the second metal layer M2 through the through-hole C20. The routing configuration of the signal line DL5 on the side of the first area 110 close to the second area 120 ′ may be symmetrical to the routing configuration on the side of the first area 110 close to the second area 120 , so that the signal line DL5 may be arranged again between the signal line DL4 and the signal line DL6 .

[0062] In the first region 110, portions of signal line DL2 and signal line DL5 can be arranged between isolation element K1 and isolation element K2, and portions of signal line DL2 and signal line DL5 can be arranged adjacent to each other. On the side of the first region 110 near the second region 120, the routing path of signal line DL3 can be bent to bring it closer to signal line DL6. Furthermore, on the side of the first region 110 near the second region 120', the routing configuration of signal line DL3 can be symmetrical to the routing configuration on the side of the first region 110 near the second region 120, so that signal line DL3 can be again arranged between signal line DL2 and signal line DL4.

[0063] In the first region 110 , a portion of the signal line DL3 and a portion of the signal line DL6 may be disposed between the isolation element K2 and the isolation element K3 , and the portion of the signal line DL3 and the portion of the signal line DL6 may be disposed adjacent to each other.

[0064] Between the first region 110 and the second region 120, a first portion B31 of the signal line DL10 extends through a through hole C10 to a second portion B32 located in a different metal layer (e.g., the third metal layer M3). The second portion B32 of the signal line DL10 can pass through at least one signal line (e.g., signal lines DL8 and DL9) in a top-down direction, then transfer to a different metal layer (e.g., the second metal layer M2) through a through hole C11, and then transfer to a different metal layer (e.g., the first metal layer M1) through C11. In this way, the arrangement order of multiple signal lines (e.g., signal lines DL7 to DL10) in the first region 110 (e.g., signal lines DL7, DL10, DL8, DL9) can be different from the arrangement order in the second region 120 (e.g., signal lines DL7, DL8, DL9, DL10), but the present disclosure is not limited to this. Furthermore, on the side of the first region 110 near the second region 120', the signal line DL10 may extend through the first metal layer M1 to the through-hole C28 and transfer to the second metal layer M2 through the through-hole C28. Next, the signal line DL10 may extend through the second metal layer M2 to the through-hole C27 and transfer to the third metal layer M3 through the through-hole C27. Next, the signal line DL10 may extend through the third metal layer M3 to the through-hole C26 and transfer to the second metal layer M2 through the through-hole C26. The routing configuration of the signal line DL10 on the side of the first region 110 near the second region 120' may be symmetrical to the routing configuration on the side of the first region 110 near the second region 120, so that the signal line DL10 can be again arranged between the signal line DL9 and the signal line DL11.

[0065] In the first region 110 , a portion of the signal line DL7 and a portion of the signal line DL10 may be disposed between the isolation element K3 and the isolation element K4 , and the portion of the signal line DL7 and the portion of the signal line DL10 may be disposed adjacent to each other.

[0066] It is worth noting that the signal line DL7 and the signal line DL10 can, for example, be transferred to different metal layers (e.g., the third metal layer M3) via different through-holes, and can be pulled above the signal line DL1 and the signal line DL4 in the first area 110, but the present disclosure is not limited to this. In this regard, in the first area 110, part of the signal line DL1 and part of the signal line DL7 can overlap in the top-down direction, and part of the signal line DL4 and part of the signal line DL10 can overlap in the top-down direction. On the side of the first area 110 close to the second area 120, the first portion B41 of the signal line DL11 extends through the through-hole C13 to the second portion B42 located in a different metal layer (e.g., the third metal layer M3). The second portion B42 of the signal line DL11 can pass through at least one signal line (e.g., the signal line DL9) in the top-down direction, and then transfer to a different metal layer (e.g., the second metal layer M2) through the through-hole C14, and then transfer to a different metal layer (e.g., the first metal layer M1) through C15. In this way, the arrangement order of a plurality of signal lines (for example, signal lines DL9 to DL12) in part of the first region 110 (for example, signal lines DL11, DL9, DL12) can be different from the arrangement order in the second region 120 (for example, signal lines DL9, DL11, DL12), but the present disclosure is not limited to this. Moreover, on the side of the first region 110 close to the second region 120', the signal line DL11 can extend through the first metal layer M1 to the through hole C32, and transfer to the second metal layer M2 through the through hole C32. Then, the signal line DL11 can extend through the second metal layer M2 to the through hole C31, and transfer to the third metal layer M3 through the through hole C31. Then, the signal line DL11 can extend through the third metal layer M3 to the through hole C30, and transfer to the second metal layer M2 through the through hole C30. The routing configuration of the signal line DL11 on the side of the first area 110 close to the second area 120 ′ may be symmetrical to the routing configuration on the side of the first area 110 close to the second area 120 , so that the signal line DL11 may be arranged again between the signal line DL10 and the signal line DL12 .

[0067] In the first region 110 , a portion of the signal line DL8 and a portion of the signal line DL11 may be disposed between the isolation element K4 and the isolation element K5 , and the portion of the signal line DL8 and the portion of the signal line DL11 may be disposed adjacent to each other.

[0068] It is worth noting that signal line DL8 and signal line DL11 can, for example, be routed to different metal layers (e.g., the third metal layer M3) via different vias, and then routed above signal line DL2 and signal line DL5 in first region 110, but the present disclosure is not limited thereto. In this regard, portions of signal line DL2 and signal line DL8 can overlap in a top-down direction, and portions of signal line DL5 and signal line DL11 can overlap in a top-down direction.

[0069] On the side of the first region 110 near the second region 120, the routing path of signal line DL9 can be bent to bring it closer to signal line DL12. Thus, in the first region 110, portions of signal line DL9 and portions of signal line DL12 can be arranged between isolation element K5 and isolation element K6, and portions of signal line DL9 and portions of signal line DL12 can be arranged adjacent to each other. Furthermore, the routing configuration of signal line DL9 on the side of the first region 110 near the second region 120' can be symmetrical to the routing configuration on the side of the first region 110 near the second region 120, so that signal line DL9 can be again arranged between signal line DL8 and signal line DL10.

[0070] It is worth noting that the signal line DL9 and the signal line DL12 can be transferred to different metal layers (e.g., the third metal layer M3) via different vias (e.g., vias C8 and C16), and can be routed above the signal line DL3 and the signal line DL6 in the first region 110. In this regard, portions of the signal line DL3 and the signal line DL9 can overlap in a top-down direction, and portions of the signal line DL6 and the signal line DL12 can overlap in a top-down direction.

[0071] Please refer to Figure 2 and Figure 4In one embodiment, in the first region 110, signal lines DL1 and DL4, which are controlled by the same clock signal CKH1, have a first on-time period (e.g., from time t1 to time t2) to transmit the first signal D1 and the second signal D4, respectively. Signal lines DL1 and DL4 may be arranged adjacent to each other and may form a first signal line group. Signal lines DL2 and DL5, which are controlled by the same clock signal CKH2, have a second on-time period (e.g., from time t3 to time t4) to transmit the second signal D2 and the fifth signal D5, respectively. Signal lines DL2 and DL5 may be arranged adjacent to each other and may form a second signal line group. A spacer element K1 may be disposed between the first and second signal line groups. Signal lines DL3 and DL6, which are controlled by the same clock signal CKH3, have a third on-time period (e.g., from time t5 to time t6) to transmit the third signal D3 and the sixth signal D6, respectively. Signal lines DL3 and DL6 may be arranged adjacent to each other and may form a third signal line group. The spacer element K2 can be arranged between the second signal line group and the third signal line group. Signal lines DL7 and DL10, which are controlled by the same clock signal CKH1, have a first on-time period (e.g., from time t1 to time t2). Signal lines DL7 and DL10 can be arranged adjacent to each other and can form a fourth signal line group. The spacer element K3 can be arranged between the third signal line group and the fourth signal line group. Signal lines DL8 and DL11, which are controlled by the same clock signal CKH2, have a second on-time period (e.g., from time t3 to time t4) and can be arranged adjacent to each other and can form a fifth signal line group. The spacer element K4 can be arranged between the fourth signal line group and the fifth signal line group. Signal lines DL9 and DL12, which are controlled by the same clock signal CKH3, have a third on-time period (e.g., from time t5 to time t6). Signal lines DL9 and DL12 can be arranged adjacent to each other and can form a sixth signal line group. The spacer element K5 may be disposed between the fifth signal line group and the sixth signal line group. Similarly, the spacer element K5 may be disposed between the sixth signal line group and the next signal line.

[0072] In one embodiment, the first on-time period (e.g., time t1 to time t2), the second on-time period (e.g., time t3 to time t4), and the third on-time period (e.g., time t5 to time t6) are different from each other, but are not limited thereto. For example, the start time of the first on-time period (e.g., time t1) is earlier than the start time of the second on-time period (e.g., time t3), and the start time of the second on-time period (e.g., time t3) is earlier than the start time of the third on-time period (e.g., time t5), but are not limited thereto.

[0073] In this embodiment, the isolation elements K1 to K6 may be conductive elements or insulating elements. If the isolation elements K1 to K6 are conductive elements, the isolation elements K1 to K6 may receive a reference voltage (Vcom), a ground voltage (GND) or other signals other than the display data signal, but the present disclosure is not limited thereto. In addition, the isolation element has a linear or strip-shaped appearance. The isolation element may be disposed in the same metal layer as the adjacent signal line and may be extended to another metal layer via a through-hole transfer layer. Specifically, for example, the isolation elements K1 to K3 may be disposed in the second metal layer M2. On the other hand, the isolation elements K4 to K6 may be first disposed in the second metal layer M2 and then extended to the first metal layer M1 via through-holes C7, C9, and C17, respectively. Moreover, some of the isolation elements K1 and K4 in the first region 110 may overlap in the top-view direction (i.e., the Z direction), some of the isolation elements K2 and K5 in the first region 110 may overlap in the top-view direction, some of the isolation elements K3 and K6 in the first region 110 may overlap in the top-view direction, and some of the isolation elements K1 and K4 may overlap in the top-view direction (i.e., the Z direction), but the present disclosure is not limited to this.

[0074] In addition, in one embodiment, Figure 2 The second region 120 shown includes a first reference line f1, and the first region 110 includes a second reference line f2. The first reference line f1 is parallel to the in-plane gate lines, while the second reference line f2 is perpendicular to the in-plane gate lines. Assuming the first and second reference lines f1 and f2 are equal in length, the number of signal lines spanned by the second reference line f2 on the actual substrate is greater than or equal to the number of signal lines spanned by the first reference line f1. This demonstrates that the signal lines in the first region 110 are more densely arranged than those in the second region 120, minimizing the non-display area and maximizing the display surface utilization of the display device.

[0075] Figure 3A as well as Figure 3B FIG. 1 is a schematic diagram of the width of a signal line according to an embodiment of the present disclosure. Figure 2 as well as Figure 3A ,by Figure 2 Taking signal line DL4 as an example, first portion B11 of signal line DL4 transfers to second portion B12 of signal line DL4 via through-hole C1. Signal line DL4 located in second region 120 has a width W1. First portion B11 of signal line DL4, which connects to one end of through-hole C1, has a width W2. Width W2 is greater than or equal to width W1. Furthermore, second portion B12 of signal line DL4, which connects to the other end of through-hole C1, has a width W3. Second portion B12 has a minimum width W4. Width W3 is greater than or equal to minimum width W4.

[0076] refer to Figure 2 as well as Figure 3B ,by Figure 2 Taking the signal line DL4 as an example, the second part B12 of the signal line DL4 is transferred to the third part B13 of the signal line DL4 via the through hole C2. The third part B13 of the signal line DL4 has a width W5. The third part B13 of the signal line DL4 connected to one end of the through hole C2 has a width W6. The width W6 is greater than or equal to the width W1. In addition, the second part B12 of the signal line DL4 connected to the other end of the through hole C2 has a width W7, and there is a minimum width W8 in the second part B12. The width W7 is greater than or equal to the minimum width W8. Similarly, the implementation method of the line width of the signal lines of other signal lines in the path of realizing the layer transfer can be as follows. Figure 3A and Figure 3B This can be achieved in a way that improves the alignment efficiency and the yield rate of circuit conduction during the process.

[0077] Figure 4 is a signal timing diagram of an embodiment of the present disclosure. Figure 2 as well as Figure 4 In this embodiment, the signal lines SL1 to SL4 can receive data signals S1 to S4. The gate line GL_N can receive the gate control signal GS_N, and the gate line GL_(N+1) can receive the gate control signal GS_(N+1). The clock signals CKH1 to CKH3 can turn on different switch units (ST1 to ST12) in a time-sharing manner. However, the number of clock signals, gate control signals, and data signals used in the display device disclosed herein is not limited to Figure 4 As shown, and the amount of displayed data is not limited to Figure 4 shown.

[0078] Specifically, from time t0 to time t7, the gate control signal GS_N switches from a low voltage level to a high voltage level to turn on switch units T13-T24. From time t1 to time t2, the clock signal CKH1 switches from a low voltage level to a high voltage level to turn on switch units ST1, ST4, ST7, and ST10. Therefore, the signal lines DL1, DL4, DL7, and DL10 can respectively transmit the display data D1, D4, D7, and D10 of the data signals S1-S4 provided by the signal lines SL1-SL4, and drive the pixel units P13, P16, P19, and P22. From time t2 to time t3, the clock signal CKH2 switches from a low voltage level to a high voltage level to turn on switch units ST2, ST5, ST8, and ST11. Therefore, signal lines DL2, DL5, DL8, and DL11 can respectively transmit display data D2, D5, D8, and D11 of data signals S1-S4 provided by signal lines SL1-SL4, and drive pixel cells P14, P17, P20, and P23. During time t4 to time t5, clock signal CKH3 switches from a low voltage level to a high voltage level, turning on switch units ST3, ST6, ST9, and ST12. Therefore, signal lines DL3, DL6, DL9, and DL12 can respectively transmit display data D3, D6, D9, and D12 of data signals S1-S4 provided by signal lines SL1-SL4, and drive pixel cells P15, P18, P21, and P24.

[0079] During the period from time t8 to time t15, the gate control signal GS_(N+1) switches from a low voltage level to a high voltage level to turn on the switch units T1-T12. During the period from time t9 to time t10, the clock signal CKH1 switches from a low voltage level to a high voltage level to turn on the switch units ST1, ST4, ST7, and ST10. Therefore, the signal lines DL1, DL4, DL7, and DL10 can respectively transmit the display data D1, D4, D7, and D10 of the data signals S1-S4 provided by the signal lines SL1-SL4, and drive the pixel units P1, P4, P7, and P10. During the period from time t11 to time t12, the clock signal CKH2 switches from a low voltage level to a high voltage level to turn on the switch units ST2, ST5, ST8, and ST11. Therefore, signal lines DL2, DL5, DL8, and DL11 can respectively transmit display data D2, D5, D8, and D11 of data signals S1-S4 provided by signal lines SL1-SL4, and drive pixel cells P2, P5, P8, and P11. During time t13 to time t14, clock signal CKH3 switches from a low voltage level to a high voltage level, turning on switch units ST3, ST6, ST9, and ST12. Therefore, signal lines DL3, DL6, DL9, and DL12 can respectively transmit display data D3, D6, D9, and D12 of data signals S1-S4 provided by signal lines SL1-SL4, and drive pixel cells P3, P7, P10, and P12.

[0080] In addition, in another embodiment, the display device may further include another gate line transmitting a gate control signal GS_(N-1), wherein the gate control signal GS_(N-1) may be switched from a low voltage level to a high voltage level at time t0 to turn on multiple switching units in the corresponding column, but the present disclosure is not limited to this.

[0081] In this embodiment, during the driving of the pixel units P1 to P24, although the routing pitch of some signal lines DL1 to DL12 in the first region 110 is reduced, the signal coupling effect between the signal lines DL1 to DL12 can be effectively reduced by reconfiguring the routing sequence and providing isolation elements K1 to K6.

[0082] Specifically, during the periods of respectively driving the pixel units P1, P4, P7, P10, P13, P16, P19, and P22, since some of the signal lines DL1, DL4, DL7, and DL10 can be arranged adjacent to each other in the first area 110 and isolated from other signal lines by isolation elements, the signal lines DL1, DL4, DL7, and DL10 can reduce the influence of signal coupling from other signal lines (no data is written to the other signal lines during this period) during the period when the display data D1, D4, D7, and D10 are simultaneously transmitted based on the clock signal CKH1. During the periods of respectively driving the pixel units P2, P5, P8, P11, P14, P17, P20, and P23, since some of the signal lines DL2, DL5, DL8, and DL11 can be arranged adjacent to each other in the first area 110 and isolated from other signal lines by isolation elements, the signal lines DL2, DL5, DL8, and DL11 can reduce the influence of signal coupling from other signal lines (no data is written to the other signal lines during this period) during the period when the display data D2, D5, D8, and D11 are simultaneously transmitted based on the clock signal CKH2. During the periods of respectively driving the pixel units P3, P6, P9, P12, P15, P18, P21, and P24, since some of the signal lines DL3, DL6, DL9, and DL12 can be arranged adjacent to each other in the first area 110 and isolated from other signal lines by isolation elements, the signal lines DL3, DL6, DL9, and DL12 can reduce the influence of signal coupling from other signal lines (no data is written to the other signal lines during this period) during the period when the display data D3, D6, D9, and D12 are simultaneously transmitted based on the clock signal CKH3.

[0083] Figure 5 is a schematic diagram of a display device according to another embodiment of the present disclosure. Figure 5 , the display device 10 includes a substrate 100. The substrate 100 includes a first area 110, a second area 120, 120' and a third area 130. The first area 110 is located between the second area 120 and the second area 120', and the minimum width of the first area 110 in the X direction is smaller than the minimum width of the second area 120, 120'. The third area 130 is located below the second area 120. The third area 130 may be provided with a multi-way distributor circuit 140 and a driving circuit 150. The driving circuit 150 may send signals to the second area 120, 120' and the plurality of signal lines L_1 to L_k of the first area 110 via the multi-way distributor circuit 140, where k is a positive integer. In another embodiment of the present disclosure, the substrate 100 of the display device 10 may be other irregular shapes. In this regard, in an irregularly shaped display area, for example, the routing configuration of the signal line at the location where the width is reduced in the X direction in the first area 110 may adopt the routing configuration described in the above embodiments (for example Figure 2This can be achieved by using methods such as routing, layer switching, and the provision of isolation components. This can effectively reduce the impact of signal coupling between signal lines in areas where routing space is reduced.

[0084] In addition, in this alternative embodiment, the plurality of pixels in the second regions 120, 120' may be arranged along the X-axis in a pattern of red pixels, green pixels, and blue pixels, but the present disclosure is not limited thereto. In another embodiment (not shown), the plurality of pixels in the second regions 120, 120' may also be arranged along the X-axis in a pattern of red pixels, green pixels, blue pixels, and green pixels. Alternatively, the plurality of pixels in the second regions 120, 120' may be arranged in a regular, irregular, or semi-irregular arrangement.

[0085] In summary, the display device disclosed herein utilizes a special routing configuration within the aperture boundary region of the aperture frame, combined with the design of isolation elements, to effectively reduce signal coupling interference between multiple signal lines passing through the aperture boundary region of the aperture frame. Consequently, the display device disclosed herein can provide excellent display performance.

[0086] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A display device, characterized in that: include: A substrate having a first region and a second region, wherein the second region surrounds the first region; A first signal line, a second signal line, and a third signal line are provided on the substrate, respectively extending from the second area to the first area, and respectively used for time-sharing transmission of a first signal, a second signal, and a third signal; as well as A plurality of isolation elements are disposed in the first region, The first signal and the second signal each have a first on-time period, and the third signal has a second on-time period, wherein the first on-time period is different from the second on-time period, wherein in the second region, the third signal line is arranged between the first signal line and the second signal line, In the first region, the second signal line is disposed between the first signal line and the third signal line, and one of the plurality of isolation elements is disposed between the second signal line and a portion of the third signal line.

2. The display device according to claim 1, wherein The first signal line and the second signal line respectively include a first portion, a second portion, and a third portion, wherein the second portion is connected between the first portion and the third portion.

3. The display device according to claim 2, wherein: In a plan view, the second portion of the first signal line and the second portion of the second signal line are separated from each other.

4. The display device according to claim 2, wherein: The extending directions of the second portion of the part and the first portion of the part are perpendicular to each other.

5. The display device according to claim 2, wherein The first portion and the second portion are located at different layers, and the second portion and the third portion are located at different layers.

6. The display device according to claim 1, wherein Also includes: A plurality of sub-pixels are disposed in the second region of the substrate, wherein the second signal line is electrically connected to a portion of the plurality of sub-pixels, and the third signal line is electrically connected to another portion of the plurality of sub-pixels.

7. The display device according to claim 6, wherein: The portion of the plurality of sub-pixels and the other portion of the plurality of sub-pixels are sub-pixels of the same color.

8. The display device according to claim 1, wherein In the second region of the substrate, part of the third signal line is provided between part of the first signal line and part of the second signal line, and in the first region of the substrate, the second signal line is provided between the first signal line and the third signal line.

9. The display device according to claim 1, wherein The plurality of isolation elements include conductive elements.

10. The display device according to claim 1, wherein The plurality of isolation elements include insulating elements.

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