Display panel and display device

Abstract

The invention discloses a display panel and a display device, and the display panel comprises a plurality of pixel groups, each pixel group comprises a plurality of pixel rows, and each pixel row comprises a plurality of pixel circuits; the pixel circuit comprises a frequency switching module, a driving transistor and a light-emitting element, the frequency switching module is electrically connected with a grid electrode of the driving transistor, and a first electrode of the driving transistor is electrically connected with the light-emitting element; the frequency switching modules are arranged in the pixel groups, the control ends of the frequency switching modules are electrically connected with the frequency switching control lines, the frequency switching modules in one pixel group are electrically connected to the same frequency switching control line, and the two frequency switching modules in the two adjacent pixel groups are electrically connected to the two frequency switching control lines; in the multi-frequency display mode, the display panel at least comprises two display subareas with different refresh frequencies, each display subarea comprises at least one pixel group, and the frequency switching control lines corresponding to the display subareas control the frequency switching modules to be switched on or switched off at the same time so as to control the refresh frequencies of the display subareas. According to the invention, the frame is effectively saved and optimized.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, the application scenarios of display devices are increasing, and users' display requirements for display devices are becoming more and more diverse.

[0003] Currently, based on users' demand for simultaneous display of multiple application scenarios of terminal products, some display devices have a partition refresh function.

[0004] However, the existing partition refresh related circuit architecture is relatively large, occupying a larger border area of ​​the display device, which is not conducive to a narrow border. Summary of the Invention

[0005] The present invention provides a display panel and a display device to save a frame.

[0006] According to one aspect of the present invention, there is provided a display panel, comprising:

[0007] a plurality of pixel groups arranged along a first direction, the pixel groups comprising a plurality of pixel rows arranged along the first direction, one of the pixel rows comprising a plurality of pixel circuits arranged along a second direction, the first direction intersecting the second direction;

[0008] The pixel circuit includes a frequency cutting module, a driving transistor and a light-emitting element, wherein the frequency cutting module is electrically connected in series to the gate of the driving transistor, and the first electrode of the driving transistor is electrically connected to the light-emitting element;

[0009] a driving chip and at least two frequency cutting control lines electrically connected to the driving chip, wherein a control end of the frequency cutting module is electrically connected to the frequency cutting control line, the frequency cutting modules in one pixel group are electrically connected to the same frequency cutting control line, and two frequency cutting modules in two adjacent pixel groups are electrically connected to two frequency cutting control lines;

[0010] The display panel includes a multi-frequency display mode;

[0011] In the multi-frequency display mode, the display panel includes at least two display partitions with different refresh frequencies, each display partition includes at least one pixel group, and each of the frequency cutting control lines corresponding to the display partition controls the frequency cutting modules therein to be turned on or off simultaneously to control the refresh frequency of the display partition.

[0012] According to another aspect of the present invention, a display device is provided, comprising: the display panel as described above.

[0013] In the present invention, a frequency-cutting module is provided in a pixel circuit, and a control end of the frequency-cutting module is electrically connected to a frequency-cutting control line. The frequency-cutting module in a pixel group is electrically connected to the same frequency-cutting control line, and two frequency-cutting modules in two adjacent pixel groups are electrically connected to two frequency-cutting control lines. In a multi-frequency display mode, the display panel includes at least two display partitions with different refresh frequencies, and the frequency-cutting control lines corresponding to the display partitions control the frequency-cutting modules therein to simultaneously turn on or off to control the refresh frequencies of the display partitions. The driver chip controls the switching frequency of the frequency-cutting module via the frequency-cutting control lines, thereby achieving the purpose of controlling the refresh frequency of the pixel circuit, thereby realizing multi-frequency display of the display panel and arbitrarily dividing the positions of multiple display partitions. In the present invention, the driver chip alternately connects to different pixel groups via multiple frequency-cutting control lines, thereby performing refresh drive gating control on the frequency-cutting modules within the pixel circuit, realizing independent refresh control of each pixel group, and thus realizing flexible partition refresh. Therefore, there is no need to set a refresh drive circuit and its corresponding shift register or gating circuit in the non-display area of ​​the display panel, effectively saving and optimizing the frame.

[0014] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 is a schematic diagram of a display panel provided by an embodiment of the present invention;

[0017] Figure 2 is a schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0018] Figure 3 yes Figure 1 A timing diagram of the display panel is shown;

[0019] Figure 4 is a schematic diagram of another display panel provided by an embodiment of the present invention;

[0020] Figure 5 is a schematic diagram of another display panel provided by an embodiment of the present invention;

[0021] Figure 6 yes Figure 2A timing diagram of the pixel circuit shown;

[0022] Figure 7 is a schematic diagram of another display panel provided by an embodiment of the present invention;

[0023] Figure 8 yes Figure 7 A timing diagram of the display panel is shown;

[0024] Figure 9 yes Figure 7 Another timing diagram of the display panel shown;

[0025] Figure 10 is a schematic diagram of another display panel provided by an embodiment of the present invention;

[0026] Figure 11 yes Figure 10 A schematic diagram of a pixel circuit is shown;

[0027] Figure 12 yes Figure 11 A timing diagram of the pixel circuit shown;

[0028] Figure 13 is a schematic diagram of another display panel provided by an embodiment of the present invention;

[0029] Figure 14 yes Figure 13 A timing diagram of the display panel is shown;

[0030] Figure 15 is a schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0031] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0032] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0033] Figure 1 is a schematic diagram of a display panel provided by an embodiment of the present invention, Figure 2 is a schematic diagram of a pixel circuit provided by an embodiment of the present invention, such as Figure 1 and Figure 2 The display panel 100 provided in this embodiment includes: a plurality of pixel groups 101 arranged along a first direction Y, the pixel group 101 includes a plurality of pixel rows arranged along the first direction Y, and each pixel row includes a plurality of pixel circuits 102 arranged along a second direction X, wherein the first direction Y and the second direction X intersect; the pixel circuit 102 includes a frequency cutting module 103, a driving transistor M3 and a light-emitting element 104, the frequency cutting module 103 is electrically connected in series to the gate N1 of the driving transistor M3, and the first electrode N3 of the driving transistor M3 is electrically connected to the light-emitting element 104; a driving chip 131 and at least two frequency cutting control lines Ctrl electrically connected to the driving chip 131, and the frequency cutting module The control terminal CtrlS of 103 is electrically connected to the frequency cutting control line Ctrl, the frequency cutting module 103 in one pixel group 101 is electrically connected to the same frequency cutting control line Ctrl, and the two frequency cutting modules 103 located in two adjacent pixel groups 101 are electrically connected to two frequency cutting control lines Ctrl; the display panel 100 includes a multi-frequency display mode; in the multi-frequency display mode, the display panel 100 includes at least two display partitions AA with different refresh frequencies, and the display partition AA includes at least one pixel group 101. The frequency cutting control lines Ctrl corresponding to the display partitions AA control the frequency cutting modules 103 therein to be turned on or off simultaneously to control the refresh frequency of the display partition AA. In the present invention, the electrical connection between two components may include: the two components are directly connected through a transfer part, a signal line, etc., or the two components are indirectly connected through other components, components, circuits, etc. This is not limited in the embodiments of the present invention.

[0034] In this embodiment, the display panel 100 includes a plurality of pixel groups 101 arranged along a first direction Y. The pixel groups 101 include a plurality of pixel rows arranged along the first direction Y, and each pixel row includes a plurality of pixel circuits 102 arranged along a second direction X. The number of pixel rows in two adjacent pixel groups 101 can be the same or different. Relevant practitioners can reasonably design the number of pixel rows in each pixel group 101 based on product requirements.

[0035] The pixel circuit 102 includes a driving transistor M3 and a light-emitting element 104. The driving transistor M3 includes a gate N1, a second electrode N2, and a first electrode N3. The second electrode N2 of the driving transistor M3 is electrically connected to the first power supply terminal PVDD, and the first electrode N3 of the driving transistor M3 is electrically connected to the light-emitting element 104. One of the second electrode N2 and the first electrode N3 of the driving transistor M3 is a source electrode, and the other is a drain electrode. Optionally, the first electrode N3 of the driving transistor M3 is electrically connected to the anode of the light-emitting element 104. Input signals in the pixel circuit 102 determine the on / off state of the driving transistor M3. Specifically, the driving transistor M3 is used to provide a driving current to the light-emitting element 104 during the light-emitting phase, driving the light-emitting element 104 to emit light, thereby achieving image display on the display panel 100.

[0036] The pixel circuit 102 further includes a frequency cutting module 103, which is electrically connected in series to the gate N1 of the driving transistor M3. Figure 2 As shown, the module 103a in the pixel circuit 102 is the frequency cutting module 103. The frequency cutting module 103 is connected in series to a gate signal transmission path electrically connected to the gate N1 of the driving transistor M3. Accordingly, the on-off state of the frequency cutting module 103 affects the on-off state of the gate signal transmission path of the driving transistor M3, thereby affecting the potential of the gate N1 of the driving transistor M3 in the pixel circuit 102. Specifically, if the frequency cutting module 103 in the pixel circuit 102 is disconnected, the gate signal transmission path where the frequency cutting module 103 is located is disconnected, and the various input signals in the pixel circuit 102 cannot adjust the potential of the gate N1 of the driving transistor M3, so that the pixel circuit 102 cannot refresh data. Conversely, if the frequency cutting module 103 in the pixel circuit 102 is turned on, the on-off state of the gate signal transmission path of the driving transistor M3 is determined by the various input signals in the pixel circuit 102, thereby adjusting the on-off state of the driving transistor M3 and achieving normal data refresh of the pixel circuit 102. Based on this, the frequency cutting module 103 is connected in series with the gate N1 of the driving transistor M3. By controlling the on and off of the frequency cutting module 103, the pixel circuit 102 can be controlled to refresh data, thereby controlling the refresh frequency of the display subarea AA where the pixel circuit 102 is located. Here, the frequency cutting module 103 is directly set in the pixel circuit 102, eliminating the need to set up a refresh driving circuit in the non-display area of ​​the display panel, which can effectively reduce the frame.

[0037] In this embodiment, the display panel 100 includes a driver chip 131 and a plurality of frequency cutting control lines Ctrl. The driver chip 131 is directly electrically connected to the frequency cutting control lines Ctrl and is used to independently provide a frequency cutting signal to each frequency cutting control line Ctrl. Based on different display modes of the display panel 100, the frequency cutting signals provided by the driver chip 131 to different frequency cutting control lines Ctrl may be the same or different. In the pixel circuit 102, the control terminal CtrlS of the frequency cutting module 103 is electrically connected to the frequency cutting control line Ctrl. Figure 2 As shown, the pixel circuit 102 includes a frequency cutting module 103a, and the control terminal CtrlSa of the frequency cutting module 103a is electrically connected to the frequency cutting control line Ctrl. Here, the frequency cutting control line Ctrl is directly electrically connected to the driver chip 131 and the frequency cutting module 103 in the pixel circuit 102. The control signal of the frequency cutting module 103 comes directly from the driver chip 131. The multiple frequency cutting control lines Ctrl are alternately connected to the pixel circuit 102 to implement the refresh control gating process. This eliminates the need to set up a refresh drive circuit and its matching shift register or gating circuit for controlling refresh in the non-display area of ​​the display panel, effectively reducing the border and optimizing the border to achieve a full screen.

[0038] In a pixel group 101, the same frequency cutting module 103 of each pixel circuit 102 is electrically connected to the same frequency cutting control line Ctrl. Figure 2 As shown, the pixel circuit 102 includes a frequency cutting module 103a, which is connected in series to the threshold compensation gate signal transmission path of the gate N1 of the driving transistor M3. The same frequency cutting module 103a of each pixel circuit 102 in the pixel group 101 is electrically connected to the same frequency cutting control line Ctrl. The same frequency cutting module 103a of two pixel circuits 102 in two adjacent pixel groups 101 is electrically connected to two different frequency cutting control lines Ctrl. Figure 2 As shown, the frequency cutting modules 103 a of the two pixel circuits 102 located in two adjacent pixel groups 101 are electrically connected to two different frequency control lines Ctrl.

[0039] Combine Figure 1 and Figure 2As shown, the pixel circuit 102 includes a frequency cutting module 103a, and two adjacent pixel groups 101 are electrically connected to two different frequency cutting control lines Ctrl. Based on the structure of this pixel circuit 102, the display panel 100 can be provided with two frequency cutting control lines Ctrl. For example, the display panel 100 includes at least four pixel groups 101. The two frequency cutting control lines Ctrl are labeled Ctrl1a and Ctrl1b, respectively. The four pixel groups 101 arranged sequentially along the first direction Y are labeled 101a, 101b, 101c, and 101d, respectively. The first frequency cutting control line Ctrl1a electrically connects the first pixel group 101a and the third pixel group 101c, and the second frequency cutting control line Ctrl1b electrically connects the second pixel group 101b and the fourth pixel group 101d. Specifically, in the first pixel group 101a, the control end CtrlSa of the frequency cutting module 103a of the pixel circuit 102 is electrically connected to the first frequency cutting control line Ctrl1a; in the second pixel group 101b, the control end CtrlSa of the frequency cutting module 103a of the pixel circuit 102 is electrically connected to the second frequency cutting control line Ctrl1b; in the third pixel group 101c, the control end CtrlSa of the frequency cutting module 103a of the pixel circuit 102 is electrically connected to the first frequency cutting control line Ctrl1a; in the fourth pixel group 101d, the control end CtrlSa of the frequency cutting module 103a of the pixel circuit 102 is electrically connected to the second frequency cutting control line Ctrl1b.

[0040] Based on the structure of the display panel 100, the driver chip 131 can independently control the frequency cutting modules 103 in each pixel group 101 to be turned on or off simultaneously by providing a frequency cutting signal to the frequency cutting control line Ctrl, thereby independently controlling the refresh frequency of each pixel group 101 and further realizing partitioned multi-frequency display of the display panel 100 in the first direction Y.

[0041] The display panel 100 includes a multi-frequency display mode. When the display panel 100 enters the multi-frequency display mode, the display panel 100 includes at least two display subareas AA with different refresh frequencies. The display subareas AA include at least one pixel group 101. The frequency switching control lines Ctrl corresponding to the display subareas AA control the frequency switching modules 103 therein to simultaneously turn on or off, thereby controlling the refresh frequency of the display subareas AA.

[0042] Figure 3 yes Figure 1 The timing diagram of the display panel is shown as follows: Figures 1 to 3As shown, for example, a display panel 100 in a multi-frequency display mode includes display partitions AA1 and AA2. In the pixel circuit 102, the frequency cutting module 103a includes an N-type transistor M9. The on-state level of the frequency cutting module 103a is high, and the off-state level of the frequency cutting module 103a is low. Exemplarily, the display partition AA1 includes a first pixel group 101a, and the display partition AA2 includes a second pixel group 101b, a third pixel group 101c, and a fourth pixel group 101d. The refresh rate of the display partition AA1 is greater than the refresh rate of the display partition AA2.

[0043] Specifically, the display panel 100 includes a plurality of display frames in the multi-frequency display mode, and each display frame includes a working phase FA1 of the display partition AA1 and a working phase FA2 of the display partition AA2. The display frame of the pixel circuit 102 can be divided into a refresh frame and a hold frame; in the refresh frame, the frequency cutting module 103 in the pixel circuit 102 is turned on, so that the pixel circuit 102 realizes data writing; in the hold frame, the frequency cutting module 103 in the pixel circuit 102 is turned off, so that the pixel circuit 102 does not refresh the data. Optionally, in the multi-frequency display mode, the display panel 100 includes a plurality of display frames, and the display frame includes a first display frame F1; in the first display frame F1, the display panel 100 includes a first display partition and a second display partition arranged alternately along the first direction Y, and the frequency cutting control line Ctrl provides a turn-on level in the working phase of the first display partition and provides a turn-off level in the working phase of the second display partition, so that the first display partition refreshes the screen. That is, the display frame in which the first display partition refreshes the screen and the second display partition does not refresh the screen is defined as the first display frame F1. Reference here Figure 1 As shown, the optional first display partition is display partition AA1, and the optional second display partition is display partition AA2.

[0044] Taking the case where the refresh frequency of display partition AA1 is greater than the refresh frequency of display partition AA2 as an example, in the multi-frequency display mode, the multiple display frames include multiple first display frames F1 and multiple second display frames F2. The first display frame F1 only refreshes the pixel circuit 102 in the display partition AA1, and the second display frame F2 can refresh both the display partition AA1 and the display partition AA2, so that the refresh frequency of the display partition AA1 is greater than the refresh frequency of the display partition AA2.

[0045] The operation process of the display panel 100 in the first display frame F1 includes: in the FA1 stage, the pixel circuit 102 in the first pixel group 101a performs row-by-row scanning control; in this stage, the driver chip 131 provides a high level to the frequency cutting control line Ctrl1a to simultaneously turn on the frequency cutting modules 103a in the first pixel group 101a and the third pixel group 101b, and the driver chip 131 provides a low level to the frequency cutting control line Ctrl1b to simultaneously turn off the frequency cutting modules 103a in the second pixel group 101b and the fourth pixel group 101d; then, in the display panel 100, the first pixel group 101a performs row-by-row scanning control and the frequency cutting modules 103a therein are simultaneously turned on, thereby realizing data refresh of the display partition AA1. In the FA2 stage, each pixel row after the first pixel group 101a is subjected to row-by-row scanning control. In this stage, the driver chip 131 provides a low level to both the frequency cutting control line Ctrl1a and the frequency cutting control line Ctrl1b. Then, in the display panel 100, the second pixel group 101b, the third pixel group 101c, and the fourth pixel group 101d are subjected to row-by-row scanning control, but the frequency cutting module 103a is turned off at the same time, so that the display partition AA2 does not perform data refresh.

[0046] The operation process of the display panel 100 in the second display frame F2 includes the following: in the FA1 stage, the pixel circuit 102 in the first pixel group 101a performs progressive scanning control; in this stage, the driver chip 131 provides a high level to the frequency cutting control line Ctrl1a and a low level to the frequency cutting control line Ctrl1b; then, in the display panel 100, the first pixel group 101a performs progressive scanning control and the frequency cutting module 103a is simultaneously turned on, realizing data refresh of the display partition AA1. In the FA2 stage, each pixel row after the first pixel group 101a performs progressive scanning control; in this stage, the driver chip 131 provides a high level to both the frequency cutting control line Ctrl1a and the frequency cutting control line Ctrl1b; then, in the display panel 100, the second pixel group 101b, the third pixel group 101c, and the fourth pixel group 101d perform progressive scanning control and the frequency cutting module 103a is simultaneously turned on, realizing data refresh of the display partition AA2.

[0047] As described above, in the first display frame F1, the display partition AA1 performs data refresh and the display partition AA2 does not perform data refresh, and in the second display frame F2, both the display partition AA1 and the display partition AA2 perform data refresh, so that the refresh frequency of the display partition AA1 is at least twice the refresh frequency of the display partition AA2, thereby achieving that the refresh frequency of the display partition AA1 is greater than the refresh frequency of the display partition AA2.

[0048] Based on this, in multi-frequency display mode, when pixel group 101 is refreshing data, the frequency-cutting control line Ctrl corresponding to pixel group 101 controls the frequency-cutting modules 103a therein to be turned on simultaneously; when pixel group 101 is not refreshing data, the frequency-cutting control line Ctrl corresponding to pixel group 101 controls the frequency-cutting modules 103a therein to be turned off simultaneously; in this pixel circuit 102, the on-off frequency of the frequency-cutting module 103a can be equal to the refresh frequency of pixel group 101, thereby achieving independent control of the refresh frequency of each pixel group 101, and thus enabling the flexible design of different display partitions according to display requirements. It should be noted that in the actual driving process, the scanning control of adjacent pixel rows has a shift relationship, Figure 3 The refresh frequency is only exemplified in the figure, and the relationship between different input signals in the pixel circuit 102 is not reflected. This will be described later. It is understood that the relative position relationship of at least two display partitions with different refresh frequencies can be flexibly designed according to actual needs and is not specifically limited here. Figure 1 This is only an example, but not limited to this. In addition, the size of the display partition can also be set according to actual needs.

[0049] Figure 4 is a schematic diagram of another display panel provided by an embodiment of the present invention, with reference to Figure 2 and Figure 4 As shown, the optional pixel circuit 102 includes at least one scanning end; the display panel 100 includes at least one scanning driving circuit 140, the scanning driving circuit 140 includes a plurality of scanning driving units 141, and the output end of the scanning driving unit 141 is electrically connected to the scanning end of the pixel circuit 102 in at least one pixel row.

[0050] In this embodiment, the pixel circuit 102 includes a fourth scanning terminal S4. The display panel 100 includes a scanning driving circuit 140 for providing a scanning signal to the fourth scanning terminal S4. The scanning driving circuit 140 includes a multi-stage scanning driving unit 141. The output end of the scanning driving unit 141 is electrically connected to at least one pixel row. Specifically, the output end of the scanning driving unit 141 is electrically connected to the fourth scanning terminal S4 of the pixel circuit 102. The scanning driving circuit 140 is used to implement row-by-row scanning control of the pixel circuit 102. The multi-stage scanning driving units 141 in the scanning driving circuit 140 can be cascaded and electrically connected. The scanning signal output by the output end of the scanning driving unit 141 can control the transistor M7 electrically connected to the fourth scanning terminal S4 in the pixel circuit 102 to turn on or off. Here, the frequency switching control line Ctrl is electrically connected to multiple pixel rows, and the scanning driving unit 141 is electrically connected to at least one pixel row. The pixel rows extend in the X direction, and the multiple pixel rows are arranged along the Y direction.

[0051] Figure 5 is a schematic diagram of another display panel provided by an embodiment of the present invention, with reference to Figure 2 and Figure 5 As shown, the optional display panel 100 includes the 1st to Pth frequency cutting control lines Ctrl, P≥3; the display panel 100 includes the 1st to Qth pixel groups 101 arranged in sequence along the first direction Y, Q≥3; the i-th frequency cutting control line Ctrl is electrically connected to the control end of the frequency cutting module 103 in the (a*P+i)th pixel group 101; 1≤i≤P; a=0, 1, 2, .... In this embodiment, Figure 2 For example, if the pixel circuit 102 includes a frequency cutting module 103a, then one pixel group 101 is electrically connected to one frequency cutting control line Ctrl.

[0052] Exemplarily, the display panel 100 includes three frequency-cutting control lines Ctrl and nine pixel groups 101, wherein the three frequency-cutting control lines Ctrl are marked as Ctrl1a, Ctrl1b, and Ctrl1c, respectively, and are arranged sequentially from the first pixel group 101(1) to the ninth pixel group 101(9) along the first direction Y. The first frequency-cutting control line Ctrl1a is electrically connected to the control end of the frequency-cutting module 103a of the pixel circuit 102 in the first pixel group 101(1), the fourth pixel group 101(4), and the seventh pixel group 101(7). The second frequency-cutting control line Ctrl1b is electrically connected to the control end of the frequency-cutting module 103a of the pixel circuit 102 in the second pixel group 101(2), the fifth pixel group 101(5), and the eighth pixel group 101(8). The third frequency cutting control line Ctrl1c is electrically connected to the control end of the frequency cutting module 103a of the pixel circuit 102 in the third pixel group 101(3), the sixth pixel group 101(6), and the ninth pixel group 101(9).

[0053] By connecting two adjacent pixel groups 101 to different frequency-switching control lines Ctrl, the refresh frequency of each pixel group 101 can be independently controlled, thereby enabling the flexible design of different display partitions according to display requirements, thereby achieving multi-frequency refresh of the display panel 100. It is understood that the number of frequency-switching control lines and their relative positions to the pixel groups can be flexibly designed according to actual requirements and are not specifically limited here. Figure 1 and Figure 5 This is only an example, but not limited to this. In addition, the size of the pixel group can also be adjusted according to actual needs.

[0054] In the present invention, a frequency-cutting module is provided in a pixel circuit, and a control end of the frequency-cutting module is electrically connected to a frequency-cutting control line. The frequency-cutting module in a pixel group is electrically connected to the same frequency-cutting control line, and two frequency-cutting modules in two adjacent pixel groups are electrically connected to two frequency-cutting control lines. In a multi-frequency display mode, the display panel includes at least two display partitions with different refresh frequencies, and the frequency-cutting control lines corresponding to the display partitions control the frequency-cutting modules therein to simultaneously turn on or off to control the refresh frequencies of the display partitions. The driver chip controls the switching frequency of the frequency-cutting module via the frequency-cutting control lines, thereby achieving the purpose of controlling the refresh frequency of the pixel circuit, thereby realizing multi-frequency display of the display panel and arbitrarily dividing the positions of multiple display partitions. In the present invention, the driver chip alternately connects to different pixel groups via multiple frequency-cutting control lines, thereby performing refresh drive gating control on the frequency-cutting modules within the pixel circuit, realizing independent refresh control of each pixel group, and thus realizing flexible partition refresh. Therefore, there is no need to set a refresh drive circuit and its corresponding shift register or gating circuit in the non-display area of ​​the display panel, effectively saving and optimizing the frame.

[0055] It can be understood that there are many structures of pixel circuits applicable to the display panel of the present invention. Figure 2 The pixel circuit 102 is shown as an example to illustrate the technical solution of the present invention. In subsequent embodiments, the technical solution of the present invention will be illustrated with reference to other pixel circuits.

[0056] refer to Figure 1 and Figure 2 As shown, the optional pixel circuit 102 includes a compensation module 105, the control terminal of the compensation module 105 being electrically connected to the first scanning terminal S1; the frequency cutting module 103 including a first frequency cutting module 103a, and the frequency cutting control line Ctrl including a first frequency cutting control line Ctrl1 electrically connected to the control terminal CtrlSa of the first frequency cutting module 103a; the compensation module 105 and the first frequency cutting module 103a are electrically connected in series and electrically connected between the gate N1 of the driving transistor M3 and the first electrode N3 of the driving transistor M3. The optional compensation module 105 is electrically connected between the gate N1 of the driving transistor M3 and the first frequency cutting module 103a.

[0057] In this embodiment, Figure 2 The frequency cutting module 103a is the first frequency cutting module 103a, and the frequency cutting control line Ctrl1 electrically connected to the control terminal CtrlSa of the frequency cutting module 103a is the first frequency cutting control line Ctrl1. The compensation module 105 is electrically connected to the transmission path between the gate N1 of the driving transistor and the first terminal N3 of the driving transistor. This transmission path is the threshold compensation gate signal transmission path. In other embodiments, the first frequency cutting module can also be electrically connected between the gate of the driving transistor and the compensation module.

[0058] The optional pixel circuit 102 includes a first reset module 106a; a control terminal of the first reset module 106a is electrically connected to the second scanning terminal S2, and the first reset module 106a is electrically connected between the first reset signal terminal Vref1 and the first electrode N3 of the driving transistor M3. In this embodiment, the first reset module 106a is electrically connected in the transmission path between the first reset signal terminal Vref1 and the first electrode N3 of the driving transistor M3. In other embodiments, the first reset module may alternatively be electrically connected between the first reset signal terminal and the gate N1 of the driving transistor.

[0059] It is understood that the pixel circuit 102 further includes a data write module 107, the control terminal of which is electrically connected to the third scan terminal S3. The data write module 107 is electrically connected between the data write signal terminal Data and the second electrode N2 of the driving transistor M3, and the data write signal terminal Data provides a data signal. The pixel circuit 102 further includes a first dimming module 108 and a second dimming module 109, the control terminals of which are both electrically connected to the dimming control terminal Emit. The first dimming module 108 is electrically connected between the first power supply terminal PVDD and the second electrode N2 of the driving transistor M3, and the second dimming module 109 is electrically connected between the first electrode N3 of the driving transistor M3 and the anode of the light-emitting element 104. The pixel circuit 102 further includes a second reset module 110, the control terminal of which is electrically connected to the fourth scan terminal S4, and the second reset module 110 is electrically connected between the second reset signal terminal Vref2 and the anode of the light-emitting element 104.

[0060] The optional compensation module 105 includes a compensation transistor M5; the first frequency cutting module 103a includes a first frequency cutting transistor M8; and the first reset module 106a includes a first reset transistor M4a. The optional first dimming module 108 includes a first dimming transistor M1; the second dimming module 109 includes a second dimming transistor M6; the data writing module 107 includes a data writing transistor M2; and the second reset module 110 includes a second reset transistor M7. In this embodiment, transistors M1, M2, M3, M4a, M6, and M7 may be P-type transistors, and transistors M5 and M8 may be N-type transistors; but this is not limited to this. The structure of the pixel circuit 102 is not limited to this and can be configured and adjusted according to actual needs.

[0061] In this embodiment, the compensation module 105 is electrically connected between the gate N1 of the driving transistor and the first electrode N3 of the driving transistor, and the first frequency cutting module 103a is connected in series with the compensation module 105 and connected between the gate N1 of the driving transistor M3 and the first electrode N3 of the driving transistor M3. That is, the first frequency cutting module 103a is electrically connected in series in the threshold compensation gate signal transmission path, and the on and off of the first frequency cutting module 103a will affect the on and off of the threshold compensation gate signal transmission path.

[0062] The control terminal CtrlSa of the first frequency-cutting module 103a is electrically connected to the first frequency-cutting control line Ctrl1. The first frequency-cutting modules 103a in one pixel group 101 are electrically connected to the same first frequency-cutting control line Ctrl1. Two first frequency-cutting modules 103a in two adjacent pixel groups 101 are electrically connected to two first frequency-cutting control lines Ctrl1 (e.g., Ctrl1a and Ctrl1b). The display panel 100 includes a multi-frequency display mode. In the multi-frequency display mode, the display panel 100 includes at least two display subareas AA with different refresh rates. Each display subarea AA includes at least one pixel group 101. The first frequency-cutting control lines Ctrl1 corresponding to each display subarea AA control the simultaneous on / off switching of the first frequency-cutting modules 103a therein.

[0063] Specifically, the control terminal CtrlSa of the first frequency cutting module 103a in the first pixel group 101a and the third pixel group 101c is electrically connected to the same first frequency cutting control line Ctrl1a, and the control terminal CtrlSa of the first frequency cutting module 103a in the second pixel group 101b and the fourth pixel group 101d is electrically connected to the same first frequency cutting control line Ctrl1b. Specifically, in the multi-frequency display mode, the display frame of the display panel 100 can be divided into a refresh frame and a hold frame. In the refresh frame, the first frequency cutting module 103a in the pixel circuit 102 is turned on, allowing the pixel circuit 102 to write data. In the hold frame, the first frequency cutting module 103a in the pixel circuit 102 is turned off, so that the pixel circuit 102 does not refresh data. Therefore, the purpose of controlling whether the pixel circuit 102 performs data refresh can be achieved by controlling the on-off frequency of the first frequency cutting module 103a, so that the number of retention frames between two adjacent refresh frames is different, thereby controlling the refresh frequency of the pixel group 101 where the pixel circuit 102 is located, thereby realizing the control of the refresh frequency of the pixel circuit 102 and the pixel group 101 where it is located.

[0064] Based on this, in the multi-frequency display mode, the frequency cutting control line Ctrl can optionally control the data signal to be written into the gate N1 of the driving transistor M3 at a first frequency, so that the refresh frequency of the corresponding display subarea AA is the first frequency. Specifically, for the pixel circuit 102, the first frequency cutting control line Ctrl1 provides a frequency cutting signal of the first frequency. The frequency cutting signal includes an on-level for turning on the first frequency cutting module 103a and an off-level for turning off the first frequency cutting module 103a. If the on-level of the frequency cutting signal is the first frequency, the on-frequency of the first frequency cutting module 103a is the first frequency. This can cause the data signal to be written into the gate N1 of the driving transistor M3 at the first frequency, so that the refresh frequency of the pixel circuit 102 is the first frequency, and thus the refresh frequency of the corresponding display subarea AA is the first frequency.

[0065] Figure 6 yes Figure 2 The timing diagram of the pixel circuit shown. Figure 1 、 Figure 2 and Figure 6 As shown, a driving cycle of the pixel circuit 102 includes at least a reset phase T11, a data writing phase T12, and a light emitting phase T13. The operation process of the pixel circuit 102 includes a refresh frame FS and a hold frame FB.

[0066] During the refresh frame FS, the driving process of the pixel circuit 102 includes: the control terminal CtrlSa of the first frequency cutting module 103a receives a high level, turning on the first frequency cutting transistor M8; wherein, during the reset phase T11, the first scanning terminal S1 receives a high level, turning on the compensation transistor M5, and the second scanning terminal S2 receives a low level, turning on the first reset transistor M4a, so that the first reset signal provided by the first reset signal terminal Vref1 can be transmitted to the gate N1 of the driving transistor M3; during the data writing phase T12, the first scanning terminal S1 receives a high level, turning on the compensation transistor M5, and the third scanning terminal S3 receives a low level, turning on the data writing transistor M2, so that the data voltage provided by the data writing signal terminal Data can be transmitted to the gate N1 of the driving transistor M3, thereby implementing data writing and refreshing the pixel circuit 102; during the light-emitting phase T13, the dimming control terminal Emit receives a low level, turning on both the first dimming transistor M1 and the second dimming transistor M6, and the driving transistor M3 provides a driving current to the light-emitting element 104 according to the refreshed data voltage, driving the light-emitting element 104 to emit light.

[0067] In the hold frame FB, the driving process of the pixel circuit 102 includes: the control terminal CtrlSa of the first frequency division module 103a receives a low level, turning off the first frequency division transistor M8, and disconnecting the threshold compensation gate signal transmission path electrically connected to the gate N1 of the driving transistor M3; wherein, in the reset stage T11, when the first frequency division transistor M8 is turned off, the first reset signal provided by the first reset signal terminal Vref1 cannot be transmitted to the gate N1 of the driving transistor M3; in the data writing stage T12, when the first frequency division transistor M8 is turned off, the data voltage cannot be transmitted to the gate N1 of the driving transistor M3, and the pixel circuit 102 does not perform data refreshing; in the light emitting stage T13, the driving transistor M3 provides a driving current according to the data voltage stored in the previous refresh frame, driving the light emitting element 104 to emit light with the same brightness as the previous refresh frame.

[0068] It can be understood that by controlling the frequency of the refresh frame FS of the pixel circuit 102, the refresh frequency of the pixel circuit 102 can be controlled, so that the display area of the display panel 100 can achieve frequency division display with different refresh frequencies.

[0069] Figure 7 It is a schematic diagram of another display panel provided by an embodiment of the present invention. Figure 8 is Figure 7 a timing schematic diagram of the shown display panel, combined with Figure 2 , Figure 7 and Figure 8 shown, the optional display panel 100 includes a first scan driving circuit 140a, the first scan driving circuit 140a includes a plurality of first scan driving units 141a, the output terminal of the first scan driving unit 141a is electrically connected to the scan terminals of K pixel rows, K≥1; in the first display frame F1, the effective pulse width of the frequency division control line corresponding to the first display partition AA1 is greater than or equal to La and less than or equal to Lx; La = W + K*(n1 - 1)*H; Lx = K*(n1 + n2 - 1)*H; W is the pulse width of the effective scan signal provided by the first scan driving unit 141a, n1 is the number of stages of the first scan driving unit 141a corresponding to the first display partition AA1, n2 is the number of stages of the first scan driving unit 141a corresponding to the second display partition AA2, and H is the scan duration of one pixel row. In this embodiment, the display panel 100 includes first display partitions AA1 and second display partitions AA2 arranged alternately along the Y direction, and the first display partitions AA1 located on the upper and lower sides of a second display partition AA2 are marked as the first display partition AA1a and the first display partition AA1b.

[0070] Optionally, the output terminal of the first scan driving unit 141a is electrically connected to the control terminal S1 of the compensation module 105. Optionally, W < K*n2*H. In other embodiments, optionally, the output terminal of the first scan driving unit is electrically connected to the control terminal of the first reset module.

[0071] In this embodiment, the first scan driving unit 141a is a one-drive K-level design, where K can be equal to 1 or greater than 1. Multiple frequency switching control lines Ctrl are alternately connected to different pixel groups 101. In order to ensure that each pixel group 101 is independently controlled without interfering with each other, it is necessary to reasonably design the pulse width W of the effective scan signal provided by the first scan driving unit 141a.

[0072] Taking the refresh of the first display partition AA1a as an example, the first display partition AA1a includes at least one pixel group 101. Assuming that the number of stages of the first scan driving unit 141a corresponding to the first display partition AA1a is n1, the scan duration La of the scan control of the first display partition AA1a is La = W + K * (n1 - 1) * H. In other words, the minimum effective pulse width (i.e., the conduction level pulse width) of the frequency cutting control line Ctrl corresponding to the first display partition AA1a is La. This ensures that during the scan phase of the first display partition AA1a, the conduction level provided by the frequency cutting control line Ctrl can control the conduction of the first frequency cutting module 103a of the pixel circuit 102 in the first display partition AA1a.

[0073] The second display partition AA2 includes at least one pixel group 101. Assuming that the number of levels of the first scan driving unit 141a corresponding to the second display partition AA2 is n2, the total scanning time for the scanning control of the first display partition AA1a and the second display partition AA2 is W+K*(n1+n2-1)*H.

[0074] Based on the one-drive K-stage design of the first scan driving unit 141 a , when the last pixel row of the second display partition AA2 is scanned, one or more rows of pixel circuits 102 in the adjacent first display partition AA1 b are scanned and controlled.

[0075] If the effective pulse width (i.e., the on-level pulse width) of the frequency cutting control line Ctrl corresponding to the first display partition AA1a is W+K*(n1+n2-1)*H, then one or more rows of pixel circuits 102 in the first display partition AA1b may be turned on and the frequency cutting module 103a may be turned on, thereby causing one or more rows of pixel circuits 102 in the first display partition AA1b to be incorrectly refreshed. Therefore, the maximum value of the effective pulse width (i.e., the on-level pulse width) of the frequency cutting control line Ctrl corresponding to the first display partition AA1a should be less than W+K*(n1+n2-1)*H. Specifically, the maximum value of the effective pulse width (i.e., the on-level pulse width) of the frequency cutting control line Ctrl corresponding to the first display partition AA1a is designed to be Lx, and Lx=K*(n1+n2-1)*H. Then, when the last pixel row of the second display partition AA2 is scanned, the frequency cutting control line Ctrl corresponding to the first display partition AA1a provides an invalid pulse (i.e., the off-level), which can prevent one or more rows of pixel circuits 102 in the first display partition AA1b from being incorrectly refreshed.

[0076] La is less than Lx, so W must satisfy W <n2*H。

[0077] As described above, the first scan driving unit 141a is a one-drive K-level design, where K can be equal to 1 or greater than 1. Multiple frequency switching control lines Ctrl are alternately connected to different pixel groups 101. By reasonably designing the pulse width W of the effective scan signal provided by the first scan driving unit 141a, it can be ensured that each pixel group 101 is independently controlled without interfering with each other.

[0078] Figure 9 yes Figure 7 Another timing diagram of the display panel shown, the effective scanning signal optionally provided by the first scanning driving unit 141a includes multiple effective scanning pulses, W is the duration between the start time of the first effective scanning pulse in the multiple effective scanning pulses and the end time of the last effective scanning pulse.

[0079] In this embodiment, the first scan driving unit 141a is a K-level drive design, where K can be equal to 1 or greater than 1. The effective scan signal provided by the first scan driving unit 141a can be as follows: Figure 8 The single pulse 1pulse shown in FIG. 1 is a pulse width of the effective scanning signal. The effective scanning signal provided by the first scanning driving unit 141a can also be as follows: Figure 9In the example shown in FIG1 , the effective scanning signal is a 2-pulse 2pulse signal, and the effective pulse width W of the effective scanning signal is the duration between the start time of the first effective scanning pulse and the end time of the second effective scanning pulse. The effective scanning signal provided by the first scanning driving unit 141a can also be a multi-pulse xpulse signal, and the effective pulse width W of the effective scanning signal is the duration between the start time of the first effective scanning pulse and the end time of the last effective scanning pulse.

[0080] As described above, by setting the frequency cutting module 103 in the pixel circuit 102, the frequency cutting control line Ctrl is directly electrically connected to the driving chip 131 and the frequency cutting module 103 in the pixel circuit 102, and multiple frequency cutting control lines Ctrl are alternately connected to the pixel circuit 102 to realize the refresh control selection process, thereby realizing independent refresh control of each pixel group 101, and thus realizing flexible partition refresh. There is no need to set a refresh driving circuit and its matching shift register or selection circuit for controlling refresh in the non-display area of ​​the display panel, which can effectively save the border and optimize the border to achieve a full screen, thereby achieving the purpose of controlling the refresh frequency of the pixel circuit 102, thereby realizing multi-frequency display of the display panel 100.

[0081] It can be understood that there are many structures of pixel circuits applicable to the display panel of the present invention. In this embodiment, different pixel circuits are combined. Figure 2 The pixel circuit 102 shown is used to illustrate the technical solution of the present invention.

[0082] Figure 10 is a schematic diagram of another display panel provided by an embodiment of the present invention, Figure 11 yes Figure 10 Schematic diagram of the pixel circuit shown. Figure 10 and Figure 11As shown, in the display panel 100 provided in this embodiment, the optional pixel circuit 102 includes a first reset module 106b, the control terminal of the first reset module 106b being electrically connected to the second scanning terminal S2; the frequency cutting module 103 includes a second frequency cutting module 103b, and the frequency cutting control line Ctrl includes a second frequency cutting control line Ctrl2 electrically connected to the control terminal CtrlSb of the second frequency cutting module 103b; the first reset module 106b and the second frequency cutting module 103b are electrically connected in series and electrically connected between the first reset signal terminal Vref1 and the gate N1 of the driving transistor M3. The optional first reset module 106b is electrically connected between the gate N1 of the driving transistor M3 and the second frequency cutting module 103b. The optional frequency cutting module 103 also includes a first frequency cutting module 103a, the frequency cutting control line Ctrl includes a first frequency cutting control line Ctrl1 electrically connected to the control end CtrlSa of the first frequency cutting module 103a, and the first frequency cutting module 103a is electrically connected in series in a transmission path between the gate N1 of the driving transistor M3 and the first electrode N3 of the driving transistor M3; the first frequency cutting module 103a includes a first frequency cutting transistor M8; the second frequency cutting module 103b includes a second frequency cutting transistor M9; and the first reset module 106b includes a first reset transistor M4b.

[0083] The optional pixel circuit 102 includes a compensation module 105. The control terminal of the compensation module 105 is electrically connected to the first scanning terminal S1. The compensation module 105 and the first frequency cutting module 103a are electrically connected in series and electrically connected between the gate N1 of the driving transistor M3 and the first electrode N3 of the driving transistor M3. The optional compensation module 105 is electrically connected between the gate N1 of the driving transistor M3 and the first frequency cutting module 103a. The optional compensation module 105 includes a compensation transistor M5. The first frequency cutting module 103a includes a first frequency cutting transistor M8.

[0084] In this embodiment, Figure 11The frequency cutting module 103 includes a first frequency cutting module 103a and a second frequency cutting module 103b. A frequency cutting control line Ctrl electrically connected to the control terminal CtrlSa of the first frequency cutting module 103a is a first frequency cutting control line Ctrl1, and a frequency cutting control line Ctrl electrically connected to the control terminal CtrlSb of the second frequency cutting module 103b is a second frequency cutting control line Ctrl2. The first frequency cutting module 103a is electrically connected to the threshold compensation gate signal transmission path of the gate N1 of the driving transistor. The on-off state of the first frequency cutting module 103a affects the on-off state of the threshold compensation gate signal transmission path. The first reset module 106b is electrically connected to the transmission path between the first reset signal terminal Vref1 and the gate N1 of the driving transistor M3. The transmission path between the first reset signal terminal Vref1 and the gate N1 of the driving transistor M3 serves as the reset gate signal transmission path. The second frequency cutting module 103b is electrically connected to the reset gate signal transmission path of the gate N1 of the driving transistor. The on-off state of the second frequency cutting module 103b affects the on-off state of the reset gate signal transmission path. In other embodiments, the second frequency cutting module may be optionally electrically connected between the gate of the driving transistor and the first reset module.

[0085] It is understood that the pixel circuit 102 further includes a data write module 107, the control terminal of which is electrically connected to the third scan terminal S3. The data write module 107 is electrically connected between the data write signal terminal Data and the second electrode N2 of the driving transistor M3, and the data write signal terminal Data provides a data signal. The pixel circuit 102 further includes a first dimming module 108 and a second dimming module 109, the control terminals of which are both electrically connected to the dimming control terminal Emit. The first dimming module 108 is electrically connected between the first power supply terminal PVDD and the second electrode N2 of the driving transistor M3, and the second dimming module 109 is electrically connected between the first electrode N3 of the driving transistor M3 and the anode of the light-emitting element 104. The pixel circuit 102 further includes a second reset module 110, the control terminal of which is electrically connected to the fourth scan terminal S4, and the second reset module 110 is electrically connected between the second reset signal terminal Vref2 and the anode of the light-emitting element 104.

[0086] The optional first dimming module 108 includes a first dimming transistor M1; the second dimming module 109 includes a second dimming transistor M6; the data writing module 107 includes a data writing transistor M2; and the second reset module 110 includes a second reset transistor M7. In this embodiment, the transistors M1, M2, M3, M6, and M7 can be P-type transistors, and the transistors M4b, M5, M8, and M9 can be N-type transistors; but are not limited to this. The structure of the pixel circuit 102 is not limited to this and can be set and adjusted according to actual needs. The optional first frequency cutting transistor and the second frequency cutting transistor are both NMOS or both PMOS, then the first frequency cutting control line in the pixel circuit is multiplexed as the second frequency cutting control line.

[0087] The control terminal CtrlSa of the first frequency cutting module 103a is electrically connected to the first frequency cutting control line Ctrl1. The first frequency cutting modules 103a in one pixel group 101 are electrically connected to the same first frequency cutting control line Ctrl1. The two first frequency cutting modules 103a in two adjacent pixel groups 101 are electrically connected to two first frequency cutting control lines Ctrl1 (e.g., Ctrl1a and Ctrl1b). The control terminal CtrlSb of the second frequency cutting module 103b is electrically connected to the second frequency cutting control line Ctrl2. The second frequency cutting modules 103b in one pixel group 101 are electrically connected to the same second frequency cutting control line Ctrl2. The two second frequency cutting modules 103b in two adjacent pixel groups 101 are electrically connected to two second frequency cutting control lines Ctrl2 (e.g., Ctrl2a and Ctrl2b).

[0088] The display panel 100 includes a multi-frequency display mode; in the multi-frequency display mode, the display panel 100 includes at least two display partitions AA with different refresh frequencies, and the display partition AA includes at least one pixel group 101. The first frequency cutting control line Ctrl1 and the second frequency cutting control line Ctrl2 corresponding to the display partition AA control the first frequency cutting module 103a and the second frequency cutting module 103b therein to be simultaneously turned on or off to control the refresh frequency of the display partition AA.

[0089] Specifically, the control terminal CtrlSa of the first frequency cutting module 103a in the first pixel group 101a and the third pixel group 101c is electrically connected to the same first frequency cutting control line Ctrl1a, and the control terminal CtrlSa of the first frequency cutting module 103a in the second pixel group 101b and the fourth pixel group 101d is electrically connected to the same first frequency cutting control line Ctrl1b. The control terminal CtrlSb of the second frequency cutting module 103b in the first pixel group 101a and the third pixel group 101c is electrically connected to the same second frequency cutting control line Ctrl2a, and the control terminal CtrlSb of the second frequency cutting module 103b in the second pixel group 101b and the fourth pixel group 101d is electrically connected to the same second frequency cutting control line Ctrl2b.

[0090] Specifically, in the multi-frequency display mode, the display frame of the display panel 100 can be divided into a refresh frame and a hold frame. In the refresh frame, the first frequency cutting module 103a and the second frequency cutting module 103b in the pixel circuit 102 are turned on, so that the pixel circuit 102 can write data. In the hold frame, the first frequency cutting module 103a and the second frequency cutting module 103b in the pixel circuit 102 are turned off, so that the pixel circuit 102 does not refresh data. Therefore, the purpose of controlling whether the pixel circuit 102 performs data refresh can be achieved by controlling the on-off frequency of the first frequency cutting module 103a and the on-off frequency of the second frequency cutting module 103b, so that the number of hold frames between two adjacent refresh frames is different, thereby controlling the refresh frequency of the pixel group 101 where the pixel circuit 102 is located, so as to achieve control of the refresh frequency of the pixel circuit 102 and the pixel group 101 where it is located.

[0091] Based on this, in the multi-frequency display mode, the frequency switching control line Ctrl controls the data signal to be written into the gate N1 of the driving transistor M3 at a first frequency, so that the refresh frequency of the corresponding display partition AA is the first frequency. Specifically, for the same pixel circuit 102, the first frequency cutting control line Ctrl1 provides a frequency cutting signal of the first frequency, which includes an on-level for turning on the first frequency cutting module 103a and an off-level for turning off the first frequency cutting module 103a, and the on-level of the frequency cutting signal is the first frequency; at the same time, the second frequency cutting control line Ctrl2 provides a frequency cutting signal of the first frequency, which includes an on-level for turning on the second frequency cutting module 103b and an off-level for turning off the second frequency cutting module 103b, and the on-level of the frequency cutting signal is the first frequency; based on this, the on-frequency of the first frequency cutting module 103a and the second frequency cutting module 103b are both the first frequency, wherein the first frequency cutting module 103a and the second frequency cutting module 103b are turned on or turned off at the same time; thereby, the data signal can be written into the gate N1 of the driving transistor M3 at the first frequency, so that the refresh frequency of the pixel circuit 102 is the first frequency, and thus the refresh frequency of the corresponding display partition AA is the first frequency.

[0092] Figure 12 yes Figure 11 The timing diagram of the pixel circuit shown. Figure 10 、 Figure 11 and Figure 12 As shown, a driving cycle of the pixel circuit 102 includes at least a reset phase T11, a data writing phase T12, and a light emitting phase T13. The operation process of the pixel circuit 102 includes a refresh frame FS and a hold frame FB.

[0093] In the refresh frame FS, the driving process of the pixel circuit 102 includes: the control terminal CtrlSa of the first frequency cutting module 103a receives a high level to turn on the first frequency cutting transistor M8, and the control terminal CtrlSb of the second frequency cutting module 103b receives a high level to turn on the second frequency cutting transistor M9; wherein, in the reset phase T11, the second scanning terminal S2 receives a high level to turn on the first reset transistor M4b, so that the first reset signal provided by the first reset signal terminal Vref1 can be transmitted to the gate N1 of the driving transistor M3; in the data writing phase T12, the first scanning terminal Vref1 receives a high level to turn on the first reset transistor M4b; S1 receives a high level to turn on the compensation transistor M5, and the third scanning terminal S3 receives a low level to turn on the data writing transistor M2. Then, the data voltage provided by the data writing signal terminal Data can be transmitted to the gate N1 of the driving transistor M3, thereby realizing data writing and refreshing the pixel circuit 102. In the light-emitting stage T13, the dimming control terminal Emit receives a low level to turn on both the first dimming transistor M1 and the second dimming transistor M6. The driving transistor M3 provides a driving current to the light-emitting element 104 according to the refreshed data voltage, thereby driving the light-emitting element 104 to emit light.

[0094] In the hold frame FB, the driving process of the pixel circuit 102 includes: the control terminal CtrlSa of the first frequency cutting module 103a receives a low level to turn off the first frequency cutting transistor M8, thereby disconnecting the threshold compensation gate signal transmission path electrically connected to the gate N1 of the driving transistor M3, and the control terminal CtrlSb of the second frequency cutting module 103b receives a low level to turn off the second frequency cutting transistor M9, thereby disconnecting the reset gate signal transmission path electrically connected to the gate N1 of the driving transistor M3; wherein, in the reset phase T11, the second frequency cutting transistor M9 is turned off, and the first reset signal provided by the first reset signal terminal Vref1 cannot be transmitted to the gate N1 of the driving transistor M3; in the data writing phase T12, the first frequency cutting transistor M8 is turned off, and the data voltage cannot be transmitted to the gate N1 of the driving transistor M3, and the pixel circuit 102 does not refresh the data; in the light-emitting phase T13, the driving transistor M3 provides a driving current according to the data voltage stored in the previous refresh frame, driving the light-emitting element 104 to emit light at the same brightness as the previous refresh frame.

[0095] It can be understood that by controlling the frequency of the refresh frame FS of the pixel circuit 102 , the refresh frequency of the pixel circuit 102 can be controlled, so that the display area of ​​the display panel 100 can achieve frequency division display with different refresh frequencies.

[0096] Figure 13 is a schematic diagram of another display panel provided by an embodiment of the present invention, Figure 14 yes Figure 13 The timing diagram of the display panel is shown, combined with Figure 11 、 Figure 13 and Figure 14As shown, the optional display panel 100 includes a first scan driving circuit 140b. The first scan driving circuit 140b includes multiple first scan driving units 141b. The output end of the first scan driving unit 141b is electrically connected to the scan ends of K pixel rows, where K≥1. In the first display frame F1, the effective pulse width of the switching frequency control line corresponding to the first display partition AA1 is greater than or equal to La and less than or equal to Lx; La = W + K*(n1 - 1)*H; Lx = K*(n1 + n2 - 1)*H; W is the pulse width of the effective scan signal provided by the first scan driving unit 141b, n1 is the number of stages of the first scan driving unit 141b corresponding to the first display partition AA1, n2 is the number of stages of the first scan driving unit 141b corresponding to the second display partition AA2, and H is the scan duration of one pixel row. In this embodiment, the display panel 100 includes first display partitions AA1 and second display partitions AA2 arranged alternately in the Y direction. The first display partitions AA1 located on the upper and lower sides of one second display partition AA2 are marked as first display partition AA1a and first display partition AA1b.

[0097] Optionally, the output end of the first scan driving unit 141b is electrically connected to the control end S2 of the first reset module 106b. Optionally, W < K*n2*H. In other embodiments, optionally, the output end of the first scan driving unit is electrically connected to the control end of the compensation module.

[0098] In this embodiment, the first scan driving unit 141b is a one-driving-K-stage design. K can be equal to 1 or greater than 1. Multiple switching frequency control lines Ctrl are alternately connected to different pixel groups 101. In order to ensure that each pixel group 101 is independently controlled without interference, it is necessary to reasonably design the pulse width W of the effective scan signal provided by the first scan driving unit 141a.

[0099] Taking the refresh of the first display partition AA1a as an example. The effective pulse width of the first switching frequency control line Ctrl1a corresponding to the first display partition AA1a is greater than or equal to La and less than or equal to Lx, and the effective pulse width of the second switching frequency control line Ctrl2a corresponding to the first display partition AA1a is greater than or equal to La and less than or equal to Lx. La = W + K*(n1 - 1)*H, Lx = K*(n1 + n2 - 1)*H. In this way, it can be ensured that during the scan stage of the first display partition AA1a, the conduction level provided by the first switching frequency control line Ctrl1a can control the first switching frequency module 103a of the pixel circuit 102 to conduct, and the conduction level provided by the second switching frequency control line Ctrl2a can control the second switching frequency module 103b of the pixel circuit 102 to conduct, and it can be avoided that one or more pixel circuits 102 in the first display partition AA1b are refreshed by mistake.

[0100] La is less than Lx, so W needs to satisfy W < n2 * H. As described above, the first scan driving unit 141b is a one-driving-K-stage design, where K can be equal to 1 or greater than 1. Multiple frequency-cutting control lines Ctrl are alternately connected to different pixel groups 101. By reasonably designing the pulse width W of the effective scan signal provided by the first scan driving unit 141b, it can be ensured that each pixel group 101 is independently controlled without interference.

[0101] In other embodiments, it is also optional that the effective scan signal provided by the first scan driving unit includes multiple effective scan pulses, and W is the duration from the start time of the first effective scan pulse to the end time of the last effective scan pulse among the multiple effective scan pulses.

[0102] As described above, by providing a frequency-cutting module 103 in the pixel circuit 102, the frequency-cutting control line Ctrl is directly electrically connected to the frequency-cutting module 103 in the driving chip 131 and the pixel circuit 102. Multiple frequency-cutting control lines Ctrl are alternately connected to the pixel circuit 102 to implement the selection process of the refresh control, achieve the independent refresh control of each pixel group 101, and further enable flexible zonal refresh. There is no need to set a refresh driving circuit and its matching shift register or gating circuit for controlling the refresh in the non-display area of the display panel, which can effectively save the border, optimize the border to achieve a full-screen display, and achieve the purpose of controlling the refresh frequency of the pixel circuit 102, thereby realizing multi-frequency display of the display panel 100.

[0103] Based on the same inventive concept, an embodiment of the present invention further provides a display device. Figure 15 It is a schematic diagram of a display device provided by an embodiment of the present invention. As Figure 15 shown, the display device 1 includes: the display panel 100 described in any of the above embodiments. Therefore, the display device 1 provided by the embodiment of the present invention has the technical effects of the technical solutions in any of the above embodiments, and the explanations of the same or corresponding structures and terms as those in the above embodiments will not be repeated here.

[0104] The display device 1 provided by the embodiment of the present invention can be Figure 15 the mobile phone shown in the figure, or any electronic product with a display function, including but not limited to the following categories: television, notebook computer, desktop display, tablet computer, digital camera, smart bracelet, smart glasses, vehicle-mounted display, medical device, industrial control device, touch interaction terminal, etc. The embodiment of the present invention does not make special limitations on this.

[0105] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0106] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A display panel, characterized in that: include: a plurality of pixel groups arranged along a first direction, the pixel groups comprising a plurality of pixel rows arranged along the first direction, one of the pixel rows comprising a plurality of pixel circuits arranged along a second direction, the first direction intersecting the second direction; The pixel circuit includes a frequency cutting module, a driving transistor and a light-emitting element, wherein the frequency cutting module is electrically connected in series to the gate of the driving transistor, and the first electrode of the driving transistor is electrically connected to the light-emitting element; a driving chip and at least two frequency cutting control lines electrically connected to the driving chip, wherein a control end of the frequency cutting module is electrically connected to the frequency cutting control line, the frequency cutting modules in one pixel group are electrically connected to the same frequency cutting control line, and two frequency cutting modules in two adjacent pixel groups are electrically connected to two frequency cutting control lines; The display panel includes a multi-frequency display mode; In the multi-frequency display mode, the display panel includes at least two display partitions with different refresh frequencies, each display partition includes at least one pixel group, and each of the frequency cutting control lines corresponding to the display partition controls the frequency cutting modules therein to be turned on or off simultaneously to control the refresh frequency of the display partition.

2. The display panel according to claim 1, wherein: The pixel circuit includes at least one scanning terminal; The display panel includes at least one scan driving circuit, and the scan driving circuit includes a plurality of scan driving units. The output end of the scan driving unit is electrically connected to the scan end of the pixel circuit in at least one pixel row.

3. The display panel according to claim 1, wherein: In the display panel, the number of pixel rows in the pixel groups is the same.

4. The display panel according to claim 1, wherein: The display panel includes 1st to Pth frequency cutting control lines, P≥3; The display panel includes 1st to Qth pixel groups sequentially arranged along the first direction, Q≥3; The i-th frequency cutting control line is electrically connected to the control end of the frequency cutting module in the (a*P+i)-th pixel group; 1≤i≤P; a=0, 1, 2, . . .

5. The display panel according to claim 1, wherein: In the multi-frequency display mode, the display panel includes a plurality of display frames, and the display frames include a first display frame; In the first display frame, the display panel includes a first display partition and a second display partition alternately arranged along the first direction, and the frequency switching control line provides an on-level in the working stage of the first display partition and provides an off-level in the working stage of the second display partition, so that the first display partition refreshes the screen.

6. The display panel according to claim 5, wherein: The display panel includes a first scan driving circuit, the first scan driving circuit includes a plurality of first scan driving units, and output ends of the first scan driving units are electrically connected to scan ends of K pixel rows, where K≥1; In the first display frame, the effective pulse width of the frequency switching control line corresponding to the first display partition is greater than or equal to La and less than or equal to Lx; La=W+K*(n1-1)*H; Lx=K*(n1+n2-1)*H; W is the pulse width of the effective scanning signal provided by the first scanning driving unit, n1 is the level number of the first scanning driving unit corresponding to the first display partition, n2 is the level number of the first scanning driving unit corresponding to the second display partition, and H is the scanning time length of one pixel row.

7. The display panel according to claim 6, wherein: W <K*n2*H。 8. The display panel according to claim 6, wherein: The effective scanning signal provided by the first scanning driving unit includes a plurality of effective scanning pulses, and W is the duration from the start time of the first effective scanning pulse to the end time of the last effective scanning pulse among the plurality of effective scanning pulses.

9. The display panel according to claim 6, wherein: The pixel circuit includes a compensation module, a control end of the compensation module is electrically connected to the first scanning end, and the compensation module is electrically connected in a transmission path between the gate of the driving transistor and the first electrode of the driving transistor; The output end of the first scan driving unit is electrically connected to the control end of the compensation module.

10. The display panel according to claim 6, wherein: The pixel circuit includes a first reset module, a control terminal of the first reset module is electrically connected to the second scanning terminal, and the first reset module is electrically connected in a transmission path between the first reset signal terminal and the gate of the driving transistor; An output terminal of the first scan driving unit is electrically connected to a control terminal of the first reset module.

11. The display panel according to claim 6, wherein: The pixel circuit includes a first reset module, a control end of the first reset module is electrically connected to the second scanning end, and the first reset module is electrically connected in a transmission path between the first reset signal end and the first electrode of the driving transistor; An output terminal of the first scan driving unit is electrically connected to a control terminal of the first reset module.

12. The display panel according to claim 1, wherein The pixel circuit includes a compensation module, and the control end of the compensation module is electrically connected to the first scanning end; The frequency cutting module includes a first frequency cutting module, and the frequency cutting control line includes a first frequency cutting control line electrically connected to a control end of the first frequency cutting module; The compensation module and the first frequency cutting module are electrically connected in series, and are electrically connected between the gate of the driving transistor and the first electrode of the driving transistor.

13. The display panel according to claim 12, wherein: The compensation module is electrically connected between the gate of the driving transistor and the first frequency cutting module.

14. The display panel according to claim 12, wherein: The pixel circuit includes a first reset module; The control end of the first reset module is electrically connected to the second scanning end, and the first reset module is electrically connected between the first reset signal end and the first electrode of the driving transistor.

15. The display panel according to claim 14, wherein: The compensation module includes a compensation transistor; The first frequency cutting module includes a first frequency cutting transistor; The first reset module includes a first reset transistor.

16. The display panel according to claim 1, wherein The pixel circuit includes a first reset module, wherein the control end of the first reset module is electrically connected to the second scanning end; The frequency cutting module includes a second frequency cutting module, and the frequency cutting control line includes a second frequency cutting control line electrically connected to the control end of the second frequency cutting module; The first reset module and the second frequency cutting module are electrically connected in series, and are electrically connected between a first reset signal terminal and a gate of the driving transistor.

17. The display panel according to claim 16, wherein: The first reset module is electrically connected between the gate of the driving transistor and the second frequency cutting module.

18. The display panel according to claim 16, wherein: The frequency cutting module further includes a first frequency cutting module, the frequency cutting control line includes a first frequency cutting control line electrically connected to a control end of the first frequency cutting module, and the first frequency cutting module is electrically connected in series in a transmission path between the gate of the driving transistor and the first electrode of the driving transistor; The first frequency cutting module includes a first frequency cutting transistor; The second frequency cutting module includes a second frequency cutting transistor; The first reset module includes a first reset transistor.

19. The display panel according to claim 18, wherein: The first frequency cutting transistor and the second frequency cutting transistor are both NMOS or both PMOS, and the first frequency cutting control line in the pixel circuit is multiplexed as the second frequency cutting control line.

20. The display panel according to claim 1, wherein The pixel circuit includes a data writing module, wherein the control end of the data writing module is electrically connected to the third scanning end, the data writing module is electrically connected between the data writing signal end and the second electrode of the driving transistor, and the data writing signal end provides a data signal; In the multi-frequency display mode, the frequency switching control line controls the data signal to be written into the gate of the driving transistor at a first frequency, so that the refresh frequency of the corresponding display partition is the first frequency.

21. A display device, characterized in that: include: The display panel according to any one of claims 1 to 20.

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