Compiler infrastructure based on parameterized control flow diagram and implementation method thereof

Abstract

A traditional compiler widely uses a static single assignment (SSA) form in intermediate representation (IR), and the problem of variable value conflict during control flow merging is solved through a Phi function. However, the Phi function results in deep coupling of the control flow with the data flow, resulting in IR expansion, limited optimization and difficult maintenance. In order to solve the problem, the invention provides a compiler infrastructure based on a parameterized control flow diagram and an implementation method thereof, and relates to a compiler design and code optimization technology. The explicit parameterization basic block is used for replacing a Phi function, control flow and data flow analysis is thoroughly decoupled, data flow analysis is simplified, the complexity of intermediate representation is remarkably reduced, optimization efficiency is greatly improved, and good maintainability and friendly debugging performance are achieved. The method is suitable for scenes of loop expansion, redundancy elimination and the like, and a modularized and efficient solution is provided for a modern compiler.

Description

Technical Field

[0001] The present invention relates to compiler design and code optimization technology, and specifically to a compiler infrastructure based on parameterized control flow graph (PCFG) and its implementation method, which are used to decouple control flow and data flow analysis, simplify the complexity of intermediate representation (IR), and improve the flexibility and efficiency of compiler optimization. Background Art

[0002] A compiler is a tool that converts high-level languages ​​into machine-readable low-level languages. Compiler infrastructure is shared across many different compilers and consists of multiple basic components. It is independent of the implementation of a specific programming language, stripping away the specificities of high-level and low-level languages ​​and enabling easy portability to any compiler implementation. Specifically, compiler infrastructure includes: front-end automaton-based grammatical / syntactic / semantic analysis, including automaton construction logic; mid-end syntax tree conversion to intermediate representation, conversion between different intermediate representation forms, and intermediate representation optimization.

[0003] Traditional compilers widely use the static single assignment (SSA) form in their intermediate representation (IR), using Phi functions to resolve variable value conflicts during control flow merging. However, Phi functions lead to a deep coupling between control flow and data flow, resulting in IR bloat, limited optimization, and difficult maintenance. For example, in nested loops or multi-branch structures, Phi functions require frequent updates to the predecessor list, increasing the complexity of data flow analysis.

[0004] This paper proposes a compiler infrastructure and implementation method based on parameterized control flow graphs. By replacing Phi functions with explicitly parameterized basic blocks, this approach completely decouples control flow and data flow analysis, simplifies data flow analysis, significantly reduces the complexity of intermediate representations, and significantly improves optimization efficiency. It also offers excellent maintainability and debuggability. This approach is suitable for scenarios such as loop unrolling and redundancy elimination, providing a modular and efficient solution for modern compilers. Summary of the Invention

[0005] The present invention provides a parameterized control flow graph compiler infrastructure and implementation method thereof. By using a parameterized control flow graph (PCFG), explicit parameters are introduced into basic blocks to replace the Phi function in the traditional SSA form. At the same time, the control flow is decoupled from the data flow, thereby simplifying the data flow analysis and optimization process.

[0006] The present invention provides a parameterized control flow graph compiler infrastructure and an implementation method thereof, the method comprising the following steps:

[0007] 1. User input source code

[0008] Enter the source code to be compiled (such as C / C++, Python, etc.).

[0009] 2. Front-end parsing to generate an abstract syntax tree (AST)

[0010] According to the source code input by the user, it is parsed on the front end, and AST is generated through lexical analysis and syntax analysis to mark the code structure (such as functions, loops, branches, etc.).

[0011] 3. Convert to parameterized control flow graph (PCFG)

[0012] Convert AST to PCFG through the following steps:

[0013] (a) Basic block division

[0014] Split the AST into basic blocks, each of which corresponds to a piece of code that is executed sequentially.

[0015] (b) Parameterized definition

[0016] Assign explicit parameters to each basic block:

[0017] Input parameters are responsible for defining the external data required for the execution of the basic block (such as loop variable `i`, branch condition `cond`);

[0018] Output parameters are responsible for defining the result data after the execution of the basic block (such as the updated `i+1` and branch result value).

[0019] (c) Control flow edge binding parameters: through control flow jump edges (such as `if-true`, `if-false`, `loop-back`)

[0020] Pass the output parameters to the input parameters of the target basic block, replacing the Phi function.

[0021] 4. Control flow analysis (CFG generation)

[0022] According to the converted PCFG, the jump relationship between basic blocks (such as branches, loops, function calls) is analyzed independently to complete the control flow analysis function.

[0023] Generates and outputs a traditional control flow graph (CFG) containing only jump logic and no data dependencies.

[0024] 5. Data flow analysis (parameterized DFG generation)

[0025] According to the generated CFG, data dependencies (such as variable transfer and expression calculation) are tracked based on explicit parameters to complete the data flow analysis function.

[0026] Generates and outputs a parameterized data flow graph (DFG) independent of the control flow structure.

[0027] 6. Application of optimization module

[0028] The decoupled CFG and DFG are used as inputs to the optimization module, and the following example strategy is executed for optimization:

[0029] a) Loop unrolling: pass the iteration variable through explicit parameters and directly expand the loop body.

[0030] b) Redundancy elimination: Rapidly locate repeated calculations or redundant condition judgments based on DFG.

[0031] c) Dynamic parameter adjustment: Adapt to the instruction scheduling requirements of different hardware architectures.

[0032] 7. Generate optimized intermediate representation (IR)

[0033] Based on the results generated by the optimization module application, a low-complexity intermediate representation without Phi functions is output, which can be directly used for back-end code generation.

[0034] Finally, according to the generated IR, it is transferred to the backend for processing to generate the final machine code. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 : A flow chart of a compiler infrastructure for parameterized control flow graphs and its implementation method.

[0036] Figure 2 : A flowchart of loop structure optimization of a compiler infrastructure and its implementation method for parameterized control flow graph.

[0037] Figure 3 :A flowchart of multi-branch structure optimization of a compiler infrastructure and its implementation method for parameterized control flow graph. DETAILED DESCRIPTION

[0038] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0039] The features of various aspects of the embodiments of the present invention will be described in detail below. In the detailed description below, many specific details are provided to provide a comprehensive understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can also be implemented without these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention. The present invention is not limited to any specific settings and methods provided below, but rather covers all product structures, any improvements, replacements, etc. of the methods covered without departing from the spirit of the present invention. In the various drawings and the following description, well-known structures and technologies are not shown to avoid unnecessary ambiguity in the present invention.

[0040] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other, and the embodiments can refer to and quote each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0041] This paper proposes a compiler infrastructure and implementation method based on parameterized control flow graphs. By replacing Phi functions with explicitly parameterized basic blocks, this approach completely decouples control flow and data flow analysis, simplifies data flow analysis, significantly reduces the complexity of intermediate representations, and significantly improves optimization efficiency. It also offers excellent maintainability and debuggability. This approach is suitable for scenarios such as loop unrolling and redundancy elimination, providing a modular and efficient solution for modern compilers.

[0042] Experiments show that this method reduces the number of IR instructions by an average of 15% on the LLVM test set, improves data flow analysis time by approximately 30%, reduces redundant computation by 40%, and compresses the IR volume by 25%. By explicitly parameterizing basic blocks to pass parameters, this method compresses the IR volume, reduces memory usage during compilation, and reduces maintenance costs. By completely decoupling control flow from data flow, data flow analysis is simplified, and the optimization process can directly operate on parameterized structures without traversing complex predecessor lists. It also reduces the cognitive burden of compiler development and debugging. This method is suitable for scenarios such as loop unrolling and redundancy elimination, providing a modular and efficient solution for modern compilers.

[0043] The present invention provides a compiler infrastructure based on a parameterized control flow graph and an implementation method thereof, the method comprising the following steps:

[0044] Step 1: User enters source code

[0045] The source code entered by the user can be in any high-level language such as C / C++, Java, Python, Rust, etc.

[0046] Step 2: User enters source code

[0047] Enter the source code to be compiled (such as C / C++, Python, etc.).

[0048] Step 3: Front-end parsing and generating an abstract syntax tree (AST)

[0049] According to the source code input by the user, it is parsed on the front end, and AST is generated through lexical analysis and syntax analysis to mark the code structure (such as functions, loops, branches, etc.).

[0050] Step 4: Convert to parameterized control flow graph (PCFG)

[0051] Convert AST to PCFG through the following steps:

[0052] (a) Basic block division

[0053] Split the AST into basic blocks, each of which corresponds to a section of code that is executed sequentially.

[0054] (b) Parameterized definition

[0055] Assign explicit parameters to each basic block:

[0056] Input parameters are responsible for defining the external data required for the execution of the basic block (such as loop variable `i`, branch condition `cond`);

[0057] Output parameters are responsible for defining the result data after the execution of the basic block (such as the updated `i+1` and branch result value).

[0058] (c) Control flow edge binding parameters: through control flow jump edges (such as `if-true`, `if-false`, `loop-back`)

[0059] Pass the output parameters to the input parameters of the target basic block, replacing the Phi function.

[0060] Step 5: Control Flow Analysis (CFG Generation)

[0061] According to the converted PCFG, the jump relationship between basic blocks (such as branches, loops, function calls) is analyzed independently to complete the control flow analysis function.

[0062] Generates and outputs a traditional control flow graph (CFG) containing only jump logic and no data dependencies.

[0063] Step 6: Data Flow Analysis (Parameterized DFG Generation)

[0064] According to the generated CFG, data dependencies (such as variable transfer and expression calculation) are tracked based on explicit parameters to complete the data flow analysis function.

[0065] Generates and outputs a parameterized data flow graph (DFG) independent of the control flow structure.

[0066] Step 7: Application of optimization module

[0067] The decoupled CFG and DFG are used as inputs to the optimization module, and the following example strategy is executed for optimization:

[0068] d) Loop unrolling: pass the iteration variable through explicit parameters and directly expand the loop body.

[0069] e) Redundancy elimination: Rapidly locate repeated calculations or redundant condition judgments based on DFG.

[0070] f) Dynamic parameter adjustment: Adapt to the instruction scheduling requirements of different hardware architectures.

[0071] Step 8: Generate optimized intermediate representation (IR)

[0072] Based on the results generated by the optimization module application, a low-complexity intermediate representation without Phi functions is output, which can be directly used for back-end code generation.

[0073] Finally, according to the generated IR, it is transferred to the backend for processing to generate the final machine code.

[0074] This paper presents a compiler infrastructure and implementation method based on parameterized control flow graphs. By replacing Phi functions with explicitly parameterized basic blocks, this approach decouples control flow and data flow analysis, significantly reducing the complexity of the intermediate representation and improving optimization efficiency. This approach is applicable to scenarios such as loop unrolling and redundancy elimination, providing a modular and efficient solution for modern compilers.

[0075] Example 1

[0076] Figure 2 This is a schematic diagram of loop structure optimization of a compiler infrastructure based on a parameterized control flow graph and an implementation method thereof according to an embodiment of the present invention.

[0077] like Figure 2 As shown, the method includes the following steps:

[0078] Step 101. User enters source code

[0079] The user enters the C language source code, sample code snippet:

[0080] %%C

[0081] for(int i=0; i<4; i++){

[0082] sum+=array[i];

[0083] }

[0084] ```

[0085] Step 102. Front-end parsing and generating AST

[0086] According to the source code input by the user, it is parsed on the front end, the `for` nested loop structure is identified, and its corresponding basic block loop header (Loop Header) and loop body (Loop Body) are marked.

[0087] Step 103. Convert to parameterized control flow graph (PCFG)

[0088] Convert the AST to PCFG through the following steps in sequence to parameterize the loop header basic block:

[0089] (a) Basic block division

[0090] In this embodiment, the AST is split into the following two basic blocks (Basic Block), a loop header basic block (displaying parameterized input `i` and outputting `i+1`) and a loop body basic block (inputting `i` and outputting `sum`).

[0091] (b) Parameter binding

[0092] The output parameter `i+1` of the loop header is passed to its input parameter via a control flow edge (`loop-back`).

[0093] Step 104. Control flow analysis (CFG generation)

[0094] Based on the converted PCFG, the generated CFG is: loop head → loop body → loop head (back edge). The control flow analysis module is implemented to confirm the loop jump logic.

[0095] Step 105. Data flow analysis (parameterized DFG generation)

[0096] Based on the generated CFG, the generated DFG is: tracking the explicit transfer path of `i` (`i→i+1`) and the computational dependency of `sum`. The data flow analysis module is implemented to independently track the explicit parameter transfer of `i`.

[0097] Step 106. Application of optimization module

[0098] The optimization module uses the decoupled CFG and DFG as inputs to optimize loop unrolling. The optimization strategy is to replicate the loop body four times based on the explicit parameter `i` and remove loop back edges. By unrolling the loop into four iterations, the optimization module eliminates redundant conditional checks.

[0099] The result of the optimization is the generated expanded linear code without Phi function.

[0100] Step 107. Generate optimized IR

[0101] Output of a sample IR snippet based on the results of applying the optimization module:

[0102] ```

[0103] sum+=array[0];

[0104] sum+=array[1];

[0105] sum+=array[2];

[0106] sum+=array[3];

[0107] ```

[0108] Finally, according to the generated IR, it is transferred to the backend for processing to generate the final machine code.

[0109] All steps have been completed, completing the loop structure optimization process for a compiler infrastructure and implementation method based on parameterized control flow graphs. In this example, parameterization decoupling is achieved by replacing Phi functions with explicitly parameterized basic blocks. This decoupling of control flow and data flow analysis allows for explicit data flow management, significantly reducing the complexity of the intermediate representation and effectively improving loop structure optimization efficiency. The number of IR instructions is reduced by 15%, and data flow analysis time is reduced by 30%.

[0110] Example 2

[0111] Figure 3 The present invention is a multi-branch structure diagram of a compiler infrastructure based on a parameterized control flow graph and an implementation method thereof.

[0112] like Figure 3 As shown, the method includes the following steps:

[0113] Step 201. User inputs source code

[0114] The user enters the C language source code, sample code snippet:

[0115] %%c

[0116] if(cond){

[0117] x=a+b;

[0118] y=x*2;

[0119] }else{

[0120] x=ab;

[0121] y=x / 2;

[0122] }

[0123] z=a+b; / / redundant calculation

[0124] ```

[0125] Step 202. Front-end parsing and generating AST

[0126] According to the source code input by the user, it is parsed on the front end to identify the `if-else` branch structure and subsequent code.

[0127] Step 203: Convert to parameterized control flow graph (PCFG)

[0128] Convert AST to PCFG through the following steps:

[0129] (a) Basic block division

[0130] Identify the basic blocks corresponding to multiple branches and divide them, and define the input parameters (such as branch conditions `cond`) for each branch basic block, and the output parameters are the branch result values:

[0131] (1) `if` branch block (input parameter `cond`, output `x, y`);

[0132] (2) `else` branch block (input parameter `cond`, output `x, y`);

[0133] (3) Merge blocks (input parameters `x,y`);

[0134] (4) Redundant calculation block (input parameters `a, b`, output `z`).

[0135] (b) Parameter binding

[0136] The output parameters `x,y` of the branch block are passed to the merge block through the control flow edge, so that the control flow edge of the merge node directly receives the output parameters of each branch without the need for the Phi function to merge variables.

[0137] Step 204. Control flow analysis (CFG generation)

[0138] According to the converted PCFG, the generated CFG is: branch structure → merging block → redundant calculation block.

[0139] Step 205. Data flow analysis (parameterized DFG generation)

[0140] Based on the generated CFG, the generated DFG is: Identify the repeated calculation of `a+b` in branches and redundant blocks. The data flow analysis module is implemented to quickly identify repeated calculation expressions in different branches through explicit parameters.

[0141] Step 206. Application of optimization module

[0142] The decoupled CFG and DFG are used as the input of the optimization module. The optimization strategy of extracting `a+b` to the common basic block and outputting the parameter `tmp`, as well as updating the branch block and redundant block references `tmp`, is adopted.

[0143] By extracting repeated calculations into common basic blocks, eliminating redundant calculations, and updating the parameter passing path, the number of redundant instructions is reduced and the module optimization is completed.

[0144] Step 207. Generate optimized IR

[0145] Output of a sample IR snippet based on the results of applying the optimization module:

[0146] ```

[0147] tmp=a+b;

[0148] if(cond){

[0149] y=tmp*2;

[0150] }else{

[0151] y=(ab) / 2;

[0152] }

[0153] z = tmp;

[0154] ```

[0155] Finally, according to the generated IR, it is transferred to the backend for processing to generate the final machine code.

[0156] All steps have been completed, completing the multi-branch architecture of a compiler infrastructure based on parameterized control flow graphs and its implementation method. In this embodiment, by replacing Phi functions with explicitly parameterized basic blocks, control flow and data flow analysis are decoupled, significantly reducing the complexity of the intermediate representation. Redundancy in code containing multiple conditional branches is eliminated, improving overall optimization efficiency, including a 40% reduction in redundant computation and a 25% compression of the IR size.

[0157] In summary, this paper proposes a compiler infrastructure and implementation method based on parameterized control flow graphs. By replacing Phi functions with explicitly parameterized basic blocks, this approach completely decouples control flow and data flow analysis, simplifies data flow analysis, significantly reduces the complexity of the intermediate representation, and significantly improves optimization efficiency. This approach offers excellent maintainability and debuggability. It is suitable for scenarios such as loop unrolling and redundancy elimination, providing a modular and efficient solution for modern compilers.

[0158] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with the field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should all be covered by the scope of protection of the present invention.

Claims

1. A compiler infrastructure based on parameterized control flow graph (PCFG) and its implementation method, characterized in that: By parameterizing the control flow graph (PCFG), explicit parameters are introduced for basic blocks to replace the Phi function in the traditional SSA form; at the same time, the control flow is decoupled from the data flow, thereby simplifying the data flow analysis and optimization process.

2. The compiler infrastructure according to claim 1, wherein The parameterized control flow graph (PCFG) is used to explicitly parameterize basic blocks, replacing the Phi function in the traditional static single assignment (SSA) form; In PCFG, each basic block passes data dependencies through explicit parameters. The explicit parameters include input parameters and output parameters. The input parameters define the data required for the basic block to execute, and the output parameters define the result data after the basic block is executed.

3. The compiler infrastructure according to claim 2, characterized in that The binding of the explicit parameters is achieved by controlling the connection relationship of the flow edges, without relying on the Phi function or the predecessor list update.

4. The compiler infrastructure according to claim 1, wherein: The control flow and data flow decoupling module is used to separate control flow analysis from data flow analysis and reduce the complexity of the intermediate representation (IR); The control flow and data flow decoupling module further includes: The control flow analysis submodule only processes the jump relationship between basic blocks; The data flow analysis submodule independently analyzes data dependencies based on explicit parameters.

5. The compiler infrastructure according to claim 1, wherein: The optimization module performs loop expansion, redundancy elimination, and code optimization on the intermediate representation based on the decoupled control flow and data flow information; Supports at least one of the following optimization scenarios: When loop unrolling, pass the loop iteration variable via explicit parameters; Redundancy elimination quickly identifies duplicate calculations based on parameterized data flows.

6. The method for implementing the compiler infrastructure according to any one of claims 1 to 5, characterized in that: The following steps are involved: Parse source code into an abstract syntax tree (AST); Convert the AST into a parameterized control flow graph (PCFG), assigning explicit parameters to each basic block; Perform control flow analysis and data flow analysis on PCFG to generate control flow graph (CFG) and parameterized data flow graph (DFG) respectively; Based on the decoupled control flow and data flow information, an optimization strategy is applied to generate an optimized intermediate representation.

7. The implementation method according to claim 6, characterized in that: The step of converting the parameterized control flow graph further comprises: Identify the control flow jump relationship between basic blocks; Define input parameters and output parameters for each basic block and pass parameter values ​​through control flow edges.

8. The implementation method according to claim 6, characterized in that: The optimization strategy includes dynamically adjusting the delivery path of explicit parameters to adapt to the instruction scheduling requirements of different hardware architectures.

9. The implementation method according to claim 6, characterized in that: The optimization process of the intermediate representation is completely based on the data dependency of explicit parameters without inserting Phi functions.

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