External interrupt controller for heterogeneous multi-core processor system

Abstract

The invention provides an external interrupt controller for a heterogeneous multi-core processor system, and the controller comprises an interrupt gateway which is used for carrying out the arbitration processing of to-be-processed interrupt signals transmitted by a plurality of interrupt sources, obtaining a single interrupt request signal, and transmitting the interrupt request signal to a controller core; and the controller core is used for determining target processor cores for executing interrupt processing in the heterogeneous multi-core processor system according to the interrupt request signals, and sending the interrupt request signals to each target processor core through a single interrupt port, so that the target processor cores execute the interrupt processing for the interrupt request signals. According to the method and the device, the problem of low interrupt distribution and management efficiency of a heterogeneous system multi-core processor in the prior art is solved.

Description

Technical Field

[0001] The present invention relates to the field of network security technology, and in particular to an external interrupt controller for a heterogeneous multi-core processor system. Background Art

[0002] Interrupt and exception mechanisms are crucial in processor systems. When an interrupt or exception occurs, the processor suspends the current task and executes the corresponding interrupt or exception handler, resuming the original task after the processing is complete. Because the processor handles interrupts and exceptions in a similar manner, they are generally referred to as generalized exceptions. Types of interrupts include debug interrupts, external interrupts, timer interrupts, and software interrupts. External interrupts originate from devices external to the processor, such as GPIO interfaces. In homogeneous multi-core processor systems, external interrupts typically rely on traditional interrupt controllers, using centralized, distributed, or load-balancing strategies to ensure that interrupt signals are delivered to the target processing core in a timely and effective manner.

[0003] However, heterogeneous multi-core processor systems vary in their core architectures, computing power, and functionality. External interrupt management requires both efficient interrupt distribution and inter-core compatibility, a requirement that traditional interrupt control methods struggle to meet. In heterogeneous multi-core processors, different processors may have inconsistent interrupt handling mechanisms and even differ in the number of interrupt interfaces. This poses a new technical challenge for the efficient distribution and management of external interrupts. Summary of the Invention

[0004] The present invention provides an external interrupt controller for a heterogeneous multi-core processor system, which is used to solve the problem of low efficiency in interrupt distribution and management of the heterogeneous system multi-core processor in the prior art.

[0005] The present invention provides an external interrupt controller for a heterogeneous multi-core processor system, comprising: an interrupt gateway and a controller core; The interrupt gateway is used to arbitrate pending interrupt signals sent by multiple interrupt sources to obtain a single interrupt request signal, and send the interrupt request signal to the controller core; The controller core is used to determine the target processor core that performs interrupt processing in a heterogeneous multi-core processor system based on the interrupt request signal, and send the interrupt request signal to each target processor core through a single interrupt port so that the target processor core performs interrupt processing for the interrupt request signal.

[0006] In some embodiments, the interrupt gateway is further configured to convert pending interrupt signals sent by multiple interrupt sources into a unified interrupt request format; According to the interrupt priority, the pending interrupt signal with the highest interrupt priority is arbitrated from the converted pending interrupt signals as a single interrupt request signal.

[0007] In some embodiments, the controller core is further used to send the interrupt request signal to the scheduler of the heterogeneous multi-core processor system, so that the scheduler determines at least one target processor core to perform interrupt processing among the multiple processor cores of the heterogeneous multi-core processor system.

[0008] In some embodiments, the target processor core is used to receive an interrupt notification sent by the controller core after determining the interrupt number of the interrupt request signal, and after claiming the interrupt number to the controller core, call the corresponding interrupt processing function according to the interrupt number to perform interrupt processing.

[0009] In some embodiments, the interrupt gateway is also used to arbitrate pending interrupt signals sent by multiple interrupt sources, lock the target interrupt source corresponding to the interrupt request signal after obtaining a single interrupt request signal, and unlock the target interrupt source after receiving interrupt completion information, wherein the interrupt completion information is sent after the target processor core completes the interrupt processing.

[0010] In some embodiments, the interrupt gateway supports triggering modes for interrupt signals to be processed, including at least one of level triggering and edge triggering.

[0011] The present invention also provides an interrupt control method for a heterogeneous multi-core processor system, comprising: arbitrating pending interrupt signals sent by multiple interrupt sources to obtain a single interrupt request signal, and sending the interrupt request signal to the controller core; A target processor core for executing interrupt processing is determined in a heterogeneous multi-core processor system according to the interrupt request signal, and the interrupt request signal is sent to each target processor core through a single interrupt port, so that the target processor core executes interrupt processing according to the interrupt request signal.

[0012] In some embodiments, arbitrating the pending interrupt signals sent by multiple interrupt sources to obtain a single interrupt request signal includes: Convert pending interrupt signals sent by multiple interrupt sources into a unified interrupt request format; According to the interrupt priority, the pending interrupt signal with the highest interrupt priority is arbitrated from the converted pending interrupt signals as a single interrupt request signal.

[0013] In some embodiments, determining a target processor core for executing interrupt processing in a heterogeneous multi-core processor system according to the interrupt request signal includes: The interrupt request signal is sent to a scheduler of the heterogeneous multi-core processor system, so that the scheduler determines at least one target processor core for executing interrupt processing from among the multiple processor cores of the heterogeneous multi-core processor system.

[0014] In some embodiments, the target processor core performs interrupt processing in response to the interrupt request signal, including: An interrupt notification sent after determining the interrupt number of the interrupt request signal is received, and after claiming the interrupt number, a corresponding interrupt processing function is called according to the interrupt number to execute interrupt processing.

[0015] In some embodiments, after arbitrating the pending interrupt signals sent by multiple interrupt sources to obtain a single interrupt request signal, the method further includes: The target interrupt source corresponding to the interrupt request signal is locked, and after receiving interrupt completion information, the target interrupt source is unlocked, wherein the interrupt completion information is sent after the target processor core completes the interrupt processing.

[0016] In some embodiments, the triggering mode of the interrupt signal to be processed includes at least one of level triggering and edge triggering.

[0017] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the above-mentioned interrupt control method for heterogeneous multi-core processor systems when executing the computer program.

[0018] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-mentioned interrupt control method for a heterogeneous multi-core processor system.

[0019] The present invention also provides a computer program product, comprising a computer program, which implements the above-mentioned interrupt control method for heterogeneous multi-core processor systems when executed by a processor.

[0020] The external interrupt controller for heterogeneous multi-core processor systems provided by the present invention first utilizes an interrupt gateway to arbitrate pending interrupt signals sent by multiple interrupt sources into a single interrupt request signal, thereby reducing the complexity of interrupt signal distribution and processing. Second, the controller core sends an interrupt request signal to each target processor core through a single interrupt port to perform interrupt processing. As a result, each target processor core only needs one interrupt port to receive external interrupts, resolving the problem of some processor cores having a limited or inconsistent number of interrupt ports. These two aspects improve the efficiency of interrupt distribution and management for heterogeneous multi-core processors in the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced one by one below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 This is a schematic diagram of an application of an external interrupt controller for a heterogeneous multi-core processor system provided by the present invention.

[0023] Figure 2 It is a schematic diagram of the interrupt control principle of the external interrupt controller provided by the present invention.

[0024] Figure 3 This is an application example diagram of the external interrupt controller provided by the present invention.

[0025] Figure 4 This is a flow chart of an interrupt control method for a heterogeneous multi-core processor system provided by the present invention.

[0026] Figure 5 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0027] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0028] The external interrupt controller for a heterogeneous multi-core processor system of the present invention will be described below with reference to the accompanying drawings. Figure 1FIG. 1 is a schematic diagram of an application of an external interrupt controller for a heterogeneous multi-core processor system provided by the present invention. Figure 1 As shown, the external interrupt controller is deployed inside the heterogeneous multi-core processor system. The pending interrupt signals of multiple external interrupt sources are received through the external interrupt controller and arbitrated into a single interrupt request signal. After the corresponding target processor core is queried through the scheduler, the interrupt request signals are sent to the target processor core respectively to execute interrupt processing.

[0029] Specifically, the external interrupt controller includes two modules: an interrupt gateway and a controller core. The interrupt gateway is used to arbitrate pending interrupt signals sent by multiple interrupt sources, obtain a single interrupt request signal, and send the interrupt request signal to the controller core.

[0030] like Figure 1 As shown, there are multiple external interrupt sources, each corresponding to multiple pending interrupt signals. Each pending interrupt signal is user-configured with parameters such as the interrupt number, interrupt enable, interrupt priority, interrupt handler function, and interrupt triggering method. After being sent to the external interrupt controller, these pending interrupt signals are received by the interrupt gateway. The interrupt gateway arbitrates the multiple pending interrupt signals into a single interrupt request signal based on the interrupt priority. This ensures that only one interrupt request signal is sent to the processor cores of a heterogeneous multi-core processor system. Although the processor cores themselves may also have interrupt controllers with multiple interrupt ports capable of handling multiple interrupt requests, the interrupt gateway only distributes a single interrupt request signal. Therefore, each processor core only enables one interrupt port to receive the interrupt request signal. During system deployment, a single signal line is connected between the external interrupt controller and each processor core, utilizing the interrupt port. For example, if a processor core has 240 interrupt ports, only one interrupt port is enabled to receive the interrupt request signal, leaving the remaining 239 interrupt ports unused.

[0031] The controller core is used to determine the target processor core that performs interrupt processing in the heterogeneous multi-core processor system based on the interrupt request signal, and send an interrupt request signal to each target processor core through a single interrupt port so that the target processor core performs interrupt processing for the interrupt request signal.

[0032] Here, not all processor cores of the heterogeneous multi-core processor system need to be interrupt targets. The interrupt request signal obtained after the interrupt gateway arbitration is sent to which processor cores is controlled by the scheduler of the heterogeneous multi-core processor system. Here, the target processor core for executing interrupt processing is first determined in the heterogeneous multi-core processor system based on the interrupt request signal, and since each processor core of the heterogeneous multi-core processor system only enables one interrupt port to receive external interrupts, the controller core sends the interrupt request signal to each target processor core through a single interrupt port. Figure 1 In the example, the external interrupt controller sends interrupt request signals to target processor cores 1, 2, and 3, respectively. The target processor cores then execute the interrupt processing functions corresponding to the interrupt request signals and, upon completion, send interrupt completion information back to the interrupt gateway. Upon receiving the interrupt completion information, the interrupt gateway continues to wait for and process pending interrupt signals from subsequent interrupt sources.

[0033] This embodiment of the present invention uses an interrupt gateway to arbitrate pending interrupt signals from multiple interrupt sources into a single interrupt request signal, thus reducing the complexity of interrupt signal distribution and processing. Furthermore, a controller core is used to send an interrupt request signal to each target processor core via a single interrupt port for interrupt processing. As a result, each target processor core only requires one interrupt port to receive external interrupts, resolving the issue of limited or inconsistent interrupt ports on some processor cores. This improves the efficiency of interrupt distribution and management for heterogeneous multi-core processors.

[0034] Furthermore, the interrupt gateway is also used to convert the pending interrupt signals sent by multiple interrupt sources into a unified interrupt request format, and arbitrate a pending interrupt signal with the highest interrupt priority from the converted pending interrupt signals according to the interrupt priority as the interrupt request signal.

[0035] Due to the large number and varying types of external interrupt sources, the corresponding pending interrupt signals vary. Therefore, the pending interrupt signals sent by multiple interrupt sources are converted into a unified interrupt request format to ensure that the pending interrupt signals can be received by the processor cores of the heterogeneous multi-core processor system. The pending interrupt signals are each user-configured with a corresponding interrupt priority. The highest priority pending interrupt signal is arbitrated from the converted pending interrupt signals based on the interrupt priority level and sent as a single interrupt request signal to the processor core of the heterogeneous multi-core processor system for interrupt processing.

[0036] Embodiments of the present invention convert pending interrupt signals from multiple external interrupt sources into a unified interrupt request format, thereby masking differences in interrupt handling mechanisms among different processor cores and enhancing the versatility of heterogeneous multi-core processor systems. Arbitrating multiple pending interrupt signals into a single interrupt request signal reduces the number of signals sent to each processor core in the heterogeneous multi-core processor system. When connecting an external interrupt controller, only one external interrupt signal line is required to connect to each processor core, reducing hardware wiring complexity and cabling costs.

[0037] In some embodiments, the controller core is further configured to send an interrupt request signal to a scheduler of the heterogeneous multi-core processor system, so that the scheduler determines at least one target processor core for executing interrupt processing among multiple processor cores of the heterogeneous multi-core processor system.

[0038] Here, an interrupt request signal is sent to the scheduler of the heterogeneous multi-core processor system through the controller core. After receiving the interrupt request signal, the scheduler will perform a status query, that is, determine the operating status of each processor core of the heterogeneous multi-core processor system (such as idle or task processing), and then determine which processor cores to perform interrupt processing. In this way, at least one target processor core can be determined from the heterogeneous multi-core processor system and fed back to the controller core, and the determined target processor core will be used as the interrupt target for processing the interrupt request signal.

[0039] In an embodiment of the present invention, the scheduler of a heterogeneous multi-core processor system is used to query and determine the interrupt target, thereby controlling the distribution of interrupt request signals. Not all processor cores receive the interrupt request signal, thereby improving the interrupt processing efficiency of the heterogeneous multi-core processor system and solving the problems of missed and wrong interrupts caused by the online and offline processing of processor cores in the heterogeneous multi-core processor system.

[0040] In some embodiments, the target processor core is configured to receive an interrupt notification sent by the controller core after the controller core determines the interrupt number of the interrupt request signal.

[0041] After the controller core determines the interrupt target (i.e., the target processor core) reported by the scheduler, it determines the interrupt number (ID) of the target interrupt source based on the interrupt request signal's interrupt priority. It then determines whether the interrupt source is enabled. If so, it sends an interrupt notification to the target processor core, which then receives the corresponding interrupt notification. The target processor core then requests the interrupt number from the controller core. After receiving the interrupt number from the controller core, it calls the corresponding interrupt handler function based on the interrupt number to execute the interrupt processing.

[0042] Here, the controller core sends an interrupt notification to each target processor core, distributing a single interrupt request signal to each target processor core. Each target processor core receives the interrupt notification and claims the interrupt number from the controller core, indicating that it can execute the interrupt. Each target processor core calls the corresponding interrupt handling function based on the claimed interrupt number to execute the interrupt. After the interrupt processing is completed, each target processor core sends the corresponding interrupt completion message to the interrupt gateway module.

[0043] In an embodiment of the present invention, after determining the target processor core to perform interrupt processing, a single interrupt request signal is sent to each target processor core through the controller core, and each interrupt processing is performed by claiming the interrupt number, thereby improving the interrupt processing efficiency of the heterogeneous multi-core processor system.

[0044] In some embodiments, the interrupt gateway is also used to arbitrate pending interrupt signals sent by multiple interrupt sources, lock the target interrupt source corresponding to the interrupt request signal after obtaining a single interrupt request signal, and unlock the target interrupt source after receiving the interrupt completion information, wherein the interrupt completion information is sent after the target processor core completes the interrupt processing.

[0045] like Figure 2 As shown, Figure 2 The following is a schematic diagram of the interrupt control principle of the external interrupt controller provided by the present invention, illustrating an interrupt processing flow. First, multiple interrupt sources from external resources (configured on the user side) generate corresponding pending interrupt signals, which are received by the interrupt gateway of the external interrupt controller. The interrupt gateway arbitrates these pending interrupt signals, generating a single interrupt request signal and sending it to the controller core of the external interrupt controller. At this point, if the external interrupt source still sends pending interrupt signals, the interrupt gateway locks the corresponding interrupt source, and then suspends any subsequent pending interrupt signals sent by the external interrupt source.

[0046] After the controller core executes a status query to the scheduler, the scheduler returns the status, which is feedback on which target processor cores can execute interrupt processing, that is, determining the interrupt target. Then the controller core will first determine the interrupt number and send an interrupt notification to the target processor core. After receiving the interrupt notification, the target processor core will execute interrupt claim to the controller core to obtain the interrupt number, and then call the corresponding interrupt handling function to perform interrupt processing.

[0047] After the target processor core completes interrupt processing, it sends an interrupt completion message to the interrupt gateway. After confirming the interrupt completion message, the interrupt gateway unlocks the target interrupt source, effectively unblocking the previously locked interrupt source. This allows the next interrupt processing flow to proceed, allowing the interrupt gateway to continue receiving pending interrupt signals or subsequent pending interrupt signals from external interrupt sources. It then continues to arbitrate the corresponding interrupt request signal, which it then sends to the controller core, and so on.

[0048] In an embodiment of the present invention, when an external interrupt controller executes an interrupt processing process, the interrupt source of the external resource is locked, and the interrupt source is unlocked after the execution of the interrupt processing process, so that the heterogeneous multi-core processor system can process various interrupt signals in an orderly and stable manner, avoid executing unnecessary interrupt processing programs, and improve the efficiency of interrupt processing.

[0049] In some embodiments, the interrupt gateway supports triggering modes for interrupt signals to be processed, including at least one of level triggering and edge triggering.

[0050] Here, the external interrupt controller supports both level-triggered and edge-triggered interrupt signal triggering modes. This means that the external interrupt controller can enable both level-triggered and edge-triggered interrupt signal triggering modes. However, in general, you should not enable both at the same time; only one should be enabled.

[0051] Level triggering can be either low-level or high-level. When the interrupt signal trigger mode is high (low) level triggering, a continuous high (low) level will only send a pending interrupt signal to the external interrupt controller once. At this time, based on the interrupt execution status of the heterogeneous multi-core processor system, the normal interrupt processing flow is triggered for the pending interrupt signal.

[0052] Edge triggering is divided into rising edge triggering and falling edge triggering. Rising (falling) edge triggering will cause the external interrupt controller to receive multiple pending interrupt signals. Every time the interrupt gateway receives a valid rising (falling) edge, it will record the number of times the external interrupt source in this working mode sends pending interrupt signals to the external interrupt controller within a certain period of time. After the heterogeneous multi-core processor system completes the interrupt processing, the number is updated to ensure the accurate execution of the pending interrupt signals.

[0053] In an embodiment of the present invention, by enabling an external interrupt controller to support both level-triggered and edge-triggered interrupt signal triggering modes, a heterogeneous multi-core processor system can detect various forms of pending interrupt signals generated by external resources, thereby facilitating the processor core to obtain detailed information about the external resources and adjust the interrupt processing flow of the heterogeneous multi-core processor system.

[0054] In some embodiments, the external interrupt controller further includes programmable registers. The programmable registers are used to control and manage interrupts during the interrupt handling process. The programmable registers include: an interrupt enable register, an interrupt priority register, an interrupt pending register, an interrupt pending register, an interrupt active register, an interrupt active register, an outermost interrupt number register, and an interrupt completion register, each of which is described below.

[0055] The interrupt enable register is used to determine whether the target interrupt source of the interrupt request signal can send an interrupt notification to the processor core of the heterogeneous multi-core processor system.

[0056] The interrupt priority register is used to determine the interrupt priority of the pending interrupt signal after it is converted into a unified interrupt request format, so that the interrupt gateway can perform arbitration processing on the pending interrupt signal.

[0057] The interrupt pending register is used to store the pending status of pending interrupt signals sent by multiple interrupt sources. When a heterogeneous multi-core processor system is executing interrupt processing, the corresponding interrupt source is locked through the interrupt gateway, and the subsequent pending interrupt signals sent by the external interrupt source are suspended. This interrupt suspension state is the waiting state for the pending interrupt signal. When the interrupt source is unlocked, the corresponding pending interrupt signal is also released from the interrupt suspension state and enters the external interrupt controller for interrupt processing.

[0058] The interrupt active register is used to determine the interrupt processing status of pending interrupt signals sent by multiple interrupt sources. Interrupt processing status is divided into three categories: unhandled, in-process, and handled. A pending interrupt signal is in the unhandled state before it is arbitrated by the interrupt gateway. After arbitration and before the target processor core sends an interrupt completion message to the interrupt gateway, it enters the in-processing state. After the target processor core sends an interrupt completion message to the interrupt gateway, it enters the handled state.

[0059] The outermost interrupt number register is used to determine and store the interrupt numbers of pending interrupt signals sent by multiple interrupt sources. After the interrupt number of the interrupt source corresponding to the pending signal configured by the user in the external resource, this interrupt number is stored in the outermost interrupt number register for query by the controller core.

[0060] The interrupt claim register is used to store the interrupt number of the target interrupt source corresponding to the interrupt request signal. When the controller core determines that the interrupt request signal corresponds to the interrupt number of the target interrupt source, it will write the interrupt number into the interrupt claim register for the target processor core to claim.

[0061] The interrupt completion register stores the interrupt completion message sent by the target processor core after executing interrupt processing. It also triggers the interrupt gateway to unlock the target interrupt source if the message is modified. The target processor core calls the corresponding interrupt handling function based on the interrupt number claimed by the interrupt claim register to execute the interrupt. After the interrupt is processed, the interrupt completion message is rewritten to the interrupt completion register for query by the interrupt gateway, triggering the unlocking of the target interrupt source.

[0062] This embodiment of the present invention integrates multiple programmable registers for interrupt management and control within an external interrupt controller, moving interrupt management and control from the processor core to the heterogeneous multi-core processor system. This mitigates differences in interrupt implementation between processor cores. The integration of multiple programmable registers enhances the flexibility of interrupt management in heterogeneous multi-core processor systems and improves system scalability.

[0063] The interrupt control method for a heterogeneous multi-core processor system provided by the present invention is described below. The interrupt control method for a heterogeneous multi-core processor system described below and the external interrupt controller for a heterogeneous multi-core processor system described above can be referenced to each other.

[0064] like Figure 4 As shown, the interrupt control method for a heterogeneous multi-core processor system can be implemented through steps 101 to 102, which are described one by one below.

[0065] In step 101, arbitration is performed on the pending interrupt signals sent by multiple interrupt sources to obtain a single interrupt request signal.

[0066] In step 102, a target processor core for executing interrupt processing is determined in the heterogeneous multi-core processor system according to the interrupt request signal, and an interrupt request signal is sent to each target processor core through a single interrupt port, so that the target processor core executes interrupt processing according to the interrupt request signal.

[0067] In some embodiments, arbitration is performed on pending interrupt signals sent by multiple interrupt sources to obtain a single interrupt request signal, including: converting the pending interrupt signals sent by multiple interrupt sources into a unified interrupt request format; arbitrating the pending interrupt signal with the highest interrupt priority from the converted pending interrupt signals according to the interrupt priority as a single interrupt request signal.

[0068] In some embodiments, determining a target processor core for executing interrupt processing in a heterogeneous multi-core processor system based on an interrupt request signal includes: sending an interrupt request signal to a scheduler of the heterogeneous multi-core processor system so that the scheduler determines at least one target processor core for executing interrupt processing among multiple processor cores of the heterogeneous multi-core processor system.

[0069] In some embodiments, the target processor core performs an interrupt processing process in response to an interrupt request signal, including: An interrupt notification sent after determining the interrupt number of the interrupt request signal is received, and after claiming the interrupt number, a corresponding interrupt processing function is called according to the interrupt number to execute interrupt processing.

[0070] In some embodiments, after arbitrating the pending interrupt signals sent by multiple interrupt sources and obtaining a single interrupt request signal, the target interrupt source corresponding to the interrupt request signal is also locked, and after receiving the interrupt completion information, the target interrupt source is unlocked, wherein the interrupt completion information is sent after the target processor core completes the interrupt processing.

[0071] In some embodiments, the triggering mode of the interrupt signal to be processed includes at least one of level triggering and edge triggering.

[0072] It should be noted that the above-mentioned interrupt control method for heterogeneous multi-core processor systems corresponds to the beneficial effects of the external interrupt controller of the heterogeneous multi-core processor system mentioned above, so the beneficial effects of the interrupt control method for heterogeneous multi-core processor systems will not be repeated here.

[0073] The following combination Figure 3 The specific examples in the following are used to describe the external interrupt controller and interrupt control method for a heterogeneous multi-core processor system provided by the present invention.

[0074] like Figure 3 As shown, a heterogeneous multi-core processor is a type of heterogeneous multi-core microcontroller consisting of a scheduler, a set of functionally equivalent heterogeneous processors, and peripherals (user-side). The set of functionally equivalent heterogeneous processors specifically includes four processor cores: the ARM Cortex-M3 processor, the RISC-V T-Head E906 processor, the RISC-V HBird E203 processor, and the MIPS microAptiv UC processor. These are the processor cores within the heterogeneous multi-core processor. The interrupt signals from all peripheral interrupt sources are managed by an external interrupt controller, with only one signal line connected to each processor core. Non-maskable interrupt signals (NMIs) are typically generated by peripherals such as watchdog timers and brownout detectors. The interrupt source corresponding to an NMI in the external interrupt controller is always enabled and cannot be modified. The interrupt corresponding to an NMI has a higher priority than all other interrupt sources, such as IRQs.

[0075] The following describes the connection between the external interrupt controller and each processor core in a heterogeneous multi-core microcontroller. The ARM Cortex-M3 processor supports up to 240 external interrupt requests, one system tick interrupt (SysTick), and multiple system exceptions. External interrupts are generated by peripherals such as timers, I / O ports, and communication interfaces, while other system exceptions originate from the processor core. The ARM Cortex-M3 processor provides a nested vectored interrupt controller (NVIC) for interrupt handling, generating software interrupts. The external interrupt controller connects only one signal line to the NVIC, taking over the management of the original 240 external interrupts.

[0076] The RISC-V T-Head E906 processor is compatible with the RISC-V standard exception vector numbering and supports nine system exceptions. It implements the Core Local Interrupt (CLINT) module, which includes software interrupts and timer interrupts. This module's registers are mapped in the address space of the tightly coupled IP. The RISC-V T-Head E906 processor also implements the Core Local Interrupt Controller (CLIC), which samples, prioritizes, and dispatches up to 240 external interrupt sources. Similar to the ARM Cortex-M3 processor, the external interrupt controller connects only one signal line to the CLIC, taking over management of the original 240 external interrupts.

[0077] The RISC-V HBird E203 processor is also compatible with the RISC-V standard exception vector numbering, supporting nine system exceptions. The RISC-V HBird E203 processor implements processor core local interrupts (CLINTs), including software interrupts and timer interrupts. This module's registers are mapped in the address space of the tightly coupled IP. The RISC-V HBird E203 processor also implements a platform-level interrupt controller (PLIC), which samples, prioritizes, and distributes up to 51 external interrupt sources. The external interrupt controller connects only one signal line to the PLIC, taking over management of the original 51 external interrupts.

[0078] The MIPS microAptiv UC processor supports 21 system exceptions, two software interrupts, one timer interrupt, and up to six external interrupts. The MIPS microAptiv UC processor core architecture does not have a separate interrupt handling module. Instead, it connects to the execution units within the processor core via an interrupt interface. The external interrupt controller connects only one signal line to this interrupt interface, taking over management of the six external interrupts.

[0079] In this way, the external interrupt controller is connected to each processor core via only one signal line, thereby taking over the external interrupt management of each processor core at the same time.

[0080] exist Figure 3 In the integrated solution shown, assume that at a certain point in time the scheduler determines that only three processor cores—the ARM Cortex-M3, the RISC-VT-Head E906, and the MIPS microAptiv UC—are available for interrupt processing. At this point, interrupt source 12, representing the peripheral (i.e., external resource), sends a pulsed interrupt signal to the heterogeneous multicore microcontroller as a pending interrupt. There are no other pending interrupts pending, and no other pending interrupts of higher priority arrive during the interrupt processing process to preempt it.

[0081] Based on the above scenario, the interrupt handling steps of a heterogeneous multi-core microcontroller include: 1. The user configures the interrupt enable register, determines the interrupt source enable of interrupt number 12, and registers the corresponding interrupt handling function UART0_RX_Handler() in the software; 2. The interrupt source with interrupt number 12 where the peripheral is located sends a pulse interrupt signal to the interrupt gateway; 3. The interrupt gateway converts the pulse interrupt signal into a unified interrupt request format, sends the interrupt request signal to the controller core, and locks interrupt source No. 12; 4. The controller core queries the scheduler for available processor cores and determines that the interrupt targets (i.e., target processor cores) are ARM Cortex-M3, RISC-V T-Head E906, and MIPS microAptiv UC; 5. The controller core determines that the interrupt number is 12 based on the interrupt priority and other information, and writes it into the interrupt claim register; 6. The controller core sends an interrupt notification to the three processor cores determined in step 4; 7. After receiving the interrupt notification, the three processor cores query the interrupt claim register and learn that the interrupt number they claim is 12. 8. Each of the three processor cores calls the interrupt handling function UART0_RX_Handler() corresponding to interrupt source 12 to perform interrupt processing. After the interrupt processing is completed, the interrupt completion information is sent to rewrite the interrupt completion register; 9. Activate the interrupt gateway by rewriting the interrupt completion register, and the interrupt gateway unlocks the current interrupt source No. 12; 10. If there is no pending interrupt signal, return to step 2 and wait for the subsequent pending interrupt signal to be sent. The entire interrupt processing process ends.

[0082] Figure 5 An example of a physical structure diagram of an electronic device is shown below. Figure 5 As shown, the electronic device may include: a processor 510, a communications interface 520, a memory 530, and a communications bus 540, wherein the processor 510, the communications interface 520, and the memory 530 communicate with each other via the communications bus 540. The processor 510 may call logic instructions in the memory 530 to execute an interrupt control method for a heterogeneous multi-core processor system, the method comprising: arbitrating pending interrupt signals sent by multiple interrupt sources to obtain a single interrupt request signal, and sending the interrupt request signal to the controller core; determining a target processor core for executing interrupt processing in the heterogeneous multi-core processor system based on the interrupt request signal, and sending the interrupt request signal to each target processor core via a single interrupt port, so that the target processor core executes interrupt processing in response to the interrupt request signal.

[0083] Furthermore, the logic instructions in the aforementioned memory 530 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0084] On the other hand, the present invention also provides a computer program product, which includes a computer program, which can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the interrupt control method for a heterogeneous multi-core processor system provided by the above methods. The method includes: arbitrating the pending interrupt signals sent by multiple interrupt sources to obtain a single interrupt request signal, and sending the interrupt request signal to the controller core; determining the target processor core for executing interrupt processing in the heterogeneous multi-core processor system based on the interrupt request signal, and sending the interrupt request signal to each target processor core through a single interrupt port, so that the target processor core executes interrupt processing for the interrupt request signal.

[0085] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, it is implemented to execute the interrupt control method for a heterogeneous multi-core processor system provided by the above-mentioned methods. The method includes: arbitrating the pending interrupt signals sent by multiple interrupt sources to obtain a single interrupt request signal, and sending the interrupt request signal to the controller core; determining the target processor core for executing interrupt processing in the heterogeneous multi-core processor system based on the interrupt request signal, and sending the interrupt request signal to each target processor core through a single interrupt port, so that the target processor core performs interrupt processing for the interrupt request signal.

[0086] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0087] Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented using software plus a necessary general-purpose hardware platform, or of course, hardware. Based on this understanding, the essence of the above technical solution, or the portion that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, or an optical disk, and includes a number of instructions for causing a computer device (such as a personal computer, server, or network device) to execute the methods described in each embodiment or certain portions of the embodiments.

[0088] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. An external interrupt controller for a heterogeneous multi-core processor system, characterized in that: include: Interrupt gateway and controller core; The interrupt gateway is used to arbitrate pending interrupt signals sent by multiple interrupt sources to obtain a single interrupt request signal, and send the interrupt request signal to the controller core; The controller core is used to determine the target processor core that performs interrupt processing in a heterogeneous multi-core processor system based on the interrupt request signal, and send the interrupt request signal to each target processor core through a single interrupt port so that the target processor core performs interrupt processing for the interrupt request signal.

2. The external interrupt controller for heterogeneous multi-core processor systems according to claim 1, characterized in that: The interrupt gateway is further used to convert the pending interrupt signals sent by multiple interrupt sources into a unified interrupt request format; According to the interrupt priority, the pending interrupt signal with the highest interrupt priority is arbitrated from the converted pending interrupt signals as a single interrupt request signal.

3. The external interrupt controller for heterogeneous multi-core processor systems according to claim 1, wherein: The controller core is further configured to send the interrupt request signal to a scheduler of the heterogeneous multi-core processor system, so that the scheduler determines at least one target processor core for executing interrupt processing from among the multiple processor cores of the heterogeneous multi-core processor system.

4. The external interrupt controller for heterogeneous multi-core processor systems according to claim 1, wherein: The target processor core is used to receive the interrupt notification sent by the controller core after determining the interrupt number of the interrupt request signal, and after claiming the interrupt number from the controller core, call the corresponding interrupt processing function according to the interrupt number to perform interrupt processing.

5. The external interrupt controller for heterogeneous multi-core processor systems according to claim 1, characterized in that: The interrupt gateway is further used to arbitrate pending interrupt signals sent by multiple interrupt sources, and after obtaining a single interrupt request signal, lock the target interrupt source corresponding to the interrupt request signal, and unlock the target interrupt source after receiving interrupt completion information, wherein the interrupt completion information is sent by the target processor core after executing the interrupt processing.

6. The external interrupt controller for heterogeneous multi-core processor systems according to claim 1, characterized in that: The interrupt gateway supports triggering modes for interrupt signals to be processed, including at least one of level triggering and edge triggering.

7. An interrupt control method for a heterogeneous multi-core processor system, characterized in that: The method comprises: Arbitrate pending interrupt signals sent by multiple interrupt sources to obtain a single interrupt request signal; A target processor core for executing interrupt processing is determined in a heterogeneous multi-core processor system according to the interrupt request signal, and the interrupt request signal is sent to each target processor core through a single interrupt port, so that the target processor core executes interrupt processing according to the interrupt request signal.

8. The interrupt control method for a heterogeneous multi-core processor system according to claim 7, characterized in that: The arbitrating of pending interrupt signals sent by multiple interrupt sources to obtain a single interrupt request signal includes: Convert pending interrupt signals sent by multiple interrupt sources into a unified interrupt request format; According to the interrupt priority, the pending interrupt signal with the highest interrupt priority is arbitrated from the converted pending interrupt signals as a single interrupt request signal.

9. The interrupt control method for a heterogeneous multi-core processor system according to claim 7, characterized in that: The determining, in the heterogeneous multi-core processor system according to the interrupt request signal, a target processor core for executing interrupt processing comprises: The interrupt request signal is sent to a scheduler of the heterogeneous multi-core processor system, so that the scheduler determines at least one target processor core for executing interrupt processing from among the multiple processor cores of the heterogeneous multi-core processor system.

10. The interrupt control method for a heterogeneous multi-core processor system according to claim 7, characterized in that: The target processor core performs interrupt processing in response to the interrupt request signal, comprising: An interrupt notification sent after determining the interrupt number of the interrupt request signal is received, and after claiming the interrupt number, a corresponding interrupt processing function is called according to the interrupt number to execute interrupt processing.

11. The interrupt control method for a heterogeneous multi-core processor system according to claim 7, characterized in that: After arbitrating the pending interrupt signals sent by the plurality of interrupt sources to obtain a single interrupt request signal, the method further includes: The target interrupt source corresponding to the interrupt request signal is locked, and after receiving interrupt completion information, the target interrupt source is unlocked, wherein the interrupt completion information is sent after the target processor core completes the interrupt processing.

12. The interrupt control method for a heterogeneous multi-core processor system according to claim 7, characterized in that: The triggering mode of the interrupt signal to be processed includes at least one of level triggering and edge triggering.

13. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that: When the processor executes the computer program, the interrupt control method for a heterogeneous multi-core processor system according to any one of claims 7 to 12 is implemented.

14. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the interrupt control method for a heterogeneous multi-core processor system is implemented as described in any one of claims 7 to 12.

15. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the interrupt control method for a heterogeneous multi-core processor system as claimed in any one of claims 7 to 12 is implemented.

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