Method and device for realizing receiving and transmitting of Ethernet message with any length
By converting between custom frame formats and standard formats, the problem of frame length limitation in the Ethernet standard is solved, and accurate processing and reliable forwarding of Ethernet messages of any length are achieved. Ultra-short and ultra-long data transmission is supported, which expands the application range of the tester and improves test flexibility and accuracy.
Patent Information
- Application Number
- CN202511059735.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-30
- Publication Date
- 2025-09-26
AI Technical Summary
Existing Ethernet standards limit frame lengths to between 64 and 16,383 bytes, making them unable to effectively process and forward ultra-short or ultra-long messages, limiting their testing support in new network application scenarios.
By adopting the conversion method between custom frame format and standard format, and controlling information field storage and segmentation processing, it realizes the transmission and conversion of Ethernet messages of arbitrary length, including the recognition of ultra-short frames and the caching of ultra-long frames.
It achieves accurate processing and reliable forwarding of Ethernet messages of any length, breaks through the traditional Ethernet frame length limitation, supports ultra-short and ultra-long data transmission, expands the application range of the tester, improves test flexibility and accuracy, and reduces test cost and complexity.
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Figure CN120711087A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of data transmission, and in particular to a method and device for transmitting and receiving Ethernet messages of arbitrary length. Background Art
[0002] Existing Ethernet standards specify that Ethernet frame lengths typically range from 64 to 16,383 bytes. This limitation is primarily based on the design philosophy and collision detection mechanisms of traditional Ethernet. Frames shorter than 64 bytes are discarded as invalid, while frames longer than 16,383 bytes cannot be processed or forwarded. This limitation prevents existing Ethernet testers from providing accurate and effective testing support for emerging network application scenarios, such as IoT device testing with ultra-short data transmissions and data center network testing with extremely long data packets, significantly restricting their application scope and testing capabilities. Summary of the Invention
[0003] The present application provides a method and device for transmitting and receiving Ethernet messages of arbitrary length, which solves the technical problem that the prior art cannot process and forward ultra-short or ultra-long messages.
[0004] To achieve the above objectives, this application adopts the following technical solutions:
[0005] In a first aspect, a method for transmitting and receiving Ethernet messages of arbitrary length is provided, comprising: receiving a data message in a first format; storing data in the data message based on a control information field in the data message; converting the data in the data message into a data message in a second format; wherein one of the first format and the second format is a custom frame format and the other is a standard format that complies with a transmission protocol; the data message in the custom frame format is used to transmit data of arbitrary length.
[0006] Based on the above technical solution, the method for transmitting and receiving Ethernet messages of arbitrary length provided in this application can realize the transmission of data messages of arbitrary length and the bidirectional conversion between data messages of arbitrary length and standard format messages. When necessary, data messages of arbitrary length can be converted into standard format for accurate processing. Based on this, data messages of arbitrary length can be accurately processed and reliably forwarded, including the identification and transmission of ultra-short frames and the caching and processing of ultra-long frames, thus ensuring the integrity and accuracy of the data.
[0007] In combination with the above-mentioned first aspect, in a possible implementation method, the control information field of the custom frame format includes: a type identification field and a frame length indication field; when the first format is a custom frame format and the second format is a standard format, the method of storing data in a data message based on the control information field in the data message specifically includes: after receiving a data message containing a type identification field for identifying the beginning of the data, storing the data corresponding to the length identified by the frame length indication field in the data message until a data message containing a type identification field for identifying the end of the data is received.
[0008] In combination with the first aspect above, in a possible implementation method, the method of converting data in a data message into a data message in a second format specifically includes: according to the standard transmission bit width required by the standard format, taking segmented data of corresponding length from the pre-stored data for encapsulation to obtain at least one data message in a standard format.
[0009] In conjunction with the first aspect above, in one possible implementation, a method for encapsulating segmented data of corresponding length from pre-stored data according to a standard transmission bit width required by a standard format to obtain at least one data message in a standard format specifically includes: calculating the number of segments N according to the standard transmission bit width and the data length of the data in the data message; the calculation formula is:
[0010] intN=a%b==0? a / b:a / b+1;
[0011] N is the segmented output; a is the data length; b is the standard transmission bit width; a standard protocol header is added to each data segment after segmentation to mark the valid data range, and an end flag is set in the last data segment to obtain at least one data message in a standard format.
[0012] In combination with the first aspect above, in a possible implementation, the method further includes: determining the optimal transmission bit width based on the network load parameters monitored in real time; switching the standard transmission bit width to the optimal transmission bit width; sending a test message to verify the optimal standard transmission bit width, and switching back to the standard transmission bit width if the verification fails.
[0013] In combination with the above-mentioned first aspect, in a possible implementation method, the control information field of the standard format includes: a type identification field; when the first format is a standard format and the second format is a custom frame format, a method for storing data in a data message based on the control information field in the data message specifically includes: after receiving a data message containing a type identification field for identifying the beginning of the data, storing the data in the data message until receiving a data message containing a type identification field for identifying the end of the data.
[0014] In combination with the above-mentioned first aspect, in a possible implementation method, a method for converting data in a data message into a data message of a second format specifically includes: encapsulating the data in at least one data message received between a data message containing a type identification field for identifying the start of data and a data message containing a type identification field for identifying the end of data to obtain a data message with a custom frame format; the frame length indication field of the data message is the sum of the data lengths in at least one data message received between a data message containing a type identification field for identifying the start of data and a data message containing a type identification field for identifying the end of data.
[0015] In combination with the first aspect above, in a possible implementation method, the method for storing data in a data message specifically includes: real-time monitoring of the capacity of the cache area; when the capacity of the cache area is greater than the data length of the data message, storing the data in the data message at the tail of the queue of the cache area; when the capacity of the cache area is less than the data length of the data message, suspending the reception of messages until the capacity of the cache area is greater than the data length of the data message, and continuing to store the data in the data message.
[0016] In combination with the first aspect above, in a possible implementation, the cache area includes: two physically isolated primary buffers and a secondary buffer; the method also includes: receiving data through the primary buffer and reading stored data through the secondary buffer; when the primary buffer is full or the secondary buffer is empty, exchanging the roles of the two buffers.
[0017] In a second aspect, a device for implementing the reception and transmission of Ethernet messages of arbitrary length is provided, comprising: a communication unit, a storage unit and a processing unit; the communication unit is used to receive a data message in a first format; the storage unit is used to store data in the data message based on a control information field in the data message; the processing unit is used to convert the data in the data message into a data message in a second format; of the first format and the second format, one is a custom frame format and the other is a standard format that complies with the transmission protocol; the data message in the custom frame format is used to transmit data of arbitrary length.
[0018] In a third aspect, the present application provides an apparatus for transmitting and receiving Ethernet messages of arbitrary length, comprising: a processor and a storage medium; the storage medium comprising instructions, the processor being configured to execute the instructions to implement the method described in the first aspect and any possible implementation of the first aspect. The apparatus for transmitting and receiving Ethernet messages of arbitrary length may be an electronic device or a chip within the electronic device.
[0019] In a fourth aspect, the present application provides an implementation system for receiving and sending Ethernet messages of arbitrary length, including: a communication module and a processing module; the communication module is used to receive a data message in a first format; the processing module is used to store data in the data message based on the control information field in the data message; the communication module is also used to convert the data in the data message into a data message in a second format; of the first format and the second format, one is a custom frame format and the other is a standard format that complies with the transmission protocol; the data message in the custom frame format is used to transmit data of arbitrary length.
[0020] In a fifth aspect, the present application provides a computer-readable storage medium, which stores instructions. When the instructions are executed on an implementation device for receiving and sending Ethernet messages of any length, the implementation device for receiving and sending Ethernet messages of any length executes the method described in the first aspect and any possible implementation of the first aspect.
[0021] In a sixth aspect, the present application provides a computer program product comprising instructions. When the computer program product is run on an implementation device for receiving and sending Ethernet messages of any length, the implementation device for receiving and sending Ethernet messages of any length executes the method described in the first aspect and any possible implementation of the first aspect.
[0022] This application provides a method and device for transmitting and receiving Ethernet messages of arbitrary length, enabling the transmission of data messages of arbitrary length and bidirectional conversion between data messages of arbitrary length and standard format messages. When necessary, data messages of arbitrary length can be converted into standard format for accurate processing. Based on this, data messages of arbitrary length can be accurately processed and reliably forwarded, including the identification and transmission of ultra-short frames and the caching and processing of ultra-long frames, ensuring data integrity and accuracy.
[0023] It should be understood that the description of technical features, technical solutions, beneficial effects or similar language in this application does not imply that all features and advantages can be realized in any single embodiment. On the contrary, it is understood that the description of a feature or beneficial effect means that a specific technical feature, technical solution or beneficial effect is included in at least one embodiment. Therefore, the description of a technical feature, technical solution or beneficial effect in this specification does not necessarily refer to the same embodiment. Furthermore, the technical features, technical solutions and beneficial effects described in the present embodiment can also be combined in any appropriate manner. Those skilled in the art will understand that the embodiment can be implemented without one or more specific technical features, technical solutions or beneficial effects of a specific embodiment. In other embodiments, additional technical features and beneficial effects can also be identified in specific embodiments that do not embody all embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 A system architecture diagram of a data transmission system provided in an embodiment of the present application;
[0025] Figure 2 A logical timing diagram of the FPGA and MAC IP connection provided in an embodiment of the present application;
[0026] Figure 3 A flowchart of a method for transmitting and receiving Ethernet messages of arbitrary length provided in an embodiment of the present application;
[0027] Figure 4 A flowchart of another method for transmitting and receiving Ethernet messages of arbitrary length provided in an embodiment of the present application;
[0028] Figure 5 A flowchart of another method for transmitting and receiving Ethernet messages of arbitrary length provided in an embodiment of the present application;
[0029] Figure 6 A flowchart of another method for transmitting and receiving Ethernet messages of arbitrary length provided in an embodiment of the present application;
[0030] Figure 7 A flowchart of another method for transmitting and receiving Ethernet messages of arbitrary length provided in an embodiment of the present application;
[0031] Figure 8 A flowchart of another method for transmitting and receiving Ethernet messages of arbitrary length provided in an embodiment of the present application;
[0032] Figure 9 A flowchart of another method for transmitting and receiving Ethernet messages of arbitrary length provided in an embodiment of the present application;
[0033] Figure 10 A flowchart of another method for transmitting and receiving Ethernet messages of arbitrary length provided in an embodiment of the present application;
[0034] Figure 11 A flowchart of another method for transmitting and receiving Ethernet messages of arbitrary length provided in an embodiment of the present application;
[0035] Figure 12 A functional block diagram of data processing at the sending end provided in an embodiment of the present application;
[0036] Figure 13 A simulation diagram of data processing function of a sending end provided in an embodiment of the present application;
[0037] Figure 14 A functional block diagram of data processing at a receiving end provided in an embodiment of the present application;
[0038] Figure 15 A simulation diagram of the data processing function of the receiving end provided in an embodiment of the present application;
[0039] Figure 16 A schematic structural diagram of a message transmission device provided in an embodiment of the present application;
[0040] Figure 17 A schematic diagram of the hardware structure of a message transmission device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0041] In the description of this application, unless otherwise specified, " / " means "or", for example, A / B can mean A or B. "And / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, "at least one" means one or more, and "a plurality" means two or more. Words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not limit them to be necessarily different.
[0042] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.
[0043] The implementation method for sending and receiving Ethernet messages of arbitrary length provided in the embodiment of the present application can be applied to the data transmission system 100, such as Figure 1 As shown, the data transmission system 100 includes: an interface bus 101 and a data processing and forwarding logic module 102 .
[0044] The data processing and forwarding logic module 102 includes a sending end 103 and a receiving end 104 .
[0045] Optionally, the interface bus 101 is a standard field programmable gate array (FPGA) media access control (MAC) internet protocol (IP) AXIS interface bus.
[0046] The transmitter 102 and receiver 103 are respectively configured to receive and transmit Ethernet messages in a custom frame format. This frame format is not restricted by the length rules of traditional Ethernet frames and can transmit data of any length. The custom frame format includes necessary control information fields, and can encapsulate messages of any length, whether they are 1 bit (less than 1 byte is counted as 1 byte) or longer.
[0047] Optionally, as shown in Table 1, the control information fields of the custom frame format include: start of frame (sop), end of frame (eop), data (data), and data length (len).
[0048] Table 1 Custom frame format
[0049] definition meaning length sop A frame of data begins 1 bit eop End of a frame of data 1 bit data One frame data content N bytes (N is related to the selected FPGA chip resources) len One frame data length N bytes (less than 1 byte is counted as 1 byte)
[0050] The embodiment of the present application provides a method for transmitting and receiving Ethernet messages of arbitrary lengths, which can call a MAC IP core inside an FPGA, wherein the MAC IP core has an AXIS bus interface, and adapt the custom frame format to the AXIS bus by programming the FPGA.
[0051] Among them, the FPGA and MAC IP docking logic timing diagram is as follows Figure 2 The signal definition is shown in Table 2.
[0052] Table 2 FPGA and MAC IP docking logic signal definition
[0053]
[0054] In some implementations, when sending data, the data processing and forwarding logic module 102 can encapsulate an Ethernet message of any length in a custom frame format, fill the data into the data part, and fill the length information into the len part, and then convert it into a data format that complies with the AXIS bus protocol through the sending end processing logic in the data processing and forwarding logic, and then transmit it to the MAC IP core via the AXIS bus, and the MAC IP core sends the data to the Ethernet physical layer.
[0055] In some implementations, when the data processing and forwarding logic module 102 receives data, the Ethernet data received by the MAC IP core is transmitted to the FPGA via the AXIS bus. The FPGA then parses the AXIS bus data and restores it to the custom frame format through the receiving end processing logic in the data processing and forwarding logic, thereby obtaining the transmitted Ethernet message of any length.
[0056] In some implementations, the data processing and forwarding logic module 102 may also perform necessary verification and modification operations on the Ethernet message to meet different testing requirements.
[0057] In order to solve the technical problem that the existing technology cannot process and forward ultra-short or ultra-long messages, an embodiment of the present application provides a method for transmitting and receiving Ethernet messages of arbitrary length, the method comprising: receiving a data message of a first format; storing the data in the data message based on the control information field in the data message; converting the data in the data message into a data message of a second format; of the first format and the second format, one is a custom frame format and the other is a standard format that complies with the transmission protocol; the data message in the custom frame format is used to transmit data of arbitrary length. Based on this, the transmission of data messages of arbitrary length and the two-way conversion between data messages of arbitrary length and standard format messages can be realized, and when necessary, data messages of arbitrary length can be converted into standard format for accurate processing. Based on this, data messages of arbitrary length can be accurately processed and reliably forwarded, including the identification and transmission of ultra-short frames, the caching and processing of ultra-long frames, etc., to ensure the integrity and accuracy of the data.
[0058] like Figure 3 As shown, the implementation method for sending and receiving Ethernet messages of arbitrary length provided in the embodiment of the present application includes:
[0059] S301: Receive a data message in a first format.
[0060] In some implementations, when Ethernet message testing is required, the transmitting end of the data processing and forwarding logic module needs to convert data messages of any length into a standard format required by the bus protocol. In this case, the first format is a custom frame format. The custom frame format is used to transmit data messages of any length.
[0061] In other implementations, after the test is completed, the receiving end of the data processing and forwarding logic module needs to convert the standard format into a data message of any length for transmission. In this case, the first format is the standard format.
[0062] S302: Store data in the data message based on the control information field in the data message.
[0063] In some implementations, the control information field of the custom frame format includes: a type identification field and a frame length indication field. As shown in Table 1, the type identification field includes: a sop field and an eop field, and the frame length indication field is a len field.
[0064] In some implementations, the control information field in the standard format includes a type identification field. As shown in Table 2, the type identification field includes a tx_tvalid field and a tx_tlast field.
[0065] S303: Convert the data in the data message into a data message in a second format.
[0066] Among them, one of the first format and the second format is a custom frame format, and the other is a standard format that complies with the transmission protocol.
[0067] Based on the above technical solution, the method for transmitting and receiving Ethernet messages of arbitrary length provided by this application can realize the transmission of data messages of arbitrary length and the bidirectional conversion between data messages of arbitrary length and standard format messages. When necessary, data messages of arbitrary length can be converted into standard format for accurate processing. Based on this, data messages of arbitrary length can be accurately processed and reliably forwarded, including the identification and transmission of ultra-short frames and the caching and processing of ultra-long frames, thus ensuring the integrity and accuracy of the data.
[0068] In one possible implementation, combining Figure 3 ,like Figure 4 As shown, when the first format is a custom frame format and the second format is a standard format, the above S302 can be specifically implemented through the following S401, which is specifically described below:
[0069] S401. After receiving a data message containing a type identification field for identifying the start of data, store data corresponding to the length identified by the frame length indication field in the data message until receiving a data message containing a type identification field for identifying the end of data.
[0070] In some implementations, after receiving tx_sop, the tx_data message and length tx_len information are stored. tx_sop and tx_eop information are also saved, and storage stops when tx_eop is received.
[0071] Based on the above technical solution, it is possible to accurately obtain valid data in the Ethernet message according to the frame length indication field in the custom frame format, which facilitates subsequent data processing.
[0072] In one possible implementation, combining Figure 4 ,like Figure 5 As shown, the above S303 can be specifically implemented through the following S501, which is specifically described below:
[0073] S501 : According to the standard transmission bit width required by the standard format, segmented data of corresponding length is taken from pre-stored data for encapsulation to obtain at least one data message in a standard format.
[0074] In some implementations, after a frame of information is stored, data is taken from the pre-stored data, converted into AXIS data, and then sent. Data of corresponding length is taken according to the width of the AXIS bus until all data of tx_len length is taken out and sent.
[0075] Based on the above technical solution, the integrity and accuracy of data can be ensured through a reasonable caching and segmentation processing mechanism for overlong frames.
[0076] In a possible implementation of the embodiment of the present application, combined with Figure 5 ,like Figure 6 As shown, the above S501 can be specifically implemented through the following S601 to S602, which are specifically described below:
[0077] S601: Calculate the number of segments N according to the standard transmission bit width and the data length of the data in the data message.
[0078] The calculation formula is:
[0079] intN=a%b==0? a / b:a / b+1;
[0080] N is segmented transmission; a is the data length; b is the standard transmission bit width.
[0081] S602: Add a standard protocol header to each segmented data segment to mark the valid data range, and set an end flag on the last data segment to obtain at least one data message in a standard format.
[0082] In some implementations, the tx_tvalid signal is sent when transmitting and is valid throughout the transmission process, and the tx_tlast signal is output only when the last frame is transmitted.
[0083] Based on the above technical solution, the received and sent Ethernet messages can be accurately processed according to the frame length indication field in the custom frame format, and the segmented forwarding of overlong frames can be achieved.
[0084] In a possible implementation of the embodiment of the present application, combined with Figure 6 ,like Figure 7 As shown, the above method further includes S701 to S703, which are described in detail below:
[0085] S701: Determine the optimal transmission bit width based on the network load parameters monitored in real time.
[0086] Among them, the network load parameters include: throughput, latency, and bit error rate.
[0087] In some implementations, the current network status score S = f(throughput, latency, bit error rate) is calculated based on the load parameters, and then S is compared with a preset threshold range to dynamically select the optimal transmission bit width. Among them, the calculation formula for the network status score is:
[0088] S = α(throughput / maximum theoretical throughput) + β(1 - latency / maximum allowable latency) + γ(1 - bit error rate / maximum tolerable bit error rate);
[0089] Among them, α + β + γ = 1, and α, β, γ ∈ (0, 1).
[0090] In some implementations, the bit width selection strategy includes: selecting the maximum supported bit width when S > 0.8; selecting a medium bit width (50 - 75% of the maximum bit width) when 0.5 < S ≤ 0.8; selecting the minimum bit width (≤ 30% of the maximum bit width) when S ≤ 0.5; introducing a hysteresis threshold when switching between adjacent intervals to prevent frequent oscillations.
[0091] S702. Switch the standard transmission bit width to the optimal transmission bit width.
[0092] In some implementations, the bit width switching process includes: the sender sends a bit width change request through the control channel; the receiver returns a ready response; both parties synchronously switch the bit width within the agreed time window.
[0093] S703. Send a test message to verify the optimal standard transmission bit width, and switch back to the standard transmission bit width if the verification fails.
[0094] In some implementations, after switching, send a test data packet to verify the link stability; if the verification fails, automatically fallback to the previous valid bit width.
[0095] Based on the above technical solutions, dynamic optimization of throughput can be achieved. In high - load scenarios, when it is detected that the network bandwidth utilization rate is high, automatically switch to a higher bit width, and the measured throughput is improved. In low - load scenarios, reduce the bit width during idle periods, reduce protocol overhead, and increase the proportion of the effective payload of a single link.
[0096] In a possible implementation manner of the embodiment of the present application, in combination with Figure 5 , as Figure 8 shown, when the first format is the standard format and the second format is the custom frame format, the above S302 can be specifically implemented through the following S801, and the following is a specific description:
[0097] S801. After receiving a data message containing a type identification field for identifying the start of data, store the data in the data message until receiving a data message containing a type identification field for identifying the end of data.
[0098] In some implementations, after AXIS receives a frame of valid data, it generates the rx_sop and rx_eop signals based on the combination of the rx_tvalid and rx_tlast signals. The first rising edge of rx_tvalid corresponds to rx_sop, and the simultaneous occurrence of rx_tlast and rx_tvalid corresponds to the rx_eop signal. The received data (rx_tdata) is stored sequentially, and the corresponding rx_tkeep, rx_sop, and rx_eop signals are also stored.
[0099] Based on the above technical solution, it is possible to completely obtain valid data in the Ethernet message from the segmented transmitted message, which facilitates subsequent data transmission.
[0100] In a possible implementation of the embodiment of the present application, combined with Figure 8 ,like Figure 9 As shown, the above S303 can be specifically implemented through the following S901, which is specifically described below:
[0101] S901. Encapsulate data in at least one data message received between a data message containing a type identification field for identifying the start of data and a data message containing a type identification field for identifying the end of data to obtain a data message in a custom frame format.
[0102] The frame length indication field of the data message is the sum of the data lengths of at least one data message received between the data message containing the type identification field for identifying the start of data and the data message containing the type identification field for identifying the end of data.
[0103] In some implementations, the value of rx_len is accumulated from the rx_tkeep information in at least one frame of valid data received by AXIS.
[0104] Based on the above technical solution, the control information field of the custom frame format can be determined according to the received standard format message, thereby realizing bidirectional conversion between data messages of any length and standard format messages.
[0105] In a possible implementation of the embodiment of the present application, combined with Figure 3 ,like Figure 10 As shown, the method for storing data in the data message in the above S302 can be specifically implemented through the following S1001 to S1003, which are specifically described below:
[0106] S1001. Monitor the capacity of the cache area in real time.
[0107] In some implementations, the buffer area may be a storage area of a first in first out (FIFO) data buffer.
[0108] In some implementations, the state of the buffer area can be monitored in real time through a state machine. The state machine includes the following states: idle state (waiting for read and write enable signals), parallel operation state (simultaneous double-buffered reading and writing), switch preparation state (pausing new data writing and completing current data transmission), role swap state (updating buffer identifiers and pointer initial values), and error recovery state (handling data overflow or synchronization anomalies).
[0109] S1002: When the capacity of the buffer area is greater than the data length of the data message, the data in the data message is stored at the tail of the queue of the buffer area.
[0110] In some implementations, the cache area includes two physically isolated master buffers and slave buffers.
[0111] S1003: When the capacity of the buffer area is smaller than the data length of the data message, suspend receiving the message until the capacity of the buffer area is larger than the data length of the data message, and continue storing the data in the data message.
[0112] Based on the above technical solution, continuous data streams can be cached to prevent data loss during machine access and storage operations, while avoiding frequent bus operations and reducing the burden on the CPU.
[0113] In a possible implementation of the embodiment of the present application, combined with Figure 10 ,like Figure 11 As shown, the above method further includes S1101 to S1102, which are described in detail below:
[0114] S1101, receiving data through the main buffer, and reading the stored data from the buffer.
[0115] S1102: When the primary buffer is full or the secondary buffer is empty, the roles of the two buffers are swapped.
[0116] In some implementations, the conditions for swapping the roles of the two buffers include at least one of the following: the amount of data written to the main buffer reaches 80%-95% of its capacity; the amount of data read from the slave buffer reaches 90%-100% of its capacity; an external forced switching signal is received; and it is detected that the difference in read and write rates exceeds a threshold for N consecutive clock cycles.
[0117] In some implementations, a pointer ring management mechanism may be used to implement circular reuse of the buffer.
[0118] Based on the above technical solution, the double buffer can achieve continuous data transmission through two alternating buffers (master buffer and slave buffer). When one buffer is transmitting, the other buffer can be filled or read, thereby reducing the CPU waiting time and improving real-time performance.
[0119] In an exemplary illustration, Figure 12 As shown in the transmitter data processing function block diagram, after the transmitter receives tx_sop, it stores the tx_data message and length tx_len information in the FIFO if the FIFO is not almost full. If the FIFO is almost full, it waits; at the same time, it saves tx_sop and tx_eop information, and stops storing when tx_eop is received.
[0120] When a frame of information is stored and the FIFO is not empty, data is taken from the FIFO for AXIS data conversion and then sent. Data of corresponding length is taken from the FIFO according to the width of the AXIS bus until all data of tx_len length are taken out and sent. The tx_tvalid signal is sent during sending and is valid during the entire transmission process. The tx_tlast signal is output only when the last frame is sent. The tx_tkeep information is the valid data value of the AXIS bus bit width when the non-last frame is transmitted, and it is the remaining valid bytes in the last frame.
[0121] The data processing function simulation of the sending end is as follows: Figure 13 As shown in the figure, a 1-bit ultra-short frame is used as an example. Other cases are similar. The transmitted frame is less than 1 byte, so the transmission unit is 1 byte. Because it is an ultra-short frame, tx_sop and tx_eop are issued simultaneously during transmission. The data tx_data is 0x1, and the length tx_len is 0x1. After data processing, it is sent to the AXIS bus. Since the length of an AXIS bus transmission frame is 256 bytes, the tx_tkeep information is 0x1 to indicate that the valid data transmitted is 1 byte in length. tx_tdata is the transmitted data. tx_tlast and tx_tvalid are both valid to indicate that the transmission is an ultra-short frame.
[0122] In yet another exemplary illustration, Figure 14As shown in the receiving end data processing function block diagram, after the receiving end receives a frame of valid data on AXIS, it generates rx_sop and rx_eop signals according to the combination of rx_tvalid and rx_tlast signals. The first rising edge of rx_tvalid corresponds to rx_sop, and when rx_tlast and rx_tvalid appear at the same time, it corresponds to the rx_eop signal. The received data rx_tdata is stored in the FIFO in sequence, and the corresponding rx_tkeep, rx_sop and rx_eop are also stored in the FIFO. The accumulated rx_tkeep information is the value of rx_len. Finally, the data in the FIFO is taken out for processing.
[0123] The data processing function simulation at the receiving end is as follows Figure 15 As shown in the figure, taking the ultra-short frame 1-bit transmission as an example, other situations are similar. The rx_tdata received by the AXIS bus is 0x1, the received rx_tkeep is 0x1, and rx_tvalid and rx_tlast are received at the same time, indicating that it is an ultra-short frame. The sop signal is generated by delaying the first rx_tvalid by 2 cycles, and the eop signal data is generated synchronously after receiving rx_tlast. Finally, the converted rx_tdata has a data value of 0x1 and a rx_len length of 0x1. After data processing at the receiving end, the correct transmitted data is obtained.
[0124] In combination with the above exemplary solutions, the embodiments of the present application have the following effects:
[0125] Breaking through the frame length limitation: The embodiment of the present application breaks the limitation of traditional Ethernet testers on frame length, realizes Ethernet message forwarding with a minimum of 1 bit and a theoretical maximum of infinity, and can meet the testing requirements in various special scenarios, such as ultra-short data transmission testing of IoT devices and ultra-long data message transmission testing of data centers, etc., greatly expanding the application scope of Ethernet testers.
[0126] Improved test flexibility and accuracy: By supporting Ethernet packets of any length, the tester can more flexibly simulate various network data transmission scenarios, providing more accurate test results. Whether it's precise measurement of ultra-short frames or performance evaluation of ultra-long frames, both can be effectively accomplished, providing reliable data support for performance optimization of network devices and systems.
[0127] Reduced testing costs and complexity: Traditional testing methods may require the use of multiple different test devices or complex test configurations to meet different frame length requirements. However, the Ethernet tester of this invention supports any frame length, reducing reliance on multiple test devices and lowering testing costs. It also simplifies the test process and configuration, improving test efficiency and reducing test complexity.
[0128] The above mainly introduces the scheme of the embodiment of the present application from the perspective of device implementation. It can be understood that each device, for example, the implementation device for receiving and sending Ethernet messages of arbitrary length, includes at least one of the hardware structure and software modules corresponding to the execution of each function in order to realize the above functions. It should be easy for those skilled in the art to realize that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.
[0129] The embodiment of the present application can divide the functional units of the implementation device for receiving and transmitting Ethernet messages of arbitrary length according to the above method example. For example, each functional unit can be divided according to each function, or two or more functions can be integrated into one processing unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. It should be noted that the division of units in the embodiment of the present application is schematic and is only a logical functional division. In actual implementation, there may be other division methods.
[0130] In the case of an integrated unit, Figure 16 A possible structural diagram of an implementation device for receiving and sending Ethernet messages of arbitrary length involved in the above embodiment (referred to as message transmission device 1600) is shown. The message transmission device 1600 includes a processing unit 1601 and a communication unit 1602, and may also include a storage unit 1603. Figure 16 The structural diagram shown can be used to illustrate the structure of the device for implementing the reception and transmission of Ethernet messages of arbitrary length involved in the above embodiments.
[0131] when Figure 16The structural schematic diagram shown is used to illustrate the structure of the implementation device for sending and receiving Ethernet messages of arbitrary length involved in the above-mentioned embodiment. The processing unit 1601 is used to control and manage the actions of the implementation device for sending and receiving Ethernet messages of arbitrary length, the communication unit 1602 is used for the implementation device for sending and receiving Ethernet messages of arbitrary length to communicate with other devices, and the storage unit 1603 is used to store program code and data of the implementation device for sending and receiving Ethernet messages of arbitrary length.
[0132] For example, the communication unit 1602, the processing unit 1601, and the storage unit 1603;
[0133] Communication unit 1602, used for data messages in a first format;
[0134] The storage unit 1603 is configured to store data in the data message based on the control information field in the data message;
[0135] Processing unit 1601 is used to convert the data in the data message into a data message in a second format; of the first format and the second format, one is a custom frame format and the other is a standard format that complies with the transmission protocol; the data message in the custom frame format is used to transmit data of any length.
[0136] In one possible implementation, the control information field of the custom frame format includes: a type identification field and a frame length indication field; when the first format is a custom frame format and the second format is a standard format, the storage unit 1603 is specifically used to store data corresponding to the length identified by the frame length indication field in the data message after receiving a data message containing a type identification field for identifying the beginning of data, until a data message containing a type identification field for identifying the end of data is received.
[0137] In a possible implementation, the processing unit 1601 is specifically configured to encapsulate segmented data of corresponding length from pre-stored data according to a standard transmission bit width required by the standard format, to obtain at least one data message in a standard format.
[0138] In one possible implementation, the processing unit 1601 is specifically configured to calculate the number of segments N according to the standard transmission bit width and the data length of the data in the data message; the calculation formula is:
[0139] intN=a%b==0? a / b:a / b+1;
[0140] N is the segmented output; a is the data length; b is the standard transmission bit width; a standard protocol header is added to each data segment after segmentation to mark the valid data range, and an end flag is set in the last data segment to obtain at least one data message in a standard format.
[0141] In one possible implementation, the processing unit 1601 is further used to determine the optimal transmission bit width based on the network load parameters monitored in real time; switch the standard transmission bit width to the optimal transmission bit width; send a test message to verify the optimal standard transmission bit width, and switch back to the standard transmission bit width if the verification fails.
[0142] In one possible implementation, the control information field of the standard format includes: a type identification field; when the first format is the standard format and the second format is the custom frame format, the storage unit 1603 is specifically used to store the data in the data message after receiving a data message containing a type identification field for identifying the beginning of the data until a data message containing a type identification field for identifying the end of the data is received.
[0143] In one possible implementation, the processing unit 1601 is specifically used to encapsulate data in at least one data message received between a data message containing a type identification field for identifying the start of data and a data message containing a type identification field for identifying the end of data, to obtain a data message with a custom frame format; the frame length indication field of the data message is the sum of the data lengths in at least one data message received between a data message containing a type identification field for identifying the start of data and a data message containing a type identification field for identifying the end of data.
[0144] In one possible implementation, the storage unit 1603 is specifically used to monitor the capacity of the cache area in real time; when the capacity of the cache area is greater than the data length of the data message, the data in the data message is stored at the tail of the queue of the cache area; when the capacity of the cache area is less than the data length of the data message, the reception of the message is suspended until the capacity of the cache area is greater than the data length of the data message, and the data in the data message continues to be stored.
[0145] In one possible implementation, the cache area includes: two physically isolated primary buffers and secondary buffers; a storage unit 1603 is also used to receive data through the primary buffer and read stored data through the secondary buffer; when the primary buffer is full or the secondary buffer is empty, the roles of the two buffers are exchanged.
[0146] Among them, the processing unit 1601 can be a processor or a controller, and the communication unit 1602 can be a communication interface, a transceiver, a transceiver, a transceiver circuit, a transceiver device, etc. Among them, the communication interface is a general term and can include one or more interfaces. The storage unit 1603 can be a memory. When the message transmission device 1600 is a chip, the processing unit 1601 can be a processor or a controller, and the communication unit 1602 can be an input interface and / or output interface, a pin or a circuit, etc. The storage unit 1603 can be a storage unit within the chip (for example, a register, a cache, etc.), or it can be a storage unit located outside the chip (for example, a read-only memory (ROM), a random access memory (RAM), etc.).
[0147] Among them, the communication unit can also be called a transceiver unit. The antenna and control circuit with transceiver functions in the message transmission device 1600 can be regarded as the communication unit 1602 of the message transmission device 1600, and the processor with processing function can be regarded as the processing unit 1601 of the message transmission device 1600. Optionally, the device used to implement the receiving function in the communication unit 1602 can be regarded as a communication unit, and the communication unit is used to perform the receiving steps in the embodiment of the present application. The communication unit can be a receiver, a receiver, a receiving circuit, etc. The device used to implement the sending function in the communication unit 1602 can be regarded as a sending unit, and the sending unit is used to perform the sending steps in the embodiment of the present application. The sending unit can be a transmitter, a transmitter, a sending circuit, etc.
[0148] Figure 16 If the integrated units are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the method described in each embodiment of the present application. The storage medium for storing computer software products includes various media that can store program codes, such as USB flash drives, mobile hard drives, read-only memories, random access memories, magnetic disks or optical disks.
[0149] Figure 16 A unit in a can also be called a module, for example, a processing unit can be called a processing module.
[0150] The embodiment of the present application also provides a hardware structure diagram of a device for transmitting and receiving Ethernet messages of arbitrary length (denoted as message transmission device 1700), see Figure 17 The message transmission device 1700 includes a processor 1701 and, optionally, a memory 1702 connected to the processor 1701 .
[0151] In the first possible implementation, see Figure 17 , the message transmission device 1700 also includes a transceiver 1703. The processor 1701, the memory 1702, and the transceiver 1703 are connected via a bus. The transceiver 1703 is used to communicate with other devices or a communication network. Optionally, the transceiver 1703 may include a transmitter and a receiver. The device used to implement the receiving function in the transceiver 1703 can be regarded as a receiver, and the receiver is used to perform the receiving step in the embodiment of the present application. The device used to implement the sending function in the transceiver 1703 can be regarded as a transmitter, and the transmitter is used to perform the sending step in the embodiment of the present application.
[0152] Based on the first possible implementation, Figure 17 The structural diagram shown can be used to illustrate the structure of the device for implementing the reception and transmission of Ethernet messages of arbitrary length involved in the above embodiments.
[0153] in, Figure 17 The system chip in the device for transmitting and receiving Ethernet messages of arbitrary lengths may also be illustrated. In this case, the actions performed by the device for transmitting and receiving Ethernet messages of arbitrary lengths may be performed by the system chip. The specific actions performed may be referred to above and will not be described in detail here.
[0154] During implementation, each step of the method provided in this embodiment can be completed by hardware integrated logic circuits in a processor or by software instructions. The steps of the method disclosed in the embodiments of this application can be directly implemented as execution by a hardware processor, or as a combination of hardware and software modules in a processor.
[0155] The processor in this application may include, but is not limited to, at least one of the following: a central processing unit (CPU), a microprocessor, a digital signal processor (DSP), a microcontroller unit (MCU), or an artificial intelligence processor, and other types of computing devices that run software. Each computing device may include one or more cores for executing software instructions to perform operations or processing. The processor may be a separate semiconductor chip, or it may be integrated into a semiconductor chip together with other circuits. For example, it may form an SoC (system on a chip) with other circuits (such as a codec circuit, a hardware acceleration circuit, or various bus and interface circuits), or it may be integrated into the ASIC as a built-in processor of the ASIC. The ASIC with the integrated processor may be packaged separately or together with other circuits. In addition to the core for executing software instructions to perform operations or processing, the processor may further include necessary hardware accelerators, such as a field programmable gate array (FPGA), a PLD (programmable logic device), or a logic circuit that implements dedicated logic operations.
[0156] The memory in the embodiments of the present application may include at least one of the following types: read-only memory (ROM) or other types of static storage devices that can store static information and instructions, random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or electrically erasable programmable read-only memory (EEPROM). In some scenarios, the memory may also be a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited to this.
[0157] An embodiment of the present application also provides a computer-readable storage medium, comprising instructions, which, when executed on a computer, enables the computer to execute any of the above methods.
[0158] An embodiment of the present application also provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute any of the above methods.
[0159] An embodiment of the present application also provides a chip, which includes a processor and an interface circuit, the interface circuit is coupled to the processor, the processor is used to run a computer program or instruction to implement the above method, and the interface circuit is used to communicate with other modules outside the chip.
[0160] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more media that can be integrated. The available media may be magnetic media (eg, floppy disks, hard disks, magnetic tapes), optical media (eg, DVDs), or semiconductor media (eg, solid state disks (SSDs)).
[0161] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the claimed application, those skilled in the art may understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.
[0162] Although the present application has been described with reference to specific features and embodiments thereof, it is apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present application. Accordingly, this specification and the drawings are merely illustrative of the present application as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present application. Obviously, those skilled in the art may make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, the present application is intended to include such modifications and variations as fall within the scope of the claims of the present application and their equivalents.
Claims
1. A method for transmitting and receiving Ethernet messages of arbitrary length, characterized in that: include: receiving a data message in a first format; storing data in the data message based on a control information field in the data message; The data in the data message is converted into a data message in a second format; of the first format and the second format, one is a custom frame format and the other is a standard format that complies with the transmission protocol; the data message in the custom frame format is used to transmit data of any length.
2. The method according to claim 1, characterized in that The control information field of the custom frame format includes: a type identification field and a frame length indication field; when the first format is the custom frame format and the second format is the standard format, storing the data in the data message based on the control information field in the data message includes: After receiving a data message containing a type identification field for identifying the start of data, data corresponding to the length identified by the frame length indication field in the data message is stored until a data message containing a type identification field for identifying the end of data is received.
3. The method according to claim 2, characterized in that The converting the data in the data message into a data message in a second format includes: According to the standard transmission bit width required by the standard format, segmented data of corresponding length is taken from the pre-stored data and encapsulated to obtain at least one data message in the standard format.
4. The method according to claim 3, characterized in that The step of encapsulating segmented data of corresponding length from the pre-stored data according to the standard transmission bit width required by the standard format to obtain at least one data message in the standard format includes: The number of segments N is calculated based on the standard transmission bit width and the data length of the data in the data message; the calculation formula is: intN=a%b==0? a / b:a / b+1; N is the segmented output; a is the data length; b is the standard transmission bit width; A standard protocol header is added to each segmented data segment to mark the valid data range, and an end mark is set in the last data segment to obtain at least one data message in the standard format.
5. The method according to claim 4, characterized in that Also includes: Determine the optimal transmission bit width based on the network load parameters monitored in real time; Switching the standard transmission bit width to the optimal transmission bit width; Send a test message to verify the optimal standard transmission bit width, and switch back to the standard transmission bit width if the verification fails.
6. The method according to claim 3, characterized in that The control information field of the standard format includes: the type identification field; when the first format is the standard format and the second format is the custom frame format, storing the data in the data message based on the control information field in the data message includes: After receiving a data message containing a type identification field for identifying the start of data, the data in the data message is stored until a data message containing a type identification field for identifying the end of data is received.
7. The method according to claim 6, characterized in that The converting the data in the data message into a data message in a second format includes: The data in at least one data message received between a data message containing a type identification field for identifying the start of data and a data message containing a type identification field for identifying the end of data are encapsulated to obtain a data message with the custom frame format; the frame length indication field of the data message is the sum of the data lengths in at least one data message received between a data message containing a type identification field for identifying the start of data and a data message containing a type identification field for identifying the end of data.
8. The method according to any one of claims 1 to 7, characterized in that The storing of the data in the data message includes: Real-time monitoring of the cache capacity; When the capacity of the buffer area is greater than the data length of the data message, storing the data in the data message to the tail of the queue of the buffer area; When the capacity of the buffer area is smaller than the data length of the data message, reception of the message is suspended until the capacity of the buffer area is larger than the data length of the data message, and then the data in the data message is continued to be stored.
9. The method according to claim 8, characterized in that The cache area includes: two physically isolated master buffers and slave buffers; the method further includes: receiving data through the primary buffer and reading stored data through the secondary buffer; When the primary buffer is full or the secondary buffer is empty, the roles of the two buffers are swapped.
10. A device for transmitting and receiving Ethernet messages of arbitrary length, characterized in that: The device includes: a communication unit, a storage unit and a processing unit; The communication unit is configured to receive a data message in a first format; The storage unit is configured to store the data in the data message based on the control information field in the data message; The processing unit is used to convert the data in the data message into a data message in a second format; of the first format and the second format, one is a custom frame format and the other is a standard format that complies with the transmission protocol; the data message in the custom frame format is used to transmit data of any length.