Display device

Abstract

The present disclosure relates to a display device, and more particularly, to a display device and a method for manufacturing the same, which can reduce or minimize an interfacial peeling phenomenon between a cover layer and a substrate and can block a permeation path of outside air and moisture. The display device includes: a substrate; an intermediate layer on the substrate and including a first electrode, a light emitting layer on the first electrode, a second electrode on the light emitting layer, and a fill layer on the second electrode; and a cover layer on the intermediate layer, where the cover layer is on a top surface of the intermediate layer, a side surface of the intermediate layer, and a side surface of the substrate.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0040181 filed on March 25, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a display device, and more particularly, to a display device and a method for manufacturing the display device. Background Art

[0003] A head-mounted display (HMD) is a device worn on the user's head in the form of glasses or a helmet, with an image display focused at a close distance in front of the user's eyes. A head-mounted display can implement virtual reality (VR) or augmented reality (AR).

[0004] Head-mounted displays (HMDs) use multiple lenses to magnify an image displayed on a small display device and then display the magnified image. Therefore, HMD display devices must provide high-resolution images, for example, images with a resolution of 3,000 pixels per inch (PPI) or higher. To this end, organic light-emitting diodes on silicon (OLEDoS), which are small, high-resolution organic light-emitting display devices, are used as HMD display devices. OLEDoS is an image display device in which organic light-emitting diodes (OLEDs) are provided on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is provided. Summary of the Invention

[0005] Aspects and features of embodiments of the present disclosure provide a display device and a method for manufacturing the display device that can reduce or minimize an interface peeling phenomenon between a cover layer and a substrate and can block a permeation path of external air and moisture.

[0006] According to one or more embodiments of the present disclosure, a display device includes: a substrate; an intermediate layer on the substrate and including a first electrode, a light-emitting layer on the first electrode, a second electrode on the light-emitting layer, and a filling layer on the second electrode; and a covering layer on the intermediate layer, wherein the covering layer is on a top surface of the intermediate layer, a side surface of the intermediate layer, and a side surface of the substrate.

[0007] In one or more embodiments, the cover layer is on the fill layer.

[0008] In one or more embodiments, the cover layer includes: a first sub-cover layer on the intermediate layer; and a second sub-cover layer extending from the first sub-cover layer and on a side surface of the intermediate layer and a side surface of the substrate.

[0009] In one or more embodiments, the first sub-cover layer is on the middle layer, and the second sub-cover layer is around a side surface of the middle layer and a side surface of the substrate.

[0010] In one or more embodiments, the second sub-cover layer has an obliquely inclined surface at one end.

[0011] In one or more embodiments, the inclined surface of the second sub-cover layer is on the side surface of the substrate.

[0012] In one or more embodiments, one end of the second sub-cover layer has a carbonized region.

[0013] In one or more embodiments, the cover layer surrounds the side surface of the intermediate layer and the side surface of the substrate.

[0014] In one or more embodiments, the intermediate layer is surrounded by the cover layer and the substrate.

[0015] In one or more embodiments, the substrate has grooves at the edges.

[0016] In one or more embodiments, the groove is around the intermediate layer in plan view.

[0017] In one or more embodiments, the groove has a triangular cross-section.

[0018] In one or more embodiments, a portion of the cover layer is in the groove.

[0019] In one or more embodiments, the groove includes a plurality of grooves, and the lengths of the plurality of grooves increase as the plurality of grooves are positioned closer to the side surface of the substrate.

[0020] In one or more embodiments, a portion of the cover layer is in each of the plurality of grooves.

[0021] In one or more embodiments, the display device further includes a polarizing plate on the intermediate layer.

[0022] According to one or more embodiments of the present disclosure, a display device includes: a substrate; an intermediate layer on the substrate; and a covering layer on the intermediate layer, wherein the intermediate layer includes a light-emitting layer, and the covering layer is on a top surface of the intermediate layer, a side surface of the intermediate layer, and a side surface of the substrate.

[0023] In one or more embodiments, the cover layer surrounds the side surface of the intermediate layer and the side surface of the substrate.

[0024] In one or more embodiments, the intermediate layer is surrounded by the cover layer and the substrate.

[0025] In one or more embodiments, the substrate has grooves at the edges.

[0026] In one or more embodiments, the groove is around the intermediate layer in plan view.

[0027] In one or more embodiments, the groove has a triangular cross-section.

[0028] In one or more embodiments, a portion of the cover layer is in the groove.

[0029] According to one or more embodiments of the present disclosure, a method for manufacturing a display device includes the following steps: forming an intermediate layer including a light-emitting layer on a base substrate; forming a groove at an edge of the base substrate; forming a covering layer on a top surface of the intermediate layer and a side surface of the intermediate layer, the covering layer being inserted into the groove of the base substrate; and removing an edge portion of the base substrate based on the groove to form a substrate, wherein, after removing the edge portion of the base substrate, the covering layer is formed on the top surface of the intermediate layer, the side surface of the intermediate layer, and the side surface of the substrate.

[0030] In one or more embodiments, forming the groove at the edge of the base substrate includes etching the edge of the top surface of the base substrate.

[0031] In one or more embodiments, the step of removing an edge portion of the base substrate based on the groove to form the base includes irradiating a laser beam toward the groove from below the base substrate.

[0032] According to the display device and the method for manufacturing the display device of one or more embodiments, it is possible to reduce or minimize an interface peeling phenomenon between a cover layer and a substrate, and block a permeation path of external air and moisture.

[0033] Effects, aspects, and features according to the embodiments of the present disclosure are not limited to the above-mentioned effects, aspects, and features, and more various effects, aspects, and features are included in the following description of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above and other aspects and features of the embodiments of the present disclosure will become more apparent by describing in detail the embodiments of the present disclosure with reference to the accompanying drawings, in which: Figure 1 is an exploded perspective view showing a display device according to one or more embodiments; Figure 2 is a block diagram illustrating a display device according to one or more embodiments; Figure 3 is an equivalent circuit diagram of a first subpixel according to one or more embodiments; Figure 4 It shows Figure 1 Layout diagram of an example of a display panel shown in ; Figure 5 and Figure 6 is a layout diagram showing pixels of a display area according to one or more embodiments; Figure 7 is a cross-sectional view of a display device according to one or more embodiments; Figure 8 is a perspective view of a display device according to one or more embodiments; Figures 9 to 15 is a process cross-sectional view illustrating a method of manufacturing a display device according to one or more embodiments; Figure 16 is a cross-sectional view of a display device according to one or more embodiments; Figures 17 to 23 is a process cross-sectional view illustrating a method of manufacturing a display device according to one or more embodiments; Figure 24 is a cross-sectional view of a display device according to one or more embodiments; Figure 25 is a perspective view illustrating a head-mounted display according to one or more embodiments; Figure 26 It shows Figure 25 an exploded perspective view of an example of a head-mounted display; and Figure 27 is a perspective view illustrating a head-mounted display according to one or more embodiments. DETAILED DESCRIPTION

[0035] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0036] Throughout this specification, it will be understood that when an element (or region, layer, portion, etc.) is referred to as being “on,” “connected to” or “coupled to” another element, it can be directly connected or coupled to the other element or intervening elements may be provided therebetween.

[0037] The same number or symbol always refers to the same element. In addition, in the drawings, the thickness, ratio and size of the elements are exaggerated in order to effectively describe the technical content. The term "and / or" includes all combinations of one or more combinations that can be defined by the relevant elements.

[0038] Although the terms first, second, etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the spirit and scope of the present disclosure, a first element can be referred to as a second element, and similarly, a second element can also be referred to as a first element. Unless the context clearly indicates otherwise, the singular also includes the plural.

[0039] In addition, terms such as "below", "on the lower side", "above", and "on the upper side" are used to describe the relationship of elements shown in the drawings. These terms have relative concepts and are described based on the directions indicated in the drawings.

[0040] It will be understood that when terms such as “include” or “have” are used herein, they are intended to indicate the presence of the stated features, integers, steps, operations, elements, components or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0041] As used herein, “directly disposed” may mean that there is no added layer, film, region, plate, etc. between a portion such as a layer, film, region, or plate and another portion. For example, “directly disposed” may mean that two layers or two members are disposed without using an additional member such as an adhesive member therebetween.

[0042] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. In addition, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized and / or overly formal sense unless expressly defined as such herein.

[0043] For the purposes of this disclosure, expressions such as “at least one of,” “one of,” and “selected from,” when preceding (after) a list of elements, modify the entire list of elements and do not modify the individual elements in the list. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z, such as XYZ, XYY, XZ, YZ, and ZZ, or any variation thereof. Similarly, expressions such as “at least one of A and B” may include A, B, or A and B. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, expressions such as “A and B” may include A, B, or A and B. In addition, the use of “may” when describing embodiments of the present disclosure refers to “one or more embodiments of the present disclosure.”

[0044] In addition, any numerical range disclosed and / or described herein is intended to include all subranges of the same numerical precision contained within the described range. For example, a range of "1.0 to 10.0" is intended to include all subranges between (and including) the described minimum value of 1.0 and the described maximum value of 10.0, for example, having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as 2.4 to 7.6. Any maximum numerical limit described herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit described in this specification is intended to include all higher numerical limits contained therein. Therefore, the applicant reserves the right to amend this specification (including the claims) to explicitly describe any subranges contained within the ranges explicitly described herein. All such ranges are intended to be inherently described in this specification, so that amendments to explicitly describe any such subranges will meet the requirements.

[0045] It will be understood by those skilled in the art that, in view of the overall content of the present disclosure, each suitable feature of the various embodiments of the present disclosure may be combined in part or in whole or in combination with each other, and may be technically interlocked and operated in various suitable manners, and unless otherwise stated or implied, each embodiment may be implemented independently of each other or in combination with each other in any suitable manner.

[0046] Hereinafter, a display panel and a method of manufacturing the display panel according to one or more embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0047] Figure 1 is an exploded perspective view illustrating a display device according to one or more embodiments. Figure 2 is a block diagram illustrating a display device according to one or more embodiments. Figure 3 is an equivalent circuit diagram of a first subpixel according to one or more embodiments. Figure 4 It shows Figure 1 Layout diagram of an example of a display panel shown in .

[0048] Reference Figure 1 and Figure 2The display device 10 according to one or more embodiments is a device for displaying moving images and / or still images. The display device 10 according to one or more embodiments can be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers, mobile communication terminals, electronic notepads, e-books, portable multimedia players (PMPs), navigation systems, ultra-mobile personal computers (UMPCs), and the like. For example, the display device 10 according to one or more embodiments can be applied as a display unit for a television, a laptop computer, a monitor, a billboard, and / or an Internet of Things (IoT) terminal. Alternatively, the display device 10 according to one or more embodiments can be applied to a smartwatch, a watch phone, a head-mounted display (HMD) for implementing virtual reality and / or augmented reality, and the like.

[0049] The display device 10 according to one or more embodiments includes a display panel 100 , a heat dissipation layer 200 , a circuit board 300 , a driving circuit 400 , and a power supply circuit 500 .

[0050] The display panel 100 may have a planar shape similar to a quadrilateral. For example, the display panel 100 may have a planar shape similar to a quadrilateral having short sides in a first direction DR1 and long sides in a second direction DR2 intersecting the first direction DR1. In the display panel 100, the corner where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be a right angle or rounded with a suitable curvature (e.g., a predetermined curvature). The planar shape of the display panel 100 is not limited to a quadrilateral, and may be a shape similar to another polygonal shape, a circular shape, and / or an elliptical shape. The planar shape of the display device 10 may conform to the planar shape of the display panel 100, but the present disclosure is not limited thereto.

[0051] The display panel 100 includes Figure 2 , there is a display area DAA for displaying an image and a non-display area NDA for not displaying an image.

[0052] The display area DAA includes a plurality of pixels PX, a plurality of scan lines SL, a plurality of emission control lines EL, and a plurality of data lines DL.

[0053] Each of the plurality of pixels PX includes a light-emitting element that emits light. The plurality of pixels PX may be arranged in a matrix along a first direction DR1 and a second direction DR2. For example, the plurality of pixels PX may be arranged along rows and columns of the matrix along the first direction DR1 and the second direction DR2. A plurality of scan lines SL and a plurality of emission control lines EL may extend in the first direction DR1 and be arranged along the second direction DR2. A plurality of data lines DL may extend in the second direction DR2 and be arranged along the first direction DR1.

[0054] The plurality of scan lines SL include a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines EBL. The plurality of emission control lines EL include a plurality of first emission control lines EL1 and a plurality of second emission control lines EL2.

[0055] The plurality of pixels PX include a plurality of sub-pixels SP1, SP2, and SP3. The plurality of sub-pixels SP1, SP2, and SP3 may include Figure 3 The plurality of pixel transistors shown in FIG. 3 and FIG. 4 can be formed by a semiconductor process and disposed on a semiconductor substrate SSUB (see FIG. 3 ). Figure 7 For example, the plurality of pixel transistors may be formed of a complementary metal oxide semiconductor (CMOS).

[0056] Each of the plurality of sub-pixels SP1, SP2, and SP3 can be connected to one write scan line GWL among a plurality of write scan lines GWL, one control scan line GCL among a plurality of control scan lines GCL, one bias scan line EBL among a plurality of bias scan lines EBL, one first emission control line EL1 among a plurality of first emission control lines EL1, one second emission control line EL2 among a plurality of second emission control lines EL2, and one data line DL among a plurality of data lines DL. Each of the plurality of sub-pixels SP1, SP2, and SP3 can receive a data voltage of the data line DL in response to a write scan signal of the write scan line GWL and emit light from the light-emitting element according to the data voltage.

[0057] The non-display area NDA includes a scan driving area, a data driving area, and a pad (also called a “bonding pad” or “bonding pad”) area PDA.

[0058] The scan driving area may be an area in which the scan driver 610 and the emission driver 620 are disposed. Figure 2 , the scan driver 610 is disposed on the left side of the display area DAA and the emission driver 620 is disposed on the right side of the display area DAA, but the present disclosure is not limited thereto. For example, the scan driver 610 and the emission driver 620 may be disposed on both the left and right sides of the display area DAA.

[0059] The scan driver 610 includes a plurality of scan transistors, and the emission driver 620 includes a plurality of light emitting transistors. The plurality of scan transistors and the plurality of light emitting transistors may be formed on a semiconductor substrate SSUB (see FIG. Figure 7 For example, the plurality of scanning transistors and the plurality of light emitting transistors may be formed by CMOS.

[0060] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit (e.g., a timing controller) 410 of the driver circuit 400. The write scan signal output unit 611 may generate write scan signals based on the scan timing control signal SCS from the timing control circuit 410 and sequentially output them to the write scan lines GWL. The control scan signal output unit 612 may generate control scan signals in response to the scan timing control signal SCS and sequentially output them to the control scan lines GCL. The bias scan signal output unit 613 may generate bias scan signals based on the scan timing control signal SCS and sequentially output them to the bias scan lines EBL.

[0061] The emission driver 620 includes a first emission control driver 621 and a second emission control driver 622. Each of the first emission control driver 621 and the second emission control driver 622 can receive an emission timing control signal ECS from the timing control circuit 410. The first emission control driver 621 can generate first emission control signals based on the emission timing control signal ECS and sequentially output them to the first emission control line EL1. The second emission control driver 622 can generate second emission control signals based on the emission timing control signal ECS and sequentially output them to the second emission control line EL2.

[0062] The data driving region may be a region in which the data driver 700 is disposed. The data driver 700 may include a plurality of data transistors, and the plurality of data transistors may be formed on a semiconductor substrate SSUB (see FIG. 1 ) by a semiconductor process. Figure 7 For example, the plurality of data transistors may be formed of CMOS.

[0063] The data driver 700 may receive digital video data DATA and a data timing control signal DCS from the timing control circuit 410. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to the data line DL. In this case, the sub-pixels SP1, SP2, and SP3 are selected by the write scan signal of the scan driver 610, and the data voltage may be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0064] The pad area PDA includes a plurality of pads PD arranged along the first direction DR1. Each of the plurality of pads PD may be exposed without being covered by the cover layer CVL (see FIG. Figure 7 ) and polarizer POL (see Figure 7 )cover.

[0065] The heat dissipation layer 200 may overlap the display panel 100 in a third direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be provided on one surface of the display panel 100, for example, on the rear surface of the display panel 100. The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include a layer (for example, a metal layer) containing a material having high thermal conductivity, such as graphite, silver (Ag), copper (Cu), and / or aluminum (Al).

[0066] The circuit board 300 may be electrically connected to the plurality of first pads PD1 in the pad area PDA of the display panel 100 by using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 may be a flexible printed circuit board (FPCB) and / or a flexible film having a flexible material. Figure 1 Although shown as unfolded in FIG, the circuit board 300 may be bent. In this case, one end of the circuit board 300 may be disposed on the rear surface of the display panel 100. The one end of the circuit board 300 may be an end opposite to the other end of the circuit board 300 connected to the plurality of first pads PD1 of the pad area PDA of the display panel 100 using a conductive adhesive member.

[0067] The timing control circuit 410 can receive digital video data DATA and timing signals input from the outside. In response to the timing signals, the timing control circuit 410 can generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100. The timing control circuit 410 can output the scan timing control signal SCS to the scan driver 610 and the emission timing control signal ECS to the emission driver 620. The timing control circuit 410 can output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0068] The power supply circuit (or power supply unit) 500 can generate a plurality of panel driving voltages according to the power voltage from the outside. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, a reference voltage VREF, and a third driving voltage VINT, and supply them to the display panel 100. Figure 4 A description is provided of the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT.

[0069] Each of the timing control circuit 410 and the power supply circuit 500 of the driving circuit 400 may be formed as an integrated circuit (IC) and attached to one surface of the circuit board 300. The scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing control circuit 410 may be supplied to the display panel 100 through the circuit board 300. The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply circuit 500 may be supplied to the display panel 100 through the circuit board 300.

[0070] Alternatively, similar to the scan driver 610, the emission driver 620, and the data driver 700, the timing control circuit 410 may be provided in a timing circuit region of the non-display area NDA of the display panel 100. In this case, the timing circuit region may be provided between the data driving area and the pad area PDA.

[0071] Figure 3 is an equivalent circuit diagram of a first subpixel according to one or more embodiments.

[0072] Reference Figure 3 , the first subpixel SP1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line EBL, the first emission control line EL1, the second emission control line EL2, and the data line DL. Furthermore, the first subpixel SP1 can be connected to a first drive voltage line VSL to which a first drive voltage VSS corresponding to a low potential voltage is applied, a second drive voltage line VDL to which a second drive voltage VDD corresponding to a high potential voltage is applied, and a third drive voltage line VIL to which a third drive voltage VINT corresponding to an initialization voltage is applied. That is, the first drive voltage line VSL can be a low potential voltage line, the second drive voltage line VDL can be a high potential voltage line, and the third drive voltage line VIL can be an initialization voltage line. In this case, the first drive voltage VSS can be lower than the third drive voltage VINT. The second drive voltage VDD can be higher than the third drive voltage VINT.

[0073] The first subpixel SP1 includes a plurality of transistors T1 to T6 , a light emitting element LE, a first capacitor CP1 , and a second capacitor CP2 .

[0074] The light-emitting element LE emits light in response to a drive current Ids flowing through the channel of the first transistor T1. The amount of light emitted by the light-emitting element LE may be proportional to the drive current Ids. The light-emitting element LE may be disposed between the fourth transistor T4 and the first drive voltage line VSL. A first electrode of the light-emitting element LE may be connected to the drain electrode of the fourth transistor T4, and a second electrode of the light-emitting element LE may be connected to the first drive voltage line VSL. The first electrode of the light-emitting element LE may be an anode electrode, and the second electrode of the light-emitting element LE may be a cathode electrode. The light-emitting element LE may be an organic light-emitting diode (OLED) including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first and second electrodes, but the present disclosure is not limited thereto. For example, the light-emitting element LE may be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first and second electrodes. In this case, the light-emitting element LE may be a micro light-emitting diode.

[0075] The first transistor T1 may be a driving transistor that controls a source-drain current Ids (also referred to as a "driving current") flowing between its source and drain electrodes according to a voltage applied to its gate electrode. The first transistor T1 includes a gate electrode connected to the first node N1, a source electrode connected to the drain electrode of the sixth transistor T6, and a drain electrode connected to the second node N2.

[0076] The second transistor T2 can be disposed between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by a write scan signal from the write scan line GWL to connect one electrode of the first capacitor CP1 to the data line DL. Therefore, the data voltage of the data line DL can be applied to one electrode of the first capacitor CP1. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor CP1.

[0077] The third transistor T3 can be disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by a control scan signal from the control scan line GCL to connect the first node N1 to the second node N2. To this end, because the gate and drain electrodes of the first transistor T1 are connected, the first transistor T1 can operate like a diode (e.g., the first transistor T1 can be diode-connected). The third transistor T3 includes a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0078] The fourth transistor T4 may be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first emission control signal of the first emission control line EL1 to connect the second node N2 to the third node N3. Thus, the driving current Ids of the first transistor T1 may be supplied to the light-emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0079] The fifth transistor T5 can be disposed between the third node N3 and the third drive voltage line VIL. The fifth transistor T5 is turned on by a bias scan signal from the bias scan line EBL to connect the third node N3 to the third drive voltage line VIL. Thus, the third drive voltage VINT of the third drive voltage line VIL can be applied to the first electrode of the light-emitting element LE. The fifth transistor T5 includes a gate electrode connected to the bias scan line EBL, a source electrode connected to the third node N3, and a drain electrode connected to the third drive voltage line VIL.

[0080] The sixth transistor T6 can be disposed between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by the second emission control signal of the second emission control line EL2 to connect the source electrode of the first transistor T1 to the second drive voltage line VDL. Therefore, the second drive voltage VDD of the second drive voltage line VDL can be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emission control line EL2, a source electrode connected to the second drive voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0081] The first capacitor CP1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor CP1 includes one electrode connected to the drain electrode of the second transistor T2 and the other electrode connected to the first node N1.

[0082] The second capacitor CP2 is formed between the gate electrode of the first transistor T1 and the second driving voltage line VDL. The second capacitor CP2 includes one electrode connected to the gate electrode of the first transistor T1 and the other electrode connected to the second driving voltage line VDL.

[0083] The first node N1 is a junction between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor CP1, and one electrode of the second capacitor CP2. The second node N2 is a junction between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is a junction between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE.

[0084] Each of the first to sixth transistors T1 to T6 may be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the first to sixth transistors T1 to T6 may be a P-type MOSFET, but the present disclosure is not limited thereto. Each of the first to sixth transistors T1 to T6 may be an N-type MOSFET. Alternatively, some of the first to sixth transistors T1 to T6 may be P-type MOSFETs, and each of the remaining transistors may be an N-type MOSFET.

[0085] Despite Figure 3 FIG. 4 shows that the first sub-pixel SP1 includes six transistors T1 to T6 and two capacitors CP1 and CP2, but it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to Figure 3 For example, the number of transistors and the number of capacitors of the first sub-pixel SP1 are not limited to Figure 3 The number of transistors and the number of capacitors shown in .

[0086] In addition, the equivalent circuit diagram of the second sub-pixel SP2 and the equivalent circuit diagram of the third sub-pixel SP3 can be combined with Figure 3 The equivalent circuit diagram of the first sub-pixel SP1 is substantially the same as that described above. Therefore, descriptions of the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 are omitted in this specification.

[0087] Figure 4 It shows Figure 1 The layout diagram of an example of a display panel is shown in FIG. Figure 4 , a layout diagram of a display panel 100 according to one or more embodiments is shown.

[0088] Reference Figure 4 The display area DAA of the display panel 100 according to one or more embodiments includes a plurality of pixels PX arranged in a matrix. The non-display area NDA of the display panel 100 according to one or more embodiments includes a scan driver 610, an emission driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1, and a second pad portion PDA2.

[0089] The scan driver 610 may be provided on a first side of the display area DAA, and the emission driver 620 may be provided on a second side of the display area DAA. For example, the scan driver 610 may be provided on one side of the display area DAA in the first direction DR1, and the emission driver 620 may be provided on the other side of the display area DAA in the first direction DR1. That is, the scan driver 610 may be provided on the left side of the display area DAA, and the emission driver 620 may be provided on the right side of the display area DAA. However, the present disclosure is not limited thereto, and the scan driver 610 and the emission driver 620 may be provided on both the first side and the second side of the display area DAA.

[0090] The first pad portion PDA1 may include a plurality of first pads PD1 connected to pads of the circuit board 300 through a conductive adhesive member. The first pad portion PDA1 may be disposed on a third side of the display area DAA. For example, the first pad portion PDA1 may be disposed on one side of the display area DAA in the second direction DR2.

[0091] The first pad portion PDA1 may be disposed outside the data driver 700 in the second direction DR2. That is, the first pad portion PDA1 may be disposed closer to the edge of the display panel 100 than the data driver 700.

[0092] The second pad portion PDA2 may include a plurality of second pads PD2 corresponding to inspection pads for testing whether the display panel 100 is operating normally. The plurality of second pads PD2 may be connected to a jig or probe pins during the inspection process, or may be connected to a circuit board for inspection. The circuit board for inspection may be a rigid printed circuit board (RPCB) made of a rigid material or a flexible printed circuit board (FPCB) made of a flexible material.

[0093] The first distribution circuit 710 distributes a data voltage applied through the first pad portion PDA1 to the plurality of data lines DL. For example, the first distribution circuit 710 can distribute a data voltage applied through a first pad PD1 of the first pad portion PDA1 to the plurality of data lines DL, thereby reducing the number of first pads PD1. The first distribution circuit 710 can be disposed on a third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be disposed on one side of the display area DAA in the second direction DR2. In other words, the first distribution circuit 710 can be disposed on the lower side of the display area DAA.

[0094] The second distribution circuit 720 distributes the signal applied through the second pad portion PDA2 to the scan driver 610, the emission driver 620, and the data lines DL. The second pad portion PDA2 and the second distribution circuit 720 can be configured to check the operation of each of the pixels PX in the display area DAA. The second distribution circuit 720 can be disposed on a fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be disposed on the other side of the display area DAA in the second direction DR2. In other words, the second distribution circuit 720 can be disposed on the upper side of the display area DAA.

[0095] Figure 5 and Figure 6 is a layout diagram illustrating pixels of a display area according to one or more embodiments.

[0096] Reference Figure 5 and Figure 6 , each of the pixels PX includes a first emission area EA1 as an emission area of ​​the first sub-pixel SP1, a second emission area EA2 as an emission area of ​​the second sub-pixel SP2, and a third emission area EA3 as an emission area of ​​the third sub-pixel SP3.

[0097] Each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a quadrilateral shape such as a rectangle, a square, and / or a diamond in a plan view. Figure 5 As shown in , the third emission area EA3 may have a rectangular shape having short sides in the first direction DR1 and long sides in the second direction DR2 in a plan view. Figure 5 As shown in FIG, each of the second emission area EA2 and the first emission area EA1 may have a rectangular shape having long sides in the first direction DR1 and short sides in the second direction DR2 in a plan view.

[0098] The length of the third emission area EA3 in the first direction DR1 may be smaller than the length of the second emission area EA2 in the first direction DR1, and may be smaller than the length of the first emission area EA1 in the first direction DR1. The length of the second emission area EA2 in the first direction DR1 may be substantially the same as the length of the first emission area EA1 in the first direction DR1.

[0099] The length of the third emission area EA3 in the second direction DR2 may be greater than the sum of the lengths of the second emission area EA2 and the first emission area EA1 in the second direction DR2. The length of the second emission area EA2 in the second direction DR2 may be less than the length of the first emission area EA1 in the second direction DR2.

[0100] Despite Figure 5 , each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 is shown to have a rectangular shape in a plan view, but the present disclosure is not limited thereto. For example, each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a polygonal shape other than a quadrilateral shape, a circular shape, and / or an elliptical shape in a plan view.

[0101] In each of the plurality of pixels PX, the third emission area EA3 and the second emission area EA2 may be adjacent to each other in the first direction DR1. Furthermore, the first emission area EA1 and the third emission area EA3 may be adjacent to each other in the first direction DR1. Furthermore, the second emission area EA2 and the first emission area EA1 may be adjacent to each other in the second direction DR2. The areas of the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be different.

[0102] Alternatively, as Figure 6 As shown in FIG, the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a hexagonal shape in a plan view. In this case, the first emission area EA1 and the second emission area EA2 may be adjacent to each other in the first direction DR1, the second emission area EA2 and the third emission area EA3 may be adjacent to each other in the first diagonal direction DD1, and the first emission area EA1 and the third emission area EA3 may be adjacent to each other in the second diagonal direction DD2. The first diagonal direction DD1 may be a direction between the first direction DR1 and the second direction DR2 and may refer to a direction inclined 45 degrees relative to the first direction DR1 and the second direction DR2. The second diagonal direction DD2 may be a direction perpendicular to the first diagonal direction DD1.

[0103] The first emission area EA1 can emit light of a first color, the second emission area EA2 can emit light of a second color, and the third emission area EA3 can emit light of a third color. Here, the first color light can be light in a blue wavelength band, the second color light can be light in a green wavelength band, and the third color light can be light in a red wavelength band. For example, the blue wavelength band can be a wavelength band of light having a main peak wavelength in the range of approximately 370 nm to approximately 460 nm, the green wavelength band can be a wavelength band of light having a main peak wavelength in the range of approximately 480 nm to approximately 560 nm, and the red wavelength band can be a wavelength band of light having a main peak wavelength in the range of approximately 600 nm to approximately 750 nm.

[0104] exist Figure 5, each of the plurality of pixels PX includes three emission areas EA1, EA2, and EA3 as an example, but the present disclosure is not limited thereto. That is, each of the plurality of pixels PX may include four emission areas.

[0105] In addition, the arrangement of the emission regions of the plurality of pixels PX is not limited to Figure 5 For example, the emission regions of the plurality of pixels PX may be arranged in a stripe structure in which the emission regions are arranged along the first direction DR1, a PENTILE structure in which the emission regions are arranged in a diamond shape, or a PENTILE ® structure, or an emitting region having a hexagonal shape in plan view such as Figure 6 The hexagonal structures are arranged side by side as shown in FIG. ® The pixel arrangement structure may be referred to as an RGBG matrix structure (eg, PENTILE ® Matrix structure or RGBG structure (for example, PENTILE ® structure)). PENTILE ® is a registered trademark of Samsung Display Co., Ltd. of South Korea.

[0106] Figure 7 is a cross-sectional view of a display device according to one or more embodiments, Figure 8 is a perspective view of a display device according to one or more embodiments. For example, Figure 8 Can include Figure 7 FIG. 1 is a perspective view of a display device including a semiconductor substrate SSUB, an intermediate layer LL, and a cover layer CVL.

[0107] Reference Figure 7 The display panel 100 includes a semiconductor backplane SBP, a light emitting element backplane EBP, a display element layer EML, an encapsulation layer TFE, an organic layer APL, an optical layer OPL, a filling layer FIL, a cover layer CVL and a polarizing plate POL.

[0108] The semiconductor backplane SBP includes a semiconductor substrate SSUB including a plurality of pixel transistors PTR, a plurality of semiconductor insulating layers covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors PTR. Figure 3 The first transistor T1 to the sixth transistor T6 are described.

[0109] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. The semiconductor substrate SSUB may be a substrate doped with first-type impurities. A plurality of well regions WA may be provided on the top surface of the semiconductor substrate SSUB. The plurality of well regions WA may be regions doped with second-type impurities. The second-type impurities may be different from the aforementioned first-type impurities. For example, when the first-type impurities are P-type impurities, the second-type impurities may be N-type impurities. Alternatively, when the first-type impurities are N-type impurities, the second-type impurities may be P-type impurities.

[0110] Each of the plurality of well regions WA includes a source region SA corresponding to a source electrode of the pixel transistor PTR, a drain region DA corresponding to a drain electrode of the pixel transistor PTR, and a channel region CH disposed between the source region SA and the drain region DA.

[0111] The lower insulating layer BINS may be disposed between the gate electrode GE and the well area WA. The side insulating layer SINS may be disposed on a side surface of the gate electrode GE. The side insulating layer SINS may be disposed on the lower insulating layer BINS.

[0112] Each of the source region SA and the drain region DA may be a region doped with first-type impurities. The gate electrode GE of the pixel transistor PTR may overlap the well region WA in the third direction DR3. The channel region CH may overlap the gate electrode GE in the third direction DR3. The source region SA may be provided on one side of the gate electrode GE, and the drain region DA may be provided on the other side of the gate electrode GE.

[0113] Each of the plurality of well regions WA further includes a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 may be a region having an impurity concentration lower than that of the source region SA due to the lower insulating layer BINS. The second low-concentration impurity region LDD2 may be a region having an impurity concentration lower than that of the drain region DA due to the lower insulating layer BINS. The distance between the source region SA and the drain region DA may be increased due to the presence of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2. Therefore, the length of the channel region CH of each of the pixel transistors PTR may be increased, thereby preventing a breakdown phenomenon and a hot carrier phenomenon that may be caused by a short channel.

[0114] The first semiconductor insulating layer SINS1 may be provided on the semiconductor substrate SSUB to cover the pixel transistor PTR. The first semiconductor insulating layer SINS1 may be made of silicon carbonitride (SiCN) and / or silicon oxide (SiO x )-type inorganic layer is formed, but the present disclosure is not limited thereto.

[0115] The second semiconductor insulating layer SINS2 may be provided on the first semiconductor insulating layer SINS1. The second semiconductor insulating layer SINS2 may be made of silicon oxide (SiO x )-type inorganic layer is formed, but the present disclosure is not limited thereto.

[0116] A plurality of contact terminals CTE may be disposed on the second semiconductor insulating layer SINS2. Each of the plurality of contact terminals CTE may be connected to one of the gate electrode GE, source area SA, and drain area DA of each of the pixel transistors PTR via a hole penetrating the first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2. The plurality of contact terminals CTE may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or alloys and / or compounds including one or more of these.

[0117] The third semiconductor insulating layer SINS3 may be provided on the side surface of each of the plurality of contact terminals CTE on the second semiconductor insulating layer SINS2. The top surface of each of the plurality of contact terminals CTE may be exposed without being covered by the third semiconductor insulating layer SINS3. The third semiconductor insulating layer SINS3 may be made of silicon oxide (SiO x )-type inorganic layer is formed, but the present disclosure is not limited thereto.

[0118] The semiconductor substrate SSUB can be replaced with a glass substrate and / or a polymer resin substrate such as polyimide. In this case, the thin film transistor can be provided on the glass substrate and / or the polymer resin substrate. The glass substrate can be a rigid substrate that does not bend, and the polymer resin substrate can be a flexible substrate that can be bent and / or curved.

[0119] The light emitting element backplane EBP includes a plurality of conductive layers ML1 to ML8, a plurality of vias VA1 to VA9, and a plurality of insulating layers INS1 to INS9. The light emitting element backplane EBP includes a plurality of insulating layers INS1 to INS9 disposed between the third semiconductor insulating layer SINS3 and the first conductive layer ML1, between the first conductive layer ML1 to the eighth conductive layer ML8, and between the eighth conductive layer ML8 and the display element layer EML.

[0120] The first conductive layer ML1 to the eighth conductive layer ML8 are used to connect a plurality of contact terminals CTE exposed from the semiconductor back plate SBP, thereby realizing Figure 3. For example, the first to sixth transistors T1 to T6 are formed only on the semiconductor backplane SBP, and connections between the first to sixth transistors T1 to T6 and the first and second capacitors CP1 and CP2 are established through the first to eighth conductive layers ML1 to ML8. Furthermore, connections between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE are also established through the first to eighth conductive layers ML1 to ML8.

[0121] The first insulating layer INS1 may be disposed on the semiconductor backplane SBP. Each of the first vias VA1 may penetrate the first insulating layer INS1 to connect to the contact terminal CTE exposed from the semiconductor backplane SBP. Each of the first conductive layers ML1 may be disposed on the first insulating layer INS1 and may be connected to the first vias VA1.

[0122] The second insulating layer INS2 may be disposed on the first insulating layer INS1 and the first conductive layer ML1. Each of the second via holes VA2 may penetrate the second insulating layer INS2 and may be connected to the exposed first conductive layer ML1. Each of the second conductive layers ML2 may be disposed on the second insulating layer INS2 and may be connected to the second via holes VA2.

[0123] The third insulating layer INS3 may be disposed on the second insulating layer INS2 and the second conductive layer ML2. Each of the third via holes VA3 may penetrate the third insulating layer INS3 and may be connected to the exposed second conductive layer ML2. Each of the third conductive layers ML3 may be disposed on the third insulating layer INS3 and may be connected to the third via holes VA3.

[0124] The fourth insulating layer INS4 may be disposed on the third insulating layer INS3 and the third conductive layer ML3. Each of the fourth via holes VA4 may penetrate the fourth insulating layer INS4 and may be connected to the exposed third conductive layer ML3. Each of the fourth conductive layers ML4 may be disposed on the fourth insulating layer INS4 and may be connected to the fourth via hole VA4.

[0125] The fifth insulating layer INS5 may be disposed on the fourth insulating layer INS4 and the fourth conductive layer ML4. Each of the fifth via holes VA5 may penetrate the fifth insulating layer INS5 and may be connected to the exposed fourth conductive layer ML4. Each of the fifth conductive layers ML5 may be disposed on the fifth insulating layer INS5 and may be connected to the fifth via hole VA5.

[0126] The sixth insulating layer INS6 may be disposed on the fifth insulating layer INS5 and the fifth conductive layer ML5. Each of the sixth via holes VA6 may penetrate the sixth insulating layer INS6 and may be connected to the exposed fifth conductive layer ML5. Each of the sixth conductive layers ML6 may be disposed on the sixth insulating layer INS6 and may be connected to the sixth via hole VA6.

[0127] The seventh insulating layer INS7 may be disposed on the sixth insulating layer INS6 and the sixth conductive layer ML6. Each of the seventh via holes VA7 may penetrate the seventh insulating layer INS7 and may be connected to the exposed sixth conductive layer ML6. Each of the seventh conductive layers ML7 may be disposed on the seventh insulating layer INS7 and may be connected to the seventh via hole VA7.

[0128] The eighth insulating layer INS8 may be disposed on the seventh insulating layer INS7 and the seventh conductive layer ML7. Each of the eighth via holes VA8 may penetrate the eighth insulating layer INS8 and may be connected to the exposed seventh conductive layer ML7. Each of the eighth conductive layers ML8 may be disposed on the eighth insulating layer INS8 and may be connected to the eighth via hole VA8.

[0129] The first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 may be formed of substantially the same material. The first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and / or neodymium (Nd), and / or alloys and / or compounds including one or more thereof. The first to eighth insulating layers INS1 to INS8 may be made of substantially the same material. The first to eighth insulating layers INS1 to INS8 may be made of silicon oxide (SiO x )-type inorganic layer is formed, but the present disclosure is not limited thereto.

[0130] The thicknesses of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be respectively greater than the thicknesses of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be greater than the thickness of the first conductive layer ML1. The thicknesses of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be substantially the same. For example, the thickness of the first conductive layer ML1 may be approximately 1360Å; the thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5 and the sixth conductive layer ML6 may be approximately 1440Å; and the thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5 and the sixth via VA6 may be approximately 1150Å.

[0131] The thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be greater than the thickness of the first conductive layer ML1, the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 may be greater than the thickness of the seventh via VA7 and the thickness of the eighth via VA8, respectively. The thickness of each of the seventh via VA7 and the eighth via VA8 may be greater than the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 may be substantially the same. For example, the thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be approximately 9000 Å. The thickness of each of the seventh via VA7 and the eighth via VA8 may be approximately 6000 Å.

[0132] The ninth insulating layer INS9 may be disposed on the eighth insulating layer INS8 and the eighth conductive layer ML8. The ninth insulating layer INS9 may be made of silicon oxide (SiO x )-type inorganic layer is formed, but the present disclosure is not limited thereto.

[0133] Each of the ninth vias VA9 may penetrate the ninth insulating layer INS9 and may be connected to the exposed eighth conductive layer ML8. The ninth via VA9 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or alloys and / or compounds including one or more thereof. The thickness of the ninth via VA9 may be approximately 16,500 Å.

[0134] The display element layer EML may be disposed on the light emitting element backplane EBP. The display element layer EML may include a light emitting element LE, a reflective electrode layer RL, a tenth insulating layer INS10 and an eleventh insulating layer INS11, a tenth via hole VA10, a pixel defining layer PDL, and a plurality of trenches TRC. Each light emitting element LE includes a first electrode AND, a light emitting stack ES, and a second electrode CAT.

[0135] The reflective electrode layer RL may be disposed on the ninth insulating layer INS9. The reflective electrode layer RL may include at least one reflective electrode RL1, RL2, RL3, and RL4. For example, the reflective electrode layer RL may include: Figure 7 1 to the fourth reflective electrodes RL1 , RL2 , RL3 and RL4 shown in FIG.

[0136] Each of the first reflective electrodes RL1 may be disposed on the ninth insulating layer INS9 and may be connected to the ninth via hole VA9. The first reflective electrodes RL1 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or alloys and / or compounds including one or more thereof. For example, the first reflective electrodes RL1 may include titanium nitride (TiN).

[0137] Each of the second reflective electrodes RL2 may be disposed on the first reflective electrode RL1. The second reflective electrodes RL2 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or alloys and / or compounds including one or more thereof. For example, the second reflective electrodes RL2 may include aluminum (Al).

[0138] Each of the third reflective electrodes RL3 may be disposed on the second reflective electrode RL2. The third reflective electrodes RL3 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or alloys and / or compounds including one or more thereof. For example, the third reflective electrodes RL3 may include titanium nitride (TiN).

[0139] The fourth reflective electrode RL4 may be disposed on each of the third reflective electrodes RL3. The fourth reflective electrode RL4 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or alloys and / or compounds including one or more of these. For example, the fourth reflective electrode RL4 may include titanium (Ti).

[0140] Because the second reflective electrode RL2 is an electrode that substantially reflects light from the light-emitting element LE, in one or more embodiments, the thickness of the second reflective electrode RL2 may be greater than the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4. For example, the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4 may be approximately 100 Å, and the thickness of the second reflective electrode RL2 may be 850 Å. However, in one or more embodiments, the thickness of the second reflective electrode RL2 may be substantially equal to the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4.

[0141] The tenth insulating layer INS10 may be disposed on the ninth insulating layer INS9. The tenth insulating layer INS10 may be disposed between the reflective electrode layers RL adjacent to each other in the horizontal direction (eg, the first direction DR1 or the second direction DR2). In one or more embodiments, the tenth insulating layer INS10 may be disposed on the reflective electrode layer RL in the third pixel PX3. The tenth insulating layer INS10 may be made of silicon oxide (SiO x )-type inorganic layer is formed, but the present disclosure is not limited thereto.

[0142] The eleventh insulating layer INS11 may be disposed on the tenth insulating layer INS10 and the reflective electrode layer RL. The eleventh insulating layer INS11 may be made of silicon oxide (SiO x The tenth insulating layer INS10 and the eleventh insulating layer INS11 may be optical auxiliary layers through which light reflected by the reflective electrode layer RL, among light emitted from the light emitting element LE, passes.

[0143] In order to match the resonance distance of light emitted from the light emitting element LE in at least one of the first pixel PX1 (i.e., the first sub-pixel SP1), the second pixel PX2 (i.e., the second sub-pixel SP2), and the third pixel PX3 (i.e., the third sub-pixel SP3), the tenth insulating layer INS10 and the eleventh insulating layer INS11 may not be disposed under the first electrode AND of the first pixel PX1. In one or more embodiments, the first electrode AND of the first pixel PX1 may be directly disposed on the reflective electrode layer RL. Figure 7 As shown in , the eleventh insulating layer INS11 may be disposed under the first electrode AND of the first pixel PX1, under the first electrode AND of the second pixel PX2, and under the first electrode AND of the third pixel PX3. In one or more embodiments, the tenth insulating layer INS10 and the eleventh insulating layer INS11 may be disposed under the first electrode AND of the third pixel PX3.

[0144] In summary, in the first pixel PX1, the second pixel PX2, and the third pixel PX3, the distance between the first electrode AND and the reflective electrode layer RL may be different. In order to adjust the distance from the reflective electrode layer RL to the second electrode CAT according to the main peak wavelength of light emitted from each of the first pixel PX1, the second pixel PX2, and the third pixel PX3, the presence or absence of the tenth insulating layer INS10 and the eleventh insulating layer INS11 may be set in each of the first pixel PX1, the second pixel PX2, and the third pixel PX3. In addition, the thickness of the eleventh insulating layer INS11 may be different in each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 to adjust the distance from the reflective electrode layer RL to the second electrode CAT according to the main peak wavelength of light emitted from each of the first pixel PX1, the second pixel PX2, and the third pixel PX3. For example, in Figure 7 ] It is shown that the distance between the first electrode AND and the reflective electrode layer RL in the third pixel PX3 is greater than the distance between the first electrode AND and the reflective electrode layer RL in the second pixel PX2 and the distance between the first electrode AND and the reflective electrode layer RL in the first pixel PX1, and the distance between the first electrode AND and the reflective electrode layer RL in the second pixel PX2 is greater than the distance between the first electrode AND and the reflective electrode layer RL in the first pixel PX1, but the present disclosure is not limited thereto.

[0145] In addition, although the tenth insulating layer INS10 and the eleventh insulating layer INS11 are shown in the present disclosure, a twelfth insulating layer disposed under the first electrode AND of the first pixel PX1 may be added. In this case, the eleventh insulating layer INS11 and the twelfth insulating layer may be disposed under the first electrode AND of the second pixel PX2, and the tenth insulating layer INS10, the eleventh insulating layer INS11, and the twelfth insulating layer may be disposed under the first electrode AND of the third pixel PX3.

[0146] Each of the tenth via holes VA10 may penetrate the tenth insulating layer INS10 and / or the eleventh insulating layer INS11 in the first, second, and third pixels PX1, PX2, and PX3, and may be connected between the first electrode AND and the reflective electrode layer RL of the first, second, and third pixels PX1, PX2, and PX3. The tenth via hole VA10 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or alloys and / or compounds including one or more thereof. The thickness of the tenth via hole VA10 in the second pixel PX2 may be thinner than the thickness of the tenth via hole VA10 in the third pixel PX3, and the thickness of the tenth via hole VA10 in the first pixel PX1 may be thinner than the thickness of the tenth via hole VA10 in the second pixel PX2.

[0147] The first electrode AND of each light-emitting element LE may be disposed on the eleventh insulating layer INS11 and connected to the tenth via VA10. The first electrode AND of each light-emitting element LE may be connected to the drain region DA or the source region SA of the pixel transistor PTR via the tenth via VA10, the first to fourth reflective electrodes RL1 to RL4, the first to ninth vias VA1 to VA9, the first to eighth conductive layers ML1 to ML8, and the contact terminal CTE. The first electrode AND of each light-emitting element LE may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd), and / or alloys and / or compounds including one or more of these. For example, the first electrode AND of each light-emitting element LE may be titanium nitride (TiN).

[0148] The pixel-defining film PDL may be disposed on a portion of the first electrode AND of each light-emitting element LE. The pixel-defining film PDL may cover the edge of the first electrode AND of each light-emitting element LE. The pixel-defining film PDL may be used to divide the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0149] The first emission area EA1 may be defined as an area where the first electrode AND, the light emitting stack ES, and the second electrode CAT are sequentially stacked in the first pixel PX1 to emit light. The second emission area EA2 may be defined as an area where the first electrode AND, the light emitting stack ES, and the second electrode CAT are sequentially stacked in the second pixel PX2 to emit light. The third emission area EA3 may be defined as an area where the first electrode AND, the light emitting stack ES, and the second electrode CAT are sequentially stacked in the third pixel PX3 to emit light.

[0150] The pixel definition film PDL may include first to third pixel definition films PDL1, PDL2, and PDL3. The first pixel definition film PDL1 may be provided on the edge of the first electrode AND of each of the light emitting elements LE, the second pixel definition film PDL2 may be provided on the first pixel definition film PDL1, and the third pixel definition film PDL3 may be provided on the second pixel definition film PDL2. The first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 may be made of silicon oxide (SiO x ) type inorganic layer is formed, but the present disclosure is not limited thereto. The first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 may each have a thickness of about 500 Å.

[0151] When the first, second, and third pixel-defining layers PDL1, PDL2, and PDL3 are formed into one pixel-defining layer, the height of the single pixel-defining layer increases, potentially cutting the first encapsulating inorganic layer TFE1 due to step coverage. Step coverage refers to the ratio of the amount of film applied on inclined portions to the amount applied on flat portions. The lower the step coverage, the more likely the film will be cut at the inclined portion.

[0152] Therefore, to prevent the first encapsulating inorganic layer TFE1 from being cut due to step coverage, the first, second, and third pixel defining films PDL1, PDL2, and PDL3 may have a cross-sectional structure with a stepped portion. For example, the width of the first pixel defining film PDL1 may be greater than the widths of the second and third pixel defining films PDL2, and the width of the second pixel defining film PDL2 may be greater than the width of the third pixel defining film PDL3. The width of the first pixel defining film PDL1 refers to the horizontal length of the first pixel defining film PDL1 defined in the first and second directions DR1 and DR2.

[0153] Each of the plurality of trenches TRC may penetrate the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3. Furthermore, each of the plurality of trenches TRC may penetrate the eleventh insulating layer INS11. In one or more embodiments, the tenth insulating layer INS10 may be partially recessed at each of the plurality of trenches TRC.

[0154] At least one trench TRC may be provided between adjacent pixels PX1, PX2, and PX3. Figure 7 It is shown that two trenches TRC are provided between adjacent pixels PX1 , PX2 , and PX3 , but the present disclosure is not limited thereto.

[0155] The light emitting stack ES may include a plurality of stacked layers. Figure 7 The light emitting stack body ES is shown to have a three-series structure including the first stack layer IL1, the second stack layer IL2, and the third stack layer IL3, but the present disclosure is not limited thereto. For example, the light emitting stack body ES may have a two-series structure including two sublayers.

[0156] In the triple-series structure, the light emitting stack ES may have a series structure including a plurality of stack layers IL1, IL2, and IL3 that emit different lights. For example, the light emitting stack ES may include a first stack layer IL1 that emits light of a first color, a second stack layer IL2 that emits light of a second color, and a third stack layer IL3 that emits light of a third color. The first stack layer IL1, the second stack layer IL2, and the third stack layer IL3 may be stacked sequentially.

[0157] The first stacked layer IL1 may have a structure in which a first hole transport layer, a first organic light-emitting layer emitting light of a first color, and a first electron transport layer are sequentially stacked. The second stacked layer IL2 may have a structure in which a second hole transport layer, a second organic light-emitting layer emitting light of a second color, and a second electron transport layer are sequentially stacked. The third stacked layer IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer emitting light of a third color, and a third electron transport layer are sequentially stacked.

[0158] A first charge generation layer for supplying holes to the second stack layer IL2 and electrons to the first stack layer IL1 may be provided between the first stack layer IL1 and the second stack layer IL2. The first charge generation layer may include an N-type charge generation layer for supplying electrons to the first stack layer IL1 and a P-type charge generation layer for supplying holes to the second stack layer IL2. The N-type charge generation layer may include a dopant of a metal material.

[0159] A second charge generation layer for supplying holes to the third stacked layer IL3 and electrons to the second stacked layer IL2 may be provided between the second stacked layer IL2 and the third stacked layer IL3. The second charge generation layer may include an N-type charge generation layer for supplying electrons to the second stacked layer IL2 and a P-type charge generation layer for supplying holes to the third stacked layer IL3.

[0160] The first stacked layer IL1 can be arranged on the first electrode AND and the pixel defining film PDL, and can be arranged on the bottom surface of each trench TRC. Due to the trench TRC, the first stacked layer IL1 can be separated between adjacent pixels PX1, PX2 and PX3. The second stacked layer IL2 can be arranged on the first stacked layer IL1. Due to the trench TRC, the second stacked layer IL2 can be separated between adjacent pixels PX1, PX2 and PX3. A cavity ESS or empty space can be provided between the first stacked layer IL1 and the second stacked layer IL2. The third stacked layer IL3 can be provided on the second stacked layer IL2. The third stacked layer IL3 is not cut off by the trench TRC and can be arranged to cover the second stacked layer IL2 in each of the trenches TRC. That is, in the three-series structure, each of the multiple trenches TRC can be a structure for cutting off the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML between adjacent pixels PX1, PX2 and PX3. In addition, in the two-series structure, each of the trenches TRC may be a structure for cutting off the charge generation layer provided between the lower sublayer and the upper sublayer and the lower sublayer.

[0161] In order to stably cut off the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML between adjacent pixels PX1, PX2 and PX3, the height of each of the plurality of grooves TRC may be greater than the height of the pixel-defining film PDL. The height of each of the plurality of grooves TRC refers to the length of each of the plurality of grooves TRC in the third direction DR3. The height of the pixel-defining film PDL refers to the length of the pixel-defining film PDL in the third direction DR3. In order to cut off the first stacked layer IL1 and the second stacked layer IL2 of the display element layer EML between adjacent pixels PX1, PX2 and PX3, another structure may be present instead of the grooves TRC. For example, instead of the grooves TRC, an inverted tapered partition wall may be provided on the pixel-defining film PDL.

[0162] The number of stacked layers IL1, IL2 and IL3 emitting different light is not limited to Figure 7. For example, the light-emitting stack ES may include two sublayers. In this case, one of the two sublayers may be substantially the same as the first stacked layer IL1, and the other may include a second hole transport layer, a second organic light-emitting layer, a third organic light-emitting layer, and a second electron transport layer. In this case, a charge generation layer for supplying electrons to one sublayer and holes to the other sublayer may be provided between the two sublayers.

[0163] in addition, Figure 7 The first to third stacked layers IL1, IL2, and IL3 are shown as all disposed in the first emission area EA1, the second emission area EA2, and the third emission area EA3, but the present disclosure is not limited thereto. For example, the first stacked layer IL1 may be disposed in the first emission area EA1, and may not be disposed in the second emission area EA2 and the third emission area EA3. In addition, the second stacked layer IL2 may be disposed in the second emission area EA2, and may not be disposed in the first emission area EA1 and the third emission area EA3. In addition, the third stacked layer IL3 may be disposed in the third emission area EA3, and may not be disposed in the first emission area EA1 and the second emission area EA2. In this case, the first to third color filters CF1, CF2, and CF3 of the optical layer OPL may be omitted.

[0164] The second electrode CAT may be disposed on the third stacked layer IL3. The second electrode CAT may be disposed on the third stacked layer IL3 in each of the plurality of trenches TRC. The second electrode CAT may be formed of a light-transmitting transparent conductive material (TCO), such as ITO and / or IZO, or a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), and / or an alloy of Mg and Ag. When the second electrode CAT is formed of a semi-transmissive conductive material, the microcavity effect may improve luminous efficiency in each of the first to third pixels PX1, PX2, and PX3.

[0165] The encapsulation layer TFE may be disposed on the display element layer EML. The encapsulation layer TFE may include at least one inorganic layer TFE1 and TFE2 to prevent oxygen and / or moisture from penetrating into the display element layer EML. For example, the encapsulation layer TFE may include a first encapsulation inorganic layer TFE1 and a second encapsulation inorganic layer TFE2.

[0166] The first encapsulation inorganic layer TFE1 may be provided on the second electrode CAT. The first encapsulation inorganic layer TFE1 may be formed of a material selected from silicon nitride (SiN x ), silicon oxynitride (SiON) and / or silicon oxide (SiO x ) is a multilayer of one or more inorganic layers alternately stacked. The first encapsulation inorganic layer TFE1 may be formed by a chemical vapor deposition (CVD) process.

[0167] The second encapsulating inorganic layer TFE2 may be provided on the first encapsulating inorganic layer TFE1. The second encapsulating inorganic layer TFE2 may be made of titanium oxide (TiO x ) and / or aluminum oxide (AlO x ), but the present disclosure is not limited thereto. The second encapsulating inorganic layer TFE2 may be formed by an atomic layer deposition (ALD) process. The thickness of the second encapsulating inorganic layer TFE2 may be less than the thickness of the first encapsulating inorganic layer TFE1.

[0168] The organic layer APL may be a layer for increasing the interfacial adhesion between the encapsulation layer TFE and the optical layer OPL. The organic layer APL may be an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin and / or polyimide resin.

[0169] The optical layer OPL may include a color filter layer CFL and a lens layer LSL.

[0170] The color filter layer CFL may include first to third color filters CF1, CF2, and CF3. The first to third color filters CF1, CF2, and CF3 may be disposed on the organic layer APL.

[0171] The first color filter CF1 may overlap the first emission area EA1 of the first pixel PX1. The first color filter CF1 may transmit light of the first color, that is, light in the blue wavelength band. The blue wavelength band may be approximately 370 nm to 460 nm. Therefore, the first color filter CF1 may transmit light of the first color among the light emitted from the first emission area EA1.

[0172] The second color filter CF2 may overlap the second emission area EA2 of the second pixel PX2. The second color filter CF2 may transmit light of the second color, i.e., light in the green wavelength band. The green wavelength band may be approximately 480 nm to 560 nm. Therefore, the second color filter CF2 may transmit light of the second color among the light emitted from the second emission area EA2.

[0173] The third color filter CF3 may overlap the third emission area EA3 of the third pixel PX3. The third color filter CF3 may transmit light of a third color, i.e., light in a red wavelength band. The red wavelength band may be approximately 600 nm to 750 nm. Therefore, the third color filter CF3 may transmit light of the third color among the light emitted from the third emission area EA3.

[0174] The lens layer LSL may include a plurality of lenses LNS. The plurality of lenses LNS may be disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3, respectively. Each of the plurality of lenses LNS may be configured to increase the ratio of light directed in front of the display device 10. Each of the plurality of lenses LNS may have a cross-sectional shape that is convex in an upward direction (e.g., the third direction DR3).

[0175] The filling layer FIL can be disposed on the optical layer OPL. For example, the filling layer FIL can be disposed on the lens layer LSL. In other words, the filling layer FIL can be disposed on the plurality of lenses LNS. The filling layer FIL can have a suitable refractive index (e.g., a predetermined refractive index) so that light travels in the third direction DR3 at the interface between the filling layer FIL and the plurality of lenses LNS. Furthermore, the filling layer FIL can be a planarization layer. The filling layer FIL can be an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and / or a polyimide resin.

[0176] The cover layer CVL may be provided on the filling layer FIL. In addition, the cover layer CVL may be provided on the side surface of the substrate (eg, semiconductor substrate SSUB) and the side surface of the intermediate layer LL. For example, Figure 7 and Figure 8 As shown in , the covering layer CVL can be provided on the side surface of the semiconductor substrate SSUB and the side surface of the intermediate layer LL so as to surround the side surface of the semiconductor substrate SSUB and the side surface of the intermediate layer LL (for example, surround the side surface of the semiconductor substrate SSUB and the side surface of the intermediate layer LL). The covering layer CVL can be a glass substrate and / or a polymer resin. When the covering layer CVL is a glass substrate, it can be attached to the filling layer FIL. In this case, the filling layer FIL can be used to bond the covering layer CVL. When the covering layer CVL is a glass substrate, it can be used as a packaging substrate. When the covering layer CVL is a polymer resin, it can be directly applied to the filling layer FIL.

[0177] According to one or more embodiments, the cover layer CVL may include a first sub-cover layer SBL1 and a second sub-cover layer SBL2. The first sub-cover layer SBL1 and the second sub-cover layer SBL2 may be formed as one body.

[0178] The first sub-cover layer SBL1 may be disposed on the filling layer FIL. For example, the first sub-cover layer SBL1 may be disposed on the entire surface of the filling layer FIL to overlap all components disposed below the filling layer FIL. The first sub-cover layer SBL1 may be in contact with the filling layer FIL.

[0179] The second sub-cover layer SBL2 may extend from the first sub-cover layer SBL1. For example, the second sub-cover layer SBL2 may extend from the side surface of the first sub-cover layer SBL1 in a direction opposite to the third direction DR3 (hereinafter referred to as the third opposite direction). In other words, the second sub-cover layer SBL2 may extend in a direction perpendicular to the extension direction of the first sub-cover layer SBL1. The second sub-cover layer SBL2 may be disposed on the side surface of the substrate (e.g., the semiconductor substrate SSUB) and the side surface of the intermediate layer LL. According to one or more embodiments, the second sub-cover layer SBL2 may have an obliquely slanted surface S. For example, the second sub-cover layer SBL2 may have an obliquely slanted surface S at one end, and the oblique surface S may be disposed on the side surface of the semiconductor substrate SSUB. The oblique surface S may allow the second sub-cover layer SBL2 to have an angle less than 90 degrees at the portion overlapping the side surface of the semiconductor substrate SSUB. For example, the inner angle of the second sub-cover layer SBL2 at the end overlapping the side surface of the semiconductor substrate SSUB may be an acute angle. According to one or more embodiments, at least a portion of the inclined surface S of the second sub-cover layer SBL2 may have a carbonized region.

[0180] The intermediate layer LL may include a layer disposed between the semiconductor substrate SSUB and the cover layer CVL. For example, the intermediate layer LL may include the first semiconductor insulating layer SINS1, the second semiconductor insulating layer SINS2, the third semiconductor insulating layer SINS3, the lower insulating layer BINS, the side insulating layer SINS, the gate electrode GE, the plurality of contact terminals CTE, the light emitting element backplane EBP, the display element layer EML, the encapsulation layer TFE, the organic layer APL, the optical layer OPL, and the filling layer FIL described above.

[0181] The intermediate layer LL may be surrounded by the aforementioned cover layer CVL and substrate (e.g., semiconductor substrate SSUB). In other words, the cover layer CVL and substrate may surround all surfaces of the intermediate layer LL (e.g., may surround all surfaces of the intermediate layer LL). For example, the cover layer CVL may be provided on the top and side surfaces of the intermediate layer LL, and the semiconductor substrate SSUB may be provided on the bottom surface of the intermediate layer LL, so that the cover layer CVL and semiconductor substrate SSUB surround all surfaces of the intermediate layer LL (e.g., may surround all surfaces of the intermediate layer LL).

[0182] According to one or more embodiments, because the cover layer CVL is formed not only on the top surface of the intermediate layer LL but also on the side surfaces of the intermediate layer LL and the side surfaces of the semiconductor substrate SSUB, the bonding area of ​​the cover layer CVL can be increased. Consequently, interfacial delamination between the cover layer CVL and the structures bonded thereto (e.g., the intermediate layer LL and the semiconductor substrate SSUB) can be reduced or minimized. Furthermore, because the cover layer CVL extends to the side surfaces of the semiconductor substrate SSUB, it can block the infiltration paths of external air and moisture into the intermediate layer LL and the semiconductor substrate SSUB.

[0183] The polarizing plate POL can be disposed on one surface of the cover layer CVL. For example, the polarizing plate POL can be disposed on the first sub-cover layer SBL1 of the cover layer CVL. Therefore, the first sub-cover layer SBL1 can be disposed between the aforementioned filler layer FIL and the polarizing plate POL. The polarizing plate POL can be a structure used to prevent visibility degradation caused by reflection of external light. The polarizing plate POL can include a linear polarizing plate and a phase retarder film. For example, the phase retarder film can be a λ / 4 plate (quarter-wave plate), but the present disclosure is not limited thereto. However, if visibility degradation caused by reflection of external light is sufficiently overcome by the first to third color filters CF1, CF2, and CF3, the polarizing plate POL can be omitted.

[0184] Figures 9 to 15 is a process cross-sectional view illustrating a method for manufacturing a display device according to one or more embodiments. For example, Figures 9 to 15 It can be used to describe the method for making the aforementioned Figure 7 A process cross-sectional view of a method for displaying a device.

[0185] First, if Figure 9 As shown in FIG, an intermediate layer LL may be provided on a mother substrate (e.g., a semiconductor substrate SSUB) including a base substrate BSUB. Here, as described above, the base substrate BSUB may include a well region WA, a source region SA, a drain region DA, a channel region CH, a first low-concentration impurity region LDD1, and a second low-concentration impurity region LDD2. According to one or more embodiments, the mother substrate may include a wafer.

[0186] The middle layer LL may include the first semiconductor insulating layer SINS1, the second semiconductor insulating layer SINS2, the third semiconductor insulating layer SINS3, the lower insulating layer BINS, the side insulating layer SINS, the gate electrode GE, the plurality of contact terminals CTE, the light emitting element backplane EBP, the display element layer EML, the encapsulation layer TFE, the organic layer APL, the optical layer OPL and the filling layer FIL described above.

[0187] Then, if Figure 10As shown in FIG, a groove GR may be formed at an edge of the base substrate BSUB. The groove GR may be formed in the base substrate BSUB in a concave shape in the third reverse direction. The groove GR may have a shape as shown in FIG. Figure 10 . For example, the groove GR may have a triangular cross-section with a width gradually decreasing along the third reverse direction. According to one or more embodiments, the groove GR may have a closed curve shape around the middle layer LL (e.g., surrounding the middle layer LL) in a plan view. For example, the groove GR may have a quadrilateral ring shape around the middle layer LL (e.g., surrounding the middle layer LL) in a plan view.

[0188] The groove GR may be formed by removing a portion of the base substrate BSUB. For example, the groove GR may be formed by etching the base substrate BSUB. For example, the groove GR may be formed by selectively etching the edge of the base substrate BSUB using an etchant and / or etching gas.

[0189] Afterwards, if Figure 11 As shown in , a cover layer CVL may be formed on the intermediate layer LL and the base substrate BSUB. In this case, the cover layer CVL may be disposed on the top surface of the intermediate layer LL and the side surface of the intermediate layer LL. In addition, a portion of the cover layer CVL may be disposed in the groove GR of the base substrate BSUB. For example, a first sub-cover layer SBL1 of the cover layer CVL may be disposed on the intermediate layer LL, a second sub-cover layer SBL2 of the cover layer CVL may be disposed on the side surface of the intermediate layer LL, and a portion of the second sub-cover layer SBL2 of the cover layer CVL may be disposed in the groove GR of the base substrate BSUB. According to one or more embodiments, the portion of the second sub-cover layer SBL2 may have the same cross-sectional shape as the groove GR. For example, the portion of the second sub-cover layer SBL2 disposed in the groove GR may have a triangular cross-sectional shape.

[0190] According to one or more embodiments, the cover layer CVL may be patterned through a patterning process to be disposed on the top surface of the middle layer LL and the side surface of the middle layer LL, and as shown in FIG. Figure 11 As shown in FIG, the cover layer CVL is formed by applying (or coating) a polymer resin on the filling layer FIL of the intermediate layer LL and the base substrate BSUB. The cover layer CVL is formed by patterning the polymer resin layer using the photolithography and / or etching processes described above.

[0191] Then, if Figure 12 and Figure 13As shown in , a process of removing a portion of the base substrate BSUB may be performed. For example, the process of removing a portion of the base substrate BSUB may include a dicing process of cutting the base substrate BSUB into units (or wafer chips).

[0192] The aforementioned cutting process of the base substrate BSUB may be performed, for example, by a laser cutting process. Figure 12 As shown in , the laser beam LB can be irradiated from below the base substrate BSUB toward the groove GR of the base substrate BSUB in the third direction DR3. According to one or more embodiments, the laser beam LB can be irradiated toward the vertex of the triangular groove GR. For example, the laser beam LB can be irradiated toward the lowermost portion of the groove GR located in the base substrate BSUB (e.g., the vertex of the groove GR). Then, the laser beam LB can penetrate the base substrate BSUB and reach the vertex of the groove GR. In this case, the laser beam LB can irradiate the cover layer CVL (e.g., the end of the second sub-cover layer SBL2) disposed in the groove GR. As a result, the end of the second sub-cover layer SBL2 can be at least partially carbonized. The carbonized area can have, for example, a black color.

[0193] When the aforementioned laser cutting process is completed, Figure 13 The two edge portions EG of the base substrate BSUB are removed as shown in . For example, the edge portion EG of the base substrate BSUB that is arranged outside the area irradiated by the laser beam LB can be removed. In this case, because the adhesive force between the inclined surface S of the cover layer CVL and the inclined surface of the edge portion EG facing the inclined surface S is small, when the portion of the base substrate BSUB corresponding to the apex of the above-mentioned groove GR is removed by irradiation of the laser beam LB, the edge portion EG of the base substrate BSUB can be easily removed from the main body of the base substrate BSUB. Therefore, by Figure 12 and Figure 13 The laser cutting process is used to remove the edge portion EG of the base substrate BSUB, thereby forming a single cell unit substrate (eg, semiconductor substrate SSUB). Then, as shown in FIG. Figure 14 As shown in , a cover layer CVL disposed on a top surface of the intermediate layer LL, side surfaces of the intermediate layer LL, and side surfaces of the semiconductor substrate SSUB may be formed.

[0194] Afterwards, if Figure 15 As shown in , the polarizing plate POL may be disposed on the top surface of the cover layer CVL over the intermediate layer LL. For example, the polarizing plate POL may be disposed on the first sub-cover layer SBL1 of the cover layer CVL.

[0195] Figure 16 is a cross-sectional view of a display device according to one or more embodiments.

[0196] Figure 16 The display device and the aforementioned Figure 7 The display device of FIG. 1 is different in the shape of a substrate (eg, a semiconductor substrate SSUB) and a shape of a cover layer CVL. The following description will focus on the differences.

[0197] The semiconductor substrate SSUB may have at least one groove GR. Figure 16 As shown in FIG, the groove GR may be formed at the edge of the semiconductor substrate SSUB. The groove GR may be formed in the semiconductor substrate SSUB in a concave shape in the third reverse direction. The groove GR may have a shape as shown in FIG. Figure 16 . For example, the groove GR may have a triangular cross-section with a width gradually decreasing along the third reverse direction. According to one or more embodiments, the groove GR may have a closed curve shape around the middle layer LL (e.g., surrounding the middle layer LL) in a plan view. For example, the groove GR may have a quadrilateral ring shape around the middle layer LL (e.g., surrounding the middle layer LL) in a plan view.

[0198] like Figure 16 In the example shown in FIG, the cover layer CVL may include a first sub-cover layer SBL1 and a second sub-cover layer SBL2.

[0199] because Figure 16 The first sub-cover layer SBL1 is the same as the aforementioned Figure 7 The first sub-cover layer SBL1 is the same, so use Figure 7 The description of the first sub-cover layer SBL1 is replaced by Figure 16 Description of the first sub-cover layer SBL1.

[0200] Figure 16 The second sub-cover layer SBL2 may extend from the first sub-cover layer SBL1. For example, the second sub-cover layer SBL2 may extend from the side surface of the first sub-cover layer SBL1 in a third reverse direction. In other words, the second sub-cover layer SBL2 may extend in a direction perpendicular to the extending direction of the first sub-cover layer SBL1. Figure 16 The second sub-cover layer SBL2 may be disposed on the side surface of the intermediate layer LL and the top surface of the semiconductor substrate SSUB (e.g., the top surface of the edge of the semiconductor substrate SSUB). In this case, a portion of the second sub-cover layer SBL2 may be disposed in the groove GR of the semiconductor substrate SSUB. According to one or more embodiments, the portion of the second sub-cover layer SBL2 may have the same cross-sectional shape as the groove GR. For example, the portion of the second sub-cover layer SBL2 disposed in the groove GR may have a triangular cross-sectional shape.

[0201] According to one or more embodiments, Figure 16 The second sub-cover layer SBL2 may have an oblique inclined surface S. For example, the second sub-cover layer SBL2 may have the inclined surface S at one end, and the inclined surface S may be provided on the side surface of the semiconductor substrate SSUB. The inclined surface S may allow the second sub-cover layer SBL2 to have an angle less than 90 degrees at a portion overlapping with the side surface of the semiconductor substrate SSUB. For example, at one end of the second sub-cover layer SBL2 overlapping with the side surface of the semiconductor substrate SSUB, the inner angle of the second sub-cover layer SBL2 may be an acute angle. According to one or more embodiments, at least a portion of the inclined surface S of the second sub-cover layer SBL2 may have a carbonized region.

[0202] according to Figure 16 In the display device of one or more embodiments shown in FIG, since the cover layer CVL is disposed in the groove GR, the contact area between the cover layer CVL and the semiconductor substrate SSUB can be further increased. Therefore, the interfacial delamination phenomenon between the cover layer CVL and the semiconductor substrate SSUB can be further reduced or minimized, and the penetration path of external air and moisture can be more effectively blocked.

[0203] Figures 17 to 23 is a process cross-sectional view illustrating a method for manufacturing a display device according to one or more embodiments. For example, Figures 17 to 23 It can be used to describe the method for making the aforementioned Figure 16 A process cross-sectional view of a method for displaying a device.

[0204] First, if Figure 17 As shown in FIG, an intermediate layer LL may be provided on a mother substrate (e.g., a semiconductor substrate SSUB) including a base substrate BSUB. Here, as described above, the base substrate BSUB may include a well region WA, a source region SA, a drain region DA, a channel region CH, a first low-concentration impurity region LDD1, and a second low-concentration impurity region LDD2. According to one or more embodiments, the mother substrate may include a wafer.

[0205] The middle layer LL may include the first semiconductor insulating layer SINS1, the second semiconductor insulating layer SINS2, the third semiconductor insulating layer SINS3, the lower insulating layer BINS, the side insulating layer SINS, the gate electrode GE, the plurality of contact terminals CTE, the light emitting element backplane EBP, the display element layer EML, the encapsulation layer TFE, the organic layer APL, the optical layer OPL and the filling layer FIL described above.

[0206] like Figure 18As shown in FIG, a first groove GR1 and a second groove GR2 may be formed at an edge of the base substrate BSUB. Each of the first groove GR1 and the second groove GR2 may be formed in the base substrate BSUB in a concave shape in a third reverse direction.

[0207] The first groove GR1 may have a Figure 18 . For example, the first groove GR1 may have a triangular cross-section with a width gradually decreasing along the third reverse direction. According to one or more embodiments, the first groove GR1 may have a closed curve shape around (e.g., surrounding) the middle layer LL in a plan view. For example, the first groove GR1 may have a quadrilateral ring shape around (e.g., surrounding) the middle layer LL in a plan view.

[0208] The second groove GR2 may have a Figure 18 . For example, the second groove GR2 may have a triangular cross-section with a width gradually decreasing along the third reverse direction. According to one or more embodiments, the second groove GR2 may have a closed curve shape around the middle layer LL and the first groove GR1 (e.g., surrounding the middle layer LL and the first groove GR1) in a plan view. For example, the second groove GR2 may have a quadrilateral ring shape around the middle layer LL and the first groove GR1 (e.g., surrounding the middle layer LL and the first groove GR1) in a plan view. In one or more embodiments, the first groove GR1 may be disposed between the second groove GR2 and the middle layer LL in a plan view.

[0209] According to one or more embodiments, the second groove GR2 may have a length greater than that of the first groove GR1 in a plan view. Here, the length of the first groove GR1 may be the sum of the dimension (e.g., length) of the first groove GR1 in the first direction DR1 and the dimension (e.g., length) of the first groove GR1 in the second direction DR2 in a plan view. Similarly, the length of the second groove GR2 may be the sum of the dimension (e.g., length) of the second groove GR2 in the first direction DR1 and the dimension (e.g., length) of the second groove GR2 in the second direction DR2 in a plan view.

[0210] The first groove GR1 and the second groove GR2 can be formed by partially removing the base substrate BSUB. For example, the first groove GR1 and the second groove GR2 can be formed by etching the base substrate BSUB. For example, the first groove GR1 and the second groove GR2 can be formed by selectively etching the edges of the base substrate BSUB using an etchant and / or an etching gas.

[0211] Afterwards, if Figure 19As shown in , a cover layer CVL may be formed on the intermediate layer LL and the base substrate BSUB. In this case, the cover layer CVL may be disposed on the top surface of the intermediate layer LL and the side surface of the intermediate layer LL. In addition, the cover layer CVL may be partially disposed in the first groove GR1 and the second groove GR2 of the base substrate BSUB. For example, the first sub-cover layer SBL1 of the cover layer CVL may be disposed on the intermediate layer LL, the second sub-cover layer SBL2 of the cover layer CVL may be disposed on the side surface of the intermediate layer LL, and a portion of the second sub-cover layer SBL2 of the cover layer CVL may be disposed in the first groove GR1 and the second groove GR2 of the base substrate BSUB. According to one or more embodiments, the portion of the second sub-cover layer SBL2 may have the same cross-sectional shape as the first groove GR1 and the second groove GR2. For example, the portion of the second sub-cover layer SBL2 disposed in the first groove GR1 and the second groove GR2 may have a triangular cross-section.

[0212] According to one or more embodiments, the cover layer CVL may be patterned through a patterning process to be disposed on the top surface of the middle layer LL and the side surface of the middle layer LL, and as shown in FIG. Figure 19 As shown in FIG, the first groove GR1 and the second groove GR2 of the base substrate BSUB are disposed in the first groove GR1 and the second groove GR2 of the base substrate BSUB. The aforementioned patterning process may include, for example, a photolithography process and / or an etching process. As a specific example, a polymer resin may be applied (or coated) on the filling layer FIL of the intermediate layer LL and the base substrate BSUB to form a polymer resin layer. The polymer resin layer may then be patterned using the aforementioned photolithography process and / or etching process to form the cover layer CVL.

[0213] Then, if Figure 20 and Figure 21 As shown in , a process of removing a portion of the base substrate BSUB may be performed. For example, the process of removing a portion of the base substrate BSUB may include a dicing process of cutting the base substrate BSUB into units (or wafer chips).

[0214] The aforementioned cutting process of the base substrate BSUB may be performed, for example, by a laser cutting process. Figure 20As shown in , the laser beam LB can be irradiated from below the base substrate BSUB toward the second groove GR2 of the base substrate BSUB in the third direction DR3. According to one or more embodiments, the laser beam LB can be irradiated toward the vertex of the triangular second groove GR2. For example, the laser beam LB can be irradiated toward the vertex of the second groove GR2 disposed at the outermost portion (or having the largest length in a plan view) among the plurality of grooves GR1 and GR2. In this case, the laser beam LB can be irradiated toward the portion of the second groove GR2 located at the lowermost portion of the base substrate BSUB (e.g., the vertex of the second groove GR2). The laser beam LB can then penetrate the base substrate BSUB and reach the vertex of the second groove GR2. In this case, the laser beam LB can be irradiated to the cover layer CVL disposed in the second groove GR2 (e.g., the end portion of the second sub-cover layer SBL2). As a result, the end portion of the second sub-cover layer SBL2 can be at least partially carbonized. The carbonized area can have, for example, a black color.

[0215] When the aforementioned laser cutting process is completed, Figure 21 The two edge portions EG of the base substrate BSUB are removed as shown in . For example, the edge portion EG of the base substrate BSUB disposed outside the area irradiated by the laser beam LB can be removed. In this case, because the adhesive force between the inclined surface S of the cover layer CVL and the inclined surface of the edge portion EG facing the inclined surface S is small, when the portion of the base substrate BSUB corresponding to the vertex of the aforementioned second groove GR2 is removed by irradiation of the laser beam LB, the edge portion EG of the base substrate BSUB can be easily removed from the main body of the base substrate BSUB. Therefore, by Figure 20 and Figure 21 The laser cutting process is used to remove the edge portion EG of the base substrate BSUB, thereby forming a single unit substrate (eg, semiconductor substrate SSUB). Then, as Figure 22 As shown in , a cover layer CVL disposed on a top surface of the intermediate layer LL, side surfaces of the intermediate layer LL, and side surfaces of the semiconductor substrate SSUB may be formed.

[0216] Afterwards, if Figure 23 As shown in , the polarizing plate POL may be disposed on the top surface of the cover layer CVL over the intermediate layer LL. For example, the polarizing plate POL may be disposed on the first sub-cover layer SBL1 of the cover layer CVL.

[0217] Figure 24 is a cross-sectional view of a display device according to one or more embodiments.

[0218] Figure 24 The display device and the aforementioned Figure 16 or Figure 23The display device of FIG. 1 is different in the shape of the semiconductor substrate SSUB and the shape of the cover layer CVL. The following description will focus on the differences.

[0219] like Figure 24 As shown in FIG, the semiconductor substrate SSUB may have at least one groove GR1 and GR2. Figure 24 As shown in FIG, the first groove GR1 and the second groove GR2 may be formed at an edge of the semiconductor substrate SSUB. Each of the first groove GR1 and the second groove GR2 may be formed in the semiconductor substrate SSUB in a concave shape in the third reverse direction.

[0220] The first groove GR1 may have a Figure 24 . For example, the first groove GR1 may have a triangular cross-section with a width gradually decreasing along the third reverse direction. According to one or more embodiments, the first groove GR1 may have a closed curve shape around (e.g., surrounding) the middle layer LL in a plan view. For example, the first groove GR1 may have a quadrilateral ring shape around (e.g., surrounding) the middle layer LL in a plan view.

[0221] The second groove GR2 may have a Figure 24 . For example, the second groove GR2 may have a triangular cross-section with a width gradually decreasing along the third reverse direction. According to one or more embodiments, the second groove GR2 may have a closed curve shape around the middle layer LL and the first groove GR1 (e.g., surrounding the middle layer LL and the first groove GR1) in a plan view. For example, the second groove GR2 may have a quadrilateral ring shape around the middle layer LL and the first groove GR1 (e.g., surrounding the middle layer LL and the first groove GR1) in a plan view. In one or more embodiments, the first groove GR1 may be disposed between the second groove GR2 and the middle layer LL in a plan view.

[0222] According to one or more embodiments, the second groove GR2 may have a length greater than that of the first groove GR1 in a plan view. Here, the length of the first groove GR1 may be the sum of the dimension (e.g., length) of the first groove GR1 in the first direction DR1 and the dimension (e.g., length) of the first groove GR1 in the second direction DR2 in a plan view. Similarly, the length of the second groove GR2 may be the sum of the dimension (e.g., length) of the second groove GR2 in the first direction DR1 and the dimension (e.g., length) of the second groove GR2 in the second direction DR2 in a plan view.

[0223] like Figure 24 In the example shown in FIG, the cover layer CVL may include a first sub-cover layer SBL1 and a second sub-cover layer SBL2.

[0224] because Figure 24 The first sub-cover layer SBL1 is the same as the aforementioned Figure 7 The first sub-cover layer SBL1 is the same, so use Figure 7 The description of the first sub-cover layer SBL1 is replaced by Figure 24 Description of the first sub-cover layer SBL1.

[0225] Figure 24 The second sub-cover layer SBL2 may extend from the first sub-cover layer SBL1. For example, the second sub-cover layer SBL2 may extend from the side surface of the first sub-cover layer SBL1 in a third reverse direction. In other words, the second sub-cover layer SBL2 may extend in a direction perpendicular to the extending direction of the first sub-cover layer SBL1. Figure 24 The second sub-cover layer SBL2 may be disposed on the side surface of the intermediate layer LL and the top surface of the semiconductor substrate SSUB (e.g., the top surface of the edge of the semiconductor substrate SSUB). In this case, the second sub-cover layer SBL2 may be partially disposed within the first and second grooves GR1 and GR2 of the semiconductor substrate SSUB. According to one or more embodiments, the portion of the second sub-cover layer SBL2 may have the same cross-sectional shape as the first and second grooves GR1 and GR2. For example, the portion of the second sub-cover layer SBL2 disposed within the first and second grooves GR1 and GR2 may have a triangular cross-sectional shape.

[0226] According to one or more embodiments, Figure 24 The second sub-cover layer SBL2 may have an oblique inclined surface S. For example, the second sub-cover layer SBL2 may have the inclined surface S at one end, and the inclined surface S may be provided on the side surface of the semiconductor substrate SSUB. The inclined surface S may allow the second sub-cover layer SBL2 to have an angle less than 90 degrees at a portion overlapping with the side surface of the semiconductor substrate SSUB. For example, at one end of the second sub-cover layer SBL2 overlapping with the side surface of the semiconductor substrate SSUB, the inner angle of the second sub-cover layer SBL2 may be an acute angle. According to one or more embodiments, at least a portion of the inclined surface S of the second sub-cover layer SBL2 may have a carbonized region.

[0227] As such, the display device according to one or more embodiments may include at least one groove GR1 and GR2.

[0228] According to one or more embodiments, when the display device has the plurality of grooves GR1 and GR2 , the plurality of grooves GR1 and GR2 may have greater lengths as they approach the side surface (or periphery) of the substrate (eg, semiconductor substrate SSUB).

[0229] According to one or more embodiments, Figure 24 In the display device, because the cover layer CVL is disposed in the grooves GR1 and GR2, the contact area between the cover layer CVL and the semiconductor substrate SSUB can be further increased. Therefore, the interfacial delamination phenomenon between the cover layer CVL and the semiconductor substrate SSUB can be further reduced or minimized, and the infiltration path of external air and moisture can be more effectively blocked.

[0230] Figure 25 is a perspective view illustrating a head-mounted display according to one or more embodiments. Figure 26 It shows Figure 25 An exploded perspective view of an example of a head-mounted display.

[0231] Reference Figure 25 and Figure 26 According to one or more embodiments, the head-mounted display 1000 includes a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head-mounted strap 1300, an intermediate frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600.

[0232] The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Figures 1 to 8 The display devices 10 described are substantially the same, so descriptions of the first display device 10_1 and the second display device 10_2 will be omitted.

[0233] The first optical member 1510 may be disposed between the first display device 10_1 and the first eyepiece 1210. The second optical member 1520 may be disposed between the second display device 10_2 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0234] The middle frame 1400 may be disposed between the first display device 10_1 and the control circuit board 1600 and between the second display device 10_2 and the control circuit board 1600. The middle frame 1400 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0235] The control circuit board 1600 may be disposed between the middle frame 1400 and the display device housing 1100. The control circuit board 1600 may be connected to the first display device 10_1 and the second display device 10_2 via a connector. The control circuit board 1600 may convert an image source input from the outside into digital video data DATA and transmit the digital video data DATA to the first display device 10_1 and the second display device 10_2 via the connector.

[0236] The control circuit board 1600 may transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 10_1, and may transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 10_2. Alternatively, the control circuit board 1600 may transmit the same digital video data DATA to both the first display device 10_1 and the second display device 10_2.

[0237] The display device housing 1100 is used to accommodate the first display device 10_1, the second display device 10_2, the middle frame 1400, the first optical member 1510, the second optical member 1520, and the control circuit board 1600. The housing cover 1200 is provided to cover one open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 at which the user's left eye is disposed and a second eyepiece 1220 at which the user's right eye is disposed. Figure 25 and Figure 26 It is shown that the first eyepiece 1210 and the second eyepiece 1220 are separately provided, but the present disclosure is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 may be combined into one.

[0238] The first eyepiece 1210 may be aligned with the first display device 10_1 and the first optical member 1510, and the second eyepiece 1220 may be aligned with the second display device 10_2 and the second optical member 1520. Therefore, the user may view the image of the first display device 10_1 magnified as a virtual image by the first optical member 1510 through the first eyepiece 1210, and may view the image of the second display device 10_2 magnified as a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0239] The head-mounted strap 1300 is used to fix the display device housing 1100 to the user's head so that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are respectively kept positioned on the user's left eye and right eye. When the display device housing 1100 is implemented to be lightweight and compact, the head-mounted display 1000 may be provided with a plurality of straps such as Figure 27 The eyeglass frame shown in FIG. 1 is not a headband 1300 .

[0240] In addition, the head-mounted display 1000 may further include a battery for supplying power, an external memory slot for accommodating an external memory, an external connection port for receiving an image source, and a wireless communication module. The external connection port may be a universal serial bus (USB) terminal, a display port, and / or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, and / or a Bluetooth module.

[0241] Figure 27 is a perspective view illustrating a head-mounted display according to one or more embodiments.

[0242] Reference Figure 27 The head-mounted display 1000_1 according to one or more embodiments may be a glasses-type display device in which the display device housing 1200_1 is implemented in a lightweight and compact manner. The head-mounted display 1000_1 according to one or more embodiments may include a display device 10_3, a left-eye lens 1010, a right-eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical member 1060, an optical path changing member 1070, and a display device housing 1200_1.

[0243] The display device housing 1200_1 may house the display device 10_3, the optical member 1060, and the optical path changing member 1070. The image displayed on the display device 10_3 may be magnified by the optical member 1060 and provided to the user's right eye through the right-eye lens 1020 after its optical path is changed by the optical path changing member 1070. As a result, the user may view, through the right eye, an augmented reality image in which a virtual image displayed on the display device 10_3 and a real image viewed through the right-eye lens 1020 are combined.

[0244] Figure 27 The display device housing 1200_1 is shown as being disposed at the right end of the support frame 1030, but the present disclosure is not limited thereto. For example, the display device housing 1200_1 may be disposed at the left end of the support frame 1030, and in this case, the image of the display device 10_3 can be provided to the user's left eye. Alternatively, the display device housing 1200_1 may be disposed at both the left and right ends of the support frame 1030, and in this case, the user can view the image displayed on the display device 10_3 with both the left eye and the right eye.

[0245] In summarizing the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the embodiments without departing substantially from the principles and scope of the present disclosure. Therefore, the embodiments of the present disclosure are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. A display device, comprising: substrate; an intermediate layer on the substrate and comprising a first electrode, a light-emitting layer on the first electrode, a second electrode on the light-emitting layer, and a filling layer on the second electrode; as well as a cover layer, on the intermediate layer, The covering layer is on the top surface of the intermediate layer, the side surface of the intermediate layer, and the side surface of the substrate.

2. The display device according to claim 1, wherein The covering layer is on the filling layer.

3. The display device according to claim 1, wherein The covering layer comprises: a first sub-covering layer on the intermediate layer; and A second sub-covering layer extends from the first sub-covering layer and is on the side surface of the intermediate layer and the side surface of the substrate.

4. The display device according to claim 3, wherein The first sub-covering layer is on the intermediate layer, and The second sub-covering layer is around the side surface of the intermediate layer and the side surface of the substrate.

5. The display device according to claim 3, wherein The second sub-cover layer has an obliquely inclined surface at one end. The display device according to claim 5 , wherein: The inclined surface of the second sub-cover layer is on the side surface of the substrate.

7. The display device according to claim 3, wherein: One end of the second sub-cover layer has a carbonized region.

8. The display device according to claim 1, wherein The cover layer surrounds the side surface of the intermediate layer and the side surface of the substrate.

9. The display device according to claim 1, wherein The intermediate layer is surrounded by the cover layer and the substrate.

10. The display device according to claim 1, wherein The base has a groove at the edge.

11. The display device according to claim 10, wherein: In plan view, the groove surrounds the intermediate layer.

12. The display device according to claim 10, wherein: The groove has a triangular cross-section.

13. The display device according to claim 10, wherein: A portion of the cover layer is in the groove.

14. The display device according to claim 10, wherein: The groove comprises a plurality of grooves, and The length of each of the plurality of grooves increases as the plurality of grooves are positioned closer to the side surface of the substrate.

15. The display device according to claim 14, wherein A portion of the cover layer is in each of the plurality of grooves. 16 . The display device according to claim 1 , further comprising a polarizing plate on the intermediate layer.

17. A display device, comprising: substrate; an intermediate layer on the substrate; as well as a cover layer, on the intermediate layer, Wherein, the intermediate layer includes a light-emitting layer, and The covering layer is on the top surface of the intermediate layer, the side surface of the intermediate layer, and the side surface of the substrate.

18. The display device according to claim 17, wherein: The cover layer surrounds the side surface of the intermediate layer and the side surface of the substrate.

19. The display device according to claim 17, wherein: The intermediate layer is surrounded by the cover layer and the substrate.

20. The display device according to claim 17, wherein The base has a groove at the edge.

21. The display device according to claim 20, wherein In plan view, the groove surrounds the intermediate layer.

22. The display device according to claim 20, wherein The groove has a triangular cross-section.

23. The display device according to claim 20, wherein A portion of the cover layer is in the groove.

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