A storage device, an electronic device, a data storage method, and a storage medium

Abstract

The application provides a storage device, an electronic device, a data storage method and a storage medium, relates to the technical field of data processing, and the storage device comprises a CXL interface module, a dynamic memory module, a flash memory module and a flash memory controller module; wherein the dynamic memory module comprises a plurality of device-side cycle areas, the flash memory module comprises a plurality of data placement units, and the device-side cycle areas and the data placement units correspond one by one; the CXL interface module is used for receiving host data from a host-side cycle area, and temporarily storing the host data into a device-side cycle area corresponding to the host-side cycle area in the dynamic memory module; the dynamic memory module is used for packaging the host data in the device-side cycle area after a preset time; and the flash memory controller module is used for storing the packaged host data into a data placement unit corresponding to the device-side cycle area in the flash memory module. The storage device effectively improves the write amplification phenomenon.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and in particular to a storage device, electronic device, data storage method, and storage medium. Background Technology

[0002] FDP SSD is a solution that optimizes flash memory storage efficiency through data classification management and collaborative recycling. Its core objective is to reduce the write amplification effect during garbage collection. Figure 1 As shown, its specific design is as follows: Multiple reclaim units and corresponding reclaim unit handles are divided within the physical address space of the flash memory medium. Each reclaim unit is aligned with multiple flash memory physical blocks, supporting synchronous erasure of internal data blocks. The reclaim unit handle, as a unique pointer to the reclaim unit, is responsible for managing host-written data. Each namespace, through its corresponding reclaim unit handle identifier, guides data transmission via a specific handle, enabling the distributed storage of different types of data to different reclaim units. During operation, the device first provides configuration information and a data allocation interface to the host, helping the host understand the resource topology. The host then classifies data according to its lifecycle and other characteristics, grouping similar data into the same reclaim unit to ensure consistent data expiration periods and synchronous reclaim unit recycling, thereby reducing the additional write operations caused by garbage collection.

[0003] Because FDP SSDs require integrating an NVMe module into the controller and transmitting data and physical address space information via the PCIe interface and NVMe controller, this design is only suitable for traditional NVMe over PCIe SSDs. For CXL-SSDs, adding an additional NVMe controller and transmitting data and address information via the CXL.io sub-protocol sacrifices the low-latency transmission advantages that the CXL.mem protocol should offer. Furthermore, since the NVMe protocol is better suited for large data block transmissions, processing small data blocks such as 64 bytes requires packaging them into pages in the device-side DRAM before writing them to flash memory via the flash controller. The host's operation of individually marking each small data block significantly increases data processing complexity and impacts overall performance. Summary of the Invention

[0004] This application provides a storage device, an electronic device, a data storage method, and a storage medium to at least solve the above-mentioned technical problems existing in the prior art.

[0005] According to a first aspect of this application, a storage device is provided, the storage device including a CXL interface module, a dynamic memory module, a flash memory module, and a flash memory controller module; wherein, the dynamic memory module includes multiple device-side periodic regions, the flash memory module includes multiple data placement units, and the device-side periodic regions correspond one-to-one with the data placement units;

[0006] The CXL interface module is configured to receive host data from a host-side periodic region and temporarily store the host data in a device-side periodic region corresponding to the host-side periodic region in the dynamic memory module.

[0007] The dynamic memory module is configured to encapsulate the host data in the device-side periodic region after a preset time.

[0008] The flash memory controller module is configured to store the encapsulated host data in a data placement unit corresponding to the device-side periodic region in the flash memory module.

[0009] In an implementation, the CXL interface module includes a data placement unit register and a write cache register.

[0010] The data placement unit register is configured to record first hardware information of each data placement unit in the flash memory module.

[0011] The write cache register is configured to record second hardware information of each device-side periodic region in the dynamic memory module, so that the host creates a host-side periodic region based on the first hardware information and the second hardware information.

[0012] In an implementation, the dynamic memory module further includes a logical address and physical address mapping table.

[0013] The logical address and physical address mapping table is configured to record a mapping relationship between a logical address of a device-side periodic region and a physical address of a data placement unit, so that the flash memory controller module determines a data placement unit corresponding to the device-side periodic region.

[0014] In an implementation, the CXL interface module includes a CXL.mem protocol layer configured to receive host data from a host-side periodic region and temporarily store the host data in a device-side periodic region corresponding to the host-side periodic region in the dynamic memory module.

[0015] In an implementation, the CXL interface module further includes a CXL.io protocol layer configured to send the first hardware information and the second hardware information to the host.

[0016] In an implementation, each data placement unit includes a plurality of flash memory data blocks.

[0017] In an implementation, when host data in a flash memory data block needs to be updated, the updated host data is written into another flash memory data block in the same data placement unit, and the original flash memory data block is erased.

[0018] In an implementation, the dynamic memory module further comprises a data packaging layer, the data packaging layer comprising a plurality of cycle area pages; the cycle area pages correspond to the device-side cycle areas and the data placement units respectively;

[0019] The cycle area pages are configured to receive and temporarily store packaged host data.

[0020] According to a second aspect of the present application, an electronic device is provided, the electronic device comprising a host and a storage device; the storage device comprising a CXL interface module, a dynamic memory module, a flash memory module, and a flash memory controller module; wherein the dynamic memory module comprises a plurality of device-side cycle areas, the flash memory module comprises a plurality of data placement units, and the device-side cycle areas correspond to the data placement units one by one;

[0021] The host is configured to place host data into a host-side cycle area corresponding to an update frequency of the host data according to the update frequency of the host data.

[0022] The CXL interface module is configured to receive host data from a host-side cycle area and temporarily store the host data in a device-side cycle area corresponding to the host-side cycle area in the dynamic memory module.

[0023] The dynamic memory module is configured to package host data in the device-side cycle area after a preset time.

[0024] The flash memory controller module is configured to store packaged host data in a data placement unit corresponding to the device-side cycle area in the flash memory module.

[0025] In an implementation, the CXL interface module comprises a data placement unit register and a write cache register; wherein,

[0026] The data placement unit register is configured to record first hardware information of each data placement unit in the flash memory module.

[0027] The write cache register is configured to record second hardware information of each device-side cycle area in the dynamic memory module.

[0028] The host is configured to obtain the first hardware information and the second hardware information, and construct a host-side cycle area based on the first hardware information and the second hardware information.

[0029] In an implementation, the host is further configured to,

[0030] determine the number of host-side cycle areas and the logical address range of each host-side cycle area based on the first hardware information and the second hardware information.

[0031] constructing a host-side periodic region based on the number of the host-side periodic regions, and the logical address range of each host-side periodic region.

[0032] In an implementable manner, the host is further configured to determine a time interval for sending host data to the storage device based on the first hardware information and the second hardware information.

[0033] According to a third aspect of the present application, a data storage method is provided, which is applied to a storage device including a CXL interface module, a dynamic memory module, a flash memory module, and a flash memory controller module; wherein the dynamic memory module includes a plurality of device-side periodic regions, the flash memory module includes a plurality of data placement units, and the device-side periodic regions correspond to the data placement units one by one; the method includes:

[0034] receiving host data from a host-side periodic region through the CXL interface module, and temporarily storing the host data in a device-side periodic region corresponding to the host-side periodic region in the dynamic memory module;

[0035] after a preset time, encapsulating the host data in the device-side periodic region through the dynamic memory module;

[0036] storing the encapsulated host data in a data placement unit corresponding to the device-side periodic region in the flash memory module through the flash memory controller module.

[0037] In an implementable manner, the CXL interface module includes a data placement unit register and a write cache register, and the method further includes:

[0038] recording first hardware information of each data placement unit in the flash memory module in the data placement unit register;

[0039] recording second hardware information of each device-side periodic region in the dynamic memory module in the write cache register; so that the host creates a host-side periodic region based on the first hardware information and the second hardware information.

[0040] In an implementable manner, the dynamic memory module further includes a logical address and physical address mapping table, and the storing of the encapsulated host data in the data placement unit corresponding to the device-side periodic region in the flash memory module includes:

[0041] obtaining a mapping relationship between the logical address of the device-side periodic region and the physical address of the data placement unit recorded in the logical address and physical address mapping table;

[0042] According to the mapping relationship, the encapsulated host data is stored into a data placement unit corresponding to the device-side periodic area in the flash memory module.

[0043] In an implementation, the CXL interface module includes a CXL.mem protocol layer, and correspondingly,

[0044] The receiving of the host data from the host-side periodic area and the temporary storage of the host data into the device-side periodic area corresponding to the host-side periodic area in the dynamic memory module include:

[0045] The receiving of the host data from the host-side periodic area and the temporary storage of the host data into the device-side periodic area corresponding to the host-side periodic area in the dynamic memory module include:

[0046] In an implementation, the CXL interface module further includes a CXL.io protocol layer, and the method further includes:

[0047] The sending of the first hardware information and the second hardware information to the host through the CXL.io protocol layer.

[0048] In an implementation, each data placement unit includes a plurality of flash data blocks, and the method further includes:

[0049] When the host data in a flash data block needs to be updated, the updated host data is written into another flash data block of the same data placement unit, and the original flash data block is erased.

[0050] In an implementation, the dynamic memory module further includes a data encapsulation layer, the data encapsulation layer includes a plurality of periodic area pages, and the periodic area pages correspond to the device-side periodic areas and the data placement units one by one. The method further includes:

[0051] The receiving and temporary storage of the encapsulated host data through the periodic area pages.

[0052] According to a fourth aspect of the present application, a non-transitory computer readable storage medium storing computer instructions is provided, the computer instructions being used to make the computer execute the method described in the present application.

[0053] The storage device, electronic device, data storage method, and storage medium of this application achieve efficient data storage management by dividing the dynamic memory module of the storage device into multiple device-side periodic areas and the flash memory module into multiple data placement units, establishing a one-to-one correspondence between the device-side periodic areas and the data placement units. When writing data, host data is obtained through the CXL interface module and temporarily stored in the corresponding device-side periodic area. After a preset time, the data in the device-side periodic area is encapsulated, and then the encapsulated data is stored in the corresponding data placement unit. Since data with the same failure characteristics are grouped together in the same data placement unit, when the original data needs to be updated, the updated data can be directly written to other locations within the same data placement unit without additional data transfer operations. This effectively reduces write amplification while leveraging the low latency advantage of the CXL interface.

[0054] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0055] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of this application are illustrated in the drawings by way of example and not limitation, in which:

[0056] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

[0057] Figure 1 This diagram illustrates the principle of FDP SSD technology in the prior art.

[0058] Figure 2 A schematic diagram of the composition structure of a storage device according to an embodiment of this application is shown;

[0059] Figure 3 A schematic diagram of the composition structure of another storage device according to an embodiment of this application is shown;

[0060] Figure 4 A schematic diagram of the composition structure of an electronic device according to an embodiment of this application is shown;

[0061] Figure 5 A schematic diagram of the composition structure of another electronic device according to an embodiment of this application is shown;

[0062] Figure 6 This illustration shows an application scenario diagram of an electronic device according to an embodiment of this application;

[0063] Figure 7An implementation flow diagram of a data storage method is shown.

[0064] Figure 8 A component structure diagram of an electronic device is shown. DETAILED DESCRIPTION

[0065] To make the purposes, characteristics and advantages of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0066] The CXL (Compute Express Link) protocol is composed of three sub-protocols, CXL.io, CXL.cache and CXL.mem. Among them, CXL.io is used to implement the basic communication protocol, responsible for discovering devices, reporting interrupts, initializing basic functions, etc. CXL.cache is used to implement the device-side cache system memory, ensuring cache consistency. CXL.mem is used to allow the CPU to directly access the device memory with other CXL devices. To be compatible with the existing PCIe ecosystem, CXL devices dynamically multiplex the sub-protocol stack on the PCIe physical layer (PHY) to achieve compatibility with the PCIe protocol.

[0067] On the basis of the CXL protocol, the related technology proposes a CXL-SSD (CXL interface solid state disk), the core architecture of which is to combine with flash media through CXL.mem and CXL.io interfaces, and use a large-capacity dynamic random access memory (DRAM) as the cache of the back-end flash. This device can not only take advantage of the non-volatility and high storage density of flash, but also can realize the direct access of CPU to the device memory through the CXL.mem interface, greatly improving the access speed.

[0068] However, due to the characteristics of flash media not supporting direct overwrite of data, CXL-SSD faces special restrictions when performing data update operations. That is, when existing data needs to be modified, the content cannot be directly rewritten at the original storage location, but must be marked as invalid through an address mapping table, and the updated data is written in a new physical storage location.

[0069] With the accumulation of invalid data, the CXL-SSD needs to start a garbage collection mechanism to recover storage space. This process needs to migrate valid data in the block where the invalid data is located to a new storage block, and then perform a whole erase operation on the original storage block. In this process, the migration of valid data will generate additional write operations, causing the actual write amount of the flash medium to far exceed the logical data update amount initiated by the user, i.e., the "write amplification" phenomenon. Since the service life of the flash medium directly depends on the number of erase-write cycles, the existence of the write amplification phenomenon will significantly increase the actual erase-write frequency of the flash, accelerate the aging process of the medium, and ultimately shorten the service life of the CXL-SSD.

[0070] To solve this problem, currently, technologies such as ZNS (Zone Namespace) and FDP (Flexible Data Placement) are commonly used, and the core principle is to manage the physical address of data in the flash medium through the host to reduce write amplification. However, these solutions rely on the NVMe (Non-Volatile Memory Express) standard protocol implementation, but if the CXL-SSD transmits data placement information through the CXL.io interface and the NVMe controller, the low-latency advantage of the CXL interface will be lost, and the technical characteristics cannot be fully utilized.

[0071] To solve the above problems, the first aspect of the embodiments of the present application proposes a storage device, such as Figure 2 As shown, the storage device includes a CXL interface module, a dynamic memory module, a flash module, and a flash controller module. The dynamic memory module includes a plurality of device-side cycle areas, the flash module includes a plurality of data placement units, and the device-side cycle areas and the data placement units correspond one-to-one; the CXL interface module is configured to receive host data from a host-side cycle area and temporarily store the host data in a device-side cycle area corresponding to the host-side cycle area in the dynamic memory module; the dynamic memory module is configured to encapsulate the host data in the device-side cycle area after a preset time; and the flash controller module is configured to store the encapsulated host data in a data placement unit corresponding to the device-side cycle area in the flash module.

[0072] The device-side cycle area refers to a plurality of independent temporary storage areas divided in the dynamic memory module. The data placement unit refers to a plurality of logical units divided in the flash memory module for long-term storage of data. The device-side cycle area and the data placement unit establish a one-to-one corresponding association relationship through a preset mapping rule, which can be implemented through number matching or address mapping table and the like. For example, N device-side cycle areas are divided in the dynamic memory module, which are sequentially named as device-side cycle area 1, device-side cycle area 2, device-side cycle area 3,..., and device-side cycle area N. At the same time, the same number of data placement units are divided in the physical address space of the flash memory module, which are sequentially numbered as data placement unit 1, data placement unit 2, data placement unit 3,..., and data placement unit N. Through the mapping relationship, the host data temporarily stored in the device-side cycle area 1 will be finally written into the data placement unit 1, the host data temporarily stored in the device-side cycle area 2 will be finally written into the data placement unit 2, and so on, forming a mapping link from temporary storage to long-term storage.

[0073] The specific working process of the storage device is as follows: the CXL interface module serves as a communication bridge between the host and the storage device, and is responsible for receiving host data from the host-side cycle area. Before this, the host end will classify the data generated in its own running process according to the characteristics of the data, and allocate different types of data to the corresponding host-side cycle area. The data classification can be based on the dynamic update characteristics of the data, for example, the data with high update activity is placed in the high-level host-side cycle area, and the data with less update is placed in the low-level host-side cycle area. Here, the level of the host-side cycle area can be defined according to the numbering rule, for example, the lower the number, the higher the corresponding level. Specifically, the host-side cycle area 1 is used to store the data with the highest update activity, the host-side cycle area 2 is used to store the data with the second highest update activity, and so on, and the host-side cycle area N corresponds to the data with the lowest update activity. The specific division standard corresponding to each host-side cycle area is set by the host end according to the actual demand. For example, the host can allocate the high-frequency update data generated in real-time interaction to the cycle area 1, and allocate the low-frequency update data archived in stages to the cycle area N. One of the implementable schemes can refer to Table 1 as follows:

[0074] Table 1

[0075]

[0076] The host-side periodic area and the device-side periodic area also have a one-to-one mapping relationship, so the CXL interface module can directly store the received host data in the matching device-side periodic area in the dynamic memory based on this mapping relationship. The dynamic memory module encapsulates the host data in the device-side periodic area after a preset time of data storage, and integrates multiple small-size data packets into a large-size page data. Finally, the flash controller module writes the encapsulated page data into the data placement unit corresponding to the device-side periodic area in the flash module, completing the persistent storage of the data.

[0077] The scheme of the embodiment places data with the same update frequency in the same data placement unit, so when the original data needs to be updated, the updated data can be directly written to another position in the same data placement unit, without the need for additional data moving operations. This can effectively reduce the write amplification effect while taking advantage of the low latency of the CXL interface. The CXL-SSD achieves the purpose of flexible data placement without relying on the NVMe module. Moreover, since the NVMe module is not used, the area and power consumption of the CXL-SSD are reduced.

[0078] In another embodiment of the present application, as shown in Figure 3 The CXL interface module includes a CXL.mem protocol layer for receiving host data from the host-side periodic area and temporarily storing the host data in the device-side periodic area corresponding to the host-side periodic area in the dynamic memory module.

[0079] The core function of the CXL.mem protocol layer is to receive host data from the host-side periodic area and temporarily store these data in the device-side periodic area corresponding to the host-side periodic area in the dynamic memory module. The key feature of the CXL.mem protocol layer is that it enables the device-side memory to become a memory directly managed by the host (i.e., Host-Managed Memory, HDM, such as HDM-H mode). The protocol sets up bidirectional communication channels for data transmission, including the Master-to-Subordinate (M2S) and Subordinate-to-Master (S2M) directions. The M2S direction includes a request channel (for data read requests), a data-bearing request channel (for data write requests), and a Back-Invalidate Response channel. The S2M direction includes a No-Data-Response (NDR) channel, a Data-Response (DRS) channel, and a Back-Invalidate Snoop channel. To achieve the goals of protocol logic simplification and low-latency transmission, there are no mandatory ordering constraints between these channels, ensuring efficient and flexible data interaction.

[0080] In another embodiment of the present application, as shown in Figure 3 The CXL interface module further includes a CXL.io protocol layer for sending the first hardware information and the second hardware information to the host.

[0081] The CXL.io protocol is based on the extension of the traditional PCIe protocol, which can be used for device discovery, configuration initialization, I / O virtualization, and support for core functions such as non-coherent cache-based direct memory access (DMA). In the present scheme, the host realizes the acquisition of the hardware information of the storage device through the CXL.io protocol layer. Specifically, the host sends a CXL.io configuration TLP (Transaction Layer Packet) package to the storage device to read the information related to the data placement unit and the device-side periodic area. After receiving the request, the storage device side returns the first hardware information and the second hardware information to the host.

[0082] As shown in Figure 3 The CXL interface module further includes a PHY layer (Physical Layer, port physical layer) and a CXL.mem / CXL.io multiplexing\arbitration module. Among them, the PHY layer is the basic unit of physical transmission, which is responsible for the training task in the link initialization stage, and is also responsible for the serial-parallel conversion (serial data to parallel data or parallel data to serial data) and clock recovery function, to ensure the stable transmission of data on the physical link. The CXL.mem and CXL.io two protocol stacks multiplex the hardware resources of the PCIe PHY layer to realize the sending and receiving of their own protocol data, without the need to configure a physical transmission layer for different protocols, which improves the utilization rate of hardware resources. The CXL.mem / CXL.io multiplexing\arbitration module is used for unified scheduling and management of the data streams of the two protocols. When CXL.mem and CXL.io protocols exist data transmission requirements at the same time, this module coordinates the use of PHY layer resources by the two through a preset arbitration strategy, avoids data transmission conflicts, ensures the efficient transmission of high-priority protocol data (such as low-latency CXL.mem data), and at the same time guarantees the stability and throughput of the overall link.

[0083] In another embodiment of the present application, as shown in Figure 3 The CXL interface module further includes a data placement unit register and a write cache register. The data placement unit register is used to record the first hardware information of each data placement unit in the flash module; the write cache register is used to record the second hardware information of each device-side periodic area in the dynamic memory module, so that the host creates a host-side periodic area based on the first hardware information and the second hardware information.

[0084] The data placement unit register is used to record the first hardware information of each data placement unit in the flash memory module. The first hardware information can be the number of data placement units, the size of the flash data block contained in each data placement unit, the number of physical pages contained in each flash data block, and the fixed size of data in the page. The write cache register is used to record the second hardware information of the device-side periodic area in the dynamic memory module. The second hardware information can be the number of data units (Data) in each device-side periodic area.

[0085] In an implementation, the structure of the data placement unit register can be as shown in Table 2 below:

[0086] Table 2

[0087]

[0088] In an implementation, the structure of the write cache register can be as shown in Table 3 below:

[0089] Table 3

[0090]

[0091] In another embodiment of the present application, as shown in Figure 3 each data placement unit includes a plurality of flash data blocks . Each flash data block includes a plurality of fixed physical pages P, and the data size in the page is fixed as S. Based on the physical address space of the flash medium, a corresponding address range is independently divided for each data placement unit. The total physical address space T can be obtained by the following formula (1):

[0092] (1)

[0093] where N represents the number of data placement units; represents the number of flash data blocks contained in the i-th data placement unit; P is the fixed number of physical pages in each flash data block; and S is the data size of a single physical page.

[0094] Thus, in an implementation, the physical space address of each data placement unit can be as shown in Table 4:

[0095] Table 4

[0096]

[0097] The number of device-side periodic areas in the dynamic memory module is the same as the number of data placement units, both being N. Assuming that the total capacity is Q. Each device-side periodic area is composed of a plurality of data units, wherein the i-th device-side periodic area contains Each data unit has a fixed size of C. The total capacity Q of the dynamic memory module can be calculated by formula (2) as follows:

[0098] (2)

[0099] The N device-side cycle areas in the dynamic memory module and the N data placement units in the flash memory module form a one-to-one correspondence. After being processed by the data packaging area, the data in the host-side cycle area is stored in the data placement unit with the corresponding number (for example, the data in the host-side cycle area 1 is finally stored in the data placement unit 1). This strict correspondence determines that the logical address of each host-side cycle area can only be mapped to the physical address of the data placement unit with the corresponding number, and cannot be mapped across units.

[0100] The size of the flash memory physical address space of each data placement unit is (wherein is the number of flash memory data blocks contained in the data placement unit, P is the number of physical pages of each flash memory data block, and S is the size of a single page of data), and therefore the size of the address space of the corresponding host-side cycle area is also set to the same value However, due to the limited capacity of the dynamic memory module itself, the physical storage capacity actually allocated to a device-side cycle area i (i.e. , wherein is the number of data units contained in the device-side cycle area, and C is the fixed size of a single data unit) is often smaller than the flash memory physical address space of the corresponding data placement unit, i.e. .

[0101] Based on this capacity relationship, the address range that can access the device-side cycle area i is limited to (the start value and the end value of the address range are represented by the colons before and after the address range in the formula). This address range not only matches the physical address space of the corresponding data placement unit, but also avoids wasting address resources by being constrained by the limited capacity of the dynamic memory module, ensuring that the mapping relationship between the logical address and the physical address is clear and efficient.

[0102] In another embodiment of the present application, when the host data in the flash memory data block needs to be updated, the updated host data is written into other flash memory data blocks in the same data placement unit, and the original flash memory data block is erased.

[0103] When the host data stored in the flash memory data block needs to be updated, the newly generated update data is directly written into other idle flash memory data blocks in the same data placement unit. After the update data is successfully written into the new flash memory data block, the flash memory data block where the original data is located is erased to release the physical storage space.

[0104] Since all the data in the same data placement unit have similar invalidation periods, the update operation only needs to complete data migration and old block erasure among different flash data blocks within the data placement unit, without carrying other irrelevant data across the unit, thereby avoiding a large amount of invalid data carrying caused by scattered data storage in the traditional storage scheme, significantly reducing the write amplification effect in the flash storage process, and improving the data update efficiency and the service life of the flash medium.

[0105] In another embodiment of the present application, as shown in Figure 3 The dynamic memory module further includes a data packaging layer including a plurality of period area pages; the period area pages correspond one-to-one to the device-side period areas and the data placement units; and the period area pages are configured to receive and temporarily store packaged host data.

[0106] Each period area page is configured to receive and temporarily store packaged host data from the corresponding device-side period area. Specifically, when the temporarily stored data of the device-side period area reaches a preset condition, the data is packaged into a data block conforming to the size of a flash physical page, and then transmitted to the corresponding period area page in the data packaging layer for temporary storage, thereby providing a transition buffer for the subsequent flash controller to write data into the corresponding data placement unit, and ensuring that the link from data storage to final storage is coherent and efficient.

[0107] In another embodiment of the present application, as shown in Figure 3 The dynamic memory module further includes a logical address and physical address mapping table configured to record the mapping relationship between the logical address of the device-side period area and the physical address of the data placement unit, so that the flash controller module determines the data placement unit corresponding to the device-side period area.

[0108] Specifically, when the data in the device-side period area needs to be written into the flash medium after packaging, the flash controller module can quickly determine the physical storage location of the target data placement unit corresponding to the logical address of the current device-side period area by querying the mapping table, so as to accurately and efficiently direct the packaged data to the corresponding physical storage unit, ensure accurate mapping and reliable storage from the logical layer to the physical layer, and provide a key address conversion basis for data positioning and read-write operations of the entire storage system.

[0109] A second aspect of an embodiment of the present application provides an electronic device, as shown in Figure 4As shown, the electronic device includes a host and a storage device; the storage device includes a CXL interface module, a dynamic memory module, a flash memory module, and a flash memory controller module; wherein the dynamic memory module includes a plurality of device-side cycle areas, the flash memory module includes a plurality of data placement units, and the device-side cycle areas correspond one-to-one to the data placement units; the host is configured to place host data corresponding to an update frequency of the host data into a host-side cycle area corresponding to the update frequency; the CXL interface module is configured to receive host data from the host-side cycle area and temporarily store the host data in a device-side cycle area in the dynamic memory module corresponding to the host-side cycle area; the dynamic memory module is configured to encapsulate the host data in the device-side cycle area after a preset time; and the flash memory controller module is configured to store the encapsulated host data in a data placement unit in the flash memory module corresponding to the device-side cycle area.

[0110] The host side is provided with a plurality of host-side cycle areas, each of which stores host data with a specific update characteristic. In the data writing stage, the host will classify the data into the corresponding host-side cycle area according to the update characteristic of the data, and specify the logical address of the writing according to the allocated flash logical address space range, and then transmit the host data to the corresponding device-side cycle area. The data in the device-side cycle area will be encapsulated into pages after a preset time of temporary storage. Then, the flash memory controller stores the encapsulated data into the corresponding data placement unit. Since data with the same update characteristic is concentrated in the same data placement unit, the invalidation period remains consistent, so when the original data needs to be updated, the updated data can be directly written into other flash data blocks in the same data placement unit, and the original data block is erased, without relying on the NVMe module to achieve flexible placement of data in the CXL-SSD, thereby significantly reducing the write amplification effect.

[0111] In another embodiment of the present application, as shown in Figure 5 The CXL interface module includes a data placement unit register and a write cache register; wherein the data placement unit register is configured to record first hardware information of each data placement unit in the flash memory module; the write cache register is configured to record second hardware information of each device-side cycle area in the dynamic memory module; and the host is configured to obtain the first hardware information and the second hardware information, and construct a host-side cycle area based on the first hardware information and the second hardware information.

[0112] In the initial stage of power-on, a link training process is first performed, and through the link training process, it is ensured that the physical link between the host and the storage device reaches a stable and reliable data transmission state. After the link training is completed, the host starts a device enumeration operation. Specifically, the host sends a configuration TLP packet through the CXL.io protocol layer to read the data placement unit register and the write cache register on the storage device side. After receiving the request, the storage device returns the register data containing the first hardware information and the second hardware information to the host. According to the hardware information, the host completes the construction and configuration of the host-side periodic area, and prepares for subsequent data classification storage and transmission.

[0113] In another embodiment of the present application, the host is also used to determine the number of host-side periodic areas and the logical address range of each host-side periodic area based on the first hardware information and the second hardware information; and construct the host-side periodic area based on the number of host-side periodic areas and the logical address range of each host-side periodic area.

[0114] After the host obtains the first hardware information and the second hardware information, it will perform operations according to the calculation formula given in Table 4, and then determine the number of host-side periodic areas and the corresponding logical address range of each host-side periodic area.

[0115] In another embodiment of the present application, the host will also determine the time interval for sending host data to the storage device, i.e. the transmission delay, based on the first hardware information and the second hardware information. It ensures that the device-side periodic area has enough time to accumulate data from the host, thereby optimizing the performance of the entire storage link.

[0116] In a specific example, the above scheme is described as shown in Figure 6 The scheme includes:

[0117] 1. The host reads the data placement unit register and the write cache register on the storage device side through the CXL.io configuration TLP packet;

[0118] 2. After receiving the request, the storage device returns the values of the corresponding registers to the host;

[0119] 3. The host determines the number of host-side periodic areas, the memory address range of each host-side periodic area (i.e. the flash memory logical address range corresponding to the present scheme), and calculates the transmission delay of the host-side data according to these return values.

[0120] a. The host classifies and puts the data into the corresponding host-side periodic area according to the update frequency of the host data. For example, a batch of data is allocated to the host-side periodic area 2, the host specifies a specific write address from the flash memory logical address range corresponding to the host-side periodic area 2, and then transmits the data to the device-side periodic area 2 for temporary storage through the CXL.mem protocol;

[0121] b. The data in the device-side periodic area 2 is encapsulated into a page after a preset time of data storage, and placed in the periodic area 2 page;

[0122] c. The flash memory controller writes the data in the periodic area 2 page into a certain data block in the data placement unit 2 according to the mapping relationship between the logical address and the physical address.

[0123] Since the data update cycle frequency is similar, the invalidation time of all data in the entire data placement unit is similar. When the data needs to be updated, the new data is uniformly written into another flash memory data block in the data placement unit, and the original flash memory data block is erased, so that the partial data in the original flash memory data block does not need to be moved to the new data block, thereby avoiding the increase of write operation and the write amplification phenomenon. In theory, the write amplification factor can reach 1.

[0124] According to a third aspect of the embodiments of the present application, a data storage method is provided, which is applied to a storage device including a CXL interface module, a dynamic memory module, a flash memory module, and a flash memory controller module; wherein the dynamic memory module includes a plurality of device-side periodic areas, the flash memory module includes a plurality of data placement units, and the device-side periodic areas correspond to the data placement units one by one, as shown in Figure 7 The method includes:

[0125] receiving host data from a host-side periodic area through the CXL interface module, and storing the host data in a device-side periodic area in the dynamic memory module corresponding to the host-side periodic area;

[0126] encapsulating the host data in the device-side periodic area through the dynamic memory module after a preset time;

[0127] storing the encapsulated host data in a data placement unit in the flash memory module corresponding to the device-side periodic area through the flash memory controller module.

[0128] In another embodiment of the present application, the CXL interface module includes a data placement unit register and a write cache register, and the method further includes:

[0129] recording first hardware information of each data placement unit in the flash memory module in the data placement unit register;

[0130] recording second hardware information of each device-side periodic area in the dynamic memory module in the write cache register; so that the host creates a host-side periodic area based on the first hardware information and the second hardware information.

[0131] In another embodiment of the present application, the dynamic memory module further comprises a logical address and physical address mapping table, and the storing of the encapsulated host data into the data placement unit corresponding to the device-side periodic area in the flash memory module comprises:

[0132] obtaining a mapping relationship between the logical address of the device-side periodic area and the physical address of the data placement unit recorded in the logical address and physical address mapping table;

[0133] based on the mapping relationship, storing the encapsulated host data into the data placement unit corresponding to the device-side periodic area in the flash memory module.

[0134] In another embodiment of the present application, the CXL interface module comprises a CXL.mem protocol layer, and correspondingly,

[0135] the receiving of the host data from the host-side periodic area and the temporary storage of the host data into the device-side periodic area corresponding to the host-side periodic area in the dynamic memory module comprises:

[0136] the receiving of the host data from the host-side periodic area and the temporary storage of the host data into the device-side periodic area corresponding to the host-side periodic area in the dynamic memory module comprises:

[0137] In another embodiment of the present application, the CXL interface module further comprises a CXL.io protocol layer, and the method further comprises:

[0138] sending the first hardware information and the second hardware information to the host through the CXL.io protocol layer.

[0139] In another embodiment of the present application, each data placement unit comprises a plurality of flash data blocks, and the method further comprises:

[0140] when the host data in a flash data block needs to be updated, the updated host data is written into another flash data block in the same data placement unit, and the original flash data block is erased.

[0141] In another embodiment of the present application, the dynamic memory module further comprises a data encapsulation layer, the data encapsulation layer comprises a plurality of periodic area pages; the periodic area pages correspond one-to-one to the device-side periodic areas and the data placement units respectively, and the method further comprises:

[0142] receiving and temporarily storing the encapsulated host data through the periodic area pages.

[0143] According to embodiments of the present application, the present application also provides an electronic device and a readable storage medium.

[0144] Figure 8 A schematic block diagram of an example electronic device that can be used to implement embodiments of the present application is shown. The electronic device is intended to represent various forms of digital computers, such as laptops, desktops, tablets, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular telephones, smartphones, wearable devices, and other similar computing devices. The components shown here, their connections and relationships, and their functions, are meant to be examples only, and are not intended to limit the implementations of the present application described and / or claimed in this document.

[0145] As shown in FIG. 8, the device 800 includes a computing unit 801 that can perform various suitable actions and processes in accordance with computer programs stored in a read-only memory (ROM) 802 or loaded into a random access memory (RAM) 803 from a storage unit 808. Various programs and data required for operation of the device 800 can also be stored in the RAM 803. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other by a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804. Figure 8 Various components in the device 800 are connected to the I / O interface 805, including an input unit 806, such as a keyboard, a mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a magnetic disk, an optical disk, etc.; and a communication unit 809, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 809 allows the device 800 to exchange information / data with other devices through a computer network, such as the Internet, and / or various telecommunication networks.

[0146]

[0147] ​The computing unit 801 can be various general and / or special purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various specialized artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, and the like. The computing unit 801 performs various methods and processes described above, such as the data storage method. For example, in some embodiments, the data storage method can be implemented as a computer software program tangibly embodied in a machine-readable medium, such as the storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed onto the device 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded onto the RAM 803 and executed by the computing unit 801, one or more steps of the data storage method described above can be performed. Alternatively, in other embodiments, the computing unit 801 can be configured to perform the data storage method by any other suitable means, such as by means of firmware.

[0148] Various implementations of the systems and techniques described above can be realized in digital electronic circuitry, integrated circuitry, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on a chip (SOC), a complex programmable logic device (CPLD), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0149] Program code for carrying out methods of the present application can be written in any combination of one or more programming languages. The program code can be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the program code, when executed by the processor or controller, produces the functions / operations specified in the flowcharts and / or the block diagrams. The program code can be embodied in whole or in part within a machine, executed partially on the machine, partially on a remote machine, or entirely on a remote machine or server.

[0150] In the context of this application, a machine-readable medium can be a tangible medium that can contain or store program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable storage medium can include but are not limited to an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of the machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0151] To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0152] The systems and techniques described here can be implemented in a computing system that includes a back end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front end component (e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0153] The computer system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server can arise by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0154] It should be understood that the various forms of flow shown above can be used to reorder, add, or delete steps. For example, the steps described in this application can be performed in parallel, in series, or in a different order, as long as the desired results of the technical solutions of the present application can be achieved, which are not limited herein.

[0155] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0156] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A storage device, comprising: The storage device comprises a CXL interface module, a dynamic memory module, a flash memory module and a flash memory controller module; the dynamic memory module comprises a plurality of device-side cycle areas, and the flash memory module comprises a plurality of data placement units, the device-side cycle areas and the data placement units corresponding to each other; The CXL interface module is configured to receive host data from a host-side cycle area and temporarily store the host data in a device-side cycle area corresponding to the host-side cycle area in the dynamic memory module; The dynamic memory module is configured to encapsulate the host data in the device-side cycle area after a preset time; The flash memory controller module is configured to store the encapsulated host data in a data placement unit corresponding to the device-side cycle area in the flash memory module; The CXL interface module comprises a data placement unit register and a write cache register; the data placement unit register is configured to record first hardware information of each data placement unit in the flash memory module; and the write cache register is configured to record second hardware information of each device-side cycle area in the dynamic memory module, so that the host creates a host-side cycle area based on the first hardware information and the second hardware information; The dynamic memory module further comprises a logical address and physical address mapping table; the logical address and physical address mapping table is configured to record a mapping relationship between a logical address of a device-side cycle area and a physical address of a data placement unit, so that the flash memory controller module determines a data placement unit corresponding to the device-side cycle area; Each data placement unit comprises a plurality of flash memory data blocks; when host data in a flash memory data block needs to be updated, the updated host data is written into other flash memory data blocks of the same data placement unit, and the original flash memory data block is erased; The dynamic memory module further comprises a data encapsulation layer, and the data encapsulation layer comprises a plurality of cycle area pages; the cycle area pages correspond to the device-side cycle areas and the data placement units one by one; and the cycle area pages are configured to receive and temporarily store the encapsulated host data.

2. The storage device of claim 1, wherein, The CXL interface module comprises a CXL.mem protocol layer configured to receive host data from a host-side cycle area and temporarily store the host data in a device-side cycle area corresponding to the host-side cycle area in the dynamic memory module.

3. The storage device of claim 1, wherein, The CXL interface module further comprises a CXL.io protocol layer configured to send the first hardware information and the second hardware information to the host.

4. An electronic device, comprising: The electronic device comprises a host and a storage device; the storage device comprises a CXL interface module, a dynamic memory module, a flash memory module and a flash memory controller module; the dynamic memory module comprises a plurality of device-side cycle areas, and the flash memory module comprises a plurality of data placement units, the device-side cycle areas and the data placement units corresponding to each other; The host is configured to place host data in a host-side cycle area corresponding to an update frequency of the host data according to the update frequency of the host data; The CXL interface module is configured to receive host data from a host-side periodic region and temporarily store the host data in a device-side periodic region corresponding to the host-side periodic region in the dynamic memory module; The dynamic memory module is configured to encapsulate the host data in the device-side periodic region after a preset time; The flash memory controller module is configured to store the encapsulated host data in a data placement unit corresponding to the device-side periodic region in the flash memory module; The CXL interface module includes a data placement unit register and a write cache register; the data placement unit register is configured to record first hardware information of each data placement unit in the flash memory module; the write cache register is configured to record second hardware information of each device-side periodic region in the dynamic memory module; and the host is configured to obtain the first hardware information and the second hardware information, and construct a host-side periodic region based on the first hardware information and the second hardware information. The dynamic memory module further includes a logical address and physical address mapping table; the logical address and physical address mapping table is configured to record a mapping relationship between a logical address of a device-side periodic region and a physical address of a data placement unit, so that the flash memory controller module determines a data placement unit corresponding to the device-side periodic region; Each data placement unit includes a plurality of flash memory data blocks; when host data in a flash memory data block needs to be updated, the updated host data is written into other flash memory data blocks of the same data placement unit, and the original flash memory data block is erased; The dynamic memory module further includes a data encapsulation layer, and the data encapsulation layer includes a plurality of periodic region pages; each periodic region page corresponds to one of the device-side periodic regions and the data placement units; and the periodic region pages are configured to receive and temporarily store the encapsulated host data.

5. The electronic device of claim 4, wherein, The host is further configured to, determine a number of host-side periodic regions and a logical address range of each host-side periodic region based on the first hardware information and the second hardware information; and construct the host-side periodic regions based on the number of host-side periodic regions and the logical address range of each host-side periodic region.

6. The electronic device of claim 4, wherein, The host is further configured to, determine a time interval for sending host data to the storage device based on the first hardware information and the second hardware information.

7. A data storage method characterized by, The method is applied to a storage device including a CXL interface module, a dynamic memory module, a flash memory module, and a flash memory controller module; the dynamic memory module includes a plurality of device-side periodic regions, the flash memory module includes a plurality of data placement units, and the device-side periodic regions and the data placement units correspond one-to-one; and the method includes: receiving host data from a host-side periodic region through the CXL interface module and temporarily storing the host data in a device-side periodic region corresponding to the host-side periodic region in the dynamic memory module; encapsulating the host data in the device-side periodic region through the dynamic memory module after a preset time; and The encapsulated host data is stored into a data placement unit in the flash memory module corresponding to the device-side periodic area through the flash memory controller module; The CXL interface module includes a data placement unit register and a write cache register, and the method further includes: recording first hardware information of each data placement unit in the flash memory module in the data placement unit register; recording second hardware information of each device-side periodic area in the dynamic memory module in the write cache register; so that the host creates a host-side periodic area based on the first hardware information and the second hardware information; The dynamic memory module further includes a logical address and physical address mapping table; and the encapsulated host data is stored into a data placement unit in the flash memory module corresponding to the device-side periodic area by: obtaining a mapping relationship between a logical address of the device-side periodic area and a physical address of the data placement unit recorded in the logical address and physical address mapping table; and storing the encapsulated host data into the data placement unit in the flash memory module corresponding to the device-side periodic area based on the mapping relationship. Each data placement unit includes a plurality of flash data blocks, and the method further includes: when host data in a flash data block needs to be updated, writing updated host data into other flash data blocks of the same data placement unit and performing erasing processing on the original flash data block; The dynamic memory module further includes a data encapsulation layer, and the data encapsulation layer includes a plurality of periodic area pages; the periodic area pages correspond one-to-one to the device-side periodic areas and the data placement units, respectively; and the method further includes: receiving and temporarily storing the encapsulated host data through the periodic area pages.

8. The method of claim 7, wherein, The CXL interface module includes a CXL.mem protocol layer, and correspondingly, The method further includes: The method further includes:

9. The method of claim 7, wherein, The CXL interface module further includes a CXL.io protocol layer, and the method further includes: The first hardware information and the second hardware information are sent to the host through the CXL.io protocol layer.

10. A non-transitory computer-readable storage medium having stored thereon computer instructions, wherein, The computer instructions are used to enable the computer to execute the method according to any one of claims 7-9.

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