Solid-state drive management methods, electronic devices, storage media and software products

By employing multi-core collaborative processing and a skip processing mechanism, the low execution efficiency of the SSD's Trim mechanism was resolved, enabling rapid entry into high-performance mode and resource optimization, thereby improving the overall performance of the SSD.

CN120723171BActive Publication Date: 2025-10-31INSPUR SUZHOU INTELLIGENT TECH CO LTD
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Patent Information

Application Number
CN202511204066.7
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2025-08-26
Publication Date
2025-10-31
Estimated Expiration
2045-08-26

AI Technical Summary

Technical Problem

In existing technologies, solid-state drives (SSDs) neglect execution efficiency when handling the Trim function, resulting in low processing efficiency, especially when handling large-capacity and pseudo-large segment Trim, which affects the performance of SSDs.

Method used

A multi-core collaborative processing mechanism is adopted, in which the first processor core sends a collaborative processing request to the second processor core, allocates address segments and set flag bit tables, and enables the second processor core to collaboratively process data erasure operations, making full use of the advantages of multi-core concurrent collaboration, and adopting a jump-processing pseudo-large segment and highly discretized Trim.

Benefits of technology

It improves the efficiency of the solid-state drive's Trim processing, enabling it to quickly enter high-performance mode, thereby improving overall performance and resource utilization, and solving the problem of low Trim execution efficiency.

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Abstract

This application discloses a solid-state drive (SSD) management method, electronic device, storage medium, and program product, relating to the field of SSD technology. The method involves a first processor core sending a collaborative processing request to a second processor core. The collaborative processing request includes a first address segment allocated for processing by the second processor core and a set flag bit table. Upon receiving the collaborative processing request, the second processor core performs an erase operation on the first address segment according to the set flags in the set flag bit table that indicate whether an erase operation needs to be performed on the corresponding logical block address. This achieves the purpose of collaborative processing of the data erase request by the second processor core, fully utilizing the multi-core mechanism of the SSD. By collaboratively processing the data erase request through processor cores, the efficiency of the SSD in processing Trim can be effectively improved, thereby enhancing overall performance and solving the technical problem of low efficiency in SSD Trim processing due to the lack of consideration for Trim execution efficiency.
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