Chip simulation acceleration system

Abstract

The invention relates to the technical field of chips, in particular to a chip simulation acceleration system which comprises {A1, A2,..., Am,..., AM} and {B1, B2,..., Bm,..., BM}. Bm = {B0m, B1m, B2m,..., Bim,..., Bf (m) m}; the first type Bim is used for acquiring input excitation and a data packet from an input port of the Am and transmitting the input excitation and the data packet to the B0m; the B0m is used for processing the input excitation and the data packet corresponding to the Am, generating output data and sending the output data to the first type Bim and the second type Bim; the second type Bim is used for processing the received output data and outputting the received output data to a corresponding downstream module according to a preset time sequence; the first type Bim is used for controlling the input of the next data packet based on the received output data and the output result of the second type Bim. On the premise of ensuring the time sequence of the chip, the chip simulation process is accelerated, and the chip simulation efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a chip simulation acceleration system. Background Art

[0002] During chip verification, after receiving a data packet, the chip sends it to the firmware for parsing and processing. During this process, the chip control module, which performs control functions, manages register configuration, data packet reception, data packet storage, and data packet parsing. The chip control module can take hundreds of cycles or even longer to process a single data packet. The larger the chip, the longer the chip control module takes to process a single data packet, resulting in a very slow chip simulation process and low chip simulation efficiency. During chip simulation, processing must be performed according to the chip's timing. Therefore, how to accelerate the chip simulation process and improve its efficiency while ensuring chip timing has become a pressing technical challenge. Summary of the Invention

[0003] The present invention aims to provide a chip simulation acceleration system, which accelerates the chip simulation process and improves the chip simulation efficiency while ensuring the chip timing.

[0004] According to a first aspect of the present invention, a chip simulation acceleration system is provided, comprising {A1, A2, ..., A m ,...,A M} and {B1,B2,...,B m ,...,B M}, where A m is the interface module corresponding to the mth chip control module, B m A is the chip acceleration module corresponding to the mth chip control module. m With B m Interconnection, the value of m ranges from 1 to M, where M is the total number of chip control modules; A m Based on hardware description language generation, A m Only includes the input interface and output interface of the mth chip control module; B m ={B0 m ,B1 m ,B2 m ,...,B i m ,...,B f(m) m}, B0 m is the behavior model corresponding to the mth chip control module, B0 m Based on high-level language generation, Bi m A m The corresponding i-th verification unit, B i m For UVM-based generation, the value of i ranges from 1 to f(m), where f(m) is A m The corresponding number of verification units, B i m With B0 m The input interface or output interface is interconnected with B0 m The input interface of the B i m For the first category B i m , Category IB i m Also with A m The corresponding upstream module is interconnected with B0 m The output interface of the B i m For the second type B i m , Category IIB i m Also with A m The corresponding downstream modules are interconnected; Category IB i m For use from A m The input port obtains input stimulus and data packet and transmits it to B0 m ; B0 m For processing A m The corresponding input stimulus and data packet, and generates output data to send to the first class B i m and the second category B i m ; Category IIB i m Used to process the received output data and output it to the corresponding downstream module according to the preset timing; Category IB i m Also used based on received output data and the second type B i m The output result controls the input of the next data packet.

[0005] The present invention has significant advantages and beneficial effects compared to the prior art. By utilizing the above technical solution, the chip simulation acceleration system provided by the present invention can achieve considerable technological advancement and practicality, and has wide industrial application value, with at least the following beneficial effects: The system described in this invention replaces the chip control module with an acceleration module, replacing the chip control module's processing with a corresponding behavioral model. This significantly improves processing speed and ensures chip timing through coordination between verification units. This allows the system to accelerate the chip simulation process and improve chip simulation efficiency while ensuring chip timing. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0007] Figure 1 Schematic diagram of a chip simulation acceleration system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0008] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0009] The embodiment of the present invention provides a chip simulation acceleration system, comprising {A1, A2, ..., A m ,...,A M} and {B1,B2,...,B m ,...,B M}, where A m is the interface module corresponding to the mth chip control module, B m A is the chip acceleration module corresponding to the mth chip control module. m With B m Interconnection, m ranges from 1 to M, where M is the total number of chip control modules. It should be noted that a chip may include one or more chip control modules. The simulation acceleration of the present invention mainly performs simulation acceleration on the chip control module. The simulation acceleration for each chip control module is independent, and the simulation acceleration logic is consistent. Therefore, the embodiment of the present invention performs simulation acceleration on one of the A m The simulation acceleration structure is described in detail. Figure 1 Only one group A is shown in m and B m .

[0010] A mGenerated based on hardware description language, which can be Verilog, VHDL, SystemVerilog, etc. m It only includes the input interface and output interface of the mth chip control module. It should be noted that in the existing chip simulation system, the chip control module includes the input interface, output interface and internal operation logic, while A m It only includes the input interface and output interface of the mth chip control module, the internal operation logic is empty, and the internal operation process is executed by the corresponding acceleration module.

[0011] like Figure 1 As shown, B m ={B0 m ,B1 m ,B2 m ,...,B i m ,...,B f(m) m}, B0 m is the behavior model corresponding to the mth chip control module, B0 m Generated based on high-level languages, which can be C and C++. i m A m The corresponding i-th verification unit, i ranges from 1 to f(m), f(m) is A m The corresponding number of verification units. B i m It is generated based on the Universal Verification Methodology (UVM), which is implemented in the SystemVerilog language.

[0012] like Figure 1 As shown, B i m With B0 m The input interface or output interface is interconnected with B0 m The input interface of the B i m For the first category B i m , Category IB i m Also with A m The corresponding upstream module interconnection, A m The corresponding upstream module can be a CPU (Central Processing Unit) or other chip components based on hardware description language. m The output interface of the B im For the second type B i m , Category IIB i m Also with A m The corresponding downstream modules are interconnected, and the downstream modules can specifically be other chip component modules implemented based on hardware description languages.

[0013] Category IB i m For use from A m The input port obtains input stimulus and data packet and transmits it to B0 m . B0 m For processing A m The corresponding input stimulus and data packet, and generates output data to send to the first class B i m and the second category B i m , it should be noted that B0 m Replaces the processing of the original chip control module, and because B0 m It is a behavioral model implemented based on high-level language, so the processing speed is much faster than the original chip control module. i m Used to process the received output data and output it to the corresponding downstream module according to the preset timing. i m Also used based on received output data and the second type B i m The output result controls the input of the next data packet.

[0014] In some application scenarios, the chip control module needs to send a handshake signal to perform a handshake operation before transmitting data. However, in the system described in the embodiment of the present invention, A m The system only includes the input interface and output interface of the mth chip control module, and the internal operation logic is empty, so the handshake operation cannot be performed. If it is not processed, it will cause the system to enter an infinite loop state. In order to avoid such a situation, as an embodiment, if the mth chip control module needs to perform a handshake operation, the system also includes A m The start signal (ready) set by the input interface of the chip is set to 1 at the preset time, replacing the handshake operation that the m-th chip control module needs to perform. The preset time is set based on the specific handshake operation scenario required.

[0015] As an example, the second type B i mThe second type B includes one or more of a routing unit for implementing routing functions, an address translation unit for implementing virtual address and physical address translation, a graphics processing unit for performing graphics processing, and a resource distribution unit for distributing computing resources. i m Set according to specific application requirements.

[0016] As an embodiment, the first type B i m It includes a register configuration unit, which is used to configure B in the initialization phase. m and B m The corresponding register in the downstream module. m When the corresponding register in the downstream module is set, it can be used with the second type B of the routing unit i m To achieve this, set it as the second type B of routing unit i Send the corresponding register configuration information to the corresponding downstream module to implement the corresponding register configuration.

[0017] As an embodiment, the first type B i m It includes an incentive acquisition unit, which is used to obtain the transaction information (Transaction) corresponding to the input incentive, and perform transaction-level modeling (TLM), converting the result of transaction-level modeling into a high-level language structure (struct) and sending it to B0 m It should be noted that all existing transaction-level modeling methods fall within the scope of protection of the present invention and will not be described in detail here.

[0018] As an embodiment, the first type B i m The module includes a data packet acquisition unit, which is used to acquire the data packet from the memory of the upstream module and send it to B0 at the end of the initialization phase or after the current data packet is processed. m It should be noted that the first data packet can be obtained for processing at the end of the initialization phase. Different data packets correspond to different services. In order to ensure the timing, the data packets need to be obtained in sequence. Therefore, the next data packet can be obtained for processing only after the current data packet is processed.

[0019] As an example, B0 m For processing A mCorresponding input stimulus and data packet, obtain the output result in the form of high-level language structure, convert the output result in the form of high-level language structure into transaction-level output result, and perform transaction-level modeling, and send the output data after transaction-level modeling to the first category B according to the preset processing order. i m and the second category B i m It should be noted that based on A m The corresponding input stimulus and data packet can determine the order in which the output data is sent, so the output data after transaction-level modeling can be sent to the first category B in the preset processing order. i m and the second category B i m , to ensure chip timing.

[0020] As an embodiment, the first type B i m A processing feedback unit is included, wherein the processing feedback unit is used to i m After processing the received output data, a current data packet processing completion instruction is sent to the upstream module. After receiving the current data packet processing completion instruction, the upstream module sends the next data packet to the data packet acquisition unit.

[0021] It should be noted that B0 m It can only control the output order of the output data after transaction-level modeling processing, but cannot directly guarantee the first type B i m and the second category B i m Output data timing, for B with timing dependency i m , it is necessary to ensure the chip timing requirements. In order to ensure the accuracy of the chip timing, as an example, if B1 im and B2 im With timing dependency, B1 im For one of the first category B i m , B2 im For one of the second category B i m , the system further includes B1 im The corresponding first-in-first-out queue F1 im 、B2 im The corresponding first-in-first-out queue F2 im .

[0022] If the upstream module writes data to the downstream module, and the upstream module can only send one write task at a time, and sends the next write task after receiving the reply information of the current write task, then B2 im Used to store the current data to be written, B1 im Used to store the current write response. im When the data to be written in the downstream module is written, when B2 im If it is empty, it means that all the data to be written have been written into the downstream module. im The reply information in is fed back to the upstream module, and the upstream module issues the next writing task, satisfying B1 im and B2 im Corresponding order preservation requirements.

[0023] If the upstream module writes data to the downstream module, and the upstream module can issue multiple write tasks at a time, then B2 im Used to store the currently sent data to be written, including the write task identifier, B1 im It is used to store the reply information of the writing task in order. The reply information of the writing task includes the writing task identifier. If B1 im The data to be written corresponding to the write task identifier corresponding to the reply information of the current pending write task is in B2 im If it does not exist, it means B1 im The data to be written corresponding to the reply information of the current pending write task has been written into the downstream module. im The reply information of the current pending write task is fed back to the upstream module, satisfying B1 im and B2 im Corresponding order preservation requirements.

[0024] If the upstream module reads data from the downstream module, the upstream module sends a read task instruction to the downstream module, B2 im For use in accordance with B0 m The read data is stored in the order in which the read task is received and stored according to B0 m The order of receiving read tasks is transmitted to B1 im In the middle, B1 im After adjusting the read data in B1 to the order in which the upstream module sends read task instructions to the downstream module, im The read data in B0 is sent to the upstream module. m The order in which read tasks are received may be inconsistent with the order in which the upstream module sends read task instructions to the downstream module. Therefore, B1 im After adjusting the read data in B1 to the order in which the upstream module sends read task instructions to the downstream module, im The read data in is sent to the upstream module. If the current B0 m With other B0m If there is no dependency, then the current B0 m Ability to directly adjust B1 im Otherwise, call the preset sequence adjustment function to adjust B1 im The order of reading data in B1 im and B2 im Corresponding order preservation requirements.

[0025] It should be noted that in some application scenarios, the second type B i m The chip timing is not only the same as the first type B i m It may also be related to the timing of downstream modules. i m When it is related to the timing of the downstream module, the working status of the downstream module also needs to be taken into account. As an example, if the second type B i m It has a timing dependency with the corresponding downstream module, which is the second type B i m Set the corresponding first-in-first-out queue and set the status identifier for the corresponding downstream module. The status identifier includes the working status identifier and the non-working status identifier. Specifically, the busy status bit can be set. When the busy status bit is set to 1, it means that the corresponding downstream module is in the working state. When the busy status bit is set to 0, it means that the corresponding downstream module is in the non-working state. When the second type B i m When all the corresponding FIFO queues are not empty and the status of the corresponding downstream modules is marked as non-working status, the second type B i m Send the data in the corresponding FIFO queue to the corresponding downstream module. By setting the FIFO queue combination and the status flag of the downstream module, it is possible to accurately control the execution according to the chip timing.

[0026] The system described in this embodiment of the present invention replaces the chip control module with an acceleration module, replacing the chip control module's processing with a corresponding behavioral model. This significantly improves processing speed and ensures chip timing through coordination between verification units. This allows the system described in this invention to accelerate the chip simulation process and improve chip simulation efficiency while ensuring chip timing.

[0027] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with the present profession can make slight changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A chip simulation acceleration system, characterized in that: Including {A1,A2,...,A m ,...,A M } and {B1,B2,...,B m ,...,B M }, where A m is the interface module corresponding to the mth chip control module, B m A is the chip acceleration module corresponding to the mth chip control module. m With B m Interconnection, the value of m ranges from 1 to M, where M is the total number of chip control modules; A m Based on hardware description language generation, A m Only includes the input interface and output interface of the mth chip control module; B m ={B0 m ,B1 m ,B2 m ,...,B i m ,...,B f(m) m }, B0 m is the behavior model corresponding to the mth chip control module, B0 m Based on high-level language generation, B i m A m The corresponding i-th verification unit, B i m For UVM-based generation, the value of i ranges from 1 to f(m), where f(m) is A m The corresponding number of verification units, B i m With B0 m The input interface or output interface is interconnected with B0 m The input interface of the B i m For the first category B i m , Category IB i m Also with A m The corresponding upstream module is interconnected with B0 m The output interface of the B i m For the second type B i m , Category IIB i m Also with A m The corresponding downstream modules are interconnected; Category IB i m For use from A m The input port obtains input stimulus and data packet and transmits it to B0 m ; B0 m For processing A m The corresponding input stimulus and data packet, and generates output data to send to the first class B i m and the second category B i m ; Category IIB i m Used to process the received output data and output it to the corresponding downstream module according to the preset timing; Category IB i m Also used based on received output data and the second type B i m The output result controls the input of the next data packet.

2. The system according to claim 1, wherein: If the mth chip control module needs to perform a handshake operation, the system further includes: m The start signal is set to 1 at the preset time, replacing the handshake operation that the mth chip control module needs to perform.

3. The system according to claim 1, wherein: The first category B i m It includes a register configuration unit, which is used to configure B in the initialization phase. m and B m The register in the corresponding downstream module.

4. The system according to claim 1, wherein: The first category B i m It includes an incentive acquisition unit, which is used to obtain the transaction information corresponding to the input incentive, perform transaction-level modeling, and convert the result of transaction-level modeling into a high-level language structure and send it to B0 m .

5. The system according to claim 1, wherein: The first category B i m The module includes a data packet acquisition unit, which is used to acquire the data packet from the memory of the upstream module and send it to B0 at the end of the initialization phase or after the current data packet is processed. m .

6. The system according to claim 1, wherein: B0 m For processing A m Corresponding input stimulus and data packet, obtain the output result in the form of high-level language structure, convert the output result in the form of high-level language structure into transaction-level output result, and perform transaction-level modeling, and send the output data after transaction-level modeling to the first category B according to the preset processing order. i m and the second category B i m .

7. The system according to claim 1, wherein: The first category B i m A processing feedback unit is included, wherein the processing feedback unit is used to i m After processing the received output data, a current data packet processing completion instruction is sent to the upstream module. After receiving the current data packet processing completion instruction, the upstream module sends the next data packet to the data packet acquisition unit.

8. The system according to claim 1, wherein: Category IIB i m It includes one or more of a routing unit for implementing routing functions, an address translation unit for implementing virtual address and physical address translation, a graphics processing unit for performing graphics processing, and a resource distribution unit for distributing computing resources.

9. The system according to claim 1, wherein: If B1 im and B2 im With timing dependency, B1 im For one of the first category B i m , B2 im For one of the second category B i m , the system further includes B1 im The corresponding first-in-first-out queue F1 im 、B2 im The corresponding first-in-first-out queue F2 im ; If the upstream module writes data to the downstream module, and the upstream module can only send one write task at a time, and sends the next write task after receiving the reply information of the current write task, then B2 im Used to store the current data to be written, B1 im Used to store the current write response. im When the data to be written in the downstream module is written, when B2 im If B1 is empty, im The reply information is fed back to the upstream module, and the upstream module issues the next writing task; If the upstream module writes data to the downstream module, and the upstream module can issue multiple write tasks at a time, then B2 im Used to store the currently sent data to be written, including the write task identifier, B1 im It is used to store the reply information of the writing task in order. The reply information of the writing task includes the writing task identifier. If B1 im The data to be written corresponding to the write task identifier corresponding to the reply information of the current pending write task is in B2 im If B1 does not exist, im Feedback the reply information of the current pending write task to the upstream module; If the upstream module reads data from the downstream module, the upstream module sends a read task instruction to the downstream module, B2 im For use in accordance with B0 m The read data is stored in the order in which the read task is received and stored according to B0 m The order of receiving read tasks is transmitted to B1 im In the middle, B1 im After adjusting the read data in B1 to the order in which the upstream module sends read task instructions to the downstream module, im The read data in is sent to the upstream module.

10. The system according to claim 1, wherein: If the second type B i m It has a timing dependency with the corresponding downstream module, which is the second type B i m Set the corresponding first-in-first-out queue and set the status identifier for the corresponding downstream module. The status identifier includes the working status identifier and the non-working status identifier. When the second type B i m When the corresponding FIFO queue is not empty and the status of the corresponding downstream module is marked as non-working status, the second type B i m Send the data in the corresponding first-in-first-out queue to the corresponding downstream module.

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