Battery management system and battery box
By optimizing the battery box layout and integrating the acquisition board with the BMS slave module, and using springs and NTC probes for direct contact acquisition, the compatibility and sampling frequency issues of the battery management system are resolved, resulting in a lighter battery box and improved safety.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN TECH UNIV
- Filing Date
- 2025-06-23
- Publication Date
- 2026-06-16
Smart Images
Figure CN120728031B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of battery management technology, and more specifically to a battery management system and battery box. Background Technology
[0002] Sustainable development of transportation energy and energy conservation and emission reduction in the transportation sector have been prioritized by governments worldwide. Against this backdrop, electric vehicles, due to their significant energy-saving and environmental advantages, have received strong policy support and promotion from various countries and have become a key area of technological innovation in the global automotive industry. This trend has not only accelerated the rise of the electric vehicle industry but also directly driven the rapid development of power battery technology and its management systems, providing crucial technological support for achieving green transportation and sustainable energy development.
[0003] The Battery Management System (BMS) is an indispensable core component of modern new energy vehicle technology. BMS topologies include integrated and master-slave architectures. Integrated BMSs offer advantages such as lower cost, smaller footprint within the battery system, and simpler maintenance. However, current electric vehicle voltage platforms are mostly above 300V, and the voltage monitoring chips in integrated BMS architectures often cannot meet such high voltage tolerances. Therefore, the mainstream approach is a master-slave architecture to decompose high-voltage acquisition tasks into low-voltage acquisition. Master-slave BMSs mainly consist of two modules: the master controller and the slave controller. The master controller module is responsible for data processing, communication, and diagnostics, while the slave controller module is responsible for data acquisition, monitoring, and balancing functions. Due to mass production requirements and modular design, mainstream BMS products on the market often suffer from poor compatibility between the slave controller module and the battery module, resulting in complex wiring harnesses and the potential risk of wire breakage due to manufacturing processes. Furthermore, when the number of slave controller acquisition channels does not match the number of battery cells, redundancy in the BMS slave controller channels can occur, leading to wasted space and ultimately increased costs. In addition to poor compatibility, many BMS products have problems such as slow data sampling rates. When a battery cell is damaged due to individual differences, if the BMS cannot respond quickly to cut off the high voltage output, it may damage the battery pack and cause a safety accident.
[0004] Therefore, improving the adaptability and sampling frequency of master-slave battery management systems is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0005] In view of this, the present invention provides a battery management system and a battery box, which optimizes the battery box layout and the battery management system, and improves the adaptability and sampling frequency of the battery box.
[0006] To achieve the above objectives, the present invention adopts the following technical solution:
[0007] A battery management system includes a master control module and at least one set of slave control modules;
[0008] The main control module includes an STM32 microcontroller, a relay control unit, a CAN communication unit, and a daisy-chain communication conversion unit; the STM32 microcontroller is connected to the relay control unit, the CAN communication unit, and the daisy-chain communication conversion unit respectively.
[0009] The slave control module includes a slave control AFE unit, a temperature acquisition unit, an enhanced communication unit, a passive equalization unit, and a filtering unit. The slave control AFE unit is connected to the temperature acquisition unit, the enhanced communication unit, the passive equalization unit, and the filtering unit, respectively. The passive equalization unit and the filtering unit are connected to the battery pack, respectively. The enhanced communication unit is connected to the daisy-chain communication conversion unit. Multiple slave control modules are connected in series through the enhanced communication unit.
[0010] Preferably, the slave-controlled AFE unit includes a chip U1 of model LTC6804-1. The chip U1 is equipped with an LDO (low dropout linear regulator) component. The first pin V+ of the chip U1 is connected to the positive terminal of the battery pack, and the third pin V- is connected to the negative terminal of the battery pack. The circuit step-down is achieved through the LDO component, and the stepped-down power supply is output to the third pin DRVE (output Drive1 signal).
[0011] Preferably, the enhanced communication unit includes two external resistors, two terminating resistors, two capacitors, an external transformer U2, and an isoSPI interface; pin 1 (TD+) of the external transformer U2 is connected to the IPA pin of chip U1, pin 3 (TD-) is connected to the IMA pin of chip U1, and a first terminating resistor is connected between pin 1 (TD+) and pin 3 (TD-); pin 6 (RD+) is connected to the IPB pin of chip U1, pin 8 (RD-) is connected to the IMB pin of chip U1, and a second terminating resistor is connected between pin 6 (RD+) and pin 8 (RD-); pin 2 (TCT) is connected to the first capacitor. Pin 7 (RCT) is connected to the second capacitor, and the other ends of the two capacitors are grounded respectively. Pin 14 (TX-) and pin 16 (TX+) are connected to the RX- and RX+ pins of the external transformer U2 of the enhanced communication unit in the next stage slave module, respectively. Pin 9 (RX-) and pin 11 (RX+) are connected to the TX- and TX+ pins of the external transformer U2 of the enhanced communication unit in the previous stage slave module, respectively. Pin 1 of the isoSPI interface is connected to pin 37 (Vreg1) of chip U1, pin 2 is connected to pin 40 (ISOMD) of chip U1, and pin 3 is grounded for mode selection.
[0012] Preferably, the daisy-chain communication conversion unit includes a chip U4 (model LTC6820HMS), connector CN5, connector CN2, two decoupling capacitors, and a single-channel daisy-chain circuit. The single-channel daisy-chain circuit includes two external resistors, one terminating resistor, one external transformer, and two capacitors. Chip U4 is connected to the SPI pin of the STM32 microcontroller via connector CN5. Pins 6 (VDDS), 7 (POL), 8 (PHA), and 9 (VDD) of chip U4 are connected to VCC and connected to the two decoupling capacitors. Pin 10 (IM) of chip U4 is connected to the terminating resistor and pin 3 of the external transformer, and pin 11 (IP) is connected to... The other end of the terminating resistor is connected to pin 1 of the external transformer. Pin 15 (ICMP) is grounded through the second external resistor and connected to one end of the first external resistor. Pin 16 (IBIAS) is connected to the other end of the first external resistor. Pins 2 and 5 of the external transformer are grounded through a capacitor. Pin 4 is connected to pin 2 of connector CN2, and pin 6 is connected to pin 1 of connector CN2. Pin 1 of connector CN2 is connected to the TX+ pin of external transformer U2 in the enhanced communication unit, and pin 2 is connected to the TX- pin of external transformer U2 in the enhanced communication unit, for use in series with the slave module for isoSPI communication.
[0013] Preferably, the passive equalization unit includes several equalization modules. Each equalization module includes a field-effect transistor (P-MOS), a first current-limiting resistor, a second current-limiting resistor, a discharge resistor, and a light-emitting diode (LED). The source (pin 2) of the P-MOS is connected to the positive terminal of one battery cell in the battery pack, the gate (pin 1) is connected to one end of the first current-limiting resistor, the other end of the first current-limiting resistor is connected to an equalization pin (equalization pins include pins S1-S12) of chip U1, the drain (pin 3) is connected to the anode of the LED and one end of the discharge resistor, the other end of the discharge resistor is connected to the positive terminal of another battery cell in the battery pack, the cathode of the LED is connected to one end of the second current-limiting resistor, and the other end of the second current-limiting resistor is connected to the positive terminal of another battery cell in the battery pack.
[0014] Preferably, the filtering circuit includes several sets of grounding capacitors and several sets of RC low-pass filters composed of filter resistors and filter capacitors; one end of the filter resistor is connected to the positive terminal of a battery in the battery pack, the other end is connected to a sampling pin of chip U1 (power supply pins include C1-C12 pins), and the other end is connected to one end of the grounding capacitor and one end of the filter power supply. The other end of the filter capacitor is connected to one end of the filter capacitor in another set of RC low-pass filters, and the other end of the grounding capacitor is grounded.
[0015] Preferably, the temperature acquisition unit includes several sets of temperature acquisition probes and voltage divider resistors; one end of the voltage divider resistor is connected to pin 34 VREF2 of chip U1, and the other end is connected to the GPIO1 pin built into chip U1 and one end of the temperature acquisition probe, and the other end of the temperature acquisition probe is grounded.
[0016] Preferably, the slave control module also includes a debugging module, which sets measurement points Vref1 (TP1), Vref2 (TP2), and IBIAS1 (TP3). When Vref1 = 3V, the core of chip U1 enters the Measure state. When Vref2 = 3V, the auxiliary measurement channel of chip U1 is turned on. When IBIAS1 = 2V, isoSPI in chip U1 is enabled.
[0017] Preferably, the slave control module also includes a fuse unit, which includes several fuses. One end of each fuse is connected to a data acquisition pin (C0-C12 pin) of the chip U1, and the other end is connected to the battery pack.
[0018] A battery box, employing the aforementioned battery management system, includes a box body, a battery pack, a main control PCB board, and a slave control PCB board. The main control module is integrated on the main control PCB board, and the slave control module is integrated on the slave control PCB board. The battery pack is placed inside the box body, and the main control PCB board and the slave control PCB board are fixed above the battery pack. The slave control PCB board further includes a spring, one end of which is fixed to the side of the slave control PCB board facing the battery pack and connected to a passive equalization unit, while the other end contacts the battery pack. Temperature acquisition probes of the temperature acquisition unit are spaced apart on the side of the slave control PCB board facing the battery pack.
[0019] Preferably, the battery box is also equipped with a module cover plate that is adapted to the opening on the top surface of the box, sealing the main control PCB board, slave control PCB board and battery pack inside the box.
[0020] Preferably, the module cover plate, the main control PCB board, the slave control PCB board and the housing are fixedly connected by bolts and studs.
[0021] Preferably, one end of the spring is provided with an electrode plate with good conductivity, which is in contact with the positive or negative electrode of each battery in the battery pack.
[0022] As can be seen from the above technical solutions, compared with the prior art, the present invention discloses a battery management system and a battery box. The present invention is applicable to battery modules with planar electrodes. It addresses the problems of poor adaptability of existing battery management systems to battery boxes, redundant wiring, and limitations on the design size of battery boxes. The layout of the battery box is designed to simplify battery box assembly. The acquisition board and BMS slave control are integrated into one unit. Spring acquisition and NTC probe direct contact acquisition are used to solve the problem of complex wiring inside the battery box under high voltage. It has strong adaptability to racing cars and reduces the overall weight of the battery device. The height of the battery box can be reduced by 20mm and the weight by 5kg, effectively reducing design and manufacturing costs and expanding the design space of racing cars. In addition, the present invention can disconnect the safety circuit within 0.5s after detecting an anomaly, which complies with the Formula Student battery box rules and can be applied to Formula Student battery boxes. Attached Figure Description
[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0024] Figure 1 This is a schematic diagram of the battery management system structure provided by the present invention;
[0025] Figure 2 This is a schematic diagram of the daisy-chain communication conversion unit circuit structure provided by the present invention;
[0026] Figure 3 This is a schematic diagram of the slave control module structure provided by the present invention;
[0027] Figure 4 This is a schematic diagram of the slave-controlled AFE unit circuit structure provided by the present invention;
[0028] Figure 5 A schematic diagram of the enhanced communication unit circuit structure provided by the present invention;
[0029] Figure 6 A schematic diagram of the passive equalization unit circuit structure provided by the present invention;
[0030] Figure 7 A schematic diagram of the filter unit circuit structure provided by the present invention;
[0031] Figure 8 A schematic diagram of the temperature acquisition unit circuit structure provided by the present invention;
[0032] Figure 9 A schematic diagram of the debugging module circuit structure provided by the present invention;
[0033] Figure 10 A schematic diagram of the circuit structure of the fuse unit provided by the present invention;
[0034] Figure 11 This is a schematic diagram of the battery pack structure provided by the present invention;
[0035] Figure 12 This is a schematic diagram of the PCB board structure of the slave control module provided by the present invention;
[0036] Figure 13 This is a schematic diagram of the battery box structure provided by the present invention.
[0037] In the attached diagram: 1-Module cover plate, 2-Slave control PCB board, 3-Battery cell, 4-Box, 5-Electrical tab support plate, 6-Spring, 7-NTC temperature probe. Detailed Implementation
[0038] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0039] This invention discloses a battery management system, including a master control module and at least one set of slave control modules;
[0040] The main control module includes an STM32 microcontroller, a relay control unit, a CAN communication unit, and a daisy-chain communication conversion unit. The STM32 microcontroller is connected to the relay control unit, the CAN communication unit, and the daisy-chain communication conversion unit. The CAN communication unit is connected to an external host computer and an electronic controller (ECU) via a CAN bus. The relay control unit is connected to external safety circuits and relays.
[0041] The slave control module includes a slave AFE unit, a temperature acquisition unit, an enhanced communication unit, a passive equalization unit, and a filtering unit. The slave AFE unit is connected to the temperature acquisition unit, the enhanced communication unit, the passive equalization unit, and the filtering unit, respectively. The passive equalization unit and the filtering unit are connected to the battery pack, and the enhanced communication unit is connected to the daisy-chain communication conversion unit. Multiple slave control modules are connected in series via the enhanced communication unit. ISO-SPI communication is implemented between the slave AFE unit and the daisy-chain communication conversion unit. The slave control module structure is as follows: Figure 3 As shown.
[0042] The relay control unit, controlled by an STM32 microcontroller, determines the status based on parameters acquired from the slave controller via its pins. The pins then output a voltage signal to control the switching of the P-MOS transistor in the relay for low-side drive. The CAN communication unit's main function is to convert between logic levels and the physical levels of the CAN bus. Furthermore, the slave AFE unit includes a chip U1 (LTC6804-1), which incorporates an LDO (Low Dropout Linear Regulator). Pin 1 (V+) of chip U1 is connected to the positive terminal of the battery pack, and pin 31 (V-) is connected to the negative terminal. The LDO component steps down the voltage, and the resulting power is output to pin 38 (DRVE, output Drive1 signal).
[0043] Furthermore, the enhanced communication unit includes two external resistors, two terminating resistors, two capacitors, an external transformer U2, and an isoSPI interface; pin 1 (TD+) of the external transformer U2 is connected to pin 42 (IPA) of chip U1, pin 3 (TD-) is connected to pin 41 (IMA) of chip U1, and a first terminating resistor is connected between pin 1 (TD+) and pin 3 (TD-); pin 6 (RD+) is connected to pin 48 (IPB) of chip U1, pin 8 (RD-) is connected to pin 47 (IMB) of chip U1, and a second terminating resistor is connected between pin 6 (RD+) and pin 8 (RD-); pin 2 (TCT) is connected to... Connect the first capacitor, and connect the 7th pin RCT to the second capacitor. The other ends of the two capacitors are grounded respectively. Connect the 14th pin TX- and the 16th pin TX+ to the RX- and RX+ pins of the external transformer U2 of the enhanced communication unit in the next stage slave module, respectively. Connect the 9th pin RX- and the 11th pin RX+ to the TX- and TX+ pins of the external transformer U2 of the enhanced communication unit in the previous stage slave module, respectively. Connect the 1st pin of the isoSPI interface to the 37th pin (Vreg1) of chip U1, the 2nd pin to the 40th pin (ISOMD) of chip U1, and the 3rd pin to ground for mode selection.
[0044] Furthermore, the daisy-chain communication conversion unit includes a chip U4 (model LTC6820HMS), connectors CN5 and CN2, two decoupling capacitors, and a single-channel daisy-chain circuit. The single-channel daisy-chain circuit includes two external resistors, one terminating resistor, one external transformer, and two capacitors. Chip U4 is connected to the SPI pin of the STM32 microcontroller via connector CN5. Pins 6 (VDDS), 7 (POL), 8 (PHA), and 9 (VDD) of chip U4 are connected to VCC and connected to the two decoupling capacitors. Pin 10 (IM) of chip U4 is connected to the terminating resistor and pin 3 of the external transformer. Pin 11 (IP) is connected to... The other end of the terminating resistor is connected to pin 1 of the external transformer. Pin 15 (ICMP) is grounded through the second external resistor and connected to one end of the first external resistor. Pin 16 (IBIAS) is connected to the other end of the first external resistor. Pins 2 and 5 of the external transformer are grounded through a capacitor. Pin 4 is connected to pin 2 of connector CN2, and pin 6 is connected to pin 1 of connector CN2. Pin 1 of connector CN2 is connected to the TX+ pin of external transformer U2 in the enhanced communication unit, and pin 2 is connected to the TX- pin of external transformer U2 in the enhanced communication unit, for use in series with the slave module for isoSPI communication.
[0045] Furthermore, the passive equalization unit includes several equalization modules. Each equalization module includes a field-effect transistor (P-MOS), a first current-limiting resistor, a second current-limiting resistor, a discharge resistor, and a light-emitting diode (LED). The source (pin 2) of the P-MOS is connected to the positive terminal of one cell in the battery pack, the gate (pin 1) is connected to one end of the first current-limiting resistor, the other end of the first current-limiting resistor is connected to an equalization pin of chip U1 (the equalization pins include pins S1-S12), the drain (pin 3) is connected to the anode of the LED and one end of the discharge resistor, the other end of the discharge resistor is connected to the positive terminal of another cell in the battery pack, the cathode of the LED is connected to one end of the second current-limiting resistor, and the other end of the second current-limiting resistor is connected to the positive terminal of another cell in the battery pack.
[0046] Furthermore, the filtering circuit includes several sets of grounding capacitors and several sets of RC low-pass filters composed of filter resistors and filter capacitors; one end of the filter resistor is connected to the positive terminal of a battery in the battery pack, and the other end is connected to a power supply pin of chip U1 (the power supply pins include pins C1-C12), and the other end is connected to one end of the grounding capacitor and one end of the filter power supply. The other end of the filter capacitor is connected to one end of the filter capacitor in another set of RC low-pass filters, and the other end of the grounding capacitor is grounded.
[0047] Furthermore, the temperature acquisition unit includes several sets of temperature acquisition probes and voltage divider resistors; one end of the voltage divider resistor is connected to pin 34 VREF2 of chip U1, and the other end is connected to the GPIO1 pin built into chip U1 and one end of the temperature acquisition probe, and the other end of the temperature acquisition probe is grounded.
[0048] Furthermore, the slave control module also includes a debugging section, which sets the indicator unit, measurement points Vref1 (TP1), Vref2 (TP2), and IBIAS1 (TP3). When Vref1 = 3V, the core of chip U1 enters the Measure state; when Vref2 = 3V, the auxiliary measurement channel of chip U1 is enabled; and when IBIAS1 = 2V, isoSPI in chip U1 is enabled. Figure 9 As shown, the indicator unit includes transistor U3, bypass capacitor C6, LED D2, and resistor R20. Pins 1 (B), 2 (C), and 4 (C) of transistor U3 are connected to chip U1, and pin 3 (E) is connected to pin 37 (VREG) of chip U1. The anode of LED D2 is connected to pin 37 (VREG) of chip U1, and its cathode is connected to resistor R20. The other end of resistor R20 is grounded. One end of bypass capacitor C6 is connected to pin 37 (VREG) of chip U1, and the other end is grounded. The LED indicates the circuit status, a 10KΩ resistor R20 limits current, and a 1uF bypass capacitor reduces power supply ripple. Transistor U3 is a CZT5551 TR PBFREE NPN transistor. Pin 1 is connected to the drive signal Drive1, pins 2 and 4 are connected to the power supply V1+, and pin 3 is connected to one end of bypass capacitor C6 and the anode of LED D2.
[0049] Furthermore, the slave control module also includes a fuse unit, comprising several fuses (F1-F24). One end of each fuse is connected to the acquisition pins (C0-C12 pins) of chip U1, and the other end is connected to the battery pack, such as... Figure 10 As shown.
[0050] In one specific embodiment, the circuit structure of the slave control AFE unit and its surrounding circuitry is as follows: Figure 4As shown; the LDO component is integrated into chip U1, and its related circuit structure is as follows: pin 38 DRIVE of chip U1 is connected to pin 1 of transistor U3 (CZT5551) in the debugging board, stepping down to 5V and outputting to pin 37 VREG of chip U1; pin 1 of chip U1 is connected to the positive terminal Cell_12+ of the 12th battery, and pin 31 is connected to the negative terminal Cell_1- of the first battery; pin 1B of transistor U3 is connected to pin 38 DRIVE of chip U1, and pins 2C and 4C are both connected to one end of capacitor C3 and one end of resistor R13. The other end of capacitor C3 is grounded, and the other end of resistor R13 is connected to the positive terminal of the 12th battery.
[0051] In one specific embodiment, such as Figure 5 As shown, the enhanced communication unit adopts a two-wire isolated interface and uses a simple twisted pair cable to cascade the chip U1, effectively expanding the acquisition channel. This communication method encodes the standard SPI into differential pulse isoSPI, sets the pulse strength and receiver threshold through external resistors, and uses an external transformer, which helps to improve the low packet error rate. The daisy chain conversion unit of this invention compromises power consumption and communication robustness, using two 1kΩ external resistors (R17, R18) to set the pulse strength and receiver threshold, and using 120Ω resistors (R14, R16) as terminating resistors. In order to optimize common-mode noise suppression, an HX1188NL external transformer (U2) with a center tap is used, and two 100pf capacitors (C4, C5) are also provided. The specific connection relationships are as follows: Pin 1 of U2 is connected to IPA of LTC6804-1 chip U1, pin 3 is connected to IMA of U1, and a terminating resistor R14 is connected between pin 1 and pin 3; pins 6 and 8 of U2 are connected to IPB and IMB of U1, and R16 is connected between pins 6 and pin 8; pins 2 and 7 of U2 are connected to capacitors C4 and C5 to ground respectively; pins 16 and 14 of U2 are connected to RX+ and RX- of the next level slave controller (or connected to the IP pin and IM pin of the CAN communication unit); pins 11 and 9 of U2 are connected to TX+ and TX- of the previous level slave controller; pins 4, 5, 12, and 13 of U2 are left floating; pin 1 of the isoSPI interface is connected to Vreg1 of chip U1, pin 2 is connected to ISOMD of chip U1, and pin 3 is grounded.
[0052] In one specific embodiment, the daisy-chain communication conversion unit uses an LTC6820 chip to convert standard SPI to differential isoSPI, enabling the connection of multiple LTC6804-1 chips, thereby minimizing wiring harnesses and components in the layout of this battery management system. Figure 2As shown, the daisy-chain communication conversion unit includes an LTC6820 chip U4, connectors (CN2, CN3, CN5, H10, H11, H12, H13), decoupling capacitors (C1, C4), and a single-channel daisy-chain circuit. The single-channel daisy-chain circuit includes two 1K external resistors (R2, R3) to set the pulse strength and receiver threshold, a 120Ω (R1) as a terminating resistor, an external transformer (L1) of model HM2103NLT, and 100pF capacitors (C2, C3) connected to the center tap to reduce electromagnetic interference. The specific connection relationships are as follows: U4 connects to the STM32 microcontroller's SPI interface via CN5 (MOSI, MISO, SCK, CS). H10 is a reserved interface for a logic analyzer, facilitating code debugging and SPI timing analysis. The VDDS pin and VDD pin are connected to the external power supply VCC, and VCC and GND are connected to the external power supply via H13. The EN, MSTR, and SLOW pins in U4 are reserved headers for mode settings. When EN is connected to VCC, the chip will always be in an enabled state. When EN is connected to GND, the chip will... The system sleeps for 5.5ms when there is no CS action or no IP / IM signal. When the SPI communication rate is above 200Kps, the SLOW pin of U4 must be connected to GND. When the MSTR pin is connected to VCC, U4 converts SPI to isoSPI. When the MSTR pin is connected to GND, U4 converts isoSPI to SPI. H13 is a jumper pin, and the EN pin is connected to pin 1EN of U4 to enable the chip. The SPI1 interface of the STM32 microcontroller is connected to H10 and then to U4. Connect pin 10's MOSI to pin 2MOSI of U4, pin 3MISO to pin 3MISO of U4, pin 4SCK to pin 4SCK of U4, and pin 5CS to pin 5CS of U4. Pins 6VDDS, 7POL, 8PHA, and 9VDD of U4 are connected to the VCC 5V power supply and two decoupling capacitors. The terminating resistor R1 is connected to pins 10IM and 11IP of U4 and to input pins 1 and 3 of L1. H12 is a jumper pin, and the MSTR pin... Connect pin 12MSTR to U4; H11 is a jumper pin, and the SLOW pin is connected to pin 13SLOW of U4; the GND terminal of U4 is grounded, pin 15ICMP of U4 is connected to ground through a 1k resistor R3 and to one end of a 1k resistor R2, and pin 16IBIAS of U4 is connected to the other end of R2; the center tap of L1, i.e., pins 2 and 5, is grounded through a 100pF capacitor, and pins 4 and 6 of L1 are connected to pins 2 and 1 of CN2 respectively, for serial slave communication via isoSPI.
[0053] In one specific embodiment, such as Figure 6The passive equalization unit shown is adapted to the 12 cells of the battery pack. It is equipped with 12 P-MOS field-effect transistors (Q1-Q12), 12 first current-limiting resistors (R23-R26, R39-R42, R55-R58), 12 second current-limiting resistors (R30, R32, R34, R36, R46, R48, R50, R52, R62, R64, R66, R68), 12 discharge resistors (R29, R31, R33, R35, R45, R47, R49, R51, R61, R63, R65, R67), and 12 light-emitting diodes. The first current-limiting resistor is a 3.3KΩ resistor as the current-limiting resistor for the equalization pin, the second current-limiting resistor is a 475Ω resistor as the current-limiting resistor for the LED circuit, and the discharge resistor is a 33Ω resistor. The P-MOS transistor uses the BSS84 chip, employing an external MOSFET for battery balancing. Control is achieved via the source pin, configured by the DCC bit in the configuration register. A 2512-packaged discharge resistor limits the MOSFET's power consumption, effectively dissipating heat and preventing damage due to excessive heat. Specific connections are as follows: pin 2 of Q1 (source) is connected to the positive terminal (Cell_12+) of the 12th battery; pin 1 of Q1 (gate) is connected to one end of the balancing pin current-limiting resistor R23, the other end of which is connected to pin S12 of chip U1; pin 3 of Q1 (drain) is connected to the anode of the LED and one end of the discharge resistor R29, the other end of which is connected to the positive terminal (Cell_11+) of the 11th battery; the cathode of the LED is connected to one end of the LED circuit current-limiting resistor R30, the other end of which is connected to the positive terminal (Cell_11+) of the 11th battery; other balancing circuit connections are consistent.
[0054] In one specific embodiment, such as Figure 7The filter circuit shown is adapted to a battery pack with 12 cells. It includes 12 sets of RC low-pass filters and 12 grounding capacitors (C7-C18). The RC low-pass filters reduce transient noise, and the grounding capacitors reduce high-frequency noise. The 12 sets of RC low-pass filters include 12 100Ω resistors (R21, R22, R27, R28, R37, R38, R43, R44, R53, R54, R59, R60) and 11 10nF capacitors (C19-C29). The specific connections are as follows: the positive terminal (Cell_1+) of the first cell is connected to resistor R21, and the other end of resistor R21 is connected to pin 24 (1+) of chip U1, and then connected to capacitors C7 and C19. The other end of 7 is grounded, and the other end of C19 is connected to pin 22 (2+) of chip U1; Cell_2+ is connected to resistor R27, the other end of which is connected to 2+, and capacitors C9 and C20 are connected thereto. The other end of C9 is grounded, and the other end of C20 is connected to 3+; Cell_3+ is connected to resistor R37, the other end of which is connected to 3+, and capacitors C11 and C21 are connected thereto. The other end of C11 is grounded, and the other end of C21 is connected to 4+; Cell_4+ is connected to resistor R43, the other end of which is connected to 4+, and capacitors C13 and C22 are connected thereto. The other end of C13 is grounded, and the other end of C22 is connected to 5+; Cell_ Cell 5+ is connected to resistor R53, the other end of which is connected to 5+, and then to capacitors C15 and C23. The other end of C15 is grounded, and the other end of C23 is connected to 6+. Cell 6+ is connected to resistor R59, the other end of which is connected to 6+, and then to capacitors C17 and C29. The other end of C17 is grounded, and the other end of C29 is connected to 7+. Cell 7+ is connected to resistor R22, the other end of which is connected to 7+, and then to capacitors C8 and C28. The other end of C8 is grounded, and the other end of C28 is connected to 8+. Cell 8+ is connected to resistor R28, the other end of which is connected to 8+, and then to capacitors C10 and C28. C27 and C10 are connected to ground at one end, and C27 is connected to 9+. Cell_9+ is connected to resistor R38, and R38 is connected to 9+. It is also connected to capacitors C12 and C26. C12 is connected to ground at one end, and C26 is connected to 10+. Cell_10+ is connected to resistor R44, and R44 is connected to 10+. It is also connected to capacitors C14 and C25. C14 is connected to ground at one end, and C25 is connected to 11+. Cell_11+ is connected to resistor R54, and R54 is connected to 11+. It is also connected to capacitors C16 and C24. C16 is connected to ground at one end, and C24 is connected to 12+.Cell_12+ is connected to resistor R60, the other end of resistor R60 is connected to 12+, and then to capacitor C18. The other end of C18 is grounded.
[0055] In one specific embodiment, such as Figure 8 As shown, the temperature acquisition unit is compatible with 12 batteries in the battery pack, and is equipped with 5 temperature acquisition probes (TH1, TH2, TH3, TH4, TH5) and 5 voltage divider resistors (R1, R2, R4, R5, R7). The temperature acquisition probes are TH1-TH5 NTC thermistors with a resistance of 100KΩ and a B value of 4130 at 25℃. The built-in Vref2 output of chip U1 provides bias current for the NTCs used. The 5 GPIO ports of chip U1 are used for ADC measurement, and the current temperature value is obtained through built-in functions. The specific connection relationship is: Vref2 in chip U1 is connected to resistor R1. R1, R2, R4, R5, R7; the other end of resistor R1 is connected to GPIO1 in chip U1, and then to thermistor TH1, with the other end of thermistor TH1 grounded; the other end of resistor R2 is connected to GPIO2, and then to thermistor TH2, with the other end of thermistor TH2 grounded; the other end of resistor R4 is connected to GPIO3, and then to thermistor TH3, with the other end of thermistor TH3 grounded; the other end of resistor R5 is connected to GPIO4, and then to thermistor TH4, with the other end of thermistor TH4 grounded; the other end of resistor R7 is connected to GPIO5, and then to thermistor TH5, with the other end of thermistor TH5 grounded.
[0056] On the other hand, in one specific embodiment, a battery box, employing the aforementioned battery management system, includes a box body, a battery pack, a main control PCB board, and a slave control PCB board. The main control module is integrated on the main control PCB board, and the slave control module is integrated on the slave control PCB board. The battery pack is placed inside the box body, and the main control PCB board and the slave control PCB board are fixed sequentially from top to bottom above the battery pack. The slave control PCB board further includes a spring, one end of which is fixed to the side of the slave control PCB board facing the battery pack and connected to a passive balancing unit, while the other end contacts the battery pack. Temperature acquisition probes of the temperature acquisition unit are spaced apart on the side of the slave control PCB board facing the battery pack. Figures 11-13 As shown.
[0057] Furthermore, the battery box is also equipped with a module cover plate that matches the opening on the top surface of the box, sealing the main control PCB board, slave control PCB board and battery pack inside the box.
[0058] Furthermore, the module cover plate, main control PCB board, slave control PCB board and the enclosure are fixedly connected by bolts and studs.
[0059] Furthermore, one end of the spring is provided with an electrode plate that has good conductivity, which is in contact with the positive or negative terminal of each battery in the battery pack.
[0060] In one specific embodiment, the battery box employs a flexible acquisition structure, where the control PCB board directly contacts the battery cell via a spring, and an NTC temperature probe is placed in close contact with the battery cell to achieve accurate measurement of the cell voltage and temperature, thereby replacing the traditional wire acquisition method. Figure 12 As shown, the slave control PCB module 2 integrates the acquisition spring 6, NTC temperature probe 7, cell overcurrent protection, and AFE analog front-end acquisition circuit. Structurally, this reduces the complexity of the acquisition wiring harness and the number of PCBs, making the module acquisition solution simpler and more efficient. Simultaneously, it optimizes the internal space layout of the battery box, reducing the overall system weight. For weight-sensitive applications (such as racing cars), this contributes to the lightweight design of the battery box. Figure 13 As shown, the battery box adopts a modular fastening method to ensure the stable installation of the PCB board. The M3×5 stud fasteners are fixed to the tab support plate 5 by adhesive bonding. The battery tabs of the battery pack are bent and placed in the groove of the tab support plate and fixed by laser welding of copper sheets. The slave control PCB board 2 is fastened to the M3×5 studs by 4 M3×6 bolts, thereby achieving stable support for the PCB board. The NTC temperature probes 7 are spaced apart on the bottom surface of the slave control PCB board 2, closely attached to the cell 3 to collect its temperature.
[0061] In addition, to further enhance structural reliability and ensure safe insulation coverage of high-voltage components, a module cover plate 1 made of ABS material (compliant with UL94-2013 fire rating, insulation class V0) is adopted. This cover plate is prepared using 3D printing additive manufacturing process and is fastened to the lifting lugs of the housing 4 by M4×12 bolts and M4 nuts. This prevents the PCB board from detaching from the battery cell tabs due to excessive spring force of spring 6, thus providing double clamping protection and ensuring the long-term stable operation of the data acquisition system.
[0062] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.
[0063] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A battery management system, characterized in that, It includes a master control module and at least one set of slave control modules; The main control module includes an STM32 microcontroller, a relay control unit, a CAN communication unit, and a daisy-chain communication conversion unit; the STM32 microcontroller is connected to the relay control unit, the CAN communication unit, and the daisy-chain communication conversion unit respectively. The slave control module includes a slave control AFE unit, a temperature acquisition unit, an enhanced communication unit, a passive equalization unit, and a filtering unit. The slave control AFE unit is connected to the temperature acquisition unit, the enhanced communication unit, the passive equalization unit, and the filtering unit, respectively. The passive equalization unit and the filtering unit are connected to the battery pack, and the enhanced communication unit is connected to the daisy-chain communication conversion unit. Multiple slave control modules are connected in series through the enhanced communication unit. The slave-controlled AFE unit includes a chip U1, which contains an LDO component. The V+ pin of chip U1 is connected to the positive terminal of the battery pack, and the V- pin is connected to the negative terminal of the battery pack. The power supply after being stepped down by the LDO component is output to the DRVE pin. The enhanced communication unit adopts a two-wire isolated interface and uses twisted-pair cables to cascade chips U1, thereby expanding the acquisition channels. The enhanced communication unit includes two external resistors, two terminating resistors, two capacitors, an external transformer U2, and an isoSPI interface. The TD+ pin of the external transformer U2 is connected to the IPA pin of chip U1, the TD- pin is connected to the IMA pin of chip U1, and a first terminating resistor is connected between the TD+ and TD- pins. The RD+ pin is connected to the IPB pin of chip U1, the RD- pin is connected to the IMB pin of chip U1, and a second terminating resistor is connected between the RD+ and RD- pins. The TCT pin is connected to the first capacitor, the RCT pin is connected to the second capacitor, and the other ends of the two capacitors are grounded. The TX- and TX+ pins are connected to the next-level slave module, and the RX- and RX+ pins are connected to the previous-level slave module. The first pin of the isoSPI interface is connected to the Vreg1 pin of chip U1, the second pin is connected to the ISOND pin of chip U1, and the third pin is grounded. This battery management system is used in a battery box, which includes a box body, a battery pack, a main control PCB board, and a slave control PCB board. The main control module is integrated on the main control PCB board, and the slave control module is integrated on the slave control PCB board. The battery pack is placed inside the box body, and the main control PCB board and the slave control PCB board are fixed on top of the battery pack. The slave control PCB board also includes a spring, one end of which is fixed to the side of the slave control PCB board facing the battery pack and connected to the passive equalization unit, and the other end contacts the battery pack. Temperature acquisition units are distributed at intervals on the side of the slave control PCB board facing the battery pack.
2. The battery management system according to claim 1, characterized in that, The daisy-chain communication conversion unit includes an LTC6820HMS chip U4, connectors CN5 and CN2, two decoupling capacitors, and a single-channel daisy-chain circuit. The single-channel daisy-chain circuit includes two external resistors, one terminating resistor, one external transformer, and two capacitors. Chip U4 is connected to the SPI pin of the STM32 microcontroller via connector CN5. Chip U4's VDDS, POL, PHA, and VDD pins are connected to VCC and connected to the two decoupling capacitors. Chip U4's IM pin is connected to the terminating resistor and pin 3 of the external transformer, and its IP pin is connected to the terminating resistor. The other end is connected to pin 1 of the external transformer. The ICMP pin is grounded through the second external resistor and connected to one end of the first external resistor. The IBIAS pin is connected to the other end of the first external resistor. Pins 2 and 5 of the external transformer are grounded through a capacitor. Pin 4 is connected to pin 2 of connector CN2, and pin 6 is connected to pin 1 of connector CN2. Pin 1 of connector CN2 is connected to the TX+ pin of external transformer U2 in the enhanced communication unit, and pin 2 is connected to the TX- pin of external transformer U2 in the enhanced communication unit, for use in series with the slave module for isoSPI communication.
3. The battery management system according to claim 1, characterized in that, The passive equalization unit includes several equalization modules. Each equalization module includes a field-effect transistor (P-MOS), a first current-limiting resistor, a second current-limiting resistor, a discharge resistor, and a light-emitting diode (LED). The source of the P-MOS is connected to the positive terminal of one cell in the battery pack, the gate is connected to one end of the first current-limiting resistor, the other end of the first current-limiting resistor is connected to an equalization pin of chip U1, the drain is connected to the anode of the LED and one end of the discharge resistor, the other end of the discharge resistor is connected to the positive terminal of another cell in the battery pack, the cathode of the LED is connected to one end of the second current-limiting resistor, and the other end of the second current-limiting resistor is connected to the positive terminal of another cell in the battery pack.
4. A battery management system according to claim 1, characterized in that, The filtering unit includes several sets of grounded capacitors and several sets of RC low-pass filters composed of filter resistors and filter capacitors; One end of the filter resistor is connected to the positive terminal of a battery in the battery pack, and the other end is connected to a sampling pin of chip U1. The other end is also connected to one end of the grounding capacitor and one end of the filter power supply. The other end of the filter capacitor is connected to one end of the filter capacitor in another set of RC low-pass filters, and the other end of the grounding capacitor is grounded.
5. A battery management system according to claim 1, characterized in that, The temperature acquisition unit includes several sets of temperature acquisition probes and voltage divider resistors; one end of the voltage divider resistor is connected to the VREF2 pin of chip U1, and the other end is connected to the GPIO1 pin built into chip U1 and one end of the temperature acquisition probe, and the other end of the temperature acquisition probe is grounded.
6. A battery management system according to claim 1, characterized in that, The slave control module also includes a debugging module, which sets measurement points Vref1, Vref2 and BIAS1. When Vref1=3V, the core of chip U1 enters the Measure state. When Vref2=3V, the auxiliary measurement channel of chip U1 is turned on. When IBIAS1=2V, isoSPI in chip U1 is enabled.
7. A battery management system according to claim 1, characterized in that, The slave control module also includes a fuse unit, which includes several fuses. One end of each fuse is connected to a data acquisition pin of the chip U1, and the other end is connected to the battery pack.