ESD electrostatic surge protection structure and method

Abstract

The invention relates to a special protection technology for electronic components, and provides an ESD (Electro-Static Discharge) electrostatic surge protection structure and method, which comprises a plurality of I / O (Input / Output) pins, a detection circuit, a transient voltage suppressor and a discharge channel. The I / O pin is connected with the detection circuit and is used for inputting signals. The detection circuit is used for analyzing ESD static events or surge events and inputting the ESD static events or surge events into the transient voltage suppressor and the discharge channel, and the transient voltage suppressor comprises a side TSV path and a center TSV path. The detection circuit comprises a voltage sensor and a current sensor, the voltage sensor is respectively connected with a first comparator and the amplitude detector, and the first comparator is used for monitoring the voltage slope of a signal input by the I / O pin. The current sensor is connected with a second comparator, and the second comparator is used for monitoring pulse energy and pulse duration of signals input by the plurality of I / O pins. Through multi-parameter dynamic analysis of a voltage slope, a pulse width, a voltage peak value and pulse energy, accurate event identification and classified protection are realized.

Description

Technical Field

[0001] The present invention relates to a special protection technology for electronic components, and in particular to an ESD electrostatic surge protection structure and method. Background Art

[0002] The continuous shrinking of integrated circuit (IC) process nodes and the increasing miniaturization of device dimensions have significantly increased the chip's sensitivity to transient voltage events such as electrostatic discharge (ESD) and surge. In practical applications, these high-energy, short-duration transient disturbances can cause permanent damage to the chip's internal circuitry, affecting system stability and reliability. Therefore, incorporating effective ESD surge protection structures into IC design has become an indispensable and critical step.

[0003] Traditional ESD protection solutions typically use structures such as diodes, MOS transistors, or silicon-controlled rectifiers (SCRs) as discharge paths. Their primary goal is to quickly conduct when an ESD event occurs, discharging the transient current to ground and thus protecting downstream circuitry. However, these structures often have limited response speeds and lack differentiated processing capabilities for different types of transient events (such as ESD static electricity or surges), making them prone to false triggering or insufficient response. Furthermore, traditional ESD protection devices can introduce significant parasitic capacitance in high-frequency signal paths, compromising signal integrity, particularly at high-speed I / O interfaces.

[0004] On the other hand, surge events are characterized by long duration and high energy, which are common in lightning strikes or power switching processes. Traditional ESD protection structures are unable to withstand their continuous energy impact, resulting in protection failure or even device burning.

[0005] In view of this, the existing technology still lacks a protection structure that can identify and dynamically respond to ESD and surge events, especially to achieve low parasitic capacitance, high response speed and large energy carrying capacity in high-speed signal paths. Summary of the Invention

[0006] In summary, the present invention proposes an ESD electrostatic surge protection structure and method, which aims to solve the problem of identifying and dynamically responding to ESD and surge events, and achieve rapid response and precise protection against different types of transient events.

[0007] The technical solution of the present invention is achieved as follows:

[0008] An ESD electrostatic surge protection structure includes multiple I / O pins, a detection circuit, a transient voltage suppressor, and a discharge channel, characterized in that:

[0009] The I / O pin is connected to the detection circuit for inputting a signal;

[0010] The detection circuit is used to analyze ESD static events or surge events and input transient voltage suppressors and discharge channels. The transient voltage suppressors include side TSV paths and center TSV paths.

[0011] in,

[0012] The detection circuit includes a voltage sensor and a current sensor, wherein the voltage sensor is connected to a first comparator and an amplitude detector respectively. The first comparator is used to monitor the voltage slope of the signal input by the I / O pin.

[0013] The current sensor is connected to a second comparator, which is used to monitor the pulse energy and pulse duration of the signals input by the multiple I / O pins.

[0014] The voltage slope, pulse energy, and pulse duration are input into the event analysis unit. If the voltage slope exceeds the set threshold, it is determined to be an ESD event and the side TSV path is turned on.

[0015] If the pulse width duration exceeds the set threshold, it is determined to be a surge event and the center TSV path is turned on.

[0016] It should be noted that

[0017] If the voltage slope is ≤1V / ns, it is directly determined to be a harmless noise event;

[0018] If the voltage slope is greater than 1V / ns and the pulse duration is less than or equal to 500ns, it is directly determined to be an ESD event and the side TSV path is turned on;

[0019] If the voltage slope is greater than 1V / ns and the pulse duration is greater than 500ns, the pulse energy evaluation phase is performed. If the pulse energy exceeds 5mJ, it is determined to be a surge event and the central TSV path is turned on. If the pulse energy is less than 5mJ, it is determined to be a transient interference.

[0020] It should be noted that the side TSV path has a diameter of 20 μm×200 μm, an aspect ratio of 10:1, and is composed of polysilicon filling, a TiN barrier layer, and a SiO2 insulating layer.

[0021] It should be noted that the central TSV path has a diameter of 80 μm×400 μm, an aspect ratio of 5:1, and is composed of copper filling, a TaN barrier layer, and an air gap insulation layer.

[0022] It should be noted that the transient voltage suppressor further includes a TVS diode, which is connected to the side TSV path and the center TSV path respectively. The TVS diode includes a P+ anode, an N+ cathode and an epitaxial layer.

[0023] It should be noted that the TVS diode includes a highly doped P++ substrate, on which a first epitaxial layer P++ isolation region is provided. A buried layer on the P++ isolation region forms an N+ region, and a second epitaxial process forms an N-type epitaxial layer.

[0024] It should be noted that the P++ isolation region is used as the P-type region of the TVS diode and is connected to the highly doped P++ substrate to form an N+ region on the surface of the P-type region, constituting a low breakdown voltage avalanche diode.

[0025] It should be noted that highly doped P+ and N+ regions are formed on the N-type epitaxial layer, wherein the P+ / N- / N++ structure forms a PIN type low capacitance diode D2; and the N+ / N- / P++ structure forms a NIP type low capacitance diode D1.

[0026] It should be noted that the detection circuit further includes a temperature sensor and a thermal management unit, wherein the temperature sensor is connected to the event analysis unit via the thermal management unit for monitoring temperature for overheating protection.

[0027] An ESD electrostatic surge protection method, comprising the ESD electrostatic surge protection structure according to claim 1, characterized in that it further comprises the following steps:

[0028] Step 1: Detect the voltage and current in the circuit respectively to perform transient high voltage protection and transient overcurrent protection;

[0029] Step 2: Capture the voltage peak of the input signal in real time and calculate the voltage slope of the input signal from multiple I / O pins;

[0030] Step 3: Monitor the pulse width of the input signal from the multiple I / O pins 11 and calculate the pulse energy;

[0031] Step 4: The voltage slope and pulse energy are input into the event analysis unit to analyze the specific event, and the path control unit controls the corresponding path to be turned on;

[0032] Step 5: The temperature sensor is connected to the event analysis unit via the thermal management unit to monitor the temperature for overheating protection and implement predictive protection when the temperature exceeds the threshold.

[0033] The ESD electrostatic surge protection structure and method of the present invention have the following beneficial effects:

[0034] 1. Accurately identify events and perform classified protection, and achieve nanosecond-level event judgment through multi-parameter dynamic analysis of voltage slope (dV / dt), pulse width, voltage peak and pulse energy.

[0035] 2. Dual-path coordinated discharge mechanism: The side TSV path uses polysilicon filling + TiN barrier layer structure, which has high resistance but extremely fast response to ESD static events; the central TSV path uses copper filling + Ta barrier layer + air gap insulation, which has low resistance and can carry continuous large current to deal with surge / lightning impact. The path control unit conducts the optimal path in real time according to the event type, taking into account both speed and current capacity.

[0036] 3. The TVS diode adopts a double epitaxial layer structure, and forms an avalanche diode + low-capacitance diode D1 / D2 through doping control. The breakdown voltage can be customized, saving area and reducing manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 This is a structural block diagram of the ESD electrostatic surge protection structure of the present invention;

[0038] Figure 2 This is a structural block diagram of the ESD electrostatic surge protection structure of the present invention;

[0039] Figure 3 It is a structural block diagram of the detection circuit of the present invention;

[0040] Figure 4 It is a logic block diagram of the detection circuit of the present invention;

[0041] Figure 5 is a structural block diagram of a transient voltage suppressor of the present invention;

[0042] Figure 6 is a structural block diagram of a transient voltage suppressor of the present invention;

[0043] Figure 7 Schematic diagram of the structure of the TVS diode of the present invention;

[0044] Figure 8 Flow chart of the ESD electrostatic surge protection method of the present invention;

[0045] The reference numerals are represented as follows: ESD electrostatic surge protection structure 100, I / O pin 11, detection circuit 12, voltage sensor 121, first comparator 123, amplitude detector 124, current sensor 122, second comparator 125, event analysis unit 126, path control unit 127, temperature sensor 128, thermal management unit 129, transient voltage suppressor 13, side TSV path 131, center TSV path 132, TVS diode 133, and discharge channel 14. Implementation Method

[0046] The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present invention.

[0047] Example 1

[0048] refer to Figures 1 to 2 As shown, the present invention proposes an ESD surge protection structure 100 for protecting delicate structures within integrated circuits (ICs). Under normal operating conditions, it does not interfere with circuit operation. In the event of an ESD or surge event, it quickly turns on, discharging transient high currents to ground. After the discharge, it automatically returns to a high-impedance state, ensuring continued normal system operation.

[0049] In one embodiment, an ESD surge protection structure 100 includes multiple I / O pins 11, a detection circuit 12, a transient voltage suppressor 13, and a discharge channel 14. The multiple I / O pins 11 are connected to the detection circuit 12 for inputting signals. The detection circuit 12 is configured to analyze ESD events or surge events and input signals to the transient voltage suppressor 13 and discharge channel 14 for suppression and protection.

[0050] In one embodiment, reference Figure 3 As shown, the detection circuit 12 includes a voltage sensor 121 and a current sensor 122. The voltage sensor 121 is connected to a first comparator 123 and an amplitude detector 124 respectively. The first comparator 123 is used to monitor the voltage slope of the input signal from the multiple I / O pins 11, expressed as: dV / dt. The amplitude detector 124 is used to capture the voltage peak value (Peak Value) of the input signal in real time. Accurately identify the intensity of transient events within nanoseconds and provide key parameters for event classification. The current sensor 122 is connected to the second comparator 125, and the second comparator 125 is used to monitor the pulse energy and pulse duration of the input signal from the multiple I / O pins.

[0051] The first comparator 123, the amplitude detector 124, and the second comparator 125 input the acquired parameters into the event analysis unit 126 and the path control unit 127. The transient voltage suppressor 13 includes a side TSV path 131 and a center TSV path 132. If the voltage slope exceeds a set threshold, it is determined to be an ESD event and the side TSV path is turned on. If the pulse width duration exceeds a set threshold, it is determined to be a surge event and the center TSV path is turned on.

[0052] It should be noted that the reference Figure 4 As shown, the specific working principle of the event analysis unit 126 is as follows:

[0053] First, the voltage slope in the circuit is monitored in real time. If the voltage slope is ≤1V / ns, it is directly judged as a relatively harmless noise event. If the voltage slope is >1V / ns, the system further analyzes its pulse width. If the pulse duration is less than or equal to 500ns, it is directly judged as an ESD event and the side TSV path is turned on. If the voltage slope is >1V / ns and the pulse width is >500ns, a slower event is evaluated for pulse energy. Such events may appear to be surges caused by lightning strikes or power switching. If the pulse energy exceeds 5mJ, it is judged as a surge event and the center TSV path is turned on. If the pulse energy is less than 5mJ, it is judged as a transient interference and the "No Action" option is selected to avoid frequent operations that may affect stability.

[0054] Event Analysis Unit 126 achieves rapid and accurate identification and differentiated protection against different types of transient threats through precise, step-by-step matching of characteristic parameters such as voltage slope, pulse width, and pulse energy. By dynamically selecting the optimal discharge path, it provides both rapid response to ESD and effective protection against the sustained, high-energy impact of surges, while minimizing interference with normal operation and significantly improving reliability and robustness.

[0055] In one embodiment, referring to Figures 5 and 6 As shown, the transient voltage suppressor 13 also includes a TVS diode 133, which is connected to the discharge channel 14 via a side TSV path 131 and a center TSV path 132. The TVS diode 133 includes a P+ anode, an N+ cathode, and an epitaxial layer. When external static electricity or surges intrude into the signal terminal, the TVS diode, as the first-level response unit, is activated first. The epitaxial layer between the P+ anode and the N+ cathode undergoes avalanche breakdown or Zener breakdown under high voltage, instantly switching from a high-resistance state to a low-resistance conduction state, and then is introduced into the discharge channel 14 via the side TSV path 131 or the center TSV path 132.

[0056] Specifically, the path control unit 127 controls whether the side TSV paths 131 and the center TSV paths 132 are conductive. If the event analysis unit 126 determines an ESD event, the path control unit 127 controls the side TSV paths 131 to be conductive and the center TSV paths 132 to be closed. If the event analysis unit 126 determines a surge event, the path control unit 127 controls the center TSV paths 132 to be conductive and the side TSV paths 131 to be closed. The side TSV paths 131 have a diameter of 20μm x 200μm and a depth-to-width ratio of 10:1. They are constructed with polysilicon fill, a TiN barrier layer, and a SiO2 insulation layer. They have high resistance but fast response. The center TSV paths 132 have a diameter of 80μm x 400μm and a depth-to-width ratio of 5:1. They are constructed with copper fill, a TaN barrier layer, and an air gap insulation layer. They have low resistance and can carry high currents.

[0057] In one embodiment, referring to Figure 7 As shown, improvements have been made to the process for TVS diode 133. First, a first epitaxial layer, the P++ region, is grown on a highly doped P++ substrate. This is followed by a buried layer process to form the N+ region. A second epitaxial process then proceeds to grow the N-type epitaxial layer. This second epitaxial layer, unlike the first, is a high-resistivity N-type epitaxial layer.

[0058] Further adjustments are made to the TVS diode and low-capacitance diodes D1 and D2. The P++ isolation region serves as the P-type region of the TVS diode. Connected to the highly doped P++ substrate, it forms an N+ region on the surface of the P-type region, creating a low-breakdown-voltage avalanche diode. By adjusting the doping concentration, the reverse breakdown voltage of the TVS diode can be controlled.

[0059] Highly doped P+ and N+ regions are formed on the N-type epitaxial layer. The P+ / N- / N++ structure forms a PIN-type low-capacitance diode D2, while the N+ / N- / P++ structure forms a NIP-type low-capacitance diode D1.

[0060] That is, an N-type epitaxial layer is grown on the P-type epitaxial layer, and the doping type is adjusted through ion implantation and other methods, and a TVS protection device and low-capacitance diodes D1 and D2 are formed at the same time, thereby achieving a low-cost, low parasitic capacitance and high-performance solution.

[0061] Example 2

[0062] Based on the above embodiments, Figures 1 to 8 As shown, this embodiment also provides an ESD electrostatic surge protection method, including:

[0063] Step 1: Detect the voltage and current in the circuit respectively to perform transient high voltage protection and transient overcurrent protection;

[0064] Step 2: Capture the input signal's voltage peak in real time and calculate the voltage slope of the input signals from multiple I / O pins. Detecting voltage slope is a key parameter for identifying ESD events. A typical ESD event is characterized by an extremely short voltage rise time, resulting in a large voltage slope.

[0065] Furthermore, the voltage slope is expressed as dV / dt, and the calculation formula is as follows:

[0066]

[0067] Wherein, V1 represents the voltage value at time t1, V2 represents the voltage value at time t2, ΔV represents the voltage change, ΔV=V2-V1, and Δt represents the time change, Δt=t2-t1.

[0068] For discrete calculation, the difference approximation is expressed as:

[0069]

[0070] Where V[n] represents the voltage at the nth sampling point, T s Represents the sampling period. It enables real-time, stable, and low-noise differential calculations on a nanosecond timescale. This can be applied to high-speed ESD event identification, enabling the rapid capture of the steep leading edge of ESD events.

[0071] Step 3: Monitor the pulse width duration of the signals input from the multiple I / O pins 11 and calculate the pulse energy. The calculation formula of the pulse energy is as follows:

[0072]

[0073] Where E is the pulse energy, P(t) is the instantaneous power, V(t) is the instantaneous voltage, and I(t) is the instantaneous current.

[0074] Its effectiveness lies in quantifying the destructive potential of transient events. Surge events, such as lightning induction and power switching, may have slower rise times than ESD events, but they last longer and accumulate significant energy. Relying solely on pulse width may not be sufficient to distinguish between dangerous high-energy surges and harmless low-energy transients. Combining the pulse width and duration monitored in Step 3 with the generated pulse energy provides accurate parameters for determining surge events requiring high-current discharge capabilities, such as pulse energies less than 5mJ. This avoids false triggering of low-energy events and improves system stability.

[0075] Step 4: The voltage slope and pulse energy are input into the event analysis unit 126 to analyze the specific event, and the path control unit 127 controls the corresponding path to be turned on, thereby achieving hierarchical judgment and avoiding misjudgment of a single parameter.

[0076] Among them, if the voltage slope exceeds the set threshold and the pulse duration does not exceed the set threshold, it is determined to be an ESD electrostatic event and the side TSV path is turned on; if the voltage slope exceeds the set threshold and the pulse duration exceeds the set threshold, it is determined to be a surge event and the center TSV path is turned on.

[0077] In this embodiment, the corresponding path is controlled to be conductive based on the event analysis result.

[0078] In the event of an ESD event, the fast-response side TSV path is turned on to discharge the current in a very short time, protecting sensitive circuits from nanosecond-level high-voltage shocks. However, the side TSV path has high resistance but limited current carrying capacity.

[0079] In the event of a surge, the central TSV path with low on-resistance and strong current-carrying capacity can withstand long-term high-current discharge and prevent the device from burning due to overheating.

[0080] Also, for harmless events, such as low-energy events, "No Action" is selected to minimize the impact on normal circuit operation and improve system stability and robustness.

[0081] Preferably, it also includes, Step 5: referring to Figure 3 As shown, the temperature sensor 128 is connected to the event analysis unit 126 via the thermal management unit 129 to monitor the temperature for overheating protection and implement predictive protection when the temperature exceeds a threshold.

[0082] Establish a temperature prediction model, and the calculation formula is as follows:

[0083]

[0084] Among them, T j (t) represents the real-time junction temperature, T a Indicates the ambient temperature, P s Represents power loss, R th Indicates thermal resistance. When T j (t)<125℃, no response; when T j (t)<140℃, dynamic derating is performed; when 140℃<T j (t)<150℃, forced derating is performed; when T j (t)>150℃, shut down immediately; when T j (t)>175℃, perform fuse isolation.

[0085] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An ESD electrostatic surge protection structure, comprising a plurality of I / O pins, a detection circuit, a transient voltage suppressor, and a discharge channel, characterized in that: The I / O pin is connected to the detection circuit for inputting a signal; The detection circuit is used to analyze ESD static events or surge events and input transient voltage suppressors and discharge channels. The transient voltage suppressor includes a side TSV path and a center TSV path. in, The detection circuit includes a voltage sensor and a current sensor, wherein the voltage sensor is connected to a first comparator and an amplitude detector respectively. The first comparator is used to monitor the voltage slope of the signal input by the I / O pin. The current sensor is connected to a second comparator, which is used to monitor the pulse energy and pulse duration of the signals input by the multiple I / O pins. The voltage slope, pulse energy, and pulse duration are input into the event analysis unit. If the voltage slope exceeds the set threshold, it is determined to be an ESD event and the side TSV path is turned on. If the pulse width duration exceeds the set threshold, it is determined to be a surge event and the center TSV path is turned on.

2. The ESD electrostatic surge protection structure according to claim 1, characterized in that: If the voltage slope is ≤1V / ns, it is directly determined to be a harmless noise event; If the voltage slope is greater than 1V / ns and the pulse duration is less than or equal to 500ns, it is directly determined to be an ESD event and the side TSV path is turned on; If the voltage slope is greater than 1V / ns and the pulse duration is greater than 500ns, the pulse energy evaluation phase is performed. If the pulse energy exceeds 5mJ, it is determined to be a surge event and the central TSV path is turned on. If the pulse energy is less than 5mJ, it is determined to be a transient interference.

3. The ESD electrostatic surge protection structure according to claim 1, characterized in that: The side TSV path has a diameter of 20 μm×200 μm and an aspect ratio of 10:1, and is composed of polysilicon filling, a TiN barrier layer, and a SiO2 insulating layer.

4. The ESD electrostatic surge protection structure according to claim 1, characterized in that: The central TSV path has a diameter of 80 μm×400 μm and an aspect ratio of 5:1, and is composed of a copper filling, a TaN barrier layer, and an air gap insulation layer.

5. The ESD electrostatic surge protection structure according to claim 1, characterized in that: The transient voltage suppressor further includes a TVS diode, which is connected to the side TSV path and the center TSV path respectively. The TVS diode includes a P+ anode, an N+ cathode, and an epitaxial layer.

6. The ESD electrostatic surge protection structure according to claim 5, characterized in that: The TVS diode includes a highly doped P++ substrate, a first epitaxial layer P++ isolation region is provided on the P++ substrate, a buried layer on the P++ isolation region forms an N+ region, and a second epitaxial process forms an N-type epitaxial layer.

7. The ESD electrostatic surge protection structure according to claim 6, characterized in that: The P++ isolation region is used as the P-type region of the TVS diode and is connected to the highly doped P++ substrate to form an N+ region on the surface of the P-type region, thereby constituting a low breakdown voltage avalanche diode.

8. The ESD electrostatic surge protection structure according to claim 7, characterized in that: Highly doped P+ and N+ regions are formed on the N-type epitaxial layer, wherein the P+ / N- / N++ structure forms a PIN type low capacitance diode D2; and the N+ / N- / P++ structure forms a NIP type low capacitance diode D1.

9. The ESD electrostatic surge protection structure according to claim 1, characterized in that: The detection circuit further includes a temperature sensor and a thermal management unit, wherein the temperature sensor is connected to the event analysis unit via the thermal management unit for monitoring temperature for overheating protection.

10. An ESD electrostatic surge protection method, comprising the ESD electrostatic surge protection structure according to claim 1, characterized in that: The following steps are also included: Step 1: Detect the voltage and current in the circuit respectively to perform transient high voltage protection and transient overcurrent protection; Step 2: Capture the voltage peak of the input signal in real time and calculate the voltage slope of the input signal from multiple I / O pins; Step 3: Monitor the pulse width of the input signal from the multiple I / O pins 11 and calculate the pulse energy; Step 4: The voltage slope and pulse energy are input into the event analysis unit to analyze the specific event, and the path control unit controls the corresponding path to be turned on; Step 5: The temperature sensor is connected to the event analysis unit via the thermal management unit to monitor the temperature for overheating protection and implement predictive protection when the temperature exceeds the threshold.

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