Data detection circuit and data detection method

Abstract

The present disclosure provides a data detection circuit and a data detection method, the data detection circuit comprising: a plurality of processing circuits, each of the plurality of processing circuits being configured to: obtain a first indicator based on input data, and obtain output data based on the input data; the number of 0 in the output data is smaller than the number of 0 in the input data; the plurality of processing circuits are sequentially coupled, the input data of the first processing circuit in the plurality of processing circuits comprises initial input data, and the input data of the Xth processing circuit in the plurality of processing circuits comprises the output data of the (X-1) th processing circuit; x is an integer greater than 1; and the detection circuit is configured to obtain a detection result of the initial input data based on the first indicator obtained by the plurality of processing circuits and the output data of the last processing circuit in the plurality of processing circuits.

Description

Technical Field

[0001] The present disclosure relates to the field of data processing technology, and in particular to a data detection circuit and a data detection method. Background Art

[0002] One-hot code is a special encoding method that is widely used in digital circuit design, such as state machine encoding and transmission encoding. One-hot code has the advantages of being intuitive and easy to implement, but it is also prone to generating invalid states. Therefore, it is very necessary to detect the validity of one-hot code, otherwise the circuit using one-hot code may enter an erroneous state. For one-hot codes with a small number of bits, simple combinational circuits can be used to detect them. However, as the number of bits increases, the complexity of the one-hot code detection circuit increases sharply. When facing large-scale or ultra-long one-hot code detection, the one-hot code detection circuit may have the defects of large circuit area and slow detection speed, which will limit the application scenarios of the one-hot code detection circuit. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a data detection circuit and a data detection method.

[0004] To achieve the above objectives, the technical solution of the embodiment of the present disclosure is implemented as follows:

[0005] In a first aspect, the present disclosure provides a data detection circuit, comprising:

[0006] a plurality of processing circuits, each of the plurality of processing circuits being configured to: obtain a first indicator based on input data, and obtain output data based on the input data; the number of zeros in the output data being less than the number of zeros in the input data; the plurality of processing circuits being coupled sequentially, and the input data of a first processing circuit of the plurality of processing circuits comprising initial input data, and the input data of an Xth processing circuit of the plurality of processing circuits comprising output data of an X-1th processing circuit; wherein X is an integer greater than 1;

[0007] The detection circuit is configured to obtain a detection result of the initial input data based on the first indicators obtained by the multiple processing circuits and output data of a last processing circuit among the multiple processing circuits.

[0008] In an optional embodiment, the number of bits of the input data of each processing circuit is an even number, and every two adjacent bits in the input data form a bit group; each processing circuit includes:

[0009] The compression circuit is configured to perform a first logic operation on two bits in each bit group of the input data to obtain one bit in the output data.

[0010] In an optional implementation, each of the processing circuits further includes:

[0011] The first sub-processing circuit is configured to: perform a second logical operation on two bits in each bit group of the input data to obtain a bit in the intermediate data; if the input data includes a bit group in which both bits are 1, the intermediate data includes a bit that is 0; otherwise, all bits of the intermediate data are 1.

[0012] In an optional implementation, the first indicator obtained by the last processing circuit is equal to the intermediate data obtained by the last processing circuit; and the processing circuits other than the last processing circuit in the plurality of processing circuits further include:

[0013] a second sub-processing circuit, wherein an input terminal of the second sub-processing circuit is coupled to an output terminal of the first sub-processing circuit and is configured to: perform a third logical operation on all bits in the intermediate data to obtain the first indicator; if the intermediate data includes a bit that is 0, obtain the first indicator in a first state; otherwise, obtain the first indicator in a second state.

[0014] In an optional embodiment, the detection circuit includes:

[0015] a first sub-detection circuit, configured to: perform a fourth logical operation on the first indicators obtained by the plurality of processing circuits to obtain a second indicator;

[0016] The second sub-detection circuit is configured to: perform a fifth logic operation on the second indicator and the output data of the last processing circuit to obtain a third indicator; the second indicator and the third indicator are configured to indicate the detection result of the initial input data.

[0017] In an optional embodiment, the first logical operation is an OR operation, the second logical operation and the fifth logical operation are both NAND operations, and the third logical operation and the fourth logical operation are both AND operations; the first indicator in the first state is 0, and the first indicator in the second state is 1;

[0018] If the initial input data is a one-hot code, the second indicator is 1 and the third indicator is 0;

[0019] If all bits of the initial input data are 0, the second indicator is 1, and the third indicator is 1;

[0020] If the initial input data includes at least two bits that are 1, the second indicator is 0 and the third indicator is 1.

[0021] In an optional embodiment, the second sub-processing circuit includes: a plurality of NAND gates and at least one NOR gate; the intermediate data is inputted via input terminals of the NAND gates, the input terminals of the NOR gates are coupled to output terminals of at least two of the NAND gates, and the first indicator is outputted by one of the NOR gates; or,

[0022] The second sub-processing circuit includes: a NAND gate and a NOT gate; the intermediate data is inputted through the input terminal of the NAND gate, the input terminal of the NOT gate is coupled to the output terminal of the NAND gate, and the first indicator is outputted by the NOT gate; or,

[0023] The second sub-processing circuit includes: multiple NAND gates, multiple NOR gates and a NOT gate; the intermediate data is input by the input end of the NAND gate, the input end of the NOR gate is coupled to the output end of at least two of the NAND gates, the output end of the NOR gate is coupled to the input end of at least one of the NAND gates, the input end of the NOT gate is coupled to the output end of one of the NAND gates, and the first indicator is output by the NOT gate.

[0024] In an optional implementation, the initial input data includes N bits, where N is an integer greater than 1; if N is an odd number, the input data of the first processing circuit includes the initial input data and a bit that is 0.

[0025] In an optional embodiment, the data detection circuit includes M processing circuits, where M is an integer; M is greater than or equal to the logarithm of N with base 2, and M is less than the logarithm of N with base 2 plus 1.

[0026] In a second aspect, the present disclosure provides a data detection method, comprising:

[0027] performing a plurality of processing operations, each of the plurality of processing operations comprising: obtaining a first indicator based on input data, and obtaining output data based on the input data; the number of zeros in the output data is less than the number of zeros in the input data; the input data of a first processing operation of the plurality of processing operations comprises the initial input data; the input data of an Xth processing operation of the plurality of processing operations comprises the output data of an X-1th processing operation; and X is an integer greater than 1;

[0028] A detection result of the initial input data is obtained based on the first indicator obtained through the multiple processing operations and the output data obtained through the last processing operation among the multiple processing operations.

[0029] In an optional embodiment, the number of bits of the input data for each processing operation is an even number, and every two adjacent bits in the input data form a bit group; and obtaining output data based on the input data includes:

[0030] A first logical operation is performed on two bits in each bit group of the input data to obtain one bit in the output data.

[0031] In an optional embodiment, each processing operation specifically includes:

[0032] A second logical operation is performed on the two bits in each bit group of the input data to obtain a bit in the intermediate data; if the input data includes a bit group in which both bits are 1, the intermediate data includes a bit that is 0; otherwise, all bits of the intermediate data are 1.

[0033] In an optional implementation, the first indicator obtained by the last processing operation is equal to the intermediate data obtained by the last processing operation; and the multiple processing operations other than the last processing operation further include:

[0034] A third logical operation is performed on all bits in the intermediate data to obtain the first indicator; if the intermediate data includes bits that are 0, the first indicator in the first state is obtained; otherwise, the first indicator in the second state is obtained.

[0035] In an optional embodiment, obtaining the detection result of the initial input data based on the first indicator obtained through the multiple processing operations and the output data obtained through the last processing operation among the multiple processing operations includes:

[0036] performing a fourth logical operation on the first indicator obtained through the multiple processing operations to obtain a second indicator;

[0037] A fifth logical operation is performed on the second indicator and the output data obtained through the last processing operation to obtain a third indicator; the second indicator and the third indicator are configured to indicate a detection result of the initial input data.

[0038] In an optional embodiment, the first logical operation is an OR operation, the second logical operation and the fifth logical operation are both NAND operations, and the third logical operation and the fourth logical operation are both AND operations; the first indicator in the first state is 0, and the first indicator in the second state is 1;

[0039] If the initial input data is a one-hot code, the second indicator is 1 and the third indicator is 0;

[0040] If all bits of the initial input data are 0, the second indicator is 1, and the third indicator is 1;

[0041] If the initial input data includes at least two bits that are 1, the second indicator is 0 and the third indicator is 1.

[0042] In an optional embodiment, the initial input data includes N bits, where N is an integer greater than 1; if N is an odd number, the input data of the first processing operation includes the initial input data and a bit that is 0.

[0043] In an optional embodiment, the data detection method includes M processing operations, where M is an integer; M is greater than or equal to the logarithm of N with base 2, and M is less than the logarithm of N with base 2 plus 1.

[0044] In the technical solution provided in the present disclosure, the data detection circuit may include multiple processing circuits and a detection circuit. The multiple processing circuits can quickly compress the number of 0s in the initial input data, so that the 1s (if any) in the initial input data are close to each other. At the same time, a first indicator can be obtained to indicate whether there are two adjacent bits that are both 1 in the input data of each processing circuit. The detection circuit can obtain the detection result of the initial input data based on the multiple first indicators obtained by the multiple processing circuits and the output data of the last processing circuit. Therefore, the data detection circuit can have a smaller circuit area and a faster detection speed, which is conducive to expanding the application scenarios of the data detection circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 A schematic diagram of a data detection circuit provided in an embodiment of the present disclosure;

[0046] Figure 2 A schematic diagram of a processing circuit provided in an embodiment of the present disclosure;

[0047] Figure 3 A schematic diagram of a detection circuit provided in an embodiment of the present disclosure;

[0048] Figure 4Circuit diagram of a processing circuit provided for a specific example of the present disclosure Figure 1 ;

[0049] Figure 5 Circuit diagram of a processing circuit provided for a specific example of the present disclosure Figure 2 ;

[0050] Figure 6 Circuit diagram of a processing circuit provided for a specific example of the present disclosure Figure 3 ;

[0051] Figure 7 Circuit diagram of a processing circuit provided for a specific example of the present disclosure Figure 4 ;

[0052] Figure 8 Circuit diagram of a processing circuit provided for a specific example of the present disclosure Figure 5 ;

[0053] Figure 9 Circuit diagram of a processing circuit provided for a specific example of the present disclosure Figure 6 ;

[0054] Figure 10 A circuit diagram of a detection circuit provided for a specific example of the present disclosure;

[0055] Figure 11 A flowchart of a data detection method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0056] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0057] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0058] In the drawings, like reference numerals refer to like elements throughout.

[0059] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0060] One-hot codes are a special encoding method widely used in digital circuit design, such as state machine coding and transmission coding. While intuitive and easy to implement, one-hot codes are also prone to generating invalid states. Therefore, validating one-hot codes is essential, as otherwise, circuits utilizing them may enter erroneous states. For one-hot codes with a small number of bits, simple combinational circuits can be used to detect them. For example, an adder can be used to sequentially add all bits in the sequence to be tested. If the resulting sum is 1, the sequence to be tested is considered a one-hot code; otherwise, it is considered not a one-hot code. Alternatively, a parity check can be performed on the sequence to be tested, followed by a bitwise XOR operation on the sequence to be tested, the resulting XOR sequence is bitwise inverted, and the resulting XOR sequence and the inverted sequence are bitwise ORed. If all bits in the resulting sequence are 1, the sequence to be tested is considered a one-hot code; otherwise, it is considered not a one-hot code.

[0061] However, as the number of bits in the sequence to be detected increases, the complexity of the one-hot code detection circuit will increase sharply. When facing large-scale or ultra-long one-hot code detection, the one-hot code detection circuit may have defects such as large circuit area or slow detection speed, which will limit the application scenarios of the one-hot code detection circuit.

[0062] To this end, the present disclosure proposes the following embodiments.

[0063] The present disclosure provides a data detection circuit, which includes: multiple processing circuits, each of the multiple processing circuits is configured to: obtain a first indicator based on input data, and obtain output data based on the input data; the number of zeros in the output data is less than the number of zeros in the input data; the multiple processing circuits are coupled in sequence, and the input data of the first processing circuit among the multiple processing circuits includes initial input data, and the input data of the Xth processing circuit among the multiple processing circuits includes output data of the X-1th processing circuit; X is an integer greater than 1; the detection circuit is configured to: obtain a detection result of the initial input data based on the first indicators obtained by the multiple processing circuits and the output data of the last processing circuit among the multiple processing circuits.

[0064] Figure 1 A schematic diagram of a data detection circuit provided in an embodiment of the present disclosure, referring to Figure 1 The data detection circuit includes multiple processing circuits 100, which are coupled in sequence. The input data of the first processing circuit 100 includes initial input data, and the input data of the processing circuits 100 other than the first processing circuit 100 includes the output data of the previous processing circuit 100. For each processing circuit 100, the number of zeros in its output data is less than the number of zeros in its input data. In other words, the multiple processing circuits 100 can perform multi-stage processing on the initial input data to continuously reduce the number of zeros in the initial input data. In addition, each processing circuit 100 can obtain a first indicator Check based on the input data of the processing circuit 100. The first indicators Check obtained by the multiple processing circuits 100 can all be output to the detection circuit 200. The detection circuit 200 can obtain a detection result of the initial input data based on the first indicators Check obtained by the multiple processing circuits 100 and the output data of the last processing circuit 100.

[0065] In some embodiments, the initial input data includes N bits, where N is an integer greater than 1. The number of bits in the input data of each processing circuit is an even number, and every two adjacent bits in the input data form a bit group. If N is an odd number, the input data of the first processing circuit includes the initial input data and a bit that is 0. If N is an even number, the input data of the first processing circuit includes only the initial input data. Furthermore, for processing circuits other than the first processing circuit, if the number of bits in the output data of the previous processing circuit is an odd number, the input data of the processing circuits other than the first processing circuit includes the output data of the previous processing circuit and a bit that is 0, so that the number of bits in the input data of each processing circuit is an even number.

[0066] Figure 2This is a schematic diagram of a processing circuit provided by an embodiment of the present disclosure. Each processing circuit 100 includes a compression circuit 101 configured to perform a first logical operation on two bits in each bit group of input data to obtain one bit in output data.

[0067] In some specific examples, the first logical operation is an OR operation. When both bits in a bit group are 0, one bit in the obtained output data is 0. When one bit in a bit group is 0 and the other bit is 1, or both bits are 1, one bit in the obtained output data is 1. It is understandable that the initial input data may be data output by a one-hot code generation circuit. Even in an invalid state, the number of 0s included in the data is much greater than the number of 1s. The compression circuit 101 in the processing circuit 100 processes each bit group of the input data of the processing circuit 100 using an OR operation, which not only reduces the number of bits of the input data by half, but also compresses the number of 0s in the input data. Therefore, using the compression circuits 101 in multiple processing circuits 100 can achieve rapid compression of the number of 0s in the initial input data and bring the 1s in the initial input data closer together.

[0068] In some embodiments, reference Figure 2 Each processing circuit 100 further includes: a first sub-processing circuit 102, configured to: perform a second logical operation on two bits in each bit group of the input data to obtain a bit in the intermediate data; if the input data includes a bit group in which both bits are 1, the intermediate data includes a bit that is 0; otherwise, all bits of the intermediate data are 1.

[0069] In some specific examples, the first logical operation is a NAND operation. The first sub-processing circuit 102 in the processing circuit 100 may halve the number of bits of the input data of the processing circuit 100 to obtain intermediate data, and the value of the bit in the intermediate data may indicate whether there are two adjacent bits in the input data that are both 1. If the intermediate data includes a bit that is 0, the input data includes two adjacent bits that are both 1.

[0070] In some embodiments, the first indicator obtained by the last processing circuit 100 is equal to the intermediate data obtained by the last processing circuit 100 .

[0071] In some embodiments, reference Figure 2The processing circuits other than the last processing circuit in the plurality of processing circuits further include: a second sub-processing circuit 103, where an input terminal of the second sub-processing circuit 103 is coupled to an output terminal of the first sub-processing circuit 102 and is configured to: perform a third logical operation on all bits in the intermediate data to obtain a first indicator; if the intermediate data includes a bit that is 0, obtain a first indicator in a first state; otherwise, obtain a first indicator in a second state.

[0072] In an embodiment of the present disclosure, the first indicator obtained by each processing circuit can be used to indicate whether there are two adjacent bits that are both 1 in the input data of the processing circuit. Each processing circuit can then compress the input data using an OR operation to quickly compress the number of 0s in the input data and make the 1s in the input data close to each other, while also detecting whether there are two adjacent bits that are both 1 in the input data and obtaining a first indicator indicating the detection result.

[0073] Figure 3 This is a schematic diagram of the detection circuit provided in the embodiment of the present disclosure, with reference to Figure 1 and Figure 3 The detection circuit 200 includes: a first sub-detection circuit 201, configured to: perform a fourth logical operation on multiple first indicators obtained by multiple processing circuits 100 to obtain a second indicator; a second sub-detection circuit 202, configured to: perform a fifth logical operation on the second indicator and the output data of the last processing circuit 100 to obtain a third indicator; the second indicator and the third indicator are configured to indicate the detection result of the initial input data.

[0074] In some specific examples, the third logical operation and the fourth logical operation are both AND operations, and the fifth logical operation is a NAND operation; the first indicator in the first state is 0, and the first indicator in the second state is 1.

[0075] In some specific examples, if the initial input data is a one-hot code, the initial input data only includes one bit that is 1, and the remaining bits are all 0, then the first indicators obtained by multiple processing circuits 100 are all 1, the output data of the last processing circuit 100 is 1, the second indicator obtained by the first sub-detection circuit 201 is 1, and the third indicator obtained by the second sub-detection circuit 202 is 0.

[0076] In some specific examples, if all bits of the initial input data are 0, the first indicators obtained by multiple processing circuits 100 are all 1, the output data of the last processing circuit 100 is 0, the second indicator obtained by the first sub-detection circuit 201 is 1, and the third indicator obtained by the second sub-detection circuit 202 is 1.

[0077] In some specific examples, if the initial input data includes at least two bits that are 1, the first indicator obtained by at least one processing circuit 100 among the multiple processing circuits 100 is 0, the data output by the last processing circuit 100 is 0, the second indicator obtained by the first sub-detection circuit 201 is 0, and the third indicator obtained by the second sub-detection circuit 202 is 1.

[0078] In the embodiment of the present disclosure, multiple processing circuits are used to quickly compress the number of 0s in the initial input data and make the 1s (if any) in the initial input data close to each other, so that the 1s in the initial input data can be detected more quickly. In addition, in addition to determining whether the initial input data is a one-hot code, the first indicator obtained by multiple processing circuits and the output data of the last processing circuit can also be used to determine the specific type of the initial input data. That is, the data detection circuit provided by the embodiment of the present disclosure can achieve relatively rich detection functions within a limited circuit area. Below, the specific circuit structure of the data detection circuit provided by the embodiment of the present disclosure will be introduced in conjunction with a specific example.

[0079] In the specific example provided in the present disclosure, taking the initial input data including 33 bits as an example, Figures 4 to 9 The following are circuit diagrams of 6 processing circuits, among which: Figure 4 The processing circuit 100A shown is a first processing circuit. Figure 9 The processing circuit 100F shown is the last processing circuit. Figure 10 is a circuit diagram of the detection circuit 200 .

[0080] Reference Figure 4 The processing circuit 100A may include a compression circuit 101A, a first sub-processing circuit 102A and a second sub-processing circuit 103A. The initial input data includes A <0> To A <32> The total number of bits is 32. The input data of the processing circuit 100A includes the initial input data and a bit A which is 0. <33> , A <33> The bit is used for bit filling, and its input terminal is coupled to the ground voltage Vss. Every two adjacent bits in the input data form a bit group, and the input data includes 17 bit groups in total.

[0081] The compression circuit 101A in the processing circuit 100A may include 17 sub-compression circuits consisting of one NOR gate and one NOT gate, wherein the two input ends of the NOR gate receive two bits in a bit group respectively, the output end of the NOR gate is connected to the input end of the NOT gate, and the output end of the NOT gate outputs one bit of the output data. The output data includes B <0> To B <16> There are 17 bits in total. Here, each sub-compression circuit can be configured to perform an OR operation on two bits in a bit group to obtain one bit in the output data.

[0082] The first sub-processing circuit 102A in the processing circuit 100A may include 17 NAND gates, with each NAND gate receiving two bits from a bit group at its two inputs, and outputting one bit of the intermediate data at its output. The intermediate data comprises 17 bits. The second sub-processing circuit 103A in the processing circuit 100A may include 6 NAND gates, 2 NOR gates, and 1 NOT gate. Five NAND gates constitute a first-stage circuit and can be configured to perform a NAND operation on all bits of the intermediate data. Two NOR gates constitute a second-stage circuit and can be configured to perform a NOR operation on all bits obtained by the first-stage circuit. One NAND gate and one NOT gate constitute a third-stage circuit and can be configured to perform an AND operation on all bits obtained by the second-stage circuit. A first indicator, Check1, is output by the NOT gate. The second sub-processing circuit 103A is equivalently configured to perform an AND operation on all bits of the intermediate data to obtain a first indicator, Check1, comprising one bit. When the intermediate data includes 0, the first indicator Check1 is 0; otherwise, the first indicator Check1 is 1.

[0083] Reference Figure 5 The processing circuit 100B may include a compression circuit 101B, a first sub-processing circuit 102B and a second sub-processing circuit 103B. The input data includes B <0> To B <17> A total of 18 bits, of which B <0> To B <16> is the output data of the processing circuit 100A, B <17> The bits are used for padding. Every two adjacent bits in the input data form a bit group, and the input data includes 9 bit groups in total.

[0084] The compression circuit 101B in the processing circuit 100B may include 9 sub-compression circuits consisting of 1 NOR gate and 1 NOT gate, wherein the two input ends of the NOR gate receive two bits in a bit group respectively, the output end of the NOR gate is connected to the input end of the NOT gate, and the output end of the NOT gate outputs one bit of the output data. The output data includes C <0> to C <8> A total of 9 bits.

[0085] The first sub-processing circuit 102B in the processing circuit 100B may include nine NAND gates, each with two inputs receiving two bits from a bit group, and an output of the NAND gate outputting one bit of the intermediate data, where the intermediate data comprises nine bits. The second sub-processing circuit 103B in the processing circuit 100B may include three NAND gates and one NOR gate. The three NAND gates constitute a first-stage circuit and can be configured to perform a NAND operation on all bits of the intermediate data. The one NOR gate constitutes a second-stage circuit and can be configured to perform a NOR operation on all bits obtained by the first-stage circuit. A first indicator, Check2, is output by the NOR gate. The second sub-processing circuit 103B is equivalently configured to perform an AND operation on all bits of the intermediate data to obtain a first indicator, Check2, comprising one bit. When the intermediate data includes 0, the first indicator Check2 is 0; otherwise, the first indicator Check2 is 1.

[0086] Reference Figure 6 The processing circuit 100C may include a compression circuit 101C, a first sub-processing circuit 102C and a second sub-processing circuit 103C. The input data includes C <0> to C <9> There are 10 bits in total, of which C <0> to C <8> is the output data of the processing circuit 100B, C <9> The bits are used for padding. Every two adjacent bits in the input data form a bit group, so the input data includes 5 bit groups in total.

[0087] The compression circuit 101C in the processing circuit 100C may include five sub-compression circuits consisting of one NOR gate and one NOT gate, wherein the two input terminals of the NOR gate receive two bits in a bit group respectively, the output terminal of the NOR gate is connected to the input terminal of the NOT gate, and the output terminal of the NOT gate outputs one bit of the output data. The output data includes D <0> to D <4> A total of 5 bits.

[0088] The first sub-processing circuit 102C in the processing circuit 100C may include five NAND gates, with the two input terminals of each NAND gate receiving two bits from a bit group, and the output terminal of the NAND gate outputting one bit of the intermediate data, where the intermediate data comprises five bits. The second sub-processing circuit 103C in the processing circuit 100C may include two NAND gates and one NOR gate. The two NAND gates constitute a first-stage circuit and can be configured to perform a NAND operation on all bits of the intermediate data. The one NOR gate constitutes a second-stage circuit and can be configured to perform a NOR operation on all bits obtained by the first-stage circuit. The first indicator Check3 is output by the NOR gate. The second sub-processing circuit 103C is equivalently configured to perform an AND operation on all bits of the intermediate data to obtain a first indicator Check3 comprising one bit. When the intermediate data includes 0, the first indicator Check3 is 0; otherwise, the first indicator Check3 is 1.

[0089] Reference Figure 7 The processing circuit 100D may include a compression circuit 101D, a first sub-processing circuit 102D and a second sub-processing circuit 103D. The input data includes D <0> to D <5> A total of 6 bits, of which D <0> to D <4> is the output data of the processing circuit 100C, D <5> The bits are used for padding. Every two adjacent bits in the input data form a bit group, so the input data includes 3 bit groups in total.

[0090] The compression circuit 101D in the processing circuit 100D may include three sub-compression circuits consisting of one NOR gate and one NOT gate, wherein the two input ends of the NOR gate receive two bits in a bit group respectively, the output end of the NOR gate is connected to the input end of the NOT gate, and the output end of the NOT gate outputs one bit of the output data. The output data includes E <0> to E <2> A total of 3 bits.

[0091] The first sub-processing circuit 102D in the processing circuit 100D may include three NAND gates, each with two inputs receiving two bits from a bit group, and an output of the NAND gate outputting one bit of the intermediate data, where the intermediate data includes three bits. The second sub-processing circuit 103D in the processing circuit 100D includes one NAND gate and one NOT gate, and may be configured to perform an AND operation on all bits of the intermediate data. The first indicator Check4 is output by the NOT gate. When the intermediate data includes 0, the first indicator Check4 is 0; otherwise, the first indicator Check4 is 1.

[0092] Reference Figure 8The processing circuit 100E may include a compression circuit 101E, a first sub-processing circuit 102E and a second sub-processing circuit 103E. The input data includes E <0> to E <3> A total of 4 bits, of which E <0> to E <2> is the output data of the processing circuit 100D, E <3> The bits are used for padding. Every two adjacent bits in the input data form a bit group, so the input data includes 2 bit groups in total.

[0093] The compression circuit 101E in the processing circuit 100E may include two sub-compression circuits consisting of a NOR gate and a NOT gate, wherein the two input terminals of the NOR gate receive two bits in a bit group respectively, the output terminal of the NOR gate is connected to the input terminal of the NOT gate, and the output terminal of the NOT gate outputs one bit of the output data. The output data includes F <0> and F <1> A total of 2 bits.

[0094] The first sub-processing circuit 102E in the processing circuit 100E may include two NAND gates, each of which receives two bits from a bit group at its two input terminals, and outputs one bit of the intermediate data at its output terminal, where the intermediate data includes two bits. The second sub-processing circuit 103E in the processing circuit 100E may include one NAND gate and one NOT gate, and may be configured to perform an AND operation on all bits of the intermediate data. The first indicator Check5 is output by the NOT gate. When the intermediate data includes 0, the first indicator Check5 is 0; otherwise, the first indicator Check5 is 1.

[0095] Reference Figure 9 The processing circuit 100F may include a compression circuit 101F and a first sub-processing circuit 102F, and the input data includes F <0> and F <1> A total of 2 bits, and F <0> and F <1> The processing circuit 100E outputs data, and the input data includes 1 bit group.

[0096] The compression circuit 101F in the processing circuit 100F may include a NOR gate and a NOT gate, wherein the two input ends of the NOR gate receive two bits respectively, the output end of the NOR gate is connected to the input end of the NOT gate, and the output data G <0> Output from the output terminal of the NOT gate.

[0097] The first sub-processing circuit 102F in the processing circuit 100F may include a NAND gate, wherein the two input terminals of the NAND gate respectively receive two bits of input data, and the output terminal of the NAND gate outputs intermediate data, wherein the intermediate data includes one bit. Here, the processing circuit 100F is the last processing circuit among the multiple processing circuits. The intermediate data obtained by the first sub-processing circuit 102F is equal to the first indicator Check6 obtained by the processing circuit 100F. When both bits of the input data of the processing circuit 100F are 1, the first indicator Check6 is 0; otherwise, the first indicator Check6 is 1.

[0098] Based on the above example, for processing circuits other than the last processing circuit, the second sub-processing circuit in the processing circuit includes: multiple NAND gates and at least one NOR gate; intermediate data is input by the input terminal of the NAND gate, the input terminal of the NOR gate is coupled to the output terminals of at least two NAND gates, and the first indicator is output by a NOR gate; or, the second sub-processing circuit includes: a NAND gate and a NOT gate; intermediate data is input by the input terminal of the NAND gate, the input terminal of the NOT gate is coupled to the output terminal of the NAND gate, and the first indicator is output by the NOT gate; or, the second sub-processing circuit includes: multiple NAND gates, multiple NOR gates and a NOT gate; intermediate data is input by the input terminal of the NAND gate, the input terminal of the NOR gate is coupled to the output terminals of at least two NAND gates, the output terminal of the NOR gate is coupled to the input terminal of at least one NAND gate, the input terminal of the NOT gate is coupled to the output terminal of one NAND gate, and the first indicator is output by the NOT gate.

[0099] In an embodiment of the present disclosure, the second sub-processing circuit can perform an AND operation on all bits of the intermediate data obtained by the first sub-processing circuit based on the input data. Compared to a circuit that implements the AND operation only through an AND gate, implementing the AND operation through a NAND gate, a NOR gate, and a NOT gate can achieve rapid compression of the number of bits and reduce the number of required logic gates, thereby reducing the circuit area and increasing the speed of the operation, which is beneficial for reducing the area of ​​the data detection circuit and improving the efficiency of data detection. In addition, in the second sub-processing circuit, the number of input terminals of the NOR gate and the number of input terminals of the NAND gate can both be greater than or equal to 2 and less than or equal to 4, thereby further reducing the number of required logic gates, thereby further reducing the area of ​​the data detection circuit.

[0100] It should be noted that Figures 4 to 9 The circuit composition of the processing circuit shown is only an example, and the number of logic gates in each processing circuit can be adaptively adjusted based on the number of bits in the input data to achieve detection of initial input data including different numbers of bits.

[0101] In some specific examples, refer to Figure 10The first sub-detection circuit 201 in the detection circuit 200 may include two NAND gates and one NOR gate. The six first indicators obtained by the above-mentioned six processing circuits can be input by the NAND gates, and the output end of the NAND gate is connected to the input end of the NOR gate. The NOR gate can output the second indicator Check0. Then, the first sub-detection circuit 201 is equivalent to being configured to perform an AND operation on the six first indicators to obtain the second indicator Check0. Compared with a circuit that only uses an AND gate to implement an AND operation, using a NAND gate and a NOR gate to implement an AND operation can reduce the number of required logic gates, thereby reducing the circuit area and improving the operation speed.

[0102] In some specific examples, the second sub-detection circuit 202 in the detection circuit 200 may include a NAND gate, a second indicator Check0 and an output data G of the processing circuit 100F. <0> The NAND gate can output a third indicator OneHotFlag when at least one of the six first indicators is 0 and the output data G of the processing circuit 100F is input by the two input terminals of the NAND gate. <0> When the first indicator is 1, the second indicator Check0 is 0, and the third indicator OneHotFlag is 1, indicating that the initial input data includes at least 2 bits that are 1; when the six first indicators are all 1, and the output data G of the processing circuit 100F is <0> When the first indicator is 0, the second indicator Check0 is 1, and the third indicator OneHotFlag is 1, indicating that all bits of the initial input data are 0; when the six first indicators are all 1, and the output data G of the processing circuit 100F is <0> When the value of the third indicator OneHotFlag indicates that the initial input data is not a one-hot code, combined with the value of the second indicator Check0, it can be determined that all bits of the initial input data are 0 or the initial input data includes at least two bits that are 1.

[0103] It should be noted that Figure 10The circuit composition of the detection circuit 200 shown is only an example. In other specific examples, the detection circuit 200 may have other circuit compositions. For example, the NOR gate in the first sub-detection circuit 201 may be replaced by an OR gate, and the NAND gate in the second sub-detection circuit 202 may be replaced by an XOR gate. Then, when at least one of the multiple first indicators is 0 and the output data of the last processing circuit is 1, the second indicator is 1 and the third indicator is 0, indicating that the initial input data includes at least 2 bits that are 1; when the multiple first indicators are all 1 and the output data of the last processing circuit is 0, the second indicator is 0 and the third indicator is 0, indicating that all bits of the initial input data are 0; when the multiple first indicators are all 1 and the output data of the last processing circuit is 1, the second indicator is 0 and the third indicator is 1, indicating that the initial input data is a one-hot code.

[0104] In some embodiments, the initial input data includes N bits, and the data detection circuit includes M processing circuits, where M is an integer; M is greater than or equal to the logarithm of N with base 2, and M is less than the logarithm of N with base 2 plus 1. For example, in the above specific example, the initial input data includes 33 bits, and the data detection circuit includes 6 processing circuits.

[0105] In the embodiment of the present disclosure, the number of processing circuits is a logarithmic number of the number of bits of the initial input data. As the number of bits of the initial input data increases, the growth rate of the number of processing circuits is much smaller than the growth rate of the number of bits of the initial input data. Thus, the area of ​​the data detection circuit can be effectively controlled.

[0106] In an embodiment of the present disclosure, the data detection circuit may include multiple processing circuits and a detection circuit. The multiple processing circuits can quickly compress the number of 0s in the initial input data, so that the 1s (if any) in the initial input data are close to each other. At the same time, a first indicator indicating whether there are two adjacent bits that are both 1 in the input data of each processing circuit can be obtained. The detection circuit can obtain the detection result of the initial input data based on the multiple first indicators obtained by the multiple processing circuits and the output data of the last processing circuit. Therefore, the data detection circuit can have a smaller circuit area and a faster detection speed, which is conducive to expanding the application scenarios of the data detection circuit.

[0107] Based on a concept similar to the above-mentioned data detection circuit, the present disclosure also provides a data detection method. Figure 11 The following is a flow chart of a data detection method provided in an embodiment of the present disclosure. The data detection method includes the following steps:

[0108] Step S10: performing a plurality of processing operations, each of the plurality of processing operations comprising: obtaining a first indicator based on input data, and obtaining output data based on the input data; the number of zeros in the output data is less than the number of zeros in the input data; the input data of a first processing operation of the plurality of processing operations comprises initial input data; the input data of an Xth processing operation of the plurality of processing operations comprises output data of an X-1th processing operation; and X is an integer greater than 1;

[0109] Step S20: Obtaining a detection result of the initial input data based on the first indicator obtained through the multiple processing operations and the output data obtained through the last processing operation among the multiple processing operations.

[0110] In some embodiments, the number of bits of the input data for each processing operation is an even number, and every two adjacent bits in the input data form a bit group; obtaining output data based on the input data includes: performing a first logical operation on two bits in each bit group of the input data to obtain a bit in the output data.

[0111] In some embodiments, each processing operation specifically includes: performing a second logical operation on two bits in each bit group of the input data to obtain a bit in the intermediate data; if the input data includes a bit group in which both bits are 1, the intermediate data includes a bit that is 0, otherwise, all bits of the intermediate data are 1.

[0112] In some embodiments, the first indicator obtained by the last processing operation is equal to the intermediate data obtained by the last processing operation; the processing operations other than the last processing operation in the multiple processing operations also include: performing a third logical operation on all bits in the intermediate data to obtain the first indicator; if the intermediate data includes a bit that is 0, a first indicator of the first state is obtained, otherwise, a first indicator of the second state is obtained.

[0113] In some embodiments, obtaining a detection result of the initial input data based on a first indicator obtained through multiple processing operations and output data obtained through a last processing operation among the multiple processing operations includes: performing a fourth logical operation on the first indicator obtained through the multiple processing operations to obtain a second indicator; performing a fifth logical operation on the second indicator and the output data obtained through the last processing operation to obtain a third indicator; the second indicator and the third indicator are configured to indicate the detection result of the initial input data.

[0114] In some embodiments, the first logical operation is an OR operation, the second logical operation and the fifth logical operation are both NAND operations, and the third logical operation and the fourth logical operation are both AND operations; the first indicator in the first state is 0, and the first indicator in the second state is 1; if the initial input data is a one-hot code, the second indicator is 1 and the third indicator is 0; if all bits of the initial input data are 0, the second indicator is 1 and the third indicator is 1; if the initial input data includes at least two bits that are 1, the second indicator is 0 and the third indicator is 1.

[0115] In some embodiments, the initial input data includes N bits, where N is an integer greater than 1; if N is an odd number, the input data of the first processing operation includes the initial input data and a bit that is 0.

[0116] In some embodiments, the data detection method includes M processing operations, where M is an integer; M is greater than or equal to the logarithm of N with base 2, and M is less than the logarithm of N with base 2 plus 1.

[0117] It should be noted that the data detection method provided in the present disclosure can be executed by the data detection circuit in any of the above-mentioned embodiments. Specifically, step S10 in the data detection method can be executed by multiple processing circuits in any of the above-mentioned embodiments, and one processing circuit can perform one processing operation. Step S20 can be executed by the detection circuit in any of the above-mentioned embodiments. Then, the effects that can be achieved by the data detection circuit in the above-mentioned embodiments can also be achieved by the data detection method, and they will not be repeated here.

[0118] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0119] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0120] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and they should all be covered by the protection scope of the present disclosure.

Claims

1. A data detection circuit, characterized in that: include: a plurality of processing circuits, each processing circuit of the plurality of processing circuits being configured to: derive a first indicator based on input data, and derive output data based on the input data; The number of zeros in the output data is less than the number of zeros in the input data; the plurality of processing circuits are coupled sequentially, and the input data of a first processing circuit among the plurality of processing circuits includes initial input data, and the input data of an Xth processing circuit among the plurality of processing circuits includes output data of an X-1th processing circuit; where X is an integer greater than 1; The detection circuit is configured to obtain a detection result of the initial input data based on the first indicators obtained by the multiple processing circuits and output data of a last processing circuit among the multiple processing circuits.

2. The data detection circuit according to claim 1, wherein: The number of bits of the input data of each processing circuit is an even number, and every two adjacent bits in the input data form a bit group; Each of the processing circuits comprises: The compression circuit is configured to perform a first logic operation on two bits in each bit group of the input data to obtain one bit in the output data.

3. The data detection circuit according to claim 2, wherein: Each of the processing circuits further comprises: The first sub-processing circuit is configured to: perform a second logical operation on two bits in each bit group of the input data to obtain a bit in the intermediate data; if the input data includes a bit group in which both bits are 1, the intermediate data includes a bit that is 0; otherwise, all bits of the intermediate data are 1.

4. The data detection circuit according to claim 3, wherein: The first indicator obtained by the last processing circuit is equal to the intermediate data obtained by the last processing circuit; The processing circuits other than the last processing circuit in the plurality of processing circuits further include: a second sub-processing circuit, wherein an input terminal of the second sub-processing circuit is coupled to an output terminal of the first sub-processing circuit and is configured to: perform a third logical operation on all bits in the intermediate data to obtain the first indicator; if the intermediate data includes a bit that is 0, obtain the first indicator in a first state; otherwise, obtain the first indicator in a second state.

5. The data detection circuit according to claim 4, characterized in that: The detection circuit comprises: a first sub-detection circuit, configured to: perform a fourth logical operation on the first indicators obtained by the plurality of processing circuits to obtain a second indicator; The second sub-detection circuit is configured to: perform a fifth logic operation on the second indicator and the output data of the last processing circuit to obtain a third indicator; the second indicator and the third indicator are configured to indicate the detection result of the initial input data.

6. The data detection circuit according to claim 5, characterized in that: The first logical operation is an OR operation, the second logical operation and the fifth logical operation are both NAND operations, and the third logical operation and the fourth logical operation are both AND operations; the first indicator in the first state is 0, and the first indicator in the second state is 1; If the initial input data is a one-hot code, the second indicator is 1 and the third indicator is 0; If all bits of the initial input data are 0, the second indicator is 1, and the third indicator is 1; If the initial input data includes at least two bits that are 1, the second indicator is 0 and the third indicator is 1.

7. The data detection circuit according to claim 4, characterized in that: The second sub-processing circuit includes: a plurality of NAND gates and at least one NOR gate; the intermediate data is inputted by the input terminals of the NAND gates, the input terminals of the NOR gates are coupled to the output terminals of at least two of the NAND gates, and the first indicator is outputted by one of the NOR gates; or, The second sub-processing circuit includes: a NAND gate and a NOT gate; the intermediate data is inputted through the input terminal of the NAND gate, the input terminal of the NOT gate is coupled to the output terminal of the NAND gate, and the first indicator is outputted by the NOT gate; or, The second sub-processing circuit includes: multiple NAND gates, multiple NOR gates and a NOT gate; the intermediate data is input by the input end of the NAND gate, the input end of the NOR gate is coupled to the output end of at least two of the NAND gates, the output end of the NOR gate is coupled to the input end of at least one of the NAND gates, the input end of the NOT gate is coupled to the output end of one of the NAND gates, and the first indicator is output by the NOT gate.

8. The data detection circuit according to claim 1, wherein: The initial input data includes N bits, where N is an integer greater than 1; if N is an odd number, the input data of the first processing circuit includes the initial input data and a bit that is 0.

9. The data detection circuit according to claim 8, characterized in that: The data detection circuit includes M processing circuits, where M is an integer; M is greater than or equal to the logarithm of N with base 2, and M is less than the logarithm of N with base 2 plus 1.

10. A data detection method, characterized in that: include: performing a plurality of processing operations, each of the plurality of processing operations comprising: obtaining a first indicator based on input data, and obtaining output data based on the input data; the number of zeros in the output data is less than the number of zeros in the input data; the input data of a first processing operation of the plurality of processing operations comprises the initial input data; the input data of an Xth processing operation of the plurality of processing operations comprises the output data of an X-1th processing operation; and X is an integer greater than 1; A detection result of the initial input data is obtained based on the first indicator obtained through the multiple processing operations and the output data obtained through the last processing operation among the multiple processing operations.

11. The data detection method according to claim 10, characterized in that: The number of bits of the input data of each processing operation is an even number, and every two adjacent bits in the input data form a bit group; and obtaining output data based on the input data includes: A first logical operation is performed on two bits in each bit group of the input data to obtain one bit in the output data.

12. The data detection method according to claim 11, characterized in that: Each processing operation specifically includes: A second logical operation is performed on the two bits in each bit group of the input data to obtain a bit in the intermediate data; if the input data includes a bit group in which both bits are 1, the intermediate data includes a bit that is 0; otherwise, all bits of the intermediate data are 1.

13. The data detection method according to claim 12, characterized in that: The first indicator obtained by the last processing operation is equal to the intermediate data obtained by the last processing operation; The multiple processing operations, except for the last processing operation, further include: performing a third logical operation on all bits in the intermediate data to obtain the first indicator; If the intermediate data includes a bit that is 0, the first indicator is obtained in a first state; otherwise, the first indicator is obtained in a second state.

14. The data detection method according to claim 13, characterized in that: The obtaining of the detection result of the initial input data based on the first indicator obtained through the multiple processing operations and the output data obtained through the last processing operation among the multiple processing operations comprises: performing a fourth logical operation on the first indicator obtained through the multiple processing operations to obtain a second indicator; A fifth logical operation is performed on the second indicator and the output data obtained through the last processing operation to obtain a third indicator; the second indicator and the third indicator are configured to indicate a detection result of the initial input data.

15. The data detection method according to claim 14, characterized in that: The first logical operation is an OR operation, the second logical operation and the fifth logical operation are both NAND operations, and the third logical operation and the fourth logical operation are both AND operations; the first indicator in the first state is 0, and the first indicator in the second state is 1; If the initial input data is a one-hot code, the second indicator is 1 and the third indicator is 0; If all bits of the initial input data are 0, the second indicator is 1, and the third indicator is 1; If the initial input data includes at least two bits that are 1, the second indicator is 0 and the third indicator is 1.

16. The data detection method according to claim 10, characterized in that: The initial input data includes N bits, where N is an integer greater than 1; if N is an odd number, the input data of the first processing operation includes the initial input data and a bit that is 0.

17. The data detection method according to claim 16, characterized in that: The data detection method includes M processing operations, where M is an integer; M is greater than or equal to the logarithm of N with base 2, and M is less than the logarithm of N with base 2 plus 1.

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