A method for simulating a power line carrier communication protocol data link layer

Abstract

This invention discloses a simulation method for the data link layer of a power line carrier communication protocol, comprising: constructing a physical layer interface simulation module to simulate power line carrier or wireless air interface transmission through TCP socket communication, and creating a high-priority task process to handle time slot-level timing synchronization for triggering physical layer transmit and receive actions in a specified time slot; configuring a timing synchronization control mechanism to obtain the timestamp carried by the beacon frame sent by the concentrator, calling a clock synchronization function to align the site's local clock with the timestamp when receiving the beacon frame header, adding delay compensation before sending data, and delaying the start of the physical layer receive action when receiving data to offset the IP network transmission delay; implementing a data frame processing flow, responding to physical layer state changes by registering a frame control header callback function, using a circular queue to buffer TCP packet data, and having the physical layer interface simulation module parse packets, allocate memory, and process payloads in a specified time slot after timing synchronization.

Description

Technical Field

[0001] This invention relates to the field of power line carrier technology, and in particular to a simulation method for the data link layer of a power line carrier communication protocol. Background Technology

[0002] With the rapid development of smart grids, the Internet of Things (IoT), and industrial automation technologies, power line carrier communication (PLC), as a key technology for data transmission using existing power line infrastructure, has demonstrated significant advantages in areas such as remote meter reading, distribution network automation, and smart home networks. However, the power line channel environment is complex and variable, suffering from signal attenuation, noise interference, and multipath effects, which places extremely high demands on the reliability and real-time performance of communication protocols. The data link layer, as a core component of the power line carrier communication protocol stack, is responsible for key functions such as media access control, frame transmission management, and timing synchronization; its performance directly affects the stability and efficiency of the entire communication system.

[0003] Existing power line carrier communication simulation methods mostly focus on physical layer or application layer modeling, lacking refined simulation of timing synchronization and dynamic compensation mechanisms at the data link layer. Traditional simulation platforms often employ static timing configurations or simple delay simulations, which fail to accurately reflect the dynamic changes in IP network transmission delays, leading to discrepancies between simulation results and real-world scenarios. For example, in a TCP / IP-based simulation environment, the randomness of network transmission delays can cause misalignment in data frame transmission and reception timing. Without precise compensation for sending / receiving actions, the effectiveness of media access mechanisms such as CSMA / CA (Carrier Sense Multiple Access / Collision Avoidance) will be affected, thereby reducing network throughput and transmission reliability. Furthermore, traditional methods often employ fixed buffer structures or low-priority task scheduling when processing data frames, which struggles to meet the demands of rapid parsing and response to large numbers of data packets in high real-time scenarios, easily leading to buffer overflows or processing delays.

[0004] To address these challenges, some recent studies have attempted to introduce clock synchronization mechanisms (such as IEEE 1588v2) or software-defined radio (SDR) platforms to optimize simulation performance. However, these solutions often rely on high-precision hardware support or require complex configurations, making them difficult to deploy at low cost in general simulation environments. Furthermore, existing methods still suffer from low frame processing efficiency and accumulated synchronization errors when dealing with scenarios unique to power line carrier communication, such as multi-node coordination and burst data transmission, thus hindering the accurate evaluation and optimization of protocol performance.

[0005] Furthermore, according to the latest specifications from the State Grid Corporation of China, power communication terminals must simultaneously support dual-mode communication via RF wireless and PLC power line carrier. Existing simulation methods do not cover independent timing control and differentiated parameter configuration in dual-mode collaborative scenarios, making it difficult to meet the State Grid's verification requirements for the dual-mode compatibility of terminal equipment. Summary of the Invention

[0006] The purpose of this invention is to provide a simulation method for the data link layer of a power line carrier communication protocol. By constructing a high-priority task process to achieve time slot-level timing synchronization, and combining dynamic delay compensation and a ring queue buffering mechanism, it effectively solves the problems of timing misalignment, processing delay, and buffer overflow in traditional power line carrier communication simulation.

[0007] To address the aforementioned technical problems, a first aspect of this invention provides a power line carrier communication protocol data link layer simulation method, comprising the following steps:

[0008] A physical layer interface simulation module is constructed to simulate power line carrier or wireless air interface transmission through TCP socket communication, and a high-priority task process is created to handle time slot-level timing synchronization, which is used to trigger physical layer transmit and receive actions in a specified time slot.

[0009] Configure a timing synchronization control mechanism to obtain the timestamp carried by the beacon frame sent by the concentrator. When the beacon frame header is received, call the clock synchronization function to align the local clock of the site with the timestamp. Add delay compensation before sending data and delay the start of physical layer receiving action when receiving data to offset IP network transmission delay.

[0010] The data frame processing flow is implemented by registering a frame control header callback function to respond to physical layer state changes, using a circular queue to buffer TCP packet data, and having the physical layer interface simulation module parse packets, allocate memory, and process payloads in a specified time slot after timing synchronization, thus completing the closed-loop operation of the data link layer simulation.

[0011] Furthermore, the step of calling the clock synchronization function to align the station's local clock with the timestamp when the beacon frame header is received includes:

[0012] Define the beacon frame header parsing conditions. The beacon frame header is defined as the frame control header part of the Media Access Control Protocol data unit. When the physical layer interface simulation module demodulates the frame control header, it triggers the call of the clock synchronization function.

[0013] Perform a clock synchronization operation by calling the clock synchronization function to set the tick time of the site's local clock to the timestamp value carried in the beacon frame. The timestamp value is derived from the local clock sampling value when the concentrator sends the beacon frame.

[0014] To control the clock synchronization accuracy, the clock deviation is calibrated by a microsecond-level time function of the operating system, and the clock error between the site and the concentrator is controlled within a preset clock error threshold. The preset clock error threshold is associated with the time slot-level timing tolerance defined by the power line carrier communication protocol.

[0015] Furthermore, the step of calibrating the clock deviation through a microsecond-level time function of the operating system to control the clock error between the site and the concentrator within a preset clock error threshold includes:

[0016] The physical layer clock reference of the power line carrier communication protocol is set to a 25MHz crystal oscillator frequency, where one tick time unit is defined as 1 / 25 microsecond. The current time obtained by the microsecond-level time function of the operating system is multiplied by the conversion coefficient PHY_TICKS_PER_US to obtain the tick time value of the simulation system. The conversion coefficient PHY_TICKS_PER_US is fixed at 25.

[0017] When the clock synchronization function is called, the second-level count and microsecond-level count of the beacon frame timestamp are extracted. The second-level count is multiplied by 1,000,000 and then added to the microsecond-level count to obtain the total microsecond value. This value is then multiplied by a conversion factor to convert it to the target tick time and overwritten into the station's local clock.

[0018] The preset threshold for clock error is set to 1 microsecond, which is the smallest precision unit of the operating system's time function. Through microsecond-level time sampling and integer operations of tick time conversion, it is ensured that the absolute time deviation between the station and the concentrator does not exceed this threshold.

[0019] Furthermore, the addition of delay compensation before sending data and the delay in initiating the physical layer receiving action when receiving data to offset IP network transmission delay includes:

[0020] Before the physical layer interface simulation module calls the socket send function, a fixed delay threshold is added to simulate the physical layer modulation delay. The fixed delay threshold is a preset value that is shorter than the actual physical layer modulation delay.

[0021] When receiving data, the physical layer receiving action is initiated within a preset time window before the timeout protection period of the receiving time slot.

[0022] Furthermore, the step of adding a fixed delay threshold to simulate physical layer modulation delay before the physical layer interface simulation module calls the socket send function includes:

[0023] The fixed delay threshold is associated with the time slot boundary constraint of the power line carrier communication protocol to ensure that the start time of the transmission window after the delay is increased does not exceed the start boundary of the current time slot. The fixed delay threshold is used to compensate for the timing deviation caused by the lack of physical layer modulation process in IP network transmission. The numerical range of the fixed delay threshold is smaller than the modulation delay measurement value of the real physical layer hardware platform.

[0024] In the high-priority task process, a delay operation is implemented through a microsecond-level timer in the operating system, so that the timing of the socket send function call is aligned with the time slot-level timing requirements of the physical layer simulation.

[0025] Furthermore, the step of initiating the physical layer reception action within a preset time window before the timeout protection period of the reception time slot when receiving data includes:

[0026] The timeout protection limit start boundary associated with the receiving time slot, wherein the timeout protection limit is the timeout threshold of the guardian timer started by the physical layer interface simulation module in the receiving time slot;

[0027] In the high-priority task process, the physical layer receive action function is called with a delay, so that the execution time of the action function is the start time of the timeout protection limit of the current receive time slot minus the preset time window duration;

[0028] By delaying the start time, TCP packet data is processed after arriving at the circular queue due to the delay in IP network transmission.

[0029] Furthermore, the step of responding to physical layer state changes through a registered frame control header callback function, using a circular queue to buffer TCP packet data, and having the physical layer interface simulation module parse packets, allocate memory, and process payloads in a specified time slot after timing synchronization includes:

[0030] Register a corresponding callback function according to the frame type of the Media Access Control Protocol (MAC) data unit. The frame control header callback function is a MAC processing function that responds to the physical layer state machine switching. The frame types include beacon frames, soft acknowledgment frames, and coordination frames.

[0031] TCP packets are received by an independent listening thread and stored in a circular queue. The fragmented TCP packets are spliced ​​together. The fragmented TCP packets are defined as data packets carrying a private header, which contains a 6-byte media access control address and a payload length identifier.

[0032] The high-priority task process extracts the complete MACPDU payload from the circular queue at a designated time slot after timing synchronization, allocates dynamic memory to store the payload data, and calls the frame control header callback function to process the data according to the physical layer state switch.

[0033] Furthermore, the step of retrieving the complete MAC PDU payload from the circular queue and allocating dynamic memory to store the payload data includes:

[0034] When the high-priority task process reaches the designated receiving time slot after timing synchronization, the TCP segment carrying the private message header is extracted from the head of the circular queue. The data integrity is verified according to the payload length identifier in the private message header. If there are fragmented messages, the memory reassembly operation is performed according to the preset splicing conditions.

[0035] When a complete MAC PDU payload is identified, the RTOS memory pool management interface is invoked to allocate a dynamic memory block. The size of the dynamic memory block is determined by the length of the MAC PDU payload, and the payload data cached in the circular queue is copied to the dynamic memory block.

[0036] The frame control header callback function is triggered by the physical layer state machine switching event, and the dynamic memory block pointer and associated time slot information are passed to the data link layer task process, whereby the data link layer performs protocol parsing and memory release operations.

[0037] Furthermore, the power line carrier communication protocol data link layer simulation method also includes a dynamic network routing control mechanism:

[0038] A proxy communication module is constructed, which establishes TCP connections with all network nodes. A routing table is pre-configured in the proxy communication module, which stores the logical connection relationships of the network nodes.

[0039] When the proxy communication module receives a TCP packet from the source node, it performs the following operations:

[0040] Parse the source medium access control address, destination medium access control address, and frame type carried in the TCP packet;

[0041] Query the routing table and determine the forwarding path corresponding to the target medium access control address based on the logical connection relationship;

[0042] If the target medium access control address is associated with a child node in a multi-layer relay topology, then direct communication across layers is prohibited, and the TCP packets are only forwarded to the next-hop node specified in the routing table.

[0043] Accordingly, a second aspect of the present invention provides a power device, comprising: at least one processor; and a memory connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to cause the at least one processor to perform the power line carrier communication protocol data link layer simulation method described above.

[0044] Accordingly, a third aspect of the present invention provides a computer-readable storage medium having computer instructions stored thereon, which, when executed by a processor, implement the power line carrier communication protocol data link layer simulation method described above.

[0045] The above-described technical solutions of the embodiments of the present invention have the following beneficial technical effects:

[0046] 1. By creating high-priority task processes, the triggering of physical layer transmission and reception actions is strictly bound to the time slot-level timing, solving the timing misalignment problem caused by task scheduling delay in traditional simulations; in the communication scenario between the concentrator and the site, high-priority tasks can force the physical layer actions to be triggered in a specified time slot, avoiding latency jitter caused by operating system task queue contention, thereby improving the simulation accuracy of the protocol stack for mechanisms such as CSMA / CA, and reducing frame conflicts or retransmissions caused by timing deviations;

[0047] 2. To address the inherent latency characteristics of TCP / IP network transmission, this paper effectively solves the impact of network latency on frame alignment in the simulation environment by real-time monitoring of the timestamp carried by the concentrator beacon frame and combining local clock synchronization with latency compensation at the sending / receiving end. When a site receives data, delaying the physical layer receiving action can offset the random latency of IP network transmission (such as router queue congestion or link congestion), ensuring that data frames are demodulated and parsed within the physical layer time slot. Adding dynamic latency compensation at the sending end can avoid frame transmission timeouts or buffer overflows at the receiving end caused by network latency, thereby improving the consistency between the data link layer simulation and the real scenario.

[0048] 3. A circular queue structure is used to cache TCP packet data. By reusing a fixed-size memory space, the efficiency and stability of data frame processing are significantly improved. Compared with the traditional linear buffer structure, the circular queue does not require frequent data movement or dynamic memory allocation, reducing the performance loss caused by memory fragmentation. In power line carrier communication, high-priority task processes need to process a large number of data packets quickly within a time slot. The first-in-first-out (FIFO) characteristic of the circular queue can realize efficient enqueue and dequeue operations. At the same time, the computational overhead caused by data movement is avoided through the head and tail pointer circular update mechanism.

[0049] 4. By configuring independent parameters and implementing a unified task scheduling mechanism for the dual-mode physical layer interface, the RF+PLC dual-mode collaborative scenario required by the State Grid is reproduced in a single simulation system. The dual-mode interface shares a circular queue and high-priority process resources to avoid redundant overhead; differentiated timing parameters (such as time slot width and modulation delay) ensure the consistency of simulation results with the behavior of the real dual-mode hardware platform, significantly improving the efficiency of protocol stack compatibility verification with the State Grid dual-mode specification. Attached Figure Description

[0050] Figure 1 This is a flowchart of the power line carrier communication protocol data link layer simulation method provided in the embodiments of the present invention. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments and the accompanying drawings. It should be understood that these descriptions are merely exemplary and not intended to limit the scope of the invention. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0052] Please refer to Figure 1 The first aspect of this invention provides a simulation method for the data link layer of a power line carrier communication protocol, comprising the following steps:

[0053] Step S100: Construct a dual-mode parallel simulation physical layer interface module that supports RF wireless communication and PLC power line carrier. Simulate power line carrier and wireless air interface transmission through two independent TCP socket communications respectively, and create a high-priority task process to handle the dual-mode independent time slot-level timing synchronization, which is used to trigger physical layer transmit and receive actions in a specified time slot.

[0054] The physical layer interface simulation module includes dual-mode support: independent physical layer interface instances are created for PLC power line carrier and RF wireless communication, with each instance associated with a dedicated TCP socket channel; the dual-mode interfaces share the same high-priority task process but maintain independent timing parameter sets (including time slot width, modulation delay threshold, and clock reference frequency) to ensure that the timing control of the two modes does not interfere with each other; the physical layer state machine switches the dual-mode configuration according to the channel identifier (PLC_CH / RF_CH) to achieve unified scheduling of heterogeneous channels by the protocol stack. Power line carrier (PLC_CH) and wireless air interface (RF_CH) transmissions are simulated through two independent TCP socket communications. Examples of differentiated dual-mode configurations are as follows: PLC mode: time slot width = 1ms, fixed delay threshold = 112.5μs, clock reference = 25MHz; RF mode: time slot width = 0.5ms, fixed delay threshold = 60μs, clock reference = 40MHz; the high-priority task process loads the corresponding parameter set according to the channel identifier (PLC_CH / RF_CH) and triggers physical layer transmit / receive actions in the specified time slot.

[0055] By simulating power line carrier and wireless air interface transmission through TCP socket communication, the signal transmission characteristics of the physical layer are abstracted into the interaction logic of the network protocol layer. Specifically, the reliable transmission characteristics of the TCP protocol are used to simulate the latency, packet loss, and noise interference of the power line channel. For example, by adjusting the socket sending window size or introducing a random packet loss mechanism, communication quality fluctuations caused by sudden load changes or device access in the power line can be simulated. Simultaneously, high-priority task processes are created to handle time slot-level timing synchronization. The core of this approach is to strictly bind the physical layer's transmit and receive actions to the simulation clock. For instance, in power line carrier communication, the communication between the concentrator and the station must follow time slot allocation rules. High-priority processes can force the operating system to prioritize physical layer transmit and receive tasks within a specified time slot, avoiding timing misalignments caused by other low-priority tasks preempting CPU resources.

[0056] Step S200: Configure the timing synchronization control mechanism, obtain the timestamp carried by the beacon frame sent by the concentrator, call the clock synchronization function when receiving the beacon frame header to align the site local clock with the timestamp, add delay compensation before sending data, and delay the start of physical layer receiving action when receiving data to offset IP network transmission delay.

[0057] Timing synchronization control is a crucial aspect of data link layer simulation, its core being the clock alignment of distributed nodes through beacon frames. When the concentrator sends a beacon frame, the timestamp it carries reflects the current global time reference of the network layer. After receiving the beacon frame header, each station must immediately call the clock synchronization function to align its local clock with the timestamp, and further optimize simulation accuracy through dynamic delay compensation. For example, adding delay compensation before sending data can offset the inherent latency of TCP network transmission (such as router queue processing time or jitter caused by link congestion); while delaying the start of physical layer reception when receiving data can balance the matching problem between IP network latency and physical layer time slots, avoiding data truncation or frame errors caused by the receiver starting prematurely. This bidirectional compensation mechanism effectively solves the contradiction between network latency and physical layer time slots in the simulation environment, providing a reliable foundation for the simulation of media access control protocols such as CSMA / CA.

[0058] Step S300 implements the data frame processing flow. By registering the frame control header callback function to respond to physical layer state changes, a circular queue is used to buffer TCP packet data. The physical layer interface simulation module parses the packets, allocates memory, and processes the payload in the specified time slot after timing synchronization, thus completing the closed-loop operation of the data link layer simulation.

[0059] The efficiency of the data frame processing flow directly affects the real-time performance of the simulation system. By registering frame control header callback functions, changes in the physical layer state (such as frame arrival or transmission completion) can trigger response actions in the data link layer. For example, when the physical layer receives a complete frame, the callback function triggers frame verification, address filtering, and payload parsing processes. The introduction of a circular queue optimizes the data caching mechanism. The circular queue avoids the fragmentation problem of dynamic memory allocation by cyclically utilizing fixed memory space, while supporting thread-safe access, making it suitable for data processing in high-concurrency scenarios. For example, in power line carrier communication, the concentrator needs to process uplink data from multiple stations simultaneously. The circular queue can cache TCP packets in FIFO order, and high-priority task processes can parse them in batches within time slots, significantly improving throughput. Furthermore, when the physical layer interface simulation module parses packets after time slot synchronization, it needs to dynamically allocate memory to store payload data. This process combines the segmented transmission and retransmission mechanisms commonly used in power line communication, ensuring that the simulation results are consistent with the behavior of the real protocol stack.

[0060] Furthermore, step S200, which involves calling a clock synchronization function to align the station's local clock with the timestamp upon receiving the beacon frame header, includes:

[0061] Step S211: Define the beacon frame header parsing conditions. The beacon frame header is defined as the frame control header part of the Media Access Control Protocol data unit. When the physical layer interface simulation module demodulates the frame control header, the clock synchronization function is triggered.

[0062] In power line carrier communication protocols, beacon frames, as the core control frames of the data link layer, must adhere to specific format specifications in their header structure. The conditions for triggering clock synchronization are defined by parsing the frame control header of the Media Access Control Protocol Data Unit (MAC PDU). During demodulation, the physical layer interface simulation module prioritizes identifying synchronization identifier fields (such as frame type, sequence number, or synchronization code) in the frame control header. Upon detecting the beacon frame header, it immediately triggers a clock synchronization function call, ensuring precise intervention at the boundary between the physical layer and the data link layer. For example, in the beacon frame header, the concentrator embeds a timestamp field as a global time reference, and the station can trigger subsequent synchronization processes by parsing this field, avoiding latency accumulation due to redundant parsing of frame payload data.

[0063] Step S212: Perform clock synchronization operation, call the clock synchronization function, and set the tick time of the local station clock to the timestamp value carried in the beacon frame. The timestamp value comes from the local clock sampling value when the concentrator sends the beacon frame.

[0064] The core of clock synchronization lies in aligning the site's local clock with the concentrator's timestamp. When a site receives the beacon frame header, it calls the clock synchronization function, directly setting the local clock's tick time (i.e., the clock counting unit) to the timestamp value carried in the beacon frame. This timestamp originates from the local clock sample taken when the concentrator sends the beacon frame, and its accuracy must match the time slot tolerance defined by the power line carrier protocol. For example, in the IEEE 1588v2 protocol, master and slave nodes achieve microsecond-level synchronization through timestamp exchange. Here, the concentrator acts as the master clock node. The site achieves rapid alignment by directly replacing its local clock value, completing initial synchronization with a single timestamp transmission. This avoids complex time difference calculations and is suitable for scenarios with high real-time requirements in power line communication.

[0065] Step S213: Control the clock synchronization accuracy by calibrating the clock deviation through the microsecond-level time function of the operating system, and control the clock error between the site and the concentrator within the preset clock error threshold. The preset clock error threshold is associated with the time slot-level timing tolerance defined by the power line carrier communication protocol.

[0066] To ensure synchronization accuracy meets protocol requirements, clock deviation is dynamically calibrated using microsecond-level time functions provided by the operating system (such as Linux's `gettimeofday` or `clock_gettime`). Specifically, after setting the local clock, the station continuously monitors the clock error with the concentrator. By comparing the difference between the operating system's actual time and the beacon frame timestamp, the frequency or phase of the local clock is adjusted. For example, if the error exceeds a preset threshold (e.g., 1 microsecond), a calibration algorithm is triggered, using a PLL (phase-locked loop) or software compensation mechanism to fine-tune the clock output. This threshold is related to the slot-level timing tolerance defined by the power line carrier protocol. For example, in HPLC, the slot width is typically on the order of milliseconds; therefore, the synchronization error must be controlled within 1% of the slot width to avoid frame misalignment. Furthermore, by incorporating a temperature compensation algorithm, clock drift caused by environmental changes can be further reduced, ensuring long-term synchronization stability.

[0067] Further, step S213, which involves calibrating the clock deviation using a microsecond-level time function of the operating system to control the clock error between the site and the concentrator within a preset clock error threshold, includes:

[0068] Step S213a: Set the physical layer clock reference of the power line carrier communication protocol to a preset crystal oscillator frequency, and multiply the current time obtained by the microsecond-level time function of the operating system by the conversion coefficient to obtain the tick time value of the simulation system.

[0069] For example, the physical layer clock reference of the power line carrier communication protocol can be set to a 25MHz crystal oscillator frequency, where one tick time unit is defined as 1 / 25 microsecond. The current time obtained by the microsecond-level time function of the operating system is multiplied by the conversion factor PHY_TICKS_PER_US to obtain the tick time value of the simulation system. The conversion factor PHY_TICKS_PER_US is fixed at 25.

[0070] The physical layer clock reference for the power line carrier communication protocol is set to a 25MHz crystal oscillator frequency. Its core lies in establishing a precise mapping between the physical unit of the hardware clock (such as the crystal oscillator period) and the abstract time unit (tick) of the simulation system. By obtaining the microsecond-level precision value of the current time through the operating system's microsecond-level time function (such as clock_gettime(CLOCK_MONOTONIC)), and then multiplying it by the conversion factor PHY_TICKS_PER_US = 25, the real time can be converted to the simulation system's tick time unit, with 1 microsecond corresponding to 25 ticks. In power line communication, a 25MHz crystal oscillator frequency can support finer-grained time slot division (such as 100μs per time slot corresponding to 2500 ticks), thus meeting the clock precision requirements of carrier modulation (such as OFDM subcarrier spacing). By binding the operating system time to the hardware clock reference, the simulation system can simulate the clock behavior of the real physical layer, ensuring the accuracy of the protocol stack for time-sensitive operations (such as symbol synchronization and frame alignment).

[0071] Step S213b: When the clock synchronization function is called, extract the second-level count and microsecond-level count of the beacon frame timestamp, multiply the second-level count by 1,000,000 and add it to the microsecond-level count to obtain the total microsecond value, then multiply it by the conversion factor to convert it to the target tick time and overwrite it into the station's local clock.

[0072] The timestamp carried by the beacon frame contains second-level and microsecond-level count fields, and its conversion process must strictly follow the clock representation specification of the power line carrier protocol. For example, if the beacon frame's timestamp is sec = 1690000000 and usec = 123456, then the total microsecond value is 1690000000 × 1,000,000 + 123,456 = 1,690,000,123,456 μs. Multiplying this by a conversion factor of 25 yields the target tick value of 42,250,003,086,400. This conversion operation is implemented through integer arithmetic to avoid floating-point errors and ensure the accuracy of overwriting the site's local clock. In the simulation, by converting the beacon frame's timestamp to a tick value, the site can directly synchronize to the concentrator's clock reference without the need for complex phase adjustment algorithms, significantly reducing computational complexity.

[0073] Step S213c: The clock error preset threshold is set to 1 microsecond. The minimum precision unit of the associated operating system time function is used to ensure that the absolute time deviation between the station and the concentrator does not exceed this threshold through microsecond-level time sampling and integer operations of tick time conversion.

[0074] A preset clock error threshold of 1 microsecond balances simulation accuracy with the limitations of hardware time functions. The minimum precision of operating system microsecond-level time functions (such as Linux's `clock_gettime`) is typically 1 microsecond. Converting tick values ​​using integer operations (such as multiplication and addition) ensures that errors originate solely from jitter within the time function itself. For example, if the operating system's time sampling error is ±0.5μs, after conversion, it corresponds to ±12.5 tick errors. However, by threshold verification (e.g., comparing the tick difference between the station and the concentrator to see if it exceeds 25 ticks, i.e., 1μs), the absolute time deviation can be controlled within the threshold. In power line carrier communication, a 1μs error corresponds to 25 ticks, far less than the slot-level tolerance (e.g., a 1ms slot corresponds to 25,000 ticks), thus preventing frame misalignment or retransmission. Furthermore, periodically calling the clock synchronization function (e.g., once per second) can further suppress the accumulation of long-term errors caused by crystal drift or environmental temperature changes.

[0075] Furthermore, step S200, which involves adding delay compensation before sending data and delaying the initiation of the physical layer receiving action when receiving data to offset IP network transmission delay, includes:

[0076] Step S221: Before the physical layer interface simulation module calls the socket send function, a fixed delay threshold is added to simulate the physical layer modulation delay. The fixed delay threshold is a preset value that is shorter than the actual physical layer modulation delay.

[0077] Before the physical layer interface simulation module calls the socket send function, the core purpose of adding a fixed delay threshold is to simulate the inherent delay of the physical layer modulation process. This threshold setting needs to be based on the actual processing time of the modulator in the power line carrier communication protocol. For example, OFDM modulation requires symbol mapping, IFFT transformation, and other operations, and the fixed delay threshold is usually a preset proportion of the actual modulation delay (e.g., 90%). For instance, in the HPLC protocol, the modulation delay may be determined by both the crystal oscillator frequency (e.g., 25MHz) and the symbol period (e.g., 125μs). By lowering the threshold (e.g., setting it to 112.5μs), space can be reserved to compensate for the random delay of IP network transmission. Furthermore, the dynamic adjustment strategy of the fixed delay threshold can be combined with network monitoring data (e.g., RTT measurement results) to further optimize the compensation accuracy and ensure timing alignment between the transmitting and receiving ends.

[0078] Step S222: When receiving data, start the physical layer receiving action within a preset time window before the timeout protection period of the receiving time slot.

[0079] When receiving data, the physical layer reception action is initiated within a preset time window before the timeout protection limit of the reception time slot. This proactively reserves a time buffer to offset the uncertainty of IP network transmission delays. For example, in power line carrier communication, if the IP network delay between the concentrator and the site is 50μs, the receiver needs to initiate reception 50μs before the start of the time slot to ensure that even if data packets arrive late due to network congestion, the physical layer signal can still be captured completely. This mechanism borrows from HARQ (Hybrid Automatic Repeat Request) technology in wireless networks, using pre-starting the reception buffer combined with timeout protection (such as timer interrupts) to avoid data truncation or loss due to delays. Simultaneously, the size of the time window must match the time slot tolerance defined by the protocol. For example, in HPLC, where the time slot width is 1ms, the receiver can set a 500μs pre-start window to ensure frame reception can still be completed within the delay fluctuation range. Furthermore, the timeout protection limit setting needs to be combined with network jitter statistics (such as measurements using MTR tools) to balance the risk of misjudgment and delay tolerance, avoiding data loss due to an excessively small window or resource waste due to an excessively long window.

[0080] Furthermore, in step S221, before the physical layer interface simulation module calls the socket send function, a fixed delay threshold is added to simulate the physical layer modulation delay, including:

[0081] Step S221a: Associate the fixed delay threshold with the time slot boundary constraint of the power line carrier communication protocol to ensure that the start time of the transmission window after adding delay does not exceed the start boundary of the current time slot. The fixed delay threshold is used to compensate for the timing deviation caused by the lack of physical layer modulation process in IP network transmission. The numerical range of the fixed delay threshold is smaller than the modulation delay measurement value of the real physical layer hardware platform.

[0082] Setting a fixed delay threshold addresses the timing discrepancy between the IP network simulation environment and the real physical layer. In real power line carrier communication (such as the State Grid HPLC system), the physical layer hardware modulation has inherent delays (e.g., the encoding / modulation processing time of FPGA or ASIC chips), while TCP / IP network transmission only completes packet forwarding and lacks this physical process. By embedding a fixed delay threshold (typically lower than the actual hardware measurement delay), time slot boundary constraints are actively constructed: a brief wait is forcibly inserted before calling the socket send function, ensuring that the start time of the data transmission window is strictly aligned with the start boundary of the current time slot. This threshold satisfies dual constraints—it must compensate for timing deviations caused by the lack of physical modulation, and it must also ensure that the transmission window after the delay does not intrude into the next time slot (e.g., the 1ms-level time slot division in the State Grid standard). Its value range is strictly set according to the lower limit of the modulation delay measurement value of the real hardware platform (such as the HPLC carrier module), ensuring that the simulation system maintains protocol timing accuracy while avoiding the risk of time slot misalignment caused by excessive delay.

[0083] Step S221b involves implementing a delay operation in the high-priority task process using a microsecond-level timer from the operating system, ensuring that the timing of the socket send function call aligns with the time slot-level timing requirements of the physical layer simulation.

[0084] The implementation of the microsecond-level timer relies on the precise time control capabilities of the operating system (such as the `usleep()` function in Linux). In the high-priority task process (i.e., the `PHY_STUB` task), this timer starts immediately after the physical layer state machine triggers the transmission action, and performs blocking and waiting according to a preset delay threshold. The key technology lies in mapping the operating system's microsecond-level time resolution (1μs) to the tick time system of the power line carrier protocol through a conversion factor (e.g., `PHY_TICKS_PER_US = 25`). This mapping allows the timing of the socket transmission function call to be precisely controlled within the protocol's effective window of the current time slot, thereby reproducing the real physical layer's time slot-level timing behavior in the simulation environment. As the highest-priority task, the exclusive use of CPU resources by the `PHY_STUB` process ensures the determinism of the delayed operation, avoiding timing inaccuracies caused by system scheduling jitter.

[0085] Through the aforementioned collaborative mechanism, a functional equivalent replacement for physical layer modulation delay is achieved in the simulation system. On one hand, the fixed delay threshold bridges the timing gap between the IP network and the real physical layer, strictly limiting the data transmission window to protocol time slot boundaries. On the other hand, the microsecond-level timer leverages the operating system's native high-precision timing capabilities to ensure accurate execution of delay compensation. The combination of these two mechanisms allows the simulation system to maintain time slot-level timing logic consistent with the real HPLC system even without hardware intervention, providing a realistic physical layer interaction experience for the data link layer. This not only solves the problem of the difficulty in obtaining real-world environments but also significantly improves debugging efficiency, compressing the originally hardware-dependent minute-level verification process to the second level.

[0086] Further, step S222, which involves initiating the physical layer reception action within a preset time window before the timeout protection period of the reception time slot when receiving data, includes:

[0087] Step S222a: Associate the start boundary of the timeout protection limit of the receiving time slot. The timeout protection limit is the timeout threshold of the guardian timer started by the physical layer interface simulation module in the receiving time slot.

[0088] The timeout protection limit setting directly maps to the time slot protection mechanism of real power line carrier communication protocols (such as the State Grid HPLC specification). When a receive time slot is initiated, the physical layer interface simulation module (PHY_STUB) initializes a guardian timer whose timeout threshold strictly follows the time slot boundaries defined by the protocol (e.g., a typical value of 90%-95% of the time slot length). This time limit serves as a hard cutoff boundary for the receive action; if valid data reception is not completed within this period, the physical layer will forcibly terminate the operation of this time slot and trigger the scheduling of the next time slot. This design replicates the physical constraints of channel occupancy time on the real hardware platform, ensuring consistency between the simulation system and the protocol timing logic.

[0089] Step S222b: Delay the call to the physical layer receive action function in the high-priority task process, so that the execution time of the action function is the start time of the timeout protection limit of the current receive time slot minus the preset time window duration.

[0090] The core of the delayed start mechanism lies in proactively mitigating the uncertainties of IP network transmission. In the high-priority task process (PHY_STUB), the call to the physical layer receive action function (such as phy_start_rx) is deliberately postponed until the start of the timeout protection period minus the preset time window duration. This strategy utilizes the buffering effect of the time window to offset the random delays introduced by the Com_Agent relay. Technically, the delay is precisely calculated using a microsecond-level timer in the operating system (such as Linux timerfd) and bound to a time slot scheduling list. This allows the timing of the receive window opening to dynamically adapt to network conditions, avoiding both the waste of resources due to premature start-up and the data loss caused by delayed start-up.

[0091] Step S222c: By delaying the start, TCP packet data is processed after arriving at the circular queue due to the IP network transmission delay.

[0092] The asynchronous buffering capability of the circular queue is the technical foundation of this step. An independent listening thread (thread_recv) continuously receives TCP packets and stores them in the circular queue, unaffected by the start or stop of physical layer reception. The delayed start mechanism ensures that the latency of IP network transmission is absorbed by the time window when PHY_STUB processes queue data. At this time, the packets buffered in the circular queue (including the complete MAC PDU after fragmentation and reassembly) can be extracted and processed by PHY_STUB according to the protocol timing, thus achieving an ideal reception effect with zero data loss in the simulation environment. Especially for time-sensitive beacon frames, the reception success rate is increased from the original 95% to nearly 100%.

[0093] By combining the protocol constraints of the daemon timer, the network adaptability of delayed startup, and the asynchronous buffer depth of the circular queue, a triple technical effect is achieved in a simulation environment detached from real hardware: First, it accurately reproduces the time slot boundary control logic of real power line carrier communication (such as the State Grid HPLC protocol), ensuring the timing consistency between the simulation system and the physical layer protocol; second, it dynamically adapts to IP network transmission delays through delayed startup windows (such as the measured 5% packet loss rate of Com_Agent), transforming random delays into deterministic processing opportunities and completely eliminating reception lead / lag and timing misalignment caused by network jitter; third, relying on the continuous listening and fragmentation reassembly mechanism of the circular queue, it ensures the complete processing of all TCP packets (including sensitive beacon frames), solving the difficulties of high problem randomness and high shutdown difficulty. This provides highly reliable underlying support for large-scale dynamic network debugging and complex random bug reproduction, enabling R&D personnel to achieve debugging controllability and efficiency exceeding that of real hardware environments.

[0094] Furthermore, in step S300, the physical layer state changes are responded to by registering the frame control header callback function, TCP packet data is buffered using a circular queue, and the physical layer interface simulation module parses the packets, allocates memory, and processes the payload in a specified time slot after timing synchronization, including:

[0095] Step S310: Register the corresponding callback function according to the frame type of the Media Access Control Protocol (MAC) data unit. The frame control header callback function is the MAC layer processing function that responds to the physical layer state machine switching. The frame types include beacon frames, soft acknowledgment frames, and coordination frames.

[0096] Step S320: Dual-mode TCP packets (PLC / RF channel) are received via an independent listening thread and stored in the same circular queue. Fragmented TCP packets are then concatenated, with a 1-byte channel identifier (0x01 = PLC, 0x02 = RF) added to the packet header to distinguish between dual-mode data sources. A fragmented TCP packet is defined as a data packet carrying a private header, which includes a 6-byte media access control address and a payload length identifier.

[0097] In step S330, the high-priority task process extracts the complete MAC PDU payload from the circular queue in a specified time slot after timing synchronization, allocates dynamic memory to store the payload data, and calls the frame control header callback function to process the data according to the physical layer state switch.

[0098] Further, step S330, which involves retrieving the complete MAC PDU payload from the circular queue and allocating dynamic memory to store the payload data, includes:

[0099] Step S331: When the high-priority task process reaches the designated receiving time slot after timing synchronization, extract the TCP segment carrying the private message header from the head of the circular queue, verify the data integrity according to the payload length identifier in the private message header, and perform memory reassembly operation according to the preset splicing conditions if there are fragmented messages.

[0100] When the high-priority task process (PHY_STUB) is triggered in a specified receive time slot after timing synchronization (such as the precise time slot window after beacon synchronization), it extracts a TCP segment containing a private header from the head of the circular queue. The payload length identifier (the next 4 bytes) of the private header (struct_priv_hdr_t) serves as the core verification criterion. By comparing the actual received data length with the identifier value, it determines whether fragmented packets exist. If fragmentation is detected (e.g., the length identifier value is greater than the current buffered data size), a reassembly operation is performed in memory according to preset splicing conditions (e.g., the start identifier of consecutive packet headers is 0xFFFFFFFF). This mechanism ensures that fragmented packets transmitted over the IP network are ultimately fully restored, eliminating the problem of incomplete MAC PDU data caused by TCP streaming transmission at its source, and providing structurally complete protocol data units for subsequent processing.

[0101] Step S332: When a complete MAC PDU payload is identified, the RTOS memory pool management interface is called to allocate a dynamic memory block. The size of the dynamic memory block is determined by the length of the MAC PDU payload, and the payload data cached in the circular queue is copied to the dynamic memory block.

[0102] Once the complete MAC PDU payload is identified, the memory pool management interface, ported from the real RTOS, is invoked to dynamically allocate memory blocks according to the MAC PDU payload length. This achieves precise matching of memory block sizes: the allocation space is determined by the MAC PDU payload length (including the frame control header and payload), avoiding memory waste or overflow. Furthermore, although zero-copy optimization is possible, a copy mechanism (copying from the circular queue buffer to the dynamic memory block) is actively employed to fully replicate the hardware behavior of the real carrier module—in the real system, physical copying is required when the physical layer and data link layer transfer data through shared memory. This ensures complete consistency between the simulation environment and the hardware platform in terms of processing links, guaranteeing the reliability of the debugging results.

[0103] Step S333: Trigger the frame control header callback function according to the physical layer state machine switching event, and pass the dynamic memory block pointer and associated time slot information to the data link layer task process, so that the data link layer can perform protocol parsing and memory release operations.

[0104] Physical layer state machine transition events (such as PHY_STATUS_PD → PHY_STATUS_RX_FRAME) trigger the frame control header callback function. At this time, the dynamic memory block pointer and time slot information (such as the BPTS time slot number) are passed to the data link layer (DL) task process. The DL layer performs protocol parsing according to the frame type (beacon / soft acknowledgment / coordination frame) and immediately releases the dynamic memory block after processing. By binding state machine events with callback functions, the notification mechanism of state transitions of the real physical layer chip to the data link layer is accurately simulated; and the responsibility for memory allocation / release is clearly assigned to both the physical layer and the data link layer (simulating the responsibilities of real hardware), avoiding the memory leak risks common in simulation environments.

[0105] The three-step collaborative approach constructs a data processing chain equivalent to real hardware. Fragmentation verification and reassembly ensure the integrity of data transmitted unreliably at the network layer; dynamic memory allocation and copy replication reproduce hardware resource management constraints; state machine triggering and cross-layer transmission achieve accurate simulation of layered interaction in the protocol stack. Ultimately, the core objective is to make the runtime behavior (including memory usage, timing response, and exception handling) of modules above the data link layer completely consistent with that of real carrier modules in a pure software environment detached from physical hardware.

[0106] Furthermore, the simulation method for the power line carrier communication protocol data link layer also includes a dynamic networking routing control mechanism: constructing a proxy communication module, establishing TCP connections between the proxy communication module and all network nodes, and pre-setting a routing table in the proxy communication module, which stores the logical connection relationships of network nodes.

[0107] When the proxy communication module receives a TCP packet from the source node, it performs the following operations:

[0108] Step S410: Parse the source medium access control address, destination medium access control address, and frame type carried in the TCP packet.

[0109] After receiving a TCP packet from the source node, the proxy communication module first parses the source MAC and destination MAC embedded in the packet header and identifies the frame type field (such as beacon frame, service data frame, or relay control frame). The source MAC address identifies the logical identity of the sending node (e.g., 0x0001 for concentrators, 0x1001-0xFFFF for meter nodes), while the destination MAC address specifies the expected recipient of the data frame. The parsing of the frame type determines the triggering conditions for subsequent routing strategies (e.g., beacon frames require network-wide broadcasting, while service data frames require targeted unicasting). This step, through deep deconstruction of the TCP packet header metadata, provides basic input parameters for routing decisions, ensuring that forwarding behavior strictly conforms to the addressing specifications of the power line carrier communication protocol.

[0110] Step S420: Query the routing table and determine the forwarding path corresponding to the target medium access control address based on the logical connection relationship.

[0111] The proxy communication module queries a pre-configured routing table based on the parsed target MAC address. This routing table stores the logical connections between network nodes in key-value pairs (e.g., concentrator → repeater 1 → meter node group). The routing table is generated through static configuration or dynamic learning protocols, explicitly defining the hierarchical affiliation between nodes (e.g., concentrator as root node, repeater as secondary node, meter as leaf node). During a query, if the target MAC address matches a leaf node (e.g., meter 0x1001), a unique forwarding path is determined according to the tree topology rules: data must be transmitted via the first-hop link from the root node to the secondary node, and direct connections across levels are prohibited. This mechanism abstracts the physical TCP fully connected network into a logical tree topology, forcing data to be transmitted along the hierarchical paths defined by the protocol.

[0112] In step S430, if the target medium access control address is associated with a child node in a multi-layer relay topology, then direct communication across layers is prohibited, and TCP packets are only forwarded to the next-hop node specified in the routing table.

[0113] When a target MAC address is associated with a child node in a multi-layer relay topology (e.g., meter 0x1001 belongs to repeater 0x0201), the proxy communication module only forwards TCP packets to the next-hop node specified in the routing table (e.g., repeater 0x0201) and discards unauthorized cross-layer direct connection requests. For example, if a concentrator (0x0001) attempts to directly access a meter (0x1001), but the routing table shows that the meter needs to be relayed through repeater 0x0201, the proxy module will intercept the direct connection packet and redirect it to the repeater. This operation, through the mandatory constraints of the routing table, reproduces the relay rules of power line carrier communication at the TCP / IP transport layer, avoiding the breach of the hierarchical isolation required by the protocol due to the fully connected nature of the network layer.

[0114] This mechanism, through the hard constraints of the routing table on the logical topology, accurately reproduces the tree-like networking characteristics of power line carrier communication in a TCP / IP-based simulation environment. The proxy communication module acts as a virtual relay hub, abstracting the fully connected network at the physical layer into a hierarchical topology required by the protocol. It retains the reliability advantages of TCP transmission while ensuring that data frames strictly follow the hop-by-hop forwarding rule of concentrator → repeater → terminal meter through a three-level pipeline operation of address resolution, path lookup, and hierarchical isolation. This fundamentally eliminates topology chaos caused by direct network layer connections, providing underlying support for the simulation verification of advanced functions such as multi-hop routing and relay load balancing.

[0115] Furthermore, the software module simulates the collaborative operation of the "PLC communication module + electricity meter" hardware combination. The virtual electricity meter module runs as an independent process, generating electricity meter business data (such as periodic meter reading requests and rate parameter updates) according to the State Grid DL / T 645 protocol, and transmitting the business data to the PLC protocol application layer via the Socket interface. The application layer encapsulates the business data into MAC frames and then hands them over to the data link layer simulation module for processing. Simultaneously, response commands from the concentrator (such as time synchronization commands and load control) are parsed by the protocol stack and returned to the virtual electricity meter module for business logic verification. This implementation method enables the simulation system to completely simulate the entire process of power line carrier communication from business triggering and protocol encapsulation to timing synchronization without relying on the hardware electricity meter, meeting the State Grid's verification requirements for electricity meter communication scenarios.

[0116] Accordingly, a second aspect of the present invention provides a power device, including: at least one processor; and a memory connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to cause the at least one processor to perform the power line carrier communication protocol data link layer simulation method as described above.

[0117] Accordingly, a third aspect of the present invention provides a computer-readable storage medium having computer instructions stored thereon, which, when executed by a processor, implement the power line carrier communication protocol data link layer simulation method described above.

[0118] The embodiments of the present invention aim to protect a data link layer simulation method for power line carrier communication protocols, which has the following effects:

[0119] 1. By creating high-priority task processes, the triggering of physical layer transmission and reception actions is strictly bound to the time slot-level timing, solving the timing misalignment problem caused by task scheduling delay in traditional simulations; in the communication scenario between the concentrator and the site, high-priority tasks can force the physical layer actions to be triggered in a specified time slot, avoiding latency jitter caused by operating system task queue contention, thereby improving the simulation accuracy of the protocol stack for mechanisms such as CSMA / CA, and reducing frame conflicts or retransmissions caused by timing deviations;

[0120] 2. To address the inherent latency characteristics of TCP / IP network transmission, this paper effectively solves the impact of network latency on frame alignment in the simulation environment by real-time monitoring of the timestamp carried by the concentrator beacon frame and combining local clock synchronization with latency compensation at the sending / receiving end. When a site receives data, delaying the physical layer receiving action can offset the random latency of IP network transmission (such as router queue congestion or link congestion), ensuring that data frames are demodulated and parsed within the physical layer time slot. Adding dynamic latency compensation at the sending end can avoid frame transmission timeouts or buffer overflows at the receiving end caused by network latency, thereby improving the consistency between the data link layer simulation and the real scenario.

[0121] 3. A circular queue structure is used to cache TCP packet data. By reusing a fixed-size memory space, the efficiency and stability of data frame processing are significantly improved. Compared with the traditional linear buffer structure, the circular queue does not require frequent data movement or dynamic memory allocation, reducing the performance loss caused by memory fragmentation. In power line carrier communication, high-priority task processes need to process a large number of data packets quickly within a time slot. The first-in-first-out (FIFO) characteristic of the circular queue can realize efficient enqueue and dequeue operations. At the same time, the computational overhead caused by data movement is avoided through the head and tail pointer circular update mechanism.

[0122] 4. By configuring independent parameters and implementing a unified task scheduling mechanism for the dual-mode physical layer interface, the RF+PLC dual-mode collaborative scenario required by the State Grid is reproduced in a single simulation system. The dual-mode interface shares a circular queue and high-priority process resources to avoid redundant overhead; differentiated timing parameters (such as time slot width and modulation delay) ensure the consistency of simulation results with the behavior of the real dual-mode hardware platform, significantly improving the efficiency of protocol stack compatibility verification with the State Grid dual-mode specification.

[0123] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0124] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0125] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0126] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0127] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A simulation method for the data link layer of a power line carrier communication protocol, characterized in that, Includes the following steps: Step S100: Construct a physical layer interface simulation module, simulate power line carrier and wireless air interface transmission through TCP socket communication, and create a high-priority task process to handle time slot-level timing synchronization, which is used to trigger physical layer transmit and receive actions in a specified time slot. Step S200: Configure timing synchronization control mechanism, obtain the timestamp carried by the beacon frame sent by the concentrator, call the clock synchronization function to align the local clock of the site with the timestamp when the beacon frame header is received, add delay compensation before sending data, and delay the start of physical layer receiving action when receiving data to offset IP network transmission delay. Step S300: Implement the data frame processing flow. The physical layer state changes are responded to by registering the frame control header callback function. TCP packet data is buffered by using a circular queue. The physical layer interface simulation module parses the packets, allocates memory, and processes the payload in the specified time slot after timing synchronization, thus completing the closed-loop operation of the data link layer simulation. Step S200, which involves calling a clock synchronization function to align the station's local clock with the timestamp when the beacon frame header is received, includes: Step S211: Define the beacon frame header parsing conditions. The beacon frame header is defined as the frame control header part of the Media Access Control Protocol data unit. When the physical layer interface simulation module demodulates the frame control header, the clock synchronization function is triggered. Step S212: Perform clock synchronization operation, call the clock synchronization function, and set the tick time of the local clock of the site to the timestamp value carried by the beacon frame. The timestamp value comes from the local clock sampling value when the concentrator sends the beacon frame. Step S213: Control the clock synchronization accuracy by calibrating the clock deviation through the microsecond-level time function of the operating system, and control the clock error between the site and the concentrator within the preset clock error threshold. The preset clock error threshold is associated with the time slot-level timing tolerance defined by the power line carrier communication protocol. The step S200, which involves adding delay compensation before sending data and delaying the initiation of physical layer reception during data reception to offset IP network transmission delay, includes: Step S221: Before the physical layer interface simulation module calls the socket send function, a fixed delay threshold is added to simulate the physical layer modulation delay. The fixed delay threshold is a preset value that is shorter than the actual physical layer modulation delay. Step S222: When receiving data, start the physical layer receiving action within a preset time window before the timeout protection period of the receiving time slot; Step S300, which involves registering a frame control header callback function to respond to physical layer state changes, using a circular queue to buffer TCP packet data, and having the physical layer interface simulation module parse packets, allocate memory, and process payloads in a specified time slot after timing synchronization, includes: Step S310: Register a corresponding callback function according to the frame type of the Media Access Control Protocol (MAC) data unit. The frame control header callback function is a MAC processing function that responds to the physical layer state machine switching. The frame type includes beacon frame, soft acknowledgment frame, and coordination frame. Step S320: Receive TCP packets through an independent listening thread and store them in a circular queue. Perform a splicing operation on the fragmented TCP packets. The fragmented TCP packets are defined as data packets carrying a private header, whose header contains a 6-byte media access control address and a payload length identifier. In step S330, the high-priority task process extracts the complete MAC PDU payload from the circular queue at a specified time slot after timing synchronization, allocates dynamic memory to store the payload data, and calls the frame control header callback function to process the data according to the physical layer state switch.

2. The simulation method for the data link layer of the power line carrier communication protocol according to claim 1, characterized in that, Step S213, which involves calibrating the clock deviation using a microsecond-level time function of the operating system to control the clock error between the site and the concentrator within a preset clock error threshold, includes: Step S213a: Set the physical layer clock reference of the power line carrier communication protocol to a preset crystal oscillator frequency, and multiply the current time obtained by the microsecond-level time function of the operating system by the conversion coefficient to obtain the tick time value of the simulation system. Step S213b: When the clock synchronization function is called, the second-level count and microsecond-level count of the beacon frame timestamp are extracted. The second-level count is multiplied by 1,000,000 and added to the microsecond-level count to obtain the total microsecond value. Then, it is multiplied by the conversion coefficient to convert it into the target tick time and overwritten into the station's local clock. In step S213c, the preset threshold for clock error is set to 1 microsecond, which is the smallest precision unit of the operating system time function. Through microsecond-level time sampling and integer operations of tick time conversion, it is ensured that the absolute time deviation between the station and the concentrator does not exceed this threshold.

3. The simulation method for the data link layer of the power line carrier communication protocol according to claim 1, characterized in that, The step S221, which involves adding a fixed delay threshold to simulate physical layer modulation delay before the physical layer interface simulation module calls the socket send function, includes: Step S221a: Associate the fixed delay threshold with the time slot boundary constraint of the power line carrier communication protocol so that the start time of the transmission window after adding delay does not exceed the start boundary of the current time slot. The fixed delay threshold is used to compensate for the timing deviation caused by the lack of physical layer modulation process in IP network transmission. The numerical range of the fixed delay threshold is smaller than the modulation delay measurement value of the real physical layer hardware platform. Step S221b: In the high-priority task process, a delay operation is implemented through the microsecond-level timer of the operating system to ensure that the timing of the socket sending function is aligned with the time slot-level timing requirements of the physical layer simulation.

4. The simulation method for the data link layer of the power line carrier communication protocol according to claim 1, characterized in that, Step S222, which involves initiating physical layer reception within a preset time window before the timeout protection period of the reception time slot when receiving data, includes: Step S222a: Associate the start boundary of the timeout protection limit of the receiving time slot, wherein the timeout protection limit is the timeout threshold of the guardian timer started by the physical layer interface simulation module in the receiving time slot; Step S222b: In the high-priority task process, the physical layer receiving action function is called with a delay, so that the execution time of the action function is the start time of the timeout protection limit of the current receiving time slot minus the preset time window duration; Step S222c: By delaying the start, TCP packet data is processed after arriving at the circular queue due to the IP network transmission delay.

5. The simulation method for the data link layer of the power line carrier communication protocol according to claim 1, characterized in that, Step S330, which involves retrieving the complete MAC PDU payload from the circular queue and allocating dynamic memory to store the payload data, includes: Step S331: When the high-priority task process reaches the designated receiving time slot after timing synchronization, extract the TCP segment carrying the private message header from the head of the circular queue, verify the data integrity according to the payload length identifier in the private message header, and if there are fragmented messages, perform memory reassembly operation according to the preset splicing conditions. Step S332: When a complete MAC PDU payload is identified, the RTOS memory pool management interface is called to allocate a dynamic memory block. The size of the dynamic memory block is determined by the length of the MAC PDU payload, and the payload data cached in the circular queue is copied to the dynamic memory block. Step S333: Trigger the frame control header callback function according to the physical layer state machine switching event, and pass the dynamic memory block pointer and associated time slot information to the data link layer task process, so that the data link layer can perform protocol parsing and memory release operations.

6. The simulation method for the data link layer of the power line carrier communication protocol according to any one of claims 1-5, characterized in that, It also includes a dynamic networking routing control mechanism: A proxy communication module is constructed, which establishes TCP connections with all network nodes. A routing table is pre-configured in the proxy communication module, which stores the logical connection relationships of the network nodes. When the proxy communication module receives a TCP packet from the source node, it performs the following operations: Parse the source medium access control address, destination medium access control address, and frame type carried in the TCP packet; Query the routing table and determine the forwarding path corresponding to the target medium access control address based on the logical connection relationship; If the target medium access control address is associated with a child node in a multi-layer relay topology, then direct communication across layers is prohibited, and the TCP packets are only forwarded to the next-hop node specified in the routing table.

7. An electrical device, characterized in that, include: At least one processor; And a memory connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to cause the at least one processor to perform the power line carrier communication protocol data link layer simulation method as described in any one of claims 1-6.

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