Method of manufacturing a copper interconnect structure and semiconductor structure

Abstract

The application discloses a manufacturing method of copper interconnection structure and a semiconductor structure. The manufacturing method of copper interconnection structure comprises the following steps: providing a semiconductor substrate; forming a low dielectric constant medium layer with gradually increasing density from bottom to top on the semiconductor substrate; forming a copper interconnection groove in the medium layer; forming a copper barrier layer on the sidewall and bottom of the groove; and filling metal copper on the copper barrier layer in the copper interconnection groove. By using the method, the copper interconnection structure process capable of inhibiting copper diffusion is realized, and the reliability problem caused by the existing barrier layer tantalum nitride / tantalum deposition process with the reduction of the line width of the metal layer is avoided.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, specifically to a method for manufacturing a copper interconnect structure. This application also relates to various semiconductor structures. Background Technology

[0002] As integrated circuit feature sizes shrink (e.g., to the nanometer scale), semiconductor devices face the challenge of enhanced Joule heating due to size reduction. To address this challenge, copper, a metal with low resistance and strong electromigration resistance, is generally used as the conductor to form the metal interconnect structure of semiconductor devices. However, copper-based metal interconnect structures are subject to copper diffusion issues to some extent, thus posing a challenge in the manufacturing process of copper-based metal interconnect structures.

[0003] To effectively address copper diffusion, existing technologies employ tantalum nitride / tantalum (TaN / Ta) structures to encapsulate copper, thereby blocking the diffusion of copper atoms (ions). TaN exhibits high chemical stability and strong barrier properties against Cu atoms (ions); while Ta possesses adhesive properties. Depositing a TaN / Ta barrier layer can, to some extent, prevent copper diffusion. However, existing tantalum nitride / tantalum barrier layer deposition schemes suffer from low reliability as the metal layer linewidth shrinks. The resistivity of the barrier layer is significantly higher than that of copper (TaN resistivity: 210 μΩ·cm, Cu resistivity: 1.67 μΩ·cm), and the barrier layer thickness directly affects the total interconnect resistance, especially in narrow linewidth scenarios where the resistance may increase with decreasing linewidth. As process nodes shrink (e.g., from 28nm to 5nm), the barrier layer thickness is forced to decrease from several nanometers to near a single atomic layer, leading to deteriorated step coverage and increased susceptibility to defects at edges / corners. Thinning the barrier layer weakens the adhesion of the Ta layer to copper, making delamination at the interface more likely and accelerating electromigration failure. On the other hand, TaN / Ta barrier layers can be deposited using atomic layer deposition (ALD) to achieve sub-nanometer thickness control and excellent step coverage. However, the maintenance and application costs of ALD single-atom deposition process are relatively high.

[0004] Therefore, how to manufacture copper interconnect structures with strong copper diffusion suppression effects to avoid reliability problems arising from existing barrier layer tantalum nitride / tantalum deposition processes as linewidth shrinks is a problem that needs to be solved. Summary of the Invention

[0005] This application provides a method for manufacturing a copper interconnect structure and various semiconductor structures, which can provide better suppression of copper diffusion and avoid reliability problems caused by the existing barrier layer tantalum nitride / tantalum deposition process as the metal layer linewidth shrinks. The specific solution is as follows:

[0006] In a first aspect, this application provides a method for manufacturing a copper interconnect structure, the method comprising: providing a semiconductor substrate; forming a low dielectric constant dielectric layer with gradually increasing density from bottom to top on the semiconductor substrate; forming a copper interconnect trench in the dielectric layer; forming a copper barrier layer on the sidewalls and bottom of the trench; and filling the copper barrier layer in the copper interconnect trench with metallic copper.

[0007] Optionally, forming a low dielectric constant dielectric layer with a density gradient increasing from bottom to top on the semiconductor substrate includes: the dielectric layer comprising at least a first dielectric sublayer located at the bottom and a second dielectric sublayer located at the top with a density greater than that of the first dielectric sublayer; or, the dielectric layer comprising at least a first dielectric sublayer located at the bottom, a second dielectric sublayer located in the middle, and a third dielectric sublayer located at the top, wherein the density of the first dielectric sublayer, the second dielectric sublayer, and the third dielectric sublayer gradually increases; or the dielectric layer comprises a plurality of dielectric sublayers from bottom to top, wherein the density of the plurality of dielectric sublayers gradually increases, or the spacing increases, or the gradient increases uniformly or non-uniformly; or for each dielectric sublayer, there is a dielectric sublayer below it with a density not greater than that sublayer.

[0008] Optionally, a method for forming a low dielectric constant dielectric layer with progressively increasing density from bottom to top on the semiconductor substrate includes: during the formation of the dielectric layer, increasing the power of a radio frequency power supply used to apply energy to the feed gas.

[0009] Optionally, the incremental radio frequency power used to apply energy to the feed gas includes:

[0010] The radio frequency power used to apply energy to the feed gas is gradually increased in a gradient and / or in stages to form the low dielectric constant dielectric layer with increasing density.

[0011] Optionally, when the radio frequency power used to apply energy to the feed gas is increased in stages, the formed dielectric layer comprises multiple dielectric sublayers.

[0012] Optionally, the stepwise increasing of the radio frequency power applied to the raw material gas to form the dielectric layer with increasing density further includes: dividing the deposition process of the dielectric layer into multiple power stages, executing each power stage sequentially, and forming a dielectric sublayer of the power stage in each power stage with an increased radio frequency power compared to the previous power stage, wherein the dielectric sublayer formed in each power stage has increased density compared to the dielectric sublayer formed in the previous power stage.

[0013] Optionally, the plurality of power stages include at least a low-power stage and a high-power stage; wherein, in the low-power stage, the radio frequency power supply applied to the raw material gas dissociates the precursor used to form the dielectric layer and forms the bottom dielectric sublayer of the dielectric layer, and the power value of the radio frequency power supply in the low-power stage is a first preset power value; in the high-power stage, the power value of the radio frequency power supply is increased to a second preset power value, and the top dielectric sublayer of the dielectric layer is formed at the interface near the metal layer protected by the dielectric layer; the first preset power value is lower than the second preset power value.

[0014] Optionally, the dielectric constant of the bottom dielectric sublayer is less than 2.5; the density of the top dielectric sublayer is greater than... .

[0015] Optionally, the plurality of power stages include four power stages that are performed sequentially for deposition. The power range of the RF power supply in each of the four power stages is 150W~250W, 350W~450W, 550W~650W, and 750W~850W, respectively, and the deposition time range of each stage is 35s~25s, 10s~20s, 5s~15s, and 3s~10s, respectively.

[0016] Optionally, the process formulation data for fabricating the dielectric layer includes: the number of dielectric sublayers of the dielectric layer and the process parameters for forming each dielectric sublayer; the process formulation data is determined based on the design requirements information of the semiconductor device; the design requirements information includes the dielectric constant of the dielectric layer and the resistance, capacitance, and delay characteristics of the semiconductor device containing the dielectric layer.

[0017] Optionally, the process parameters for forming each dielectric sublayer include: the radio frequency power applied to the feed gas during the formation of the dielectric sublayer, and the thickness and / or deposition time of the dielectric sublayer.

[0018] Optionally, the process formulation data is further determined based on a density-power relationship model, which is used to optimize the process formulation data based on the design requirements information.

[0019] Optionally, the density-power relationship model includes: a first relationship between the power of each power stage and the film porosity of each dielectric sublayer, and a second relationship between the dielectric constant of each dielectric sublayer and the power of each power stage; the first and second relationships are constructed using RF power as a process adjustment variable; a third relationship characterizing the intrinsic density of the dielectric layer; the third relationship is constructed based on the deposition time of each dielectric sublayer and the film porosity of the corresponding dielectric sublayer; a fourth relationship characterizing the intrinsic dielectric constant of the dielectric layer; the fourth relationship is constructed based on the deposition time of each dielectric sublayer; the method further includes: determining the number of dielectric sublayers, the deposition time of each dielectric sublayer, and the RF power used to form each dielectric sublayer based on the intrinsic dielectric constant that meets the design requirements and the total thickness of each dielectric sublayer of the dielectric layer, using the first, second, third, and fourth relationships, as target recipe data, the target recipe data being used to fabricate a dielectric layer that meets the intrinsic dielectric constant and total thickness conditions of the dielectric layer in the design requirements; the deposition time of each dielectric sublayer characterizes the thickness of the corresponding dielectric sublayer.

[0020] Optionally, the density-power relationship model includes process adjustment variables; the process adjustment variables include one or more of the following: high-frequency radio frequency power, low-frequency radio frequency power, silane flow rate, and nitrous oxide flow rate.

[0021] Optionally, the raw materials used to form the dielectric layer include one or more of SiO2, SiCOH, SiCN, FSG, and porous SiO2.

[0022] Secondly, this application also provides a semiconductor structure, comprising: a semiconductor substrate; a dielectric layer formed on the semiconductor substrate; a copper interconnect trench formed in the dielectric layer; a copper barrier layer formed on the sidewalls and bottom of the trench; and metallic copper filling the copper barrier layer in the copper interconnect trench; wherein the dielectric layer is a low dielectric constant dielectric layer with a density gradient increasing from bottom to top.

[0023] Thirdly, this application also provides another semiconductor structure, including: at least two stacked semiconductor dielectric layers; copper interconnect trenches formed in the two adjacent semiconductor dielectric layers; copper barrier layers formed on the sidewalls and bottom of each copper interconnect trench; and copper metal filling each copper barrier layer; wherein the upper semiconductor dielectric layer in the two adjacent semiconductor dielectric layers is a low dielectric constant dielectric layer with gradually increasing density from bottom to top.

[0024] Fourthly, this application also provides another semiconductor structure, comprising: a semiconductor substrate; a dielectric layer formed on the semiconductor substrate; at least two adjacent and spaced-apart copper interconnect trenches formed in the dielectric layer; copper barrier layers formed on the sidewalls and bottom of each copper interconnect trench; and copper metal filling in each copper barrier layer; wherein the dielectric layer is a low-dielectric-constant dielectric layer with a density that gradually increases from the center towards the two copper metal layers respectively filled. Alternatively, a semiconductor substrate may have dielectric layers formed on both sides, and copper interconnect trenches formed in each side dielectric layer; copper barrier layers formed on the sidewalls and bottom of each copper interconnect trench; and copper metal filling in each copper barrier layer; wherein the dielectric layer is a low-dielectric-constant dielectric layer with a density that gradually increases from the center towards the copper metal layers on both sides.

[0025] Compared with the prior art, this application has the following advantages:

[0026] The manufacturing method and semiconductor structure of the copper interconnect structure provided in this application involve providing a semiconductor substrate; forming a low-dielectric-constant dielectric layer with gradually increasing density from bottom to top on the semiconductor substrate; forming copper interconnect trenches in the dielectric layer; forming copper barrier layers on the sidewalls and bottom of the trenches; and filling the copper barrier layers in the copper interconnect trenches with metallic copper. Therefore, the density of the dielectric layer gradually increases in the direction towards the copper barrier layer, resulting in a high interface density between the dielectric layer and the copper barrier layer, thereby improving the resistance to copper diffusion.

[0027] Preferably, during the deposition of the dielectric layer, the radio frequency power used to apply energy to the feed gas in the deposition chamber is increased incrementally, forming a dielectric layer with increasing density. The feed gas refers to the gas introduced into the deposition chamber for depositing the dielectric layer and subjected to plasma bombardment during the deposition process. This allows for a balance between the film density and dielectric properties of the dielectric layer during formation, facilitating the formation of a dielectric layer with both low total interconnect resistance and good resistance to copper diffusion. This provides a basis for reducing the thickness of the TaN / Ta barrier layer to address the gradually shrinking linewidth of the metal layer. Attached Figure Description

[0028] Figure 1 This is a schematic cross-sectional view of a semiconductor structure formed based on existing copper interconnect technology.

[0029] Figure 2 This is a schematic cross-sectional view of a semiconductor dielectric layer formed by a manufacturing method based on the copper interconnect structure provided in one embodiment of this application.

[0030] Figure 3This is a schematic diagram showing the relationship between the dielectric constant and the resistance to copper diffusion at the interface of the dielectric layer, provided in one embodiment of this application. Detailed Implementation

[0031] To enable those skilled in the art to better understand the technical solutions of this application, the application will be clearly and completely described below with reference to the accompanying drawings of the embodiments. However, this application can be implemented in many other ways different from those described below. Therefore, based on the embodiments provided in this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application.

[0032] It should be noted that the terms "first," "second," etc., in the claims, specification, and drawings of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. Such data are interchangeable where appropriate so that the embodiments of this application described herein can be implemented in a sequence other than that shown or described herein. Furthermore, the terms "comprising," "having," and their variations are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0033] To facilitate understanding of the various embodiments of this application, some concepts involved in the embodiments are given.

[0034] Copper diffusion refers to the strong tendency of copper atoms (ions) in the metal layer to diffuse into the dielectric layer, thereby contaminating the dielectric layer. Copper diffusion may further lead to leakage current, voltage decay, or even breakdown of the dielectric layer, seriously threatening the reliability of semiconductor devices.

[0035] Dielectric constant: Characterizes the electrical insulation capability of a dielectric layer. The larger the dielectric constant k, the better the insulation performance.

[0036] Low-k dielectric layer: also known as low-k dielectric layer, refers to the interlayer dielectric layer made of low-k dielectric material. It is mainly used in integrated circuits to reduce parasitic capacitance between interconnects and improve signal transmission speed and chip performance.

[0037] Resistive-capacitive delay characteristic (RC delay) refers to the delay phenomenon caused by charge accumulation and release when a signal passes through a circuit composed of resistors (R) and capacitors (C). Low-k dielectric layers can be used to reduce the delay time of RC delay in circuits.

[0038] Porosity (ρ): Characterizes the size and number of pores in a dielectric layer, and its value reflects the density of the dielectric layer. The larger the ρ value, the more porous the membrane layer.

[0039] Example 1

[0040] The first embodiment of this application provides a method for manufacturing a copper interconnect structure. For ease of understanding, a cross-sectional structure of a semiconductor structure including a copper interconnect structure fabricated using existing technology is first given. Please refer to... Figure 1 , Figure 1 This is a schematic cross-sectional view of a semiconductor structure formed using existing copper interconnect technology. It illustrates a cross-sectional structure of a semiconductor stacked structure comprising multiple semiconductor layers, including two semiconductor layers. and ,by For example, a semiconductor layer includes: a substrate 100; a dielectric layer 200 located on the surface of the substrate, wherein the dielectric layer 200 is a low-k dielectric layer; a barrier layer 300 deposited on the surface of a trench etched on the dielectric layer; and a metal layer 400 located on the barrier layer, wherein the top surface is flush with the surface of the dielectric layer 300, wherein the metal layer 100 is particularly a copper interconnect structure.

[0041] The Low-k dielectric layer is a porous SiCOH material, i.e., carbon-doped silicon oxide. The barrier layer 300 is made of TaN / Ta, protecting the metal layer 400. However, as the linewidth of the metal layer decreases, the reliability of the barrier layer 300 may decrease.

[0042] To address the aforementioned problems, this embodiment provides a method for manufacturing a copper interconnect structure. The method includes: providing a semiconductor substrate; forming a low-dielectric-constant dielectric layer on the semiconductor substrate with gradually increasing density from bottom to top; forming a copper interconnect trench in the dielectric layer; forming a copper barrier layer on the sidewalls and bottom of the trench; and filling the copper barrier layer in the copper interconnect trench with metallic copper.

[0043] For simplicity, the semiconductor substrate can be a substrate that has already undergone processing (such as epitaxial growth, doping, photolithography, etc.) or a substrate on which device structures (such as integrated circuits, optoelectronic devices, etc.) have already been formed. The semiconductor substrate can also refer to a semiconductor layer containing the device structure. The manufacturing method of the copper interconnect structure provided in this embodiment can refer to fabricating the copper interconnect structure on a processed substrate and / or on a substrate containing the device structure, or it can refer to fabricating the copper interconnect structure on a semiconductor layer containing the device structure. This embodiment can manufacture a multilayer copper interconnect structure, and copper interconnect structures of different layers can be formed by iteratively applying this manufacturing method. Of course, the process provided by this manufacturing method can also be combined with the process for forming the copper interconnect structure to fabricate a multilayer copper interconnect structure. It is understood that when manufacturing the copper interconnect structure, the low-dielectric-constant dielectric layer can be deposited on the processed substrate and / or on the device structure, or it can be deposited on the semiconductor layer.

[0044] The semiconductor substrate may be, but is not limited to, a silicon (Si) substrate, a gallium arsenide (GaAs) substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, a sapphire (Al2O3) substrate, a zinc oxide (ZnO), or a gallium oxide (Ga2O3).

[0045] Preferably, the low-dielectric-constant dielectric layer with a density gradient increasing from bottom to top comprises multiple dielectric sublayers. Specifically, forming a low-dielectric-constant dielectric layer with a density gradient increasing from bottom to top on the semiconductor substrate includes: the dielectric layer comprising at least a first dielectric sublayer located at the bottom and a second dielectric sublayer located at the top with a density greater than that of the first dielectric sublayer; or, the dielectric layer comprising at least a first dielectric sublayer located at the bottom, a second dielectric sublayer located in the middle, and a third dielectric sublayer located at the top, wherein the density of the first, second, and third dielectric sublayers gradually increases; or the dielectric layer comprises multiple dielectric sublayers from bottom to top, wherein the density of the multiple dielectric sublayers gradually increases, or the spacing between them increases, or the gradient increases uniformly or non-uniformly; or for each dielectric sublayer, there is a dielectric sublayer below it with a density not greater than that sublayer. Of course, a dielectric sublayer can contain dielectric sublayers with the same density. If a dielectric sublayer contains multiple dielectric sublayers, the density of one of these sublayers may be greater than the density of its upper sublayer. However, the overall density of the dielectric sublayers should increase towards the top sublayer. It can be understood that the density of a dielectric sublayer can be uniform or non-uniform. In the case of non-uniformity, the density can gradually increase within the sublayer or vary irregularly.

[0046] Please refer to Figure 2The figure shows a cross-sectional schematic diagram of a copper interconnect structure fabricated based on the method provided in this embodiment, with a semiconductor layer. For example, its dielectric layer consists of four dielectric sublayers, as shown in the figure from bottom to top: dielectric sublayer 201, dielectric sublayer 202, dielectric sublayer 203, and dielectric sublayer 204. The density gradually increases from dielectric sublayer 201 to 204, achieving a higher density (e.g., greater than 100%). A copper interconnect trench 301 is formed in the dielectric sublayer 204, and a copper barrier layer 302 is formed on the sidewalls and bottom of the copper interconnect trench 301. Metallic copper (Cu) is filled on the copper barrier layer 302. Because the interface (trench sidewalls and bottom) between the dielectric sublayer 204 and the copper barrier layer 302 has a high density, it can prevent the diffusion of copper atoms of the filled metallic copper into the dielectric layer, thereby improving the copper diffusion suppression effect.

[0047] For example, a low-dielectric-constant dielectric layer with progressively increasing density from bottom to top is fabricated on a semiconductor substrate by constructing a dielectric layer interface densification adjustment mechanism. Copper interconnect structures are defined and formed within this dielectric layer. This dielectric layer can suppress copper diffusion at smaller linewidths, avoiding reliability issues associated with traditional copper barrier layers (such as tantalum nitride / tantalum) as linewidth shrinks. The definition within the dielectric layer refers to transferring the designed circuit pattern onto the actual physical dielectric layer, creating the designed circuit pattern or structure within the dielectric layer. This can include, but is not limited to, the following process steps: photolithography preparation, exposure, development, and etching.

[0048] For example, the densification mechanism of the dielectric layer interface can be specifically achieved by progressively controlling the energy of the feed gas applied during the deposition of the dielectric layer. Specifically, a method for forming a low-dielectric-constant dielectric layer with progressively increasing density from bottom to top on the semiconductor substrate includes: during the formation of the dielectric layer, increasing the radio frequency power supply used to apply energy to the feed gas. In practice, the feed gas is introduced into the deposition chamber for depositing the dielectric layer, the feed gas being used to achieve plasma bombardment during the deposition of the dielectric layer; during the deposition of the dielectric layer, the radio frequency power supply used to apply energy to the feed gas is increased to form the dielectric layer with progressively increasing density.

[0049] For example, the feedstock gas may include a reactive gas and an inert gas. The reactive gas is used to directly participate in the chemical reaction to form a deposit; for example, the reactive gas includes one or more of gases such as silane, methane, ammonia, and nitrous oxide. The inert gas is used to provide an inert environment and protect the reaction process; for example, it may include argon and / or helium. The feedstock gas may also include reactive gases, such as hydrogen as a reducing agent and oxygen as a promoting oxidation.

[0050] For example, the radio frequency (RF) power supply that applies energy to the feed gas can be an LF (Low Frequency) RF power supply or an HF (High Frequency) RF power supply. Ion bombardment is performed during the deposition of the dielectric layer by applying the RF power supply to the feed gas in the deposition chamber to control the density of the dielectric layer. Alternatively, a low-energy ion beam can be obtained by applying a low-frequency RF power supply to the feed gas before deposition to bombard the interface surface to which the dielectric layer needs to be attached. This can remove surface contaminants, increase surface roughness, and improve the adhesion of the dielectric layer to the interface surface. The interface surface to which the dielectric layer needs to be attached can be the upper surface of the substrate material.

[0051] Preferably, the increasing radio frequency (RF) power applied to the feed gas includes: a gradient increase and / or a phased increase in the RF power applied to the feed gas, forming a low dielectric constant dielectric layer with increasing density. Gradient increase can be achieved by gradually increasing the RF power during deposition, which may be according to a predetermined increase rule or a function of an adjustment variable (such as deposition time). Phased increase can be achieved by dividing the deposition process into multiple stages, with the RF power in each stage increasing relative to the previous stage. In some process procedures, gradient increase and phased increase can be combined. For example, in some stages, the preset power value of the RF power is higher than the power value of the previous stage; or the RF power in some stages increases compared to the previous stage while the RF power is gradient-increased within the same stage. Furthermore, when the RF power applied to the feed gas is increased in a phased manner, the formed dielectric layer comprises multiple film layers, each film layer being understood as a dielectric sublayer. In practical applications, low-frequency (e.g., 400kHz) radio frequency (RF) power can dominate ion bombardment energy. Furthermore, the step-by-step increasing RF power applied to the feed gas to form a dielectric layer with increasing density further includes: dividing the deposition process into multiple power stages, executing each power stage sequentially, and forming a film layer (i.e., a dielectric sublayer) in each power stage with an increased RF power compared to the previous power stage. The film layer formed in each power stage has increased density compared to the film layer formed in the previous power stage. Through this step-by-step energy control mechanism (e.g., 200W→400W→600W→800W), a gradient increase in plasma ion bombardment intensity is achieved. In the early stages of the deposition process, the precursor can be fully dissociated and form a basic network structure through a low-power stage (e.g., 200W) using a low-frequency radio frequency power supply, which is the bottom layer of the dielectric layer (i.e., the bottom dielectric sublayer). Subsequently, in the high-power stage (e.g., 400W / 600W / 800W), the pores are compressed by controlled ion bombardment, thereby enhancing the density of the dielectric film.

[0052] Taking the interface-bulk phase layering design of the deposited layer and the application of LF radio frequency power to the raw material gas to form the dielectric layer as an example, the interface layer (or "adhesion layer of the dielectric layer") to which the dielectric layer is attached is, for example, the contact interface between the dielectric layer and the substrate material (such as a silicon wafer). The surface of the dielectric layer closer to the metal layer is the interface surface of the dielectric layer (or "inner surface of the dielectric layer"). During the deposition process of the dielectric layer, the LF radio frequency power can be gradually increased in stages to achieve a gradient increase in the ion bombardment intensity of the plasma, so that the adhesion layer of the dielectric layer is formed into a film with the intrinsic dielectric constant of the dielectric layer (e.g., k < 2.5), and a high-density (e.g., density > 2.2 g / cm³) surface is formed on the inner surface of the dielectric layer. The adhesion layer of the deposited dielectric layer can refer to the bottom film layer of the dielectric layer deposited on the substrate surface where the dielectric layer needs to be deposited. The inner surface of the deposited dielectric layer can be the interface between the dielectric layer and the barrier layer of the metal layer in the direction away from the substrate surface, which is the top film layer of the dielectric layer. The direction from the bottom film layer to the top film layer away from the substrate surface is from bottom to top. This achieves synergistic optimization of copper barrier capability and dielectric properties. Please refer to this again. Figure 2 The figure shows a cross-sectional schematic diagram of a copper interconnect structure manufactured based on the method provided in this embodiment. The formed dielectric layer includes four sublayers, as shown from bottom to top in the figure: dielectric sublayer 201, dielectric sublayer 202, dielectric sublayer 203, and dielectric sublayer 204. Of course, the number of dielectric sublayers (i.e., the number of film layers) can be increased or decreased as needed.

[0053] In practice, the existing deposition process for Low-k dielectric layers can be modified by increasing the power of the low-frequency radio frequency power supply in the deposition step to achieve the effect of gradient-enhanced plasma bombardment. This achieves the goal of bottom-up gradient densification of the film layer, which can make the interface between the dielectric layer and the metal layer (such as Cu) or the barrier layer of the metal layer (i.e., the top layer of the dielectric layer) more compact, while retaining the overall loose and porous nature of the Low-k dielectric layer, thus achieving the low dielectric constant required by the design.

[0054] For example, the plurality of power stages include at least a low-power stage and a high-power stage; wherein, in the low-power stage, the radio frequency power applied to the raw material gas dissociates (especially fully dissociates) the precursor used to form the dielectric layer and forms the bottom dielectric sublayer of the dielectric layer, for example, forming a basic network structure at the interface layer to which the dielectric layer needs to be attached, the basic network structure being the bottom dielectric sublayer of the dielectric layer; in the low-power stage, the power value of the radio frequency power is a first preset power value; in the high-power stage, the power value of the radio frequency power is increased to a second preset power value, the increased power value of the radio frequency power bombards the compressed pores, and a top dielectric sublayer of the dielectric layer is formed at the interface near the metal layer protected by the dielectric layer; the first preset power value is lower than the second preset power value. The bottom dielectric sublayer has the intrinsic dielectric constant of the low dielectric constant dielectric layer; the top dielectric layer has a high density. Preferably, the dielectric constant of the bottom dielectric sublayer is less than 2.5; the density of the top dielectric sublayer is greater than... Along the direction from the bottom dielectric sublayer to the top dielectric sublayer, the density of each film layer of the dielectric layer gradually increases.

[0055] In a preferred embodiment, the plurality of power stages includes four power stages performed sequentially for deposition. The power range of the RF power supply in each of the four sequentially performed power stages is 100W~300W, 350W~450W, 550W~650W, and 750W~850W, respectively, and the corresponding deposition time ranges are 35s~25s, 10s~20s, 5s~15s, and 3s~10s, respectively; four film layers are formed from bottom to top. A preferred set of power parameters is 200W, 400W, 600W, and 800W, and the deposition time parameters are 30s, 15s, 10s, and 5s. This preferred set of power parameters enables a uniform gradient change in film density. During implementation, as shown in Table 1, the optimized process formulation data divides the deposition step of the dielectric layer into four steps, as indicated by steps 3 to 6 in Table 1, corresponding to deposition densities 1 to 4. The deposition times for each step are 30s / 15s / 10s / 5s, respectively. The LF RF power supply power is progressively increased for each step, with LF RF power supplies of 200W / 400W / 600W / 800W for deposition densities 1 to 4, respectively. Table 1 is as follows:

[0056]

[0057] Please continue to refer to this. Figure 2Dielectric sublayer 201 is the bottom layer formed during the low-power stage; dielectric sublayers 202 and 203 are two layers formed at 400W and 600W respectively; and dielectric sublayer 204 is the top layer formed at high power (800W). This represents the stacked semiconductor layers shown in the diagram. The dielectric layer in the middle, along the distance from the semiconductor layer The metal layer in the middle and facing In the direction of the metal layer, the density of each film layer gradually increases. The bottom film layer is an intrinsic film layer with dielectric constants that meet the design requirements of semiconductor devices. The dielectric sublayers 201 to 204 gradually become denser, reducing the possibility of copper atoms diffusing into the porous Low-k dielectric layer at the interface between the dielectric layer and the copper barrier layer, while also possessing a lower intrinsic dielectric constant. In practical applications, this can be achieved by... The dielectric layer of this semiconductor layer is also fabricated using the same, similar, or different process formulation data. The number of dielectric layers in different semiconductor layers can be the same or different. Process iterations can also be performed on stacked multilayer semiconductor layers to generate the dielectric layer for each semiconductor layer.

[0058] Furthermore, while lower porosity can enhance the density of Low-k dielectric layers, excessively dense layers can lead to an increase in dielectric constant, deteriorating the RC delay characteristics of the circuit. Therefore, targeted optimization of process formulations is necessary for different semiconductor device designs to obtain optimal process formulation data for fabricating semiconductor dielectric layers. Targeted optimization refers to adjusting some or all of the process formulation data to obtain better process formulation data while still forming a semiconductor dielectric layer that meets the design requirements. For example, the number (N) of different film layer structures and the thickness of the film layers can be targetedly adjusted according to the design requirements. And the low-frequency radio frequency power (Wn) of different layers. Preferably, the process formulation data for fabricating the dielectric layer includes: the number of dielectric sublayers (i.e., the number of film layers) of the dielectric layer and the process parameters for forming each dielectric sublayer; the process formulation data is determined according to the design requirements information of the semiconductor device; the design requirements information includes the dielectric constant of the dielectric layer and the resistance, capacitance, and delay characteristics of the semiconductor device containing the dielectric layer. The process parameters for forming each dielectric sublayer include: the radio frequency power applied to the raw material gas during the formation of the dielectric sublayer and the thickness and / or deposition time of the dielectric sublayer. For example, the number (N) of different dielectric sublayer structures and the thickness of each dielectric sublayer can be directionally adjusted according to the design requirements information of the semiconductor device. The thickness of the dielectric sublayer can be determined based on the deposition time for forming the dielectric sublayer and / or the low-frequency RF power required to form different dielectric sublayers. Please refer to some process adjustment variables in Table 2, which refers to adjustable process parameters in the process formulation. For example, the deposition process in the table is divided into 1-N deposition steps, where N or n can be understood as representing the sequence number. Table 2 is as follows:

[0059]

[0060] Furthermore, the process formulation data is determined based on a density-power relationship model, which is used to optimize the process formulation data based on the design requirements information. That is, the density-power relationship model allows adjustment of process control variables in the process formulation data, thereby achieving targeted optimization of the semiconductor device's process formulation. For example, the density-power relationship model is a mathematical model that optimizes process parameters based on the design requirements of the semiconductor device's RC delay characteristics. Specifically, it can be a model relating the porosity ρ of the Low-k dielectric layer to the low-frequency RF power Wn, where the porosity characterizes the density of the Low-k dielectric layer. Preferably, the density-power relationship model includes:

[0061] A first relationship between the power of each power stage and the porosity of each dielectric sublayer, and a second relationship between the dielectric constant of each dielectric sublayer and the power of each power stage; the first and second relationships are constructed using the RF power supply as a process adjustment variable.

[0062] A third relation characterizing the intrinsic compactness of a dielectric layer; the third relation is constructed based on the deposition time of each dielectric sublayer and the film porosity of the corresponding dielectric sublayer;

[0063] A fourth relation characterizing the intrinsic dielectric constant of a dielectric layer; the fourth relation is constructed based on the deposition time of each dielectric sublayer;

[0064] The method further includes: determining the number of dielectric sublayers, the deposition time of each dielectric sublayer, and the RF power used to form each dielectric sublayer based on the intrinsic dielectric constant and the total thickness of each dielectric sublayer in the dielectric layer, using the first, second, third, and fourth relational expressions, as target recipe data. The target recipe data is used to fabricate a dielectric layer that meets the intrinsic dielectric constant and total thickness conditions of the dielectric layer in the design requirements information. The deposition time of each dielectric sublayer characterizes the thickness of the corresponding dielectric sublayer. The target recipe data represents a preferred value that satisfies the aforementioned design requirements information.

[0065] Exemplarily, the construction process of the density-power relationship model is as follows:

[0066] Step 1): Set the total thickness of the Low-k dielectric layer as T, and the thickness of the Nth layer is ; The density of the Nth layer is characterized by the porosity, which is ; The dielectric constant of the Nth layer is ; Each layer refers to a dielectric sublayer (i.e., a film layer);

[0067] Step 2): Taking the low-frequency radio frequency (LF) power as an example, with LF as the process adjustment variable, construct the relationship between the LF power Wn (0 < Wn < 1500W, that is, Wn is greater than 0 watts and less than 1500 watts) of each step in the process recipe and the porosity of each layer of the film layer as the first relationship:

[0068] (Formula 1);

[0069] Construct the relationship between the dielectric constant of each layer of the film layer and the LF power as the second relationship:

[0070] (Formula 2);

[0071] where A and B can be empirical constants;

[0072] Step 3): Construct a relationship formula characterizing the intrinsic density of the dielectric layer as the third relationship:

[0073] (Formula 3);

[0074] Step 4): Construct a relationship formula characterizing the intrinsic dielectric constant of the dielectric layer as the fourth relationship:

[0075] (Formula 4);

[0076] Step 5): Express the total thickness T of the dielectric layer included in the design requirement information as:

[0077] T = (Formula 5)

[0078] Step 6): According to the intrinsic dielectric constant k and the total thickness T of the dielectric layer that meet the device design requirement information, use a computer to solve the system of equations联立由公式(1)至(5)联立的方程组 by numerical solution method, and obtain the optimal number of film layers and the thickness of each layer under the conditions of the intrinsic dielectric constant k and the total thickness T of the dielectric layer required for device design The LF power Wn and the number of film layers can be used as the number of deposition steps n (i.e., the number of power stages) in the deposition process, thereby obtaining the optimal solution of process parameters that have both strong Low-k dielectric layer density and low dielectric constant, so that the Low-k dielectric layer has good resistance to Cu diffusion and low RC delay.

[0079] Furthermore, the density-power relationship model includes one or more process control variables; these process control variables include one or more of the following: high-frequency radio frequency power, low-frequency radio frequency power, silane flow rate, and nitrous oxide flow rate. The high-frequency radio frequency power is the radio frequency power applied to the feed gas during the ionization stage of the deposition process. The low-frequency radio frequency power is the radio frequency power applied to the feed gas during the deposition stage. The silane flow rate / nitrous oxide flow rate is the flow rate of the feed gas.

[0080] Preferably, the raw materials used to form the dielectric layer include one or more of SiO2 (silicon dioxide), SiCOH (carbon-doped silicon oxide), SiCN (silicon carbon nitride), FSG (fluorosilicate glass), and porous SiO2. Changing the process adjustment parameters only requires fine-tuning the above-mentioned relationship model.

[0081] Please refer to Figure 3 The figure shows two curves relating the dielectric constant to the copper diffusion resistance at the dielectric layer interface. Curve 1 shows the relationship between the dielectric constant of a semiconductor dielectric layer formed using existing technology and the copper diffusion resistance at the dielectric layer interface. Curve 2 shows the relationship between the dielectric constant of a semiconductor dielectric layer fabricated using the method provided in this embodiment and the copper diffusion resistance at the dielectric layer interface. A higher film density at the dielectric layer interface provides better copper diffusion resistance. It can be seen that, for the same copper diffusion resistance, the dielectric constant of the dielectric layer fabricated using the method provided in this embodiment is lower.

[0082] For example, existing deposition processes for Low-k dielectric layers can be optimized in a targeted manner, achieving a gradient improvement in the density and Cu migration resistance of the dielectric layer through stepwise energy control of the process. Furthermore, flexible process adjustment capabilities can be provided to complement semiconductor device products, thereby maximizing the optimization of Cu blocking capability and dielectric properties of the Low-k dielectric layer for specific semiconductor devices. The Low-k dielectric layer process can also be flexibly adjusted based on different voltage and resistance data contained in the semiconductor device design requirements. In practical applications, Low-k dielectric layer deposition processes can be iterated, and the process formulation can be targeted to different semiconductor product platforms, avoiding the following dilemma: as linewidth gradually decreases, a thicker TaN / Ta blocking layer leads to increased overall RC delay, while thinning TaN / Ta makes it difficult to prevent Cu diffusion into the Low-k dielectric layer, leading to failure. This concludes the description of the method provided in this embodiment. The method involves progressively increasing plasma bombardment intensity during the deposition process to form a multi-layered dielectric layer, balancing the density and dielectric properties of the Low-k dielectric layer. This results in a Low-k dielectric layer with higher resistance to copper diffusion. Therefore, the thickness of the TaN / Ta barrier layer can be reduced to accommodate the gradually decreasing linewidth of the metal layer, achieving both lower total interconnect resistance (providing lower RC delay) and good resistance to copper diffusion. This avoids the need for costly single-atom deposition processes to grow the TaN / Ta barrier layer while still achieving good resistance to copper diffusion.

[0083] Example 2

[0084] Based on the above embodiments, this embodiment provides a semiconductor structure, including: a semiconductor substrate;

[0085] A dielectric layer is formed on the semiconductor substrate; copper interconnect trenches are formed in the dielectric layer; copper barrier layers are formed on the sidewalls and bottom of the trenches; metallic copper is filled on the copper barrier layers in the copper interconnect trenches; wherein the dielectric layer is a low dielectric constant dielectric layer with a density gradient increasing from bottom to top.

[0086] Example 3

[0087] Based on the above embodiments, this embodiment provides another semiconductor structure, including:

[0088] At least two stacked semiconductor dielectric layers; copper interconnect trenches are formed in the two adjacent semiconductor dielectric layers; copper barrier layers are formed on the sidewalls and bottom of each copper interconnect trench; each copper barrier layer is filled with metallic copper; wherein the upper semiconductor dielectric layer in the two adjacent semiconductor dielectric layers is a low dielectric constant dielectric layer with gradually increasing density from bottom to top.

[0089] Example 4

[0090] Based on the above embodiments, this embodiment provides another semiconductor structure, including:

[0091] A semiconductor substrate; a dielectric layer formed on the semiconductor substrate; at least two adjacent and spaced-apart copper interconnect trenches formed in the dielectric layer; copper barrier layers formed on the sidewalls and bottom of each copper interconnect trench; and metallic copper filled in each copper barrier layer; wherein the dielectric layer is a low dielectric constant dielectric layer with a density that gradually increases from the middle towards the two layers of metallic copper that are filled in.

[0092] Although this application discloses preferred embodiments as described above, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be determined by the scope defined in the claims of this application.

Claims

1. A method for manufacturing a copper interconnect structure, characterized in that... include: Provide semiconductor substrates; A low-dielectric-constant dielectric layer with gradually increasing density from bottom to top is formed on the semiconductor substrate; Copper interconnect trenches are formed in the dielectric layer; A copper barrier layer is formed on the sidewalls and bottom of the trench; The copper barrier layer in the copper interconnect trench is filled with metallic copper; The method for forming a low dielectric constant dielectric layer with gradually increasing density from bottom to top on the semiconductor substrate includes: during the formation of the dielectric layer, increasing in a gradient and / or increasing in stages the radio frequency power used to apply energy to the feed gas, thereby forming a low dielectric constant dielectric layer with gradually increasing density from bottom to top on the semiconductor substrate. The low dielectric constant dielectric layer comprises multiple dielectric sublayers, and the copper interconnect trench is formed in the top dielectric sublayer of the multiple dielectric sublayers.

2. The method for manufacturing a copper interconnect structure according to claim 1, characterized in that, Forming a low-dielectric-constant dielectric layer with a gradient increasing density from bottom to top on the semiconductor substrate includes: The dielectric layer comprises at least a first dielectric sublayer located at the bottom and a second dielectric sublayer located at the top with a density greater than that of the first dielectric sublayer; or... The dielectric layer includes at least a first dielectric sublayer at the bottom, a second dielectric sublayer in the middle, and a third dielectric sublayer at the top, with the density of the first, second, and third dielectric sublayers gradually increasing; or The dielectric layer comprises multiple dielectric sublayers from bottom to top, and the density of the multiple dielectric sublayers gradually increases, or the spacing increases, or the gradient increases uniformly or non-uniformly, or for each dielectric sublayer, there is a dielectric sublayer below it with a density not greater than that of the sublayer.

3. The method according to claim 1, characterized in that, When the radio frequency power used to apply energy to the raw material gas is increased in stages, the formed dielectric layer comprises multiple dielectric sublayers.

4. The method according to claim 3, characterized in that, The method further includes: progressively increasing the radio frequency power used to apply energy to the raw material gas to form the dielectric layer with increasing density, and further comprising: The deposition process of the dielectric layer is divided into multiple power stages, and each power stage is executed sequentially. In each power stage, the dielectric sublayer of the power stage is formed with an increased radio frequency power compared to the previous power stage, wherein the dielectric sublayer formed in each power stage has increased density compared to the dielectric sublayer formed in the previous power stage.

5. The method according to claim 4, characterized in that, The plurality of power stages include at least a low-power stage and a high-power stage; wherein... In the low-power stage, the radio frequency power supply applied to the raw material gas dissociates the precursor used to form the dielectric layer and forms the bottom dielectric sublayer of the dielectric layer. In the low-power stage, the power value of the radio frequency power supply is a first preset power value. During the high-power phase, the power value of the radio frequency power supply is increased to a second preset power value, and a top dielectric sublayer of the dielectric layer is formed at the interface near the metal layer protected by the dielectric layer; the first preset power value is lower than the second preset power value.

6. The method according to claim 5, characterized in that, The dielectric constant of the bottom dielectric sublayer is less than 2.5; the density of the top dielectric sublayer is greater than... .

7. The method according to claim 4, characterized in that, The multiple power stages include four power stages that are deposited sequentially. The power range of the RF power supply in each of the four power stages is 150W~250W, 350W~450W, 550W~650W, and 750W~850W, respectively, and the corresponding deposition time ranges are 35s~25s, 10s~20s, 5s~15s, and 3s~10s, respectively.

8. The method according to claim 1, characterized in that, The process formulation data for manufacturing the dielectric layer includes: the number of dielectric sublayers of the dielectric layer and the process parameters for forming each dielectric sublayer; The process formulation data is determined based on the design requirements of the semiconductor device; the design requirements include the dielectric constant of the dielectric layer and the resistance, capacitance, and delay characteristics of the semiconductor device containing the dielectric layer.

9. The method according to claim 8, characterized in that, The process parameters used to form each dielectric sublayer include: the radio frequency power applied to the feed gas during the formation of the dielectric sublayer, and the thickness and / or deposition time of the dielectric sublayer.

10. The method according to claim 1, characterized in that, The raw materials used to form the dielectric layer include one or more of SiO2, SiCOH, SiCN, and FSG.

11. A semiconductor structure, characterized in that, The semiconductor structure includes a copper interconnect structure manufactured using the method described in any one of claims 1-10, comprising: Semiconductor substrate; A dielectric layer formed on the semiconductor substrate; Copper interconnect trenches are formed in the dielectric layer; A copper barrier layer is formed on the sidewalls and bottom of the trench; The copper barrier layer in the copper interconnect trench is filled with metallic copper; wherein, The dielectric layer is a low dielectric constant dielectric layer with a density gradient increasing from bottom to top.

12. A semiconductor structure, characterized in that, The semiconductor structure includes a copper interconnect structure manufactured using the method described in any one of claims 1-10, comprising: At least two stacked semiconductor dielectric layers; Copper interconnect trenches are formed in the two adjacent semiconductor dielectric layers; A copper barrier layer is formed on the sidewall and bottom of each of the copper interconnect trenches; Each of the copper barrier layers is filled with metallic copper; wherein... The upper semiconductor dielectric layer in the two adjacent semiconductor dielectric layers is a low dielectric constant dielectric layer with gradually increasing density from bottom to top.

13. A semiconductor structure, characterized in that, The semiconductor structure includes a copper interconnect structure manufactured using the method described in any one of claims 1-10, comprising: Semiconductor substrate; A dielectric layer formed on the semiconductor substrate; At least two adjacent and spaced copper interconnect trenches are formed in the dielectric layer; A copper barrier layer is formed on the sidewall and bottom of each of the copper interconnect trenches; Each of the copper barrier layers is filled with metallic copper; wherein... The dielectric layer is a low dielectric constant dielectric layer whose density gradually increases from the center toward the two separately filled copper metal layers.

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