Display substrate and preparation method thereof, display panel and display device

Abstract

The invention provides a display substrate and a preparation method thereof, a display panel and a display device, and the display substrate comprises a substrate, and a transparent conductive layer, a first metal layer, a first insulating layer, an active layer, a second insulating layer and a second metal layer which are sequentially stacked on one side of the substrate, the orthographic projection of the first metal layer on the substrate is located in the orthographic projection of the transparent conductive layer on the substrate, the first metal layer comprises a first pole, the first insulating layer is provided with a first via hole, and the first via hole penetrates through the first insulating layer and exposes at least part of the surface of the transparent conductive layer; the active layer comprises a channel, a first conductor region and a second conductor region, the first conductor region and the second conductor region are located on the two sides of the channel, the first conductor region is connected with the transparent conductive layer through a first via hole, and the second metal layer comprises a grid electrode. According to the embodiment of the invention, the etching damage to the active layer can be reduced, the film stripping risk caused by the lap joint of the active layer and the first electrode can be reduced, and the product yield is improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of display devices, and in particular to a display substrate and a preparation method thereof, a display panel, and a display device. Background Art

[0002] Thin-film transistors (TFTs), as switching control elements or integrated components in peripheral driver circuits, are widely used in various display devices and are core components in flat-panel display technology. In related art, the conductive region of the active layer of a TFT on a display substrate overlaps the source and / or drain electrodes. However, this overlap can lead to film delamination and damage during the formation process, resulting in film reduction and affecting the yield of the display substrate. Summary of the Invention

[0003] The embodiments of the present disclosure provide a display substrate and a method for manufacturing the same, a display panel, and a display device to solve or alleviate one or more technical problems in the prior art.

[0004] As a first aspect of an embodiment of the present disclosure, an embodiment of the present disclosure provides a display substrate, including:

[0005] substrate;

[0006] a transparent conductive layer, located on one side of the substrate;

[0007] A first metal layer is located on a side of the transparent conductive layer facing away from the substrate, an orthographic projection of the first metal layer on the substrate is located within an orthographic projection of the transparent conductive layer on the substrate, and the first metal layer includes a first electrode;

[0008] a first insulating layer, located on a side of the first metal layer facing away from the substrate, the first insulating layer being provided with a first via hole, the first via hole penetrating the first insulating layer and exposing at least a portion of the surface of the transparent conductive layer;

[0009] an active layer located on a side of the first insulating layer facing away from the substrate, the active layer comprising a channel, and a first conductive region and a second conductive region located on both sides of the channel, the first conductive region being connected to the transparent conductive layer through a first via;

[0010] a second insulating layer, located on a side of the active layer facing away from the substrate;

[0011] The second metal layer is located on a side of the second insulating layer facing away from the substrate, and the second metal layer includes a gate.

[0012] In some possible implementations, the transparent conductive layer includes a first transparent electrode, the orthographic projection of the first electrode on the substrate is located within the orthographic projection of the first transparent electrode on the substrate, the first via hole passes through the first insulating layer and exposes at least a portion of the surface of the first transparent electrode, and the first conductive area is connected to the first transparent electrode through the first via hole.

[0013] In some possible implementations, the first transparent electrode includes a first part and a second part, the orthographic projection of the first part on the substrate coincides with the orthographic projection of the first electrode on the substrate, the orthographic projection of the first via on the substrate does not overlap with the orthographic projection of the first electrode on the substrate, and the first via passes through the first insulating layer to expose at least a portion of the surface of the second part.

[0014] In some possible implementations, the first transparent electrode includes a first portion, an orthographic projection of the first portion on the substrate coincides with an orthographic projection of the first electrode on the substrate, and the first via hole passes through the first insulating layer and the first electrode to expose at least a portion of the surface of the first portion.

[0015] In some possible implementations, the transparent conductive layer further includes a second transparent electrode, the first metal layer further includes a light-shielding portion, the orthographic projection of the second transparent electrode on the substrate is located within the orthographic projection of the light-shielding portion on the substrate, and the orthographic projection of the channel on the substrate is located within the orthographic projection of the light-shielding portion on the substrate.

[0016] In some possible implementations, the diameter of the first via hole is 4 μm-6 μm.

[0017] In some possible implementations, the material of the transparent conductive layer includes transparent metal oxide; and / or the material of the first metal layer includes copper; and / or the material of the active layer includes oxide semiconductor.

[0018] In some possible implementations,

[0019] a third insulating layer, located on a side of the second metal layer facing away from the substrate;

[0020] an organic planar layer, located on a side of the third insulating layer facing away from the substrate;

[0021] a third metal layer, located on a side of the organic planar layer facing away from the substrate, the third metal layer comprising a common electrode;

[0022] a fourth insulating layer located on a side of the third metal layer facing away from the substrate, the fourth insulating layer being provided with a second via hole, the second via hole penetrating the fourth insulating layer, the organic planarizing layer, and the third insulating layer to expose at least a portion of a surface of the second conductive region;

[0023] The fourth metal layer is located on a side of the fourth insulating layer facing away from the substrate. The fourth metal layer includes a first electrode. The first electrode is connected to the second conductive area through a second via hole.

[0024] As a second aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a method for preparing a display substrate, comprising:

[0025] forming a transparent conductive layer on one side of the substrate;

[0026] forming a first metal layer on a side of the transparent conductive layer facing away from the substrate, wherein the orthographic projection of the first metal layer on the substrate is located within the orthographic projection of the transparent conductive layer on the substrate, and the first metal layer includes a first electrode;

[0027] forming a first insulating layer on a side of the first metal layer facing away from the substrate, wherein the first insulating layer is provided with a first via hole, the first via hole penetrating the first insulating layer and exposing at least a portion of the surface of the transparent conductive layer;

[0028] An active layer is formed on a side of the first insulating layer facing away from the substrate, the active layer comprising a channel, and a first conductive region and a second conductive region located on both sides of the channel, the first conductive region being connected to the transparent conductive layer through a first via hole;

[0029] forming a second insulating layer on a side of the active layer facing away from the substrate;

[0030] A second metal layer is formed on a side of the second insulating layer facing away from the substrate, and the second metal layer includes a gate.

[0031] As a third aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display panel comprising the display substrate of any one of the embodiments of the present disclosure.

[0032] As a fourth aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display device, comprising the display substrate of any one of the embodiments of the present disclosure or the display panel of any one of the embodiments of the present disclosure.

[0033] The technical solution of the embodiment of the present disclosure can achieve the following beneficial effects: this display substrate can reduce etching damage to the active layer, and can also reduce the risk of film peeling caused by overlapping of the active layer and the first electrode, thereby improving product yield.

[0034] The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present disclosure will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments according to the present disclosure and should not be regarded as limiting the scope of the present disclosure.

[0036] Figure 1 A schematic structural diagram of a display substrate in related art;

[0037] Figure 2 This is a light microscope image of a display substrate film layer peeling off in the related art;

[0038] Figure 3 This is a scanning electron microscope microscopic morphology image of a cross section of a display substrate film layer when peeling occurs in the related art;

[0039] Figure 4 is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure;

[0040] Figure 5 A cross-sectional scanning electron microscope diagram of the connection between the transparent conductive layer and the first electrode according to an embodiment of the present disclosure;

[0041] Figure 6 is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure;

[0042] Figure 7 is a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure;

[0043] Figure 8a A cross-sectional schematic diagram showing a transparent conductive layer and a first metal layer formed on a display substrate according to an embodiment of the present disclosure;

[0044] Figure 8b A schematic plan view of forming a transparent conductive layer and a first metal layer on a display substrate according to an embodiment of the present disclosure;

[0045] Figure 8c A schematic cross-sectional view of forming a first via hole on a display substrate according to an embodiment of the present disclosure;

[0046] Figure 8d A schematic plan view of forming a first via hole on a display substrate according to an embodiment of the present disclosure;

[0047] Figure 8e A schematic cross-sectional view of forming an active layer on a display substrate according to an embodiment of the present disclosure;

[0048] Figure 8f A schematic plan view of forming an active layer on a display substrate according to an embodiment of the present disclosure;

[0049] Figure 8g A schematic plan view of forming a second metal layer on a display substrate according to an embodiment of the present disclosure;

[0050] Figure 8h FIG. 1 is a schematic plan view of a display substrate according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] Hereinafter, only certain exemplary embodiments are briefly described. As will be appreciated by those skilled in the art, the described embodiments may be modified in various ways without departing from the spirit or scope of the present disclosure. Therefore, the drawings and description are to be considered as illustrative in nature and not restrictive.

[0052] Thin film transistors include bottom-gate thin film transistors and top-gate thin film transistors. There are two main problems with bottom-gate thin film transistors. The first is the control of back channel etching (BCE). Back channel etching can easily affect the channel device of the thin film transistor due to over-etching, which has an adverse effect on the performance of the thin film transistor. Although an etching protection layer (ES) can be used to solve the back channel etching problem. However, the use of an etching protection layer will increase the complexity of the process. Second, bottom-gate thin film transistors are not easy to achieve self-alignment. There are compatibility issues between the back exposure technology and the existing process. The traditional preparation method will cause the bottom-gate thin film transistor to have a large overlapping area, resulting in a large overlapping capacitance, which is not conducive to reducing the channel size. The large overlapping capacitance will also reduce the operating speed of the driving circuit, making it difficult to use it to drive high-resolution active matrix organic light-emitting diode (AMOLED) displays or liquid crystal displays (LCDs).

[0053] The top-gate thin-film transistor can solve the problems and shortcomings of the bottom-gate thin-film transistor. First, the top-gate thin-film transistor does not have the problem of over-etching damage, and the gate dielectric layer (GI) in the top-gate thin-film transistor can protect the active layer above the active layer (Active). Secondly, the top-gate structure has the advantage of achieving self-alignment, and the process is relatively simple. For example, by plasma treatment of the source and drain, hydrogen can be added to the source and drain regions of the active layer to increase the conductivity of the source and drain regions of the active layer. The self-aligned structure can avoid overlapping areas, and there is no overlapping capacitance. The channel size of the thin-film transistor can be more accurately controlled, and a shorter channel can be achieved.

[0054] Figure 1 Schematic diagram of the structure of the display substrate of the related art. Figure 1As shown, the display substrate includes a substrate 1, a first metal layer 2 located on one side of the substrate 1, and the first metal layer 2 includes a first electrode 201 and a second electrode 202. A first insulating layer 3 is located on the side of the first metal layer 2 facing away from the substrate 1. The first insulating layer 3 is provided with a first via B1 and a second via B2. The first via B1 penetrates the first insulating layer 3 and exposes at least a portion of the surface of the first electrode 201. The second via B2 penetrates the first insulating layer 3 and exposes at least a portion of the surface of the second electrode 202. An active layer 4 is provided on the side of the first insulating layer 3 facing away from the substrate 1. The active layer 4 includes a channel 401 and a first conductive region 402 and a second conductive region 403 located on either side of the channel 401. The first conductive region 402 is connected to the first electrode 201 via the first via B1, and the second conductive region 403 is connected to the second electrode 202 via the second via B2. The second insulating layer 5 is located on the side of the active layer 4 facing away from the substrate 1. The second metal layer 6 is located on the side of the second insulating layer 5 facing away from the substrate 1. The second metal layer 6 includes a gate 61. The third insulating layer 7 is located on the side of the second metal layer 6 facing away from the substrate 1.

[0055] Exemplarily, the second insulating layer 5 is a gate insulating layer (GI), and the third insulating layer 7 is a passivation layer (PVX). The first metal layer 2 is made of copper, and the first and second vias B1 and B2 expose at least a portion of the surface of the first electrode 201 and the second electrode 202 of the first metal layer 2. When the active layer 4 is subjected to a high-temperature baking process, the copper in the first metal layer 2 is easily oxidized, resulting in poor coverage and connection between the first and second conductive regions 402 and 403 and the first and second electrodes 201 and 202. This can cause film peeling during etching of the gate 61, resulting in a defective display substrate.

[0056] Figure 2 This is a schematic diagram of peeling off the display substrate film layer according to an embodiment of the present disclosure. Figure 3 This is a schematic cross-sectional view of the display substrate film layer peeling electron microscope of the embodiment of the present disclosure. Figure 2 and Figure 3 As shown, the first conductive area and the first pole, the second conductive area and the second pole of the active layer 4 of the display substrate are severely oxidized due to the high-temperature baking of the active layer 4, resulting in poor coverage of the subsequent film layer, thereby causing (copper film peeling) Cu Peeling, resulting in a defective display substrate.

[0057] For example, after forming the second metal layer 6, the material of the second insulating layer 5 other than the gate of the second metal layer 6 is etched away using the second metal layer 6 as a mask. In display substrates of related art, etching of both the second insulating layer 5 and the first insulating layer 3 causes film reduction on the active layer 4, thereby reducing the thickness of the active layer 4. The thinner the thickness of the active layer 4, the greater the impedance of the first conductive region 402 and the second conductive region 403 of the active layer 4, thereby reducing the stability of the thin film transistor.

[0058] In order to solve the problem of film peeling in display substrates in related technologies, an embodiment of the present disclosure provides a display substrate. The technical solution of the display substrate of the present disclosure is described in detail below through embodiments.

[0059] Figure 4 Schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure. Figure 4 As shown, an embodiment of the present disclosure provides a display substrate, which includes a substrate 10, a transparent conductive layer 20, a first metal layer 30, a first insulating layer 40, an active layer 50, a second insulating layer 60 and a second metal layer 70.

[0060] Reference Figure 4 As shown, specifically, the transparent conductive layer 20 is located on one side of the substrate 10. The first metal layer 30 is located on the side of the transparent conductive layer 20 facing away from the substrate 10. The orthographic projection of the first metal layer 30 on the substrate 10 is located within the orthographic projection of the transparent conductive layer 20 on the substrate 10. The first metal layer 30 includes a first electrode 31. The first insulating layer 40 is located on the side of the first metal layer 30 facing away from the substrate 10. The first insulating layer 40 is provided with a first via K1, which penetrates the first insulating layer 40 and exposes at least a portion of the surface of the transparent conductive layer 20. The active layer 50 is located on the side of the first insulating layer 40 facing away from the substrate 10. The active layer 50 includes a channel 51 and a first conductive region 52 and a second conductive region 53 located on either side of the channel 51. The first conductive region 51 is connected to the transparent conductive layer 20 via the first via K1. The second insulating layer 60 is located on the side of the active layer 50 facing away from the substrate 10. The second metal layer 70 is located on a side of the second insulating layer 60 facing away from the substrate 10 . The second metal layer 70 includes a gate 71 .

[0061] Exemplarily, the gate 71 corresponds to the channel 51. For example, the orthographic projection of the gate 71 on the substrate 10 is located within the orthographic projection of the channel 51 on the substrate 10. It should be noted that the orthographic projection of the first metal layer 30 on the substrate 10 is located within the orthographic projection of the transparent conductive layer 20 on the substrate 10. It can be understood that the orthographic projection of the first metal layer 30 on the substrate 10 coincides with the orthographic projection of the transparent conductive layer 20 on the substrate 10, or the orthographic projection of the first metal layer 30 on the substrate 10 is completely located within the orthographic projection of the transparent conductive layer 20 on the substrate 10. In other words, the first metal layer 30 and the transparent conductive layer 20 are stacked and overlapped. The first electrode 31 and part of the transparent conductive layer 20 can be a source electrode, or the first electrode 31 and part of the transparent conductive layer 20 can be a drain electrode.

[0062] Figure 5 Schematic diagram of the transparent conductive layer and the first electrode of the embodiment of the present disclosure. Figure 5 As shown, there is no film peeling between the transparent conductive layer and the first electrode.

[0063] In related technologies, Figure 1 The first via hole B1 and the second via hole B2 of the display substrate are arranged on the first metal layer 2. When the active layer 4 is subjected to a high-temperature baking and conductive treatment, the first metal layer 2 is severely oxidized. The film coverage between the first conductive area 402 and the second conductive area 403 of the active layer 4 and the first metal layer 2 is poor, which ultimately causes Cu peeling during gate etching. Figure 2 and Figure 3 As shown, the connection between the first conductive area 402, the second conductive area 403 and the first metal layer 2 is poor, resulting in a poor display substrate, which seriously affects the consumer experience. In the display substrate of the embodiment of the present disclosure, the first insulating layer 40 is provided with a first via K1. The first via K1 penetrates the first insulating layer 40 and exposes at least part of the surface of the transparent conductive layer 20. The first conductive area 51 is connected to the transparent conductive layer 20 through the first via K1. With this arrangement, when the active layer 40 is baked at a high temperature, since the first conductive area 51 is connected to the transparent conductive layer 20, the first conductive area 51 and the transparent conductive layer 20 will not peel off. Figure 5 As shown, the connection between the first conductive area 51 and the first electrode 31 is not affected, thereby improving the yield of the display substrate and enhancing the user experience.

[0064] Table 1 is a comparative table showing the active layer film thickness reduction of the display substrate of the conventional technical solution and the embodiment of the present disclosure. As shown in Table 1, the conventional technical solution causes film thickness reduction in both the first and second insulating layers during dry etching, resulting in a smaller residual thickness of the active layer. The lower the residual thickness of the active layer, the greater the impedance and the worse the stability. For example, in the conventional technical solution, when the active layer thickness is 500 angstroms, dry etching of the gate insulating layer causes the active layer film thickness to be reduced to 140 angstroms, and dry etching of the first insulating layer causes the active layer film thickness to be reduced to 100 angstroms, leaving the remaining thickness of the active layer at 260 angstroms. In contrast, in the display substrate of the embodiment of the present disclosure, dry etching of the gate insulating layer causes the active layer film thickness to be reduced to 140 angstroms, and dry etching of the first insulating layer causes the active layer film thickness to be reduced to 0, leaving the remaining thickness of the active layer at 360 angstroms. The display substrate of the embodiment of the present disclosure can reduce etching damage to the active layer, reduce the impedance of the conductive region of the active layer, and improve stability.

[0065]

[0066] Table 1 Schematic comparison of active layer film reduction of display substrates in conventional technical solutions and embodiments of the present disclosure

[0067] In the display substrate of the disclosed embodiment, a first insulating layer 40 is located on the side of the first metal layer 30 facing away from the substrate 10. A first via K1 is provided in the first insulating layer 40, penetrating the first insulating layer 40 and exposing at least a portion of the surface of the transparent conductive layer 20. An active layer 50 is located on the side of the first insulating layer 40 facing away from the substrate 10. The active layer 50 includes a channel 51 and a first conductive region 52 and a second conductive region 53 located on either side of the channel 51. The first conductive region 51 is connected to the transparent conductive layer 20 via the first via K1. The provision of the first via K1 in the first insulating layer 40 avoids damage to the active layer caused by insulating layer etching in the related art, reduces film loss on the active layer, lowers the impedance of the conductive region of the active layer, and improves stability. Furthermore, the connection of the first conductive region 52 of the active layer 50 to the transparent conductive layer 20 via the first via K1 avoids delamination between the first conductive region and the first polarization layer caused by high-temperature baking of the active layer in the related art, thereby improving the yield of the display substrate and enhancing the user experience.

[0068] Reference Figure 4 As shown, in one embodiment, the transparent conductive layer 20 includes a first transparent electrode 21, the orthographic projection of the first electrode 31 on the substrate 10 is located within the orthographic projection of the first transparent electrode 21 on the substrate 10, the first via K1 passes through the first insulating layer 40 and exposes at least a portion of the surface of the first transparent electrode 21, and the first conductive area 52 is connected to the first transparent electrode 21 through the first via K1.

[0069] Exemplarily, the orthographic projection of the first electrode 31 on the substrate 10 is located within the orthographic projection of the first transparent electrode 21 on the substrate 10, that is, the orthographic projection of the first electrode 31 on the substrate 10 coincides with the orthographic projection of the first transparent electrode 21 on the substrate 10, or the orthographic projection of the first electrode 31 on the substrate 10 is entirely located within the orthographic projection of the first transparent electrode 21 on the substrate 10. The first transparent electrode 21 and the first electrode 31 as a whole form the source of the thin film transistor, or the first transparent electrode 21 and the first electrode 31 as a whole form the drain of the thin film transistor.

[0070] For example, the first via K1 passes through the first insulating layer 40 and exposes at least a portion of the surface of the first transparent electrode 21. The first conductive region 52 can be entirely overlapped with the first transparent electrode 21, or the first conductive region 52 can be partially overlapped with the first transparent electrode 21, with the remaining portion of the first conductive region 52 overlapping with the first electrode 31. Both of these can prevent film peeling.

[0071] Reference Figure 4 As shown, in one embodiment, the first transparent electrode 21 includes a first portion 211 and a second portion 212. The orthographic projection of the first portion 211 on the substrate 10 coincides with the orthographic projection of the first electrode 31 on the substrate 10, and the orthographic projection of the first via K1 on the substrate 10 does not overlap with the orthographic projection of the first electrode 31 on the substrate 10. The first via K1 passes through the first insulating layer 40 and exposes at least a portion of the surface of the second portion 212.

[0072] Exemplarily, the first transparent electrode 21 and the first electrode 31 can both be square in shape, and the orthographic projection of the first portion 11 on the substrate 10 coincides with the orthographic projection of the first electrode 31 on the substrate 10. That is, the first portion 11 overlaps the surface of the first electrode 31 on the side facing away from the substrate 10. The orthographic projection of the first via K1 on the substrate 10 does not overlap with the orthographic projection of the first electrode 31 on the substrate 10, and the first conductive region 52 does not overlap with the first electrode 31. The first via K1 penetrates the first insulating layer 40 and exposes at least a portion of the surface of the second portion 212. The orthographic projection of the first via K1 on the substrate 10 is located within the orthographic projection of the second portion 212 on the substrate 10, or the orthographic projection of the first via K1 on the substrate 10 is partially located within the orthographic projection of the second portion 212 on the substrate 10.

[0073] In the display substrate of the disclosed embodiment, the first transparent electrode 21 is divided into a first portion 211 and a second portion 212. The orthographic projection of the first portion 211 on the substrate 10 coincides with the orthographic projection of the first electrode 31 on the substrate 10. The orthographic projection of the first via K1 on the substrate does not overlap with the orthographic projection of the first electrode 31 on the substrate 10. Furthermore, the first via K1 penetrates the first insulating layer 40, exposing at least a portion of the surface of the second portion 212. This arrangement ensures that the first conductive region 52 overlaps the second portion 212, but does not overlap the first conductive region 52 and the first electrode 31. This prevents film delamination between the first conductive region 52 and the first electrode, ensures the stability and reliability of the connection between the first conductive region 52 and the first electrode, and improves the yield rate of the display substrate.

[0074] Figure 6 Schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure. Figure 6 As shown, in one embodiment, the first transparent electrode 21 includes a first portion 211, the orthographic projection of the first portion 211 on the substrate 10 coincides with the orthographic projection of the first pole 31 on the substrate 10, and the first via K1 passes through the first insulating layer 40 and the first pole 31 to expose at least a portion of the surface of the first portion 211.

[0075] Exemplarily, the first transparent electrode 21 includes a first portion 211, whose orthographic projection on the substrate 10 coincides with the orthographic projection of the first electrode 31 on the substrate 10. For example, the orthographic projection of the first transparent electrode 21 on the substrate 10 coincides with the orthographic projection of the first electrode 31 on the substrate 10. The first via K1 penetrates the first insulating layer 40 and the first electrode 31, exposing at least a portion of the surface of the first portion 211. This arrangement allows the first conductive region 52 to partially overlap the surface of the first portion 211 and to partially connect to the first electrode 31, preventing film delamination between the first conductive region 52 and the first electrode, ensuring the stability and reliability of the connection between the first conductive region 52 and the first electrode, and improving the yield of the display substrate.

[0076] Reference Figure 4 As shown, in one embodiment, the transparent conductive layer 20 further includes a second transparent electrode 22, the first metal layer 30 further includes a light-shielding portion 32, the orthographic projection of the second transparent electrode 22 on the substrate 10 is located within the orthographic projection of the light-shielding portion 32 on the substrate 10, and the orthographic projection of the channel 51 on the substrate 10 is located within the orthographic projection of the light-shielding portion 32 on the substrate 10.

[0077] Exemplarily, the orthographic projection of the second transparent electrode 22 on the substrate 10 is located within the orthographic projection of the light shielding portion 32 on the substrate 10. The orthographic projection of the second transparent electrode 22 on the substrate 10 coincides with the orthographic projection of the light shielding portion 32 on the substrate 10, or the orthographic projection of the second transparent electrode 22 on the substrate 10 is completely located within the orthographic projection of the light shielding portion 32 on the substrate 10, and the light shielding portion 32 covers the second transparent electrode 22 as a whole.

[0078] Exemplarily, the second transparent electrode 22 and the light shielding portion 32 are formed as a whole together with the first transparent electrode 21 and the first electrode 31 through a single patterning process, which can reduce the number of masks and reduce costs.

[0079] In one embodiment, the aperture of the first via K1 is 4 μm-6 μm. For example, the first via K1 can be a circular hole or a square hole, or the first via K1 can also be a via of other shapes. The specific shape of the first via K1 is not limited here and can be set according to actual use requirements. The aperture of the first via K1 can be 4 μm, 4.5 μm, 5 μm, 5.5 μm, or 6 μm. The specific value of the aperture of the first via K1 is not limited here and can be set according to actual use requirements.

[0080] In one embodiment, the material of the transparent conductive layer 20 includes a transparent metal oxide. For example, the transparent conductive layer 20 may be indium tin oxide (ITO). The specific material of the transparent conductive layer 20 is not limited here and can be set according to actual use requirements.

[0081] In one embodiment, the material of the first metal layer 30 includes copper. The specific material of the first metal layer 30 is not limited here and can be set according to actual use requirements.

[0082] For example, thin film transistors mainly include amorphous silicon thin film transistors and polycrystalline silicon thin film transistors. Amorphous silicon (a-Si) thin film transistors are used in display panels as drive circuits or switch control elements. The mobility of amorphous silicon is less than 1 cm 2 / V·S, polysilicon has poor uniformity, complex process and high cost, and is sensitive to visible light and cannot work under visible light, making it difficult to use in large-size and high-resolution display panels.

[0083] In a disclosed embodiment, the material of the active layer 50 includes a metal oxide material and / or a metal oxynitride material, and the metal oxide material includes but is not limited to: indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxide (In-free OS), rare earth doped oxide (Ln-OS), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb and Cd-Sn-O.

[0084] The metal oxynitride material includes, but is not limited to, zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, silicon oxynitride, or a combination thereof.

[0085] The material of the active layer 50 may be in an amorphous, partially crystalline, single crystal or polycrystalline state, and may also be a single layer or multilayer structure. The thin film transistor (Oxide TFT) formed by the oxide semiconductor has good uniformity and high mobility. The display substrate formed by the embodiment of the present disclosure has a top-gate thin film transistor, which has a high on-state current and a stable current. The display substrate can be applied to active matrix light emitting diode display products (AMOLED). The display substrate formed by the embodiment of the present disclosure has a top-gate thin film transistor, which has a high on-state current and low capacitance. The display substrate can be applied to liquid crystal display products.

[0086] In one embodiment, the material of the transparent conductive layer 20 includes transparent metal oxide, the material of the first metal layer 30 includes copper, and the material of the active layer 50 includes oxide semiconductor.

[0087] Figure 7 Schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure. Figure 7As shown, in one embodiment, the display substrate further includes a third insulating layer 100, an organic planarizing layer 110, a third metal layer 80, a fourth insulating layer 120, and a fourth metal layer 90. The third insulating layer 100 is located on the side of the second metal layer 70 facing away from the substrate 10. The organic planarizing layer 110 is located on the side of the third insulating layer 100 facing away from the substrate 10. The third metal layer 80 is located on the side of the organic planarizing layer 110 facing away from the substrate 10 and includes a common electrode 81 (Com). The fourth insulating layer 120 is located on the side of the third metal layer 80 facing away from the substrate 10 and is provided with a second via K2. The second via K2 penetrates the fourth insulating layer 120, the organic planarizing layer 110, and the third insulating layer 100, exposing at least a portion of the surface of the second conductive area 53. The fourth metal layer 90 is located on the side of the fourth insulating layer 120 facing away from the substrate 10 and includes a first electrode 91 connected to the second conductive area 53 through the second via K2.

[0088] In the display substrate of the embodiment of the present disclosure, the first electrode 91 is a pixel electrode, and the second conductive area 53 is located in the pixel area of ​​the display substrate. Therefore, a portion of the second conductive area 53 overlaps with the first electrode 91 to serve as a pixel electrode.

[0089] The present disclosure also provides a method for preparing a display substrate, comprising:

[0090] A transparent conductive layer 20 is formed on one side of the substrate 10 .

[0091] A first metal layer 30 is formed on the side of the transparent conductive layer 20 facing away from the substrate 10 . The orthographic projection of the first metal layer 30 on the substrate 10 is located within the orthographic projection of the transparent conductive layer 20 on the substrate 10 . The first metal layer 30 includes a first electrode 31 .

[0092] A first insulating layer 40 is formed on a side of the first metal layer 30 facing away from the substrate 10 . The first insulating layer 40 is provided with a first via hole K1 . The first via hole K1 passes through the first insulating layer 40 and exposes at least a portion of the surface of the transparent conductive layer 20 .

[0093] An active layer 50 is formed on the side of the first insulating layer 40 facing away from the substrate 10 . The active layer 50 includes a channel 51 and a first conductive region 52 and a second conductive region 53 located on both sides of the channel 51 . The first conductive region 52 is connected to the transparent conductive layer 20 through a first via K1 .

[0094] A second insulating layer 60 is formed on a side of the active layer 50 facing away from the substrate 10 .

[0095] A second metal layer 70 is formed on a side of the second insulating layer 60 facing away from the substrate 10 . The second metal layer 70 includes a gate 71 .

[0096] The following is an embodiment of the present disclosure Figure 7 The preparation process of the display substrate shown further illustrates the technical solution of the embodiment of the present disclosure. It can be understood that the "patterning process" in the present disclosure, when the patterned material is an inorganic material or a metal layer, the "patterning process" may include processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist. When the patterned material is an organic material (such as photoresist or organic resin), the "patterning process" may include processes such as mask exposure and development. The evaporation, deposition, coating, and coating in the present disclosure are all mature preparation processes in the relevant technology.

[0097] A transparent conductive material is deposited on one side of the substrate 10 to form a transparent conductive layer 20. A first metal thin film is deposited on the side of the transparent conductive layer 20 facing away from the substrate 10 to form a first metal layer 30. The orthographic projection of the first metal layer 30 on the substrate 10 is located within the orthographic projection of the transparent conductive layer 20 on the substrate 10. Through a patterning process, the transparent conductive layer 20 and the first metal layer 30 form a first transparent electrode 21 and a first polarization layer, a second transparent electrode 22, and a light shielding portion 32. The orthographic projection of the first transparent electrode 21 on the substrate coincides with the orthographic projection of the first polarization layer on the substrate, and the orthographic projection of the second transparent electrode 22 on the substrate coincides with the orthographic projection of the light shielding portion 32 on the substrate. The first electrode layer is then patterned to remove part of the material of the first electrode layer, so that the first electrode layer forms the first electrode 31. The first transparent electrode 21 is divided into a first portion 211 and a second portion 212. The orthographic projection of the first portion 211 on the substrate 10 coincides with the orthographic projection of the first electrode 31 on the substrate 10, and the orthographic projection of the second portion 212 on the substrate 10 does not overlap with the orthographic projection of the first electrode 31 on the substrate 10. Figure 8a and Figure 8b As shown, Figure 8a This is a cross-sectional schematic diagram of forming a transparent conductive layer and a first metal layer on a display substrate according to an embodiment of the present disclosure. Figure 8b A plan view of forming a transparent conductive layer and a first metal layer on a display substrate according to an embodiment of the present disclosure.

[0098] A first insulating material film is deposited on the side of the first metal layer 30 facing away from the substrate 10, and the first insulating material film is patterned to form a first insulating layer 40. The first insulating layer 40 is patterned to form a first via hole K1. The first via hole K1 passes through the first insulating layer 40 and exposes at least a portion of the surface of the second portion 212 of the transparent conductive layer 20. The aperture of the first via hole K1 is 4 μm-6 μm. Figure 8c and Figure 8d As shown, Figure 8c Schematic cross-sectional view of forming a first via hole on a display substrate according to an embodiment of the present disclosure. Figure 8dThe diagram is a plan view of forming a first via hole on a display substrate according to an embodiment of the present disclosure.

[0099] An active material film is deposited on the side of the first insulating layer 40 facing away from the substrate 10, and the active film is conductively converted to form an active layer. Figure 8e and Figure 8f As shown, Figure 8e Schematic cross-sectional view of forming an active layer on a display substrate according to an embodiment of the present disclosure. Figure 8f The figure is a plan view of forming an active layer on a display substrate according to an embodiment of the present disclosure.

[0100] A second insulating material film is deposited on the side of the active layer 50 facing away from the substrate 10, and the second insulating material film is patterned to form a second insulating layer 60. A second metal material film is deposited on the side of the second insulating layer 60 facing away from the substrate 10, and a second metal layer 70 is formed by a patterning process. The second metal layer 70 includes a gate 71. The second metal layer 70 is used as a mask and the second insulating layer 60 is etched by a dry etching process. The second insulating layer 50 located in the area where the gate 71 is located is retained. The active layer 50 is subjected to a conductorization process. For example, a suitable conductorization process, such as an ion implantation process or an ion bombardment process, can be selected so that when the active layer 50 is fully conductorized, the active layer 50 includes a channel 51, and a first conductorization region 52 and a second conductorization region 53 located on both sides of the channel 51. The first conductorization region 51 is connected to the second portion 212 of the transparent conductive layer 20 through a first via K1. The conductorization process can be a plasma treatment process of He or He+Ar. Figure 7 and Figure 8g As shown, Figure 8g This is a plan view of forming a second metal layer on a display substrate according to an embodiment of the present disclosure.

[0101] A third insulating material film is deposited on the side of the second metal layer 70 facing away from the substrate 10, and the third insulating material film is patterned to form a third insulating layer 100, such as Figure 7 As shown in Figure 1 and Figure 8h, Figure 8h FIG. 1 is a schematic plan view of a display substrate according to an embodiment of the present disclosure.

[0102] An organic material film is deposited on the side of the third insulating layer 100 facing away from the substrate 10, and the organic material film is patterned to form an organic planar layer 110, such as Figure 7 As shown in FIG8h and FIG8h , the thickness of the organic planar layer 110 is 20,000 angstroms to 30,000 angstroms, for example.

[0103] A third metal material film is deposited on the side of the organic planar layer 110 facing away from the substrate 10, and the third metal material film is patterned to form a third metal layer 80. The third metal layer 80 includes a common electrode 81, such as Figure 7 As shown in FIG8h and FIG8h . The material of the third metal layer 80 is a transparent conductive material. For example, the material of the third metal layer 80 is a metal oxide such as indium tin oxide (ITO). The thickness of the third metal layer 80 is 700 angstroms to 1000 angstroms.

[0104] A fourth insulating material film is deposited on the side of the third metal layer 80 facing away from the substrate 10, and the fourth insulating material film is patterned to form a fourth insulating layer 120. The fourth insulating layer 120 is provided with a second via K2. The second via K2 penetrates the fourth insulating layer 120, the organic planarizing layer 110, and the third insulating layer 100 to expose at least a portion of the surface of the second conductive region 53. Figure 7 As shown in Figures 8h and 8h, for example, the diameter of the second via hole K2 is 4 μm-6 μm.

[0105] A fourth metal material film is deposited on the side of the fourth insulating layer 120 facing away from the substrate 10, and the fourth metal material film is patterned to form a fourth metal layer 90. The fourth metal layer 90 includes a first electrode 91. The first electrode 91 is connected to the second conductive area 53 through a second via K2. The first electrode 91 serves as a pixel electrode and is connected to the pixel area. Figure 7 As shown in FIG8h and FIG8h . Exemplarily, the thickness of the first electrode 91 is 700 angstroms to 1000 angstroms. The fourth metal layer 90 is made of a metal oxide such as indium tin oxide (ITO).

[0106] For example, the first insulating layer 40, the second insulating layer 60, the third insulating layer 100, and the fourth insulating layer 120 may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or a composite layer. The first insulating layer 40 may be called a buffer layer, which is used to improve the substrate's resistance to water and oxygen. The second insulating layer 60 may be called a gate insulating (GI) layer, and the third insulating layer 100 may be called an interlayer dielectric (ILD) layer.

[0107] For example, the first metal layer 30 and the second metal layer 70 can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti. The organic planar layer 110 can be made of polyimide, acrylic or polyethylene terephthalate. The active layer 50 can be made of various materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, polythiophene, etc., that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology and organic technology.

[0108] The embodiments of the present disclosure provide a display panel, comprising the display substrate of any one of the embodiments of the present disclosure. For example, the display panel may be a liquid crystal display panel, or the display panel may also be an OLED display panel.

[0109] Yet another embodiment of the present disclosure provides a display device, comprising the display substrate described in any embodiment of the present disclosure or the display panel described in any embodiment of the present disclosure.

[0110] The display device provided in the embodiments of the present disclosure can be any product or component with display and touch functions, such as a smartphone, a wearable smart watch, smart glasses, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, a car display, an e-book, a biometric device such as a smart skin device, a soft robot, and a biomedical device.

[0111] The display device of the embodiment of the present disclosure adopts the display substrate described in any embodiment of the present disclosure or the display panel described in any embodiment of the present disclosure, and the light shielding portion and the first electrode can be manufactured on the same layer, thereby reducing the number of masks and lowering costs. In addition, the first electrode uses a double-layer structure of a transparent conductive layer and a first metal layer. The first conductive region of the active layer is connected to the transparent conductive layer through a first via, thereby avoiding the problem of the first conductive region being connected to the first electrode of the first metal layer in the related art, which easily causes film peeling during high-temperature oxidation at the overlapping position of the first conductive region. The first via penetrates the first insulating layer, thereby avoiding the problem of film damage to the active layer caused by etching the gate insulating layer and the first insulating layer together in the related art.

[0112] The display substrate, display panel and other components of the display device in the above embodiment can adopt various technical solutions known to ordinary technicians in this field now and in the future, and will not be described in detail here.

[0113] In the description of this specification, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0114] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout the present disclosure, "plurality" means two or more, unless otherwise specifically defined.

[0115] In this disclosure, unless otherwise expressly specified or limited, terms such as "mounted," "connected," "connect," and "fixed" should be understood broadly. For example, they may refer to fixed connections, detachable connections, or integration; mechanical connections, electrical connections, or communication; direct connections or indirect connections through an intermediate medium; and internal connections between two components or interactions between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on specific circumstances.

[0116] In the present disclosure, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0117] The disclosure above provides many different embodiments or examples for implementing different structures of the present disclosure. In order to simplify the present disclosure, the components and settings of specific examples are described above. Of course, these are merely examples and are not intended to limit the present disclosure. In addition, the present disclosure may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed.

[0118] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any person skilled in the art can easily conceive of various modifications or substitutions within the technical scope disclosed in this disclosure, and such modifications or substitutions should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate, characterized in that: include: substrate; a transparent conductive layer, located on one side of the substrate; a first metal layer, located on a side of the transparent conductive layer facing away from the substrate, wherein an orthographic projection of the first metal layer on the substrate is located within an orthographic projection of the transparent conductive layer on the substrate, and the first metal layer includes a first electrode; a first insulating layer, located on a side of the first metal layer facing away from the substrate, the first insulating layer being provided with a first via hole, the first via hole penetrating the first insulating layer and exposing at least a portion of a surface of the transparent conductive layer; an active layer located on a side of the first insulating layer facing away from the substrate, the active layer comprising a channel, and a first conductive region and a second conductive region located on both sides of the channel, the first conductive region being connected to the transparent conductive layer through the first via; a second insulating layer, located on a side of the active layer facing away from the substrate; The second metal layer is located on a side of the second insulating layer facing away from the substrate, and the second metal layer includes a gate.

2. The display substrate according to claim 1, wherein: The transparent conductive layer includes a first transparent electrode, the orthographic projection of the first electrode on the substrate is located within the orthographic projection of the first transparent electrode on the substrate, the first via hole penetrates the first insulating layer and exposes at least a portion of the surface of the first transparent electrode, and the first conductive area is connected to the first transparent electrode through the first via hole.

3. The display substrate according to claim 2, wherein: The first transparent electrode includes a first part and a second part, the orthographic projection of the first part on the substrate coincides with the orthographic projection of the first pole on the substrate, the orthographic projection of the first via on the substrate does not overlap with the orthographic projection of the first pole on the substrate, and the first via passes through the first insulating layer to expose at least a portion of the surface of the second part.

4. The display substrate according to claim 2, wherein: The first transparent electrode includes a first portion, an orthographic projection of the first portion on the substrate coincides with an orthographic projection of the first electrode on the substrate, and the first via hole passes through the first insulating layer and the first electrode to expose at least a portion of a surface of the first portion.

5. The display substrate according to claim 2, wherein: The transparent conductive layer further includes a second transparent electrode, the first metal layer further includes a light-shielding portion, the orthographic projection of the second transparent electrode on the substrate is located within the orthographic projection of the light-shielding portion on the substrate, and the orthographic projection of the channel on the substrate is located within the orthographic projection of the light-shielding portion on the substrate.

6. The display substrate according to claim 1, wherein: The aperture of the first via hole is 4 μm-6 μm.

7. The display substrate according to claim 1, wherein: The material of the transparent conductive layer includes transparent metal oxide; and / or the material of the first metal layer includes copper; and / or the material of the active layer includes oxide semiconductor.

8. The display substrate according to claim 1, wherein: The display substrate further includes: a third insulating layer, located on a side of the second metal layer facing away from the substrate; an organic planar layer, located on a side of the third insulating layer facing away from the substrate; a third metal layer, located on a side of the organic planar layer facing away from the substrate, the third metal layer comprising a common electrode; a fourth insulating layer, located on a side of the third metal layer facing away from the substrate, the fourth insulating layer being provided with a second via hole, the second via hole penetrating the fourth insulating layer, the organic planarizing layer, and the third insulating layer to expose at least a portion of a surface of the second conductive region; A fourth metal layer is located on a side of the fourth insulating layer facing away from the substrate. The fourth metal layer includes a first electrode. The first electrode is connected to the second conductive area through the second via.

9. A method for preparing a display substrate, characterized in that: include: forming a transparent conductive layer on one side of the substrate; forming a first metal layer on a side of the transparent conductive layer facing away from the substrate, wherein the orthographic projection of the first metal layer on the substrate is located within the orthographic projection of the transparent conductive layer on the substrate, and the first metal layer includes a first electrode; forming a first insulating layer on a side of the first metal layer facing away from the substrate, wherein the first insulating layer is provided with a first via hole, the first via hole penetrating the first insulating layer and exposing at least a portion of the surface of the transparent conductive layer; forming an active layer on a side of the first insulating layer facing away from the substrate, the active layer comprising a channel, and a first conductive region and a second conductive region located on both sides of the channel, the first conductive region being connected to the transparent conductive layer through the first via hole; forming a second insulating layer on a side of the active layer facing away from the substrate; A second metal layer is formed on a side of the second insulating layer facing away from the substrate, wherein the second metal layer includes a gate.

10. A display panel, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 8.

11. A display device, characterized in that: The display device comprises the display substrate according to any one of claims 1 to 8 or the display panel according to claim 10.

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